diff options
Diffstat (limited to 'nx-X11/extras/Mesa/src/mesa/drivers/dri/ffb/server')
3 files changed, 0 insertions, 924 deletions
diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/ffb/server/ffb_dac.h b/nx-X11/extras/Mesa/src/mesa/drivers/dri/ffb/server/ffb_dac.h deleted file mode 100644 index 08114282e..000000000 --- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/ffb/server/ffb_dac.h +++ /dev/null @@ -1,367 +0,0 @@ -/* - * Acceleration for the Creator and Creator3D framebuffer - DAC register layout. - * - * Copyright (C) 2000 David S. Miller (davem@redhat.com) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * DAVID MILLER BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/sunffb/ffb_dac.h,v 1.2 2001/04/05 17:42:33 dawes Exp $ */ - -#ifndef _FFB_DAC_H -#define _FFB_DAC_H - -#define Bool int - -/* FFB utilizes two different ramdac chips: - * - * 1) BT9068 "Pacifica1", used in all FFB1 and - * FFB2 boards. - * - * 2) BT498(a) "Pacifica2", used in FFB2+ and - * AFB boards. - * - * They are mostly equivalent, except in a few key areas: - * - * 1) WID register layout - * 2) Number of CLUT tables - * 3) Presence of Window Address Mask register - * 4) Method of GAMMA correction support - */ - -/* NOTE: All addresses described in this file are DAC - * indirect addresses. - */ - -/* DAC color values are in the following format. */ -#define FFBDAC_COLOR_BLUE 0x00ff0000 -#define FFBDAC_COLOR_BLUE_SHFT 16 -#define FFBDAC_COLOR_GREEN 0x0000ff00 -#define FFBDAC_COLOR_GREEN_SHFT 8 -#define FFBDAC_COLOR_RED 0x000000ff -#define FFBDAC_COLOR_RED_SHFT 0 - -/* Cursor DAC register addresses. */ -#define FFBDAC_CUR_BITMAP_P0 0x000 /* Plane 0 cursor bitmap */ -#define FFBDAC_CUR_BITMAP_P1 0x080 /* Plane 1 cursor bitmap */ -#define FFBDAC_CUR_CTRL 0x100 /* Cursor control */ -#define FFBDAC_CUR_COLOR0 0x101 /* Cursor Color 0 */ -#define FFBDAC_CUR_COLOR1 0x102 /* Cursor Color 1 (bg) */ -#define FFBDAC_CUR_COLOR2 0x103 /* Cursor Color 2 (fg) */ -#define FFBDAC_CUR_POS 0x104 /* Active cursor position */ - -/* Cursor control register. - * WARNING: Be careful, reverse logic on these bits. - */ -#define FFBDAC_CUR_CTRL_P0 0x00000001 /* Plane0 display disable */ -#define FFBDAC_CUR_CTRL_P1 0x00000002 /* Plane1 display disable */ - -/* Active cursor position register */ -#define FFBDAC_CUR_POS_Y_SIGN 0x80000000 /* Sign of Y position */ -#define FFBDAC_CUR_POS_Y 0x0fff0000 /* Y position */ -#define FFBDAC_CUR_POS_X_SIGN 0x00008000 /* Sign of X position */ -#define FFBDAC_CUR_POS_X 0x00000fff /* X position */ - -/* Configuration and Palette DAC register addresses. */ -#define FFBDAC_CFG_PPLLCTRL 0x0000 /* Pixel PLL Control */ -#define FFBDAC_CFG_GPLLCTRL 0x0001 /* General Purpose PLL Control */ -#define FFBDAC_CFG_PFCTRL 0x1000 /* Pixel Format Control */ -#define FFBDAC_CFG_UCTRL 0x1001 /* User Control */ -#define FFBDAC_CFG_CLUP_BASE 0x2000 /* Color Lookup Palette */ -#define FFBDAC_CFG_CLUP(entry) (FFBDAC_CFG_CLUP_BASE + ((entry) * 0x100)) -#define FFBDAC_PAC2_SOVWLUT0 0x3100 /* Shadow Overlay Window Lookup 0*/ -#define FFBDAC_PAC2_SOVWLUT1 0x3101 /* Shadow Overlay Window Lookup 1*/ -#define FFBDAC_PAC2_SOVWLUT2 0x3102 /* Shadow Overlay Window Lookup 2*/ -#define FFBDAC_PAC2_SOVWLUT3 0x3103 /* Shadow Overlay Window Lookup 3*/ -#define FFBDAC_PAC2_AOVWLUT0 0x3210 /* Active Overlay Window Lookup 0*/ -#define FFBDAC_PAC2_AOVWLUT1 0x3211 /* Active Overlay Window Lookup 1*/ -#define FFBDAC_PAC2_AOVWLUT2 0x3212 /* Active Overlay Window Lookup 2*/ -#define FFBDAC_PAC2_AOVWLUT3 0x3213 /* Active Overlay Window Lookup 3*/ -#define FFBDAC_CFG_WTCTRL 0x3150 /* Window Transfer Control */ -#define FFBDAC_CFG_TMCTRL 0x3151 /* Transparent Mask Control */ -#define FFBDAC_CFG_TCOLORKEY 0x3152 /* Transparent Color Key */ -#define FFBDAC_CFG_WAMASK 0x3153 /* Window Address Mask (PAC2 only) */ -#define FFBDAC_PAC1_SPWLUT_BASE 0x3100 /* Shadow Primary Window Lookups */ -#define FFBDAC_PAC1_SPWLUT(entry) (FFBDAC_PAC1_SPWLUT_BASE + (entry)) -#define FFBDAC_PAC1_APWLUT_BASE 0x3120 /* Active Primary Window Lookups */ -#define FFBDAC_PAC1_APWLUT(entry) (FFBDAC_PAC1_APWLUT_BASE + (entry)) -#define FFBDAC_PAC2_SPWLUT_BASE 0x3200 /* Shadow Primary Window Lookups */ -#define FFBDAC_PAC2_SPWLUT(entry) (FFBDAC_PAC2_SPWLUT_BASE + (entry)) -#define FFBDAC_PAC2_APWLUT_BASE 0x3240 /* Active Primary Window Lookups */ -#define FFBDAC_PAC2_APWLUT(entry) (FFBDAC_PAC2_APWLUT_BASE + (entry)) -#define FFBDAC_CFG_SANAL 0x5000 /* Signature Analysis Control */ -#define FFBDAC_CFG_DACCTRL 0x5001 /* DAC Control */ -#define FFBDAC_CFG_TGEN 0x6000 /* Timing Generator Control */ -#define FFBDAC_CFG_VBNP 0x6001 /* Vertical Blank Negation Point */ -#define FFBDAC_CFG_VBAP 0x6002 /* Vertical Blank Assertion Point*/ -#define FFBDAC_CFG_VSNP 0x6003 /* Vertical Sync Negation Point */ -#define FFBDAC_CFG_VSAP 0x6004 /* Vertical Sync Assertion Point */ -#define FFBDAC_CFG_HSNP 0x6005 /* Horz Serration Negation Point */ -#define FFBDAC_CFG_HBNP 0x6006 /* Horz Blank Negation Point */ -#define FFBDAC_CFG_HBAP 0x6007 /* Horz Blank Assertion Point */ -#define FFBDAC_CFG_HSYNCNP 0x6008 /* Horz Sync Negation Point */ -#define FFBDAC_CFG_HSYNCAP 0x6009 /* Horz Sync Assertion Point */ -#define FFBDAC_CFG_HSCENNP 0x600A /* Horz SCEN Negation Point */ -#define FFBDAC_CFG_HSCENAP 0x600B /* Horz SCEN Assertion Point */ -#define FFBDAC_CFG_EPNP 0x600C /* Eql'zing Pulse Negation Point */ -#define FFBDAC_CFG_EINP 0x600D /* Eql'zing Intvl Negation Point */ -#define FFBDAC_CFG_EIAP 0x600E /* Eql'zing Intvl Assertion Point*/ -#define FFBDAC_CFG_TGVC 0x600F /* Timing Generator Vert Counter */ -#define FFBDAC_CFG_TGHC 0x6010 /* Timing Generator Horz Counter */ -#define FFBDAC_CFG_DID 0x8000 /* Device Identification */ -#define FFBDAC_CFG_MPDATA 0x8001 /* Monitor Port Data */ -#define FFBDAC_CFG_MPSENSE 0x8002 /* Monitor Port Sense */ - -/* Pixel PLL Control Register */ -#define FFBDAC_CFG_PPLLCTRL_M 0x0000007f /* PLL VCO Multiplicand */ -#define FFBDAC_CFG_PPLLCTRL_D 0x00000780 /* PLL VCO Divisor */ -#define FFBDAC_CFG_PPLLCTRL_PFD 0x00001800 /* Post VCO Frequency Divider */ -#define FFBDAC_CFG_PPLLCTRL_EN 0x00004000 /* Enable PLL as pixel clock src */ - -/* General Purpose PLL Control Register */ -#define FFBDAC_CFG_GPLLCTRL_M 0x0000007f /* PLL VCO Multiplicand */ -#define FFBDAC_CFG_GPLLCTRL_D 0x00000780 /* PLL VCO Divisor */ -#define FFBDAC_CFG_GPLLCTRL_PFD 0x00001800 /* Post VCO Frequency Divider */ -#define FFBDAC_CFG_GPLLCTRL_EN 0x00004000 /* Enable PLL as Gen. Purpose clk*/ - -/* Pixel Format Control Register */ -#define FFBDAC_CFG_PFCTRL_2_1 0x00000000 /* 2:1 pixel interleave format */ -#define FFBDAC_CFG_PFCTRL_4_1 0x00000001 /* 4:1 pixel interleave format */ -#define FFBDAC_CFG_PFCTRL_42_1 0x00000002 /* 4/2:1 pixel interleave format */ -#define FFBDAC_CFG_PFCTRL_82_1 0x00000003 /* 8/2:1 pixel interleave format */ - -/* User Control Register */ -#define FFBDAC_UCTRL_IPDISAB 0x00000001 /* Disable input pullup resistors*/ -#define FFBDAC_UCTRL_ABLANK 0x00000002 /* Asynchronous Blank */ -#define FFBDAC_UCTRL_DBENAB 0x00000004 /* Double-Buffer Enable */ -#define FFBDAC_UCTRL_OVENAB 0x00000008 /* Overlay Enable */ -#define FFBDAC_UCTRL_WMODE 0x00000030 /* Window Mode */ -#define FFBDAC_UCTRL_WM_COMB 0x00000000 /* Window Mode = Combined */ -#define FFBDAC_UCTRL_WM_S4 0x00000010 /* Window Mode = Seperate_4 */ -#define FFBDAC_UCTRL_WM_S8 0x00000020 /* Window Mode = Seperate_8 */ -#define FFBDAC_UCTRL_WM_RESV 0x00000030 /* Window Mode = reserved */ -#define FFBDAC_UCTRL_MANREV 0x00000f00 /* 4-bit Manufacturing Revision */ - -/* Overlay Window Lookup Registers (PAC2 only) */ -#define FFBDAC_CFG_OVWLUT_PSEL 0x0000000f /* Palette Section, Seperate_4 */ -#define FFBDAC_CFG_OVWLUT_PTBL 0x00000030 /* Palette Table */ -#define FFBDAC_CFG_OVWLUT_LKUP 0x00000100 /* 1 = Use palette, 0 = Bypass */ -#define FFBDAC_CFG_OVWLUT_OTYP 0x00000c00 /* Overlay Type */ -#define FFBDAC_CFG_OVWLUT_O_N 0x00000000 /* Overlay Type - None */ -#define FFBDAC_CFG_OVWLUT_O_T 0x00000400 /* Overlay Type - Transparent */ -#define FFBDAC_CFG_OVWLUT_O_O 0x00000800 /* Overlay Type - Opaque */ -#define FFBDAC_CFG_OVWLUT_O_R 0x00000c00 /* Overlay Type - Reserved */ -#define FFBDAC_CFG_OVWLUT_PCS 0x00003000 /* Psuedocolor Src */ -#define FFBDAC_CFG_OVWLUT_P_XO 0x00000000 /* Psuedocolor Src - XO[7:0] */ -#define FFBDAC_CFG_OVWLUT_P_R 0x00001000 /* Psuedocolor Src - R[7:0] */ -#define FFBDAC_CFG_OVWLUT_P_G 0x00002000 /* Psuedocolor Src - G[7:0] */ -#define FFBDAC_CFG_OVWLUT_P_B 0x00003000 /* Psuedocolor Src - B[7:0] */ - -/* Window Transfer Control Register */ -#define FFBDAC_CFG_WTCTRL_DS 0x00000001 /* Device Status, 1 = Busy */ -#define FFBDAC_CFG_WTCTRL_TCMD 0x00000002 /* Transfer Command - * 1 = Transfer, 0 = No Action - */ -#define FFBDAC_CFG_WTCTRL_TE 0x00000004 /* Transfer Event - * 1 = Next Frame, 0 = Next Field - */ -#define FFBDAC_CFG_WTCTRL_DRD 0x00000008 /* Drawing Data - * 1 = Local Drawing Active - * 0 = Local Drawing Idle - */ -#define FFBDAC_CFG_WTCTRL_DRS 0x00000010 /* Drawing Status - * 1 = Network Drawing Active - * 0 = Network Drawing Idle - */ - -/* Transparent Mask Control Register */ -#define FFBDAC_CFG_TMCTRL_OMSK 0x000000ff /* Overlay Mask */ - -/* Transparent Color Key Register */ -#define FFBDAC_CFG_TCOLORKEY_K 0x000000ff /* Overlay Color Key */ - -/* Window Address Mask Register (PAC2 only) */ -#define FFBDAC_CFG_WAMASK_PMSK 0x0000003f /* PWLUT select PMASK */ -#define FFBDAC_CFG_WAMASK_OMSK 0x00000300 /* OWLUT control OMASK */ - -/* (non-Overlay) Window Lookup Table Registers, PAC1 format */ -#define FFBDAC_PAC1_WLUT_DB 0x00000020 /* 0 = Buffer A, 1 = Buffer B */ -#define FFBDAC_PAC1_WLUT_C 0x0000001c /* C: Color Model Selection */ -#define FFBDAC_PAC1_WLUT_C_8P 0x00000000 /* C: 8bpp Pseudocolor */ -#define FFBDAC_PAC1_WLUT_C_8LG 0x00000004 /* C: 8bpp Linear Grey */ -#define FFBDAC_PAC1_WLUT_C_8NG 0x00000008 /* C: 8bpp Non-Linear Grey */ -#define FFBDAC_PAC1_WLUT_C_24D 0x00000010 /* C: 24bpp Directcolor */ -#define FFBDAC_PAC1_WLUT_C_24LT 0x00000014 /* C: 24bpp Linear Truecolor */ -#define FFBDAC_PAC1_WLUT_C_24NT 0x00000018 /* C: 24bpp Non-Linear Truecolor */ -#define FFBDAC_PAC1_WLUT_PCS 0x00000003 /* Pseudocolor Src */ -#define FFBDAC_PAC1_WLUT_P_XO 0x00000000 /* Pseudocolor Src - XO[7:0] */ -#define FFBDAC_PAC1_WLUT_P_R 0x00000001 /* Pseudocolor Src - R[7:0] */ -#define FFBDAC_PAC1_WLUT_P_G 0x00000002 /* Pseudocolor Src - G[7:0] */ -#define FFBDAC_PAC1_WLUT_P_B 0x00000003 /* Pseudocolor Src - B[7:0] */ - -/* (non-Overlay) Window Lookup Table Registers, PAC2 format */ -#define FFBDAC_PAC2_WLUT_PTBL 0x00000030 /* Palette Table Entry */ -#define FFBDAC_PAC2_WLUT_LKUP 0x00000100 /* 1 = Use palette, 0 = Bypass */ -#define FFBDAC_PAC2_WLUT_PCS 0x00003000 /* Pseudocolor Src */ -#define FFBDAC_PAC2_WLUT_P_XO 0x00000000 /* Pseudocolor Src - XO[7:0] */ -#define FFBDAC_PAC2_WLUT_P_R 0x00001000 /* Pseudocolor Src - R[7:0] */ -#define FFBDAC_PAC2_WLUT_P_G 0x00002000 /* Pseudocolor Src - G[7:0] */ -#define FFBDAC_PAC2_WLUT_P_B 0x00003000 /* Pseudocolor Src - B[7:0] */ -#define FFBDAC_PAC2_WLUT_DEPTH 0x00004000 /* 0 = Pseudocolor, 1 = Truecolor*/ -#define FFBDAC_PAC2_WLUT_DB 0x00008000 /* 0 = Buffer A, 1 = Buffer B */ - -/* Signature Analysis Control Register */ -#define FFBDAC_CFG_SANAL_SRR 0x000000ff /* DAC Seed/Result for Red */ -#define FFBDAC_CFG_SANAL_SRG 0x0000ff00 /* DAC Seed/Result for Green */ -#define FFBDAC_CFG_SANAL_SRB 0x00ff0000 /* DAC Seed/Result for Blue */ -#define FFBDAC_CFG_SANAL_RQST 0x01000000 /* Signature Capture Request */ -#define FFBDAC_CFG_SANAL_BSY 0x02000000 /* Signature Analysis Busy */ -#define FFBDAC_CFG_SANAL_DSM 0x04000000 /* Data Strobe Mode - * 0 = Signature Analysis Mode - * 1 = Data Strobe Mode - */ - -/* DAC Control Register */ -#define FFBDAC_CFG_DACCTRL_O2 0x00000003 /* Operand 2 Select - * 00 = Normal Operation - * 01 = Select 145mv Reference - * 10 = Select Blue DAC Output - * 11 = Reserved - */ -#define FFBDAC_CFG_DACCTRL_O1 0x0000000c /* Operand 1 Select - * 00 = Normal Operation - * 01 = Select Green DAC Output - * 10 = Select Red DAC Output - * 11 = Reserved - */ -#define FFBDAC_CFG_DACCTRL_CR 0x00000010 /* Comparator Result - * 0 = operand1 < operand2 - * 1 = operand1 > operand2 - */ -#define FFBDAC_CFG_DACCTRL_SGE 0x00000020 /* Sync-on-Green Enable */ -#define FFBDAC_CFG_DACCTRL_PE 0x00000040 /* Pedestal Enable */ -#define FFBDAC_CFG_DACCTRL_VPD 0x00000080 /* VSYNC* Pin Disable */ -#define FFBDAC_CFG_DACCTRL_SPB 0x00000100 /* Sync Polarity Bit - * 0 = VSYNC* and CSYNC* active low - * 1 = VSYNC* and CSYNC* active high - */ - -/* Timing Generator Control Register */ -#define FFBDAC_CFG_TGEN_VIDE 0x00000001 /* Video Enable */ -#define FFBDAC_CFG_TGEN_TGE 0x00000002 /* Timing Generator Enable */ -#define FFBDAC_CFG_TGEN_HSD 0x00000004 /* HSYNC* Disabled */ -#define FFBDAC_CFG_TGEN_VSD 0x00000008 /* VSYNC* Disabled */ -#define FFBDAC_CFG_TGEN_EQD 0x00000010 /* Equalization Disabled */ -#define FFBDAC_CFG_TGEN_MM 0x00000020 /* 0 = Slave, 1 = Master */ -#define FFBDAC_CFG_TGEN_IM 0x00000040 /* 1 = Interlaced Mode */ - -/* Device Identification Register, should be 0xA236E1AD for FFB bt497/bt498 */ -#define FFBDAC_CFG_DID_ONE 0x00000001 /* Always set */ -#define FFBDAC_CFG_DID_MANUF 0x00000ffe /* Manufacturer ID */ -#define FFBDAC_CFG_DID_PNUM 0x0ffff000 /* Device Part Number */ -#define FFBDAC_CFG_DID_REV 0xf0000000 /* Device Revision */ - -/* Monitor Port Data Register */ -#define FFBDAC_CFG_MPDATA_SCL 0x00000001 /* SCL Data */ -#define FFBDAC_CFG_MPDATA_SDA 0x00000002 /* SDA Data */ - -/* Monitor Port Sense Register */ -#define FFBDAC_CFG_MPSENSE_SCL 0x00000001 /* SCL Sense */ -#define FFBDAC_CFG_MPSENSE_SDA 0x00000002 /* SDA Sense */ - -/* DAC register access shorthands. */ -#define DACCUR_READ(DAC, ADDR) ((DAC)->cur = (ADDR), (DAC)->curdata) -#define DACCUR_WRITE(DAC, ADDR, VAL) ((DAC)->cur = (ADDR), (DAC)->curdata = (VAL)) -#define DACCFG_READ(DAC, ADDR) ((DAC)->cfg = (ADDR), (DAC)->cfgdata) -#define DACCFG_WRITE(DAC, ADDR, VAL) ((DAC)->cfg = (ADDR), (DAC)->cfgdata = (VAL)) - -typedef struct ffb_dac_hwstate { - unsigned int ppllctrl; - unsigned int gpllctrl; - unsigned int pfctrl; - unsigned int uctrl; - unsigned int clut[256 * 4]; /* One 256 entry clut on PAC1, 4 on PAC2 */ - unsigned int ovluts[4]; /* Overlay WLUTS, PAC2 only */ - unsigned int wtctrl; - unsigned int tmctrl; - unsigned int tcolorkey; - unsigned int wamask; - unsigned int pwluts[64]; - unsigned int dacctrl; - unsigned int tgen; - unsigned int vbnp; - unsigned int vbap; - unsigned int vsnp; - unsigned int vsap; - unsigned int hsnp; - unsigned int hbnp; - unsigned int hbap; - unsigned int hsyncnp; - unsigned int hsyncap; - unsigned int hscennp; - unsigned int hscenap; - unsigned int epnp; - unsigned int einp; - unsigned int eiap; -} ffb_dac_hwstate_t; - -typedef struct { - Bool InUse; - - /* The following fields are undefined unless InUse is TRUE. */ - int refcount; - Bool canshare; - unsigned int wlut_regval; - int buffer; /* 0 = Buffer A, 1 = Buffer B */ - int depth; /* 8 or 32 bpp */ - int greyscale; /* 1 = greyscale, 0 = color */ - int linear; /* 1 = linear, 0 = non-linear */ - int direct; /* 1 = 24bpp directcolor */ - int channel; /* 0 = X, 1 = R, 2 = G, 3 = B */ - int palette; /* Only PAC2 has multiple CLUTs */ -} ffb_wid_info_t; - -#define FFB_MAX_PWIDS 64 -typedef struct { - int num_wids; - int wid_shift; /* To get X channel value */ - ffb_wid_info_t wid_pool[FFB_MAX_PWIDS]; -} ffb_wid_pool_t; - -typedef struct ffb_dac_info { - unsigned int flags; -#define FFB_DAC_PAC1 0x00000001 /* Pacifica1 DAC, BT9068 */ -#define FFB_DAC_PAC2 0x00000002 /* Pacifica2 DAC, BT498 */ -#define FFB_DAC_ICURCTL 0x00000004 /* Inverted CUR_CTRL bits */ - - unsigned int kernel_wid; - - /* These registers need to be modified when changing DAC - * timing state, so at init time we capture their values. - */ - unsigned int ffbcfg0; - unsigned int ffbcfg2; - unsigned int ffb_passin_ctrl; /* FFB2+/AFB only */ - - ffb_dac_hwstate_t kern_dac_state; - ffb_dac_hwstate_t x_dac_state; - - ffb_wid_pool_t wid_table; -} ffb_dac_info_t; - -#endif /* _FFB_DAC_H */ diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/ffb/server/ffb_drishare.h b/nx-X11/extras/Mesa/src/mesa/drivers/dri/ffb/server/ffb_drishare.h deleted file mode 100644 index baf2f0d0a..000000000 --- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/ffb/server/ffb_drishare.h +++ /dev/null @@ -1,48 +0,0 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/sunffb/ffb_drishare.h,v 1.2 2000/06/21 00:47:37 dawes Exp $ */ - -#ifndef _FFB_DRISHARE_H -#define _FFB_DRISHARE_H - -typedef struct ffb_dri_state { - int flags; -#define FFB_DRI_FFB2 0x00000001 -#define FFB_DRI_FFB2PLUS 0x00000002 -#define FFB_DRI_PAC1 0x00000004 -#define FFB_DRI_PAC2 0x00000008 - - /* Indexed by DRI drawable id. */ -#define FFB_DRI_NWIDS 64 - unsigned int wid_table[FFB_DRI_NWIDS]; -} ffb_dri_state_t; - -#define FFB_DRISHARE(SAREA) \ - ((ffb_dri_state_t *) (((char *)(SAREA)) + sizeof(drm_sarea_t))) - -typedef struct { - drm_handle_t hFbcRegs; - drmSize sFbcRegs; - - drm_handle_t hDacRegs; - drmSize sDacRegs; - - drm_handle_t hSfb8r; - drmSize sSfb8r; - - drm_handle_t hSfb32; - drmSize sSfb32; - - drm_handle_t hSfb64; - drmSize sSfb64; - - /* Fastfill/Pagefill parameters. */ - unsigned char disable_pagefill; - int fastfill_small_area; - int pagefill_small_area; - int fastfill_height; - int fastfill_width; - int pagefill_height; - int pagefill_width; - short Pf_AlignTab[0x800]; -} FFBDRIRec, *FFBDRIPtr; - -#endif /* !(_FFB_DRISHARE_H) */ diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/ffb/server/ffb_regs.h b/nx-X11/extras/Mesa/src/mesa/drivers/dri/ffb/server/ffb_regs.h deleted file mode 100644 index 7f383d38d..000000000 --- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/ffb/server/ffb_regs.h +++ /dev/null @@ -1,509 +0,0 @@ -/* - * Acceleration for the Creator and Creator3D framebuffer - register layout. - * - * Copyright (C) 1998,1999,2000 Jakub Jelinek (jakub@redhat.com) - * Copyright (C) 1998 Michal Rehacek (majkl@iname.com) - * Copyright (C) 1999 David S. Miller (davem@redhat.com) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * JAKUB JELINEK, MICHAL REHACEK, OR DAVID MILLER BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE - * USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/sunffb/ffb_regs.h,v 1.1 2000/05/18 23:21:37 dawes Exp $ */ - -#ifndef FFBREGS_H -#define FFBREGS_H - -/* Auxilliary clips. */ -typedef struct { - volatile unsigned int min; - volatile unsigned int max; -} ffb_auxclip, *ffb_auxclipPtr; - -/* FFB register set. */ -typedef struct _ffb_fbc { - /* Next vertex registers, on the right we list which drawops - * use said register and the logical name the register has in - * that context. - */ /* DESCRIPTION DRAWOP(NAME) */ -/*0x00*/unsigned int pad1[3]; /* Reserved */ -/*0x0c*/volatile unsigned int alpha; /* ALPHA Transparency */ -/*0x10*/volatile unsigned int red; /* RED */ -/*0x14*/volatile unsigned int green; /* GREEN */ -/*0x18*/volatile unsigned int blue; /* BLUE */ -/*0x1c*/volatile unsigned int z; /* DEPTH */ -/*0x20*/volatile unsigned int y; /* Y triangle(DOYF) */ - /* aadot(DYF) */ - /* ddline(DYF) */ - /* aaline(DYF) */ -/*0x24*/volatile unsigned int x; /* X triangle(DOXF) */ - /* aadot(DXF) */ - /* ddline(DXF) */ - /* aaline(DXF) */ -/*0x28*/unsigned int pad2[2]; /* Reserved */ -/*0x30*/volatile unsigned int ryf; /* Y (alias to DOYF) ddline(RYF) */ - /* aaline(RYF) */ - /* triangle(RYF) */ -/*0x34*/volatile unsigned int rxf; /* X ddline(RXF) */ - /* aaline(RXF) */ - /* triangle(RXF) */ -/*0x38*/unsigned int pad3[2]; /* Reserved */ -/*0x40*/volatile unsigned int dmyf; /* Y (alias to DOYF) triangle(DMYF) */ -/*0x44*/volatile unsigned int dmxf; /* X triangle(DMXF) */ -/*0x48*/unsigned int pad4[2]; /* Reserved */ -/*0x50*/volatile unsigned int ebyi; /* Y (alias to RYI) polygon(EBYI) */ -/*0x54*/volatile unsigned int ebxi; /* X polygon(EBXI) */ -/*0x58*/unsigned int pad5[2]; /* Reserved */ -/*0x60*/volatile unsigned int by; /* Y brline(RYI) */ - /* fastfill(OP) */ - /* polygon(YI) */ - /* rectangle(YI) */ - /* bcopy(SRCY) */ - /* vscroll(SRCY) */ -/*0x64*/volatile unsigned int bx; /* X brline(RXI) */ - /* polygon(XI) */ - /* rectangle(XI) */ - /* bcopy(SRCX) */ - /* vscroll(SRCX) */ - /* fastfill(GO) */ -/*0x68*/volatile unsigned int dy; /* destination Y fastfill(DSTY) */ - /* bcopy(DSRY) */ - /* vscroll(DSRY) */ -/*0x6c*/volatile unsigned int dx; /* destination X fastfill(DSTX) */ - /* bcopy(DSTX) */ - /* vscroll(DSTX) */ -/*0x70*/volatile unsigned int bh; /* Y (alias to RYI) brline(DYI) */ - /* dot(DYI) */ - /* polygon(ETYI) */ - /* Height fastfill(H) */ - /* bcopy(H) */ - /* vscroll(H) */ - /* Y count fastfill(NY) */ -/*0x74*/volatile unsigned int bw; /* X dot(DXI) */ - /* brline(DXI) */ - /* polygon(ETXI) */ - /* fastfill(W) */ - /* bcopy(W) */ - /* vscroll(W) */ - /* fastfill(NX) */ -/*0x78*/unsigned int pad6[2]; /* Reserved */ -/*0x80*/unsigned int pad7[32]; /* Reserved */ - - /* Setup Unit's vertex state register */ -/*100*/ volatile unsigned int suvtx; -/*104*/ unsigned int pad8[63]; /* Reserved */ - - /* Frame Buffer Control Registers */ -/*200*/ volatile unsigned int ppc; /* Pixel Processor Control */ -/*204*/ volatile unsigned int wid; /* Current WID */ -/*208*/ volatile unsigned int fg; /* FG data */ -/*20c*/ volatile unsigned int bg; /* BG data */ -/*210*/ volatile unsigned int consty; /* Constant Y */ -/*214*/ volatile unsigned int constz; /* Constant Z */ -/*218*/ volatile unsigned int xclip; /* X Clip */ -/*21c*/ volatile unsigned int dcss; /* Depth Cue Scale Slope */ -/*220*/ volatile unsigned int vclipmin; /* Viewclip XY Min Bounds */ -/*224*/ volatile unsigned int vclipmax; /* Viewclip XY Max Bounds */ -/*228*/ volatile unsigned int vclipzmin; /* Viewclip Z Min Bounds */ -/*22c*/ volatile unsigned int vclipzmax; /* Viewclip Z Max Bounds */ -/*230*/ volatile unsigned int dcsf; /* Depth Cue Scale Front Bound */ -/*234*/ volatile unsigned int dcsb; /* Depth Cue Scale Back Bound */ -/*238*/ volatile unsigned int dczf; /* Depth Cue Z Front */ -/*23c*/ volatile unsigned int dczb; /* Depth Cue Z Back */ -/*240*/ unsigned int pad9; /* Reserved */ -/*244*/ volatile unsigned int blendc; /* Alpha Blend Control */ -/*248*/ volatile unsigned int blendc1; /* Alpha Blend Color 1 */ -/*24c*/ volatile unsigned int blendc2; /* Alpha Blend Color 2 */ -/*250*/ volatile unsigned int fbramitc; /* FB RAM Interleave Test Control */ -/*254*/ volatile unsigned int fbc; /* Frame Buffer Control */ -/*258*/ volatile unsigned int rop; /* Raster OPeration */ -/*25c*/ volatile unsigned int cmp; /* Frame Buffer Compare */ -/*260*/ volatile unsigned int matchab; /* Buffer AB Match Mask */ -/*264*/ volatile unsigned int matchc; /* Buffer C(YZ) Match Mask */ -/*268*/ volatile unsigned int magnab; /* Buffer AB Magnitude Mask */ -/*26c*/ volatile unsigned int magnc; /* Buffer C(YZ) Magnitude Mask */ -/*270*/ volatile unsigned int fbcfg0; /* Frame Buffer Config 0 */ -/*274*/ volatile unsigned int fbcfg1; /* Frame Buffer Config 1 */ -/*278*/ volatile unsigned int fbcfg2; /* Frame Buffer Config 2 */ -/*27c*/ volatile unsigned int fbcfg3; /* Frame Buffer Config 3 */ -/*280*/ volatile unsigned int ppcfg; /* Pixel Processor Config */ -/*284*/ volatile unsigned int pick; /* Picking Control */ -/*288*/ volatile unsigned int fillmode; /* FillMode */ -/*28c*/ volatile unsigned int fbramwac; /* FB RAM Write Address Control */ -/*290*/ volatile unsigned int pmask; /* RGB PlaneMask */ -/*294*/ volatile unsigned int xpmask; /* X PlaneMask */ -/*298*/ volatile unsigned int ypmask; /* Y PlaneMask */ -/*29c*/ volatile unsigned int zpmask; /* Z PlaneMask */ -/*2a0*/ ffb_auxclip auxclip[4]; /* Auxilliary Viewport Clip */ - - /* New 3dRAM III support regs */ -/*2c0*/ volatile unsigned int rawblend2; -/*2c4*/ volatile unsigned int rawpreblend; -/*2c8*/ volatile unsigned int rawstencil; -/*2cc*/ volatile unsigned int rawstencilctl; -/*2d0*/ volatile unsigned int threedram1; -/*2d4*/ volatile unsigned int threedram2; -/*2d8*/ volatile unsigned int passin; -/*2dc*/ volatile unsigned int rawclrdepth; -/*2e0*/ volatile unsigned int rawpmask; -/*2e4*/ volatile unsigned int rawcsrc; -/*2e8*/ volatile unsigned int rawmatch; -/*2ec*/ volatile unsigned int rawmagn; -/*2f0*/ volatile unsigned int rawropblend; -/*2f4*/ volatile unsigned int rawcmp; -/*2f8*/ volatile unsigned int rawwac; -/*2fc*/ volatile unsigned int fbramid; - -/*300*/ volatile unsigned int drawop; /* Draw OPeration */ -/*304*/ unsigned int pad10[2]; /* Reserved */ -/*30c*/ volatile unsigned int lpat; /* Line Pattern control */ -/*310*/ unsigned int pad11; /* Reserved */ -/*314*/ volatile unsigned int fontxy; /* XY Font coordinate */ -/*318*/ volatile unsigned int fontw; /* Font Width */ -/*31c*/ volatile unsigned int fontinc; /* Font Increment */ -/*320*/ volatile unsigned int font; /* Font bits */ -/*324*/ unsigned int pad12[3]; /* Reserved */ -/*330*/ volatile unsigned int blend2; -/*334*/ volatile unsigned int preblend; -/*338*/ volatile unsigned int stencil; -/*33c*/ volatile unsigned int stencilctl; - -/*340*/ unsigned int pad13[4]; /* Reserved */ -/*350*/ volatile unsigned int dcss1; /* Depth Cue Scale Slope 1 */ -/*354*/ volatile unsigned int dcss2; /* Depth Cue Scale Slope 2 */ -/*358*/ volatile unsigned int dcss3; /* Depth Cue Scale Slope 3 */ -/*35c*/ volatile unsigned int widpmask; -/*360*/ volatile unsigned int dcs2; -/*364*/ volatile unsigned int dcs3; -/*368*/ volatile unsigned int dcs4; -/*36c*/ unsigned int pad14; /* Reserved */ -/*370*/ volatile unsigned int dcd2; -/*374*/ volatile unsigned int dcd3; -/*378*/ volatile unsigned int dcd4; -/*37c*/ unsigned int pad15; /* Reserved */ -/*380*/ volatile unsigned int pattern[32]; /* area Pattern */ -/*400*/ unsigned int pad16[8]; /* Reserved */ -/*420*/ volatile unsigned int reset; /* chip RESET */ -/*424*/ unsigned int pad17[247]; /* Reserved */ -/*800*/ volatile unsigned int devid; /* Device ID */ -/*804*/ unsigned int pad18[63]; /* Reserved */ -/*900*/ volatile unsigned int ucsr; /* User Control & Status Register */ -/*904*/ unsigned int pad19[31]; /* Reserved */ -/*980*/ volatile unsigned int mer; /* Mode Enable Register */ -/*984*/ unsigned int pad20[1439]; /* Reserved */ -} ffb_fbc, *ffb_fbcPtr; - -/* Draw operations */ -#define FFB_DRAWOP_DOT 0x00 -#define FFB_DRAWOP_AADOT 0x01 -#define FFB_DRAWOP_BRLINECAP 0x02 -#define FFB_DRAWOP_BRLINEOPEN 0x03 -#define FFB_DRAWOP_DDLINE 0x04 -#define FFB_DRAWOP_AALINE 0x05 -#define FFB_DRAWOP_TRIANGLE 0x06 -#define FFB_DRAWOP_POLYGON 0x07 -#define FFB_DRAWOP_RECTANGLE 0x08 -#define FFB_DRAWOP_FASTFILL 0x09 -#define FFB_DRAWOP_BCOPY 0x0a /* Not implemented in any FFB, VIS is faster */ -#define FFB_DRAWOP_VSCROLL 0x0b /* Up to 12x faster than BCOPY, 3-4x faster than VIS */ - -/* FastFill operation codes. */ -#define FFB_FASTFILL_PAGE 0x01 -#define FFB_FASTFILL_BLOCK 0x02 -#define FFB_FASTFILL_COLOR_BLK 0x03 -#define FFB_FASTFILL_BLOCK_X 0x04 - -/* Spanfill Unit Line Pattern */ -#define FFB_LPAT_SCALEPTR 0xf0000000 -#define FFB_LPAT_SCALEPTR_SHIFT 28 -#define FFB_LPAT_PATPTR 0x0f000000 -#define FFB_LPAT_PATPTR_SHIFT 24 -#define FFB_LPAT_SCALEVAL 0x00f00000 -#define FFB_LPAT_SCALEVAL_SHIFT 20 -#define FFB_LPAT_PATLEN 0x000f0000 -#define FFB_LPAT_PATLEN_SHIFT 16 -#define FFB_LPAT_PATTERN 0x0000ffff -#define FFB_LPAT_PATTERN_SHIFT 0 - -/* Pixel processor control */ -/* Force WID */ -#define FFB_PPC_FW_DISABLE 0x800000 -#define FFB_PPC_FW_ENABLE 0xc00000 -#define FFB_PPC_FW_MASK 0xc00000 -/* Auxiliary clip */ -#define FFB_PPC_ACE_DISABLE 0x040000 -#define FFB_PPC_ACE_AUX_SUB 0x080000 -#define FFB_PPC_ACE_AUX_ADD 0x0c0000 -#define FFB_PPC_ACE_MASK 0x0c0000 -/* Depth cue */ -#define FFB_PPC_DCE_DISABLE 0x020000 -#define FFB_PPC_DCE_ENABLE 0x030000 -#define FFB_PPC_DCE_MASK 0x030000 -/* Alpha blend */ -#define FFB_PPC_ABE_DISABLE 0x008000 -#define FFB_PPC_ABE_ENABLE 0x00c000 -#define FFB_PPC_ABE_MASK 0x00c000 -/* View clip */ -#define FFB_PPC_VCE_DISABLE 0x001000 -#define FFB_PPC_VCE_2D 0x002000 -#define FFB_PPC_VCE_3D 0x003000 -#define FFB_PPC_VCE_MASK 0x003000 -/* Area pattern */ -#define FFB_PPC_APE_DISABLE 0x000800 -#define FFB_PPC_APE_ENABLE 0x000c00 -#define FFB_PPC_APE_MASK 0x000c00 -/* Transparent background */ -#define FFB_PPC_TBE_OPAQUE 0x000200 -#define FFB_PPC_TBE_TRANSPARENT 0x000300 -#define FFB_PPC_TBE_MASK 0x000300 -/* Z source */ -#define FFB_PPC_ZS_VAR 0x000080 -#define FFB_PPC_ZS_CONST 0x0000c0 -#define FFB_PPC_ZS_MASK 0x0000c0 -/* Y source */ -#define FFB_PPC_YS_VAR 0x000020 -#define FFB_PPC_YS_CONST 0x000030 -#define FFB_PPC_YS_MASK 0x000030 -/* X source */ -#define FFB_PPC_XS_WID 0x000004 -#define FFB_PPC_XS_VAR 0x000008 -#define FFB_PPC_XS_CONST 0x00000c -#define FFB_PPC_XS_MASK 0x00000c -/* Color (BGR) source */ -#define FFB_PPC_CS_VAR 0x000002 -#define FFB_PPC_CS_CONST 0x000003 -#define FFB_PPC_CS_MASK 0x000003 - -/* X Clip */ -#define FFB_XCLIP_XREF 0x000000ff -#define FFB_XCLIP_TEST_MASK 0x00070000 -#define FFB_XCLIP_TEST_ALWAYS 0x00000000 -#define FFB_XCLIP_TEST_GT 0x00010000 -#define FFB_XCLIP_TEST_EQ 0x00020000 -#define FFB_XCLIP_TEST_GE 0x00030000 -#define FFB_XCLIP_TEST_NEVER 0x00040000 -#define FFB_XCLIP_TEST_LE 0x00050000 -#define FFB_XCLIP_TEST_NE 0x00060000 -#define FFB_XCLIP_TEST_LT 0x00070000 - -/* FB Control register */ -/* Write buffer dest */ -#define FFB_FBC_WB_A 0x20000000 -#define FFB_FBC_WB_B 0x40000000 -#define FFB_FBC_WB_AB 0x60000000 -#define FFB_FBC_WB_C 0x80000000 -#define FFB_FBC_WB_AC 0xa0000000 -#define FFB_FBC_WB_BC 0xc0000000 -#define FFB_FBC_WB_ABC 0xe0000000 -#define FFB_FBC_WB_MASK 0xe0000000 -/* Write enable */ -#define FFB_FBC_WE_FORCEOFF 0x00100000 -#define FFB_FBC_WE_FORCEON 0x00200000 -#define FFB_FBC_WE_USE_WMASK 0x00300000 -#define FFB_FBC_WE_MASK 0x00300000 -/* Write group mode */ -#define FFB_FBC_WM_RSVD 0x00040000 -#define FFB_FBC_WM_COMBINED 0x00080000 -#define FFB_FBC_WM_SEPARATE 0x000c0000 -#define FFB_FBC_WM_MASK 0x000c0000 -/* Read buffer src */ -#define FFB_FBC_RB_A 0x00004000 -#define FFB_FBC_RB_B 0x00008000 -#define FFB_FBC_RB_C 0x0000c000 -#define FFB_FBC_RB_MASK 0x0000c000 -/* Stereo buf dest */ -#define FFB_FBC_SB_LEFT 0x00001000 -#define FFB_FBC_SB_RIGHT 0x00002000 -#define FFB_FBC_SB_BOTH 0x00003000 -#define FFB_FBC_SB_MASK 0x00003000 -/* Z plane group enable */ -#define FFB_FBC_ZE_OFF 0x00000400 -#define FFB_FBC_ZE_ON 0x00000800 -#define FFB_FBC_ZE_MASK 0x00000c00 -/* Y plane group enable */ -#define FFB_FBC_YE_OFF 0x00000100 -#define FFB_FBC_YE_ON 0x00000200 -#define FFB_FBC_YE_MASK 0x00000300 -/* X plane group enable */ -#define FFB_FBC_XE_OFF 0x00000040 -#define FFB_FBC_XE_ON 0x00000080 -#define FFB_FBC_XE_MASK 0x000000c0 -/* B plane group enable */ -#define FFB_FBC_BE_OFF 0x00000010 -#define FFB_FBC_BE_ON 0x00000020 -#define FFB_FBC_BE_MASK 0x00000030 -/* G plane group enable */ -#define FFB_FBC_GE_OFF 0x00000004 -#define FFB_FBC_GE_ON 0x00000008 -#define FFB_FBC_GE_MASK 0x0000000c -/* R plane group enable */ -#define FFB_FBC_RE_OFF 0x00000001 -#define FFB_FBC_RE_ON 0x00000002 -#define FFB_FBC_RE_MASK 0x00000003 -/* Combined */ -#define FFB_FBC_RGBE_OFF 0x00000015 -#define FFB_FBC_RGBE_ON 0x0000002a -#define FFB_FBC_RGBE_MASK 0x0000003f - -/* Raster OP */ -#define FFB_ROP_YZ_MASK 0x008f0000 -#define FFB_ROP_X_MASK 0x00008f00 -#define FFB_ROP_RGB_MASK 0x0000008f - -/* Now the rops themselves which get shifted into the - * above fields. - */ -#define FFB_ROP_EDIT_BIT 0x80 -#define FFB_ROP_ZERO 0x80 -#define FFB_ROP_NEW_AND_OLD 0x81 -#define FFB_ROP_NEW_AND_NOLD 0x82 -#define FFB_ROP_NEW 0x83 -#define FFB_ROP_NNEW_AND_OLD 0x84 -#define FFB_ROP_OLD 0x85 -#define FFB_ROP_NEW_XOR_OLD 0x86 -#define FFB_ROP_NEW_OR_OLD 0x87 -#define FFB_ROP_NNEW_AND_NOLD 0x88 -#define FFB_ROP_NNEW_XOR_NOLD 0x89 -#define FFB_ROP_NOLD 0x8a -#define FFB_ROP_NEW_OR_NOLD 0x8b -#define FFB_ROP_NNEW 0x8c -#define FFB_ROP_NNEW_OR_OLD 0x8d -#define FFB_ROP_NNEW_OR_NOLD 0x8e -#define FFB_ROP_ONES 0x8f - -/* FB Compare */ -#define FFB_CMP_MATCHC_MASK 0x8f000000 -#define FFB_CMP_MAGNC_MASK 0x00870000 -#define FFB_CMP_MATCHAB_MASK 0x0000ff00 -#define FFB_CMP_MAGNAB_MASK 0x000000ff - -/* Compare Match codes */ -#define FFB_CMP_MATCH_EDIT_BIT 0x80 -#define FFB_CMP_MATCH_ALWAYS 0x80 -#define FFB_CMP_MATCH_NEVER 0x81 -#define FFB_CMP_MATCH_EQ 0x82 -#define FFB_CMP_MATCH_NE 0x83 -#define FFB_CMP_MATCH_A_ALWAYS 0xc0 -#define FFB_CMP_MATCH_B_ALWAYS 0xa0 - -/* Compare Magnitude codes */ -#define FFB_CMP_MAGN_EDIT_BIT 0x80 -#define FFB_CMP_MAGN_ALWAYS 0x80 -#define FFB_CMP_MAGN_GT 0x81 -#define FFB_CMP_MAGN_EQ 0x82 -#define FFB_CMP_MAGN_GE 0x83 -#define FFB_CMP_MAGN_NEVER 0x84 -#define FFB_CMP_MAGN_LE 0x85 -#define FFB_CMP_MAGN_NE 0x86 -#define FFB_CMP_MAGN_LT 0x87 -#define FFB_CMP_MAGN_A_ALWAYS 0xc0 -#define FFB_CMP_MAGN_B_ALWAYS 0xa0 - -/* User Control and Status */ -#define FFB_UCSR_FIFO_MASK 0x00000fff -#define FFB_UCSR_PICK_NO_HIT 0x00020000 -#define FFB_UCSR_PICK_HIT 0x00030000 -#define FFB_UCSR_PICK_DISABLE 0x00080000 -#define FFB_UCSR_PICK_ENABLE 0x000c0000 -#define FFB_UCSR_FB_BUSY 0x01000000 -#define FFB_UCSR_RP_BUSY 0x02000000 -#define FFB_UCSR_ALL_BUSY (FFB_UCSR_RP_BUSY|FFB_UCSR_FB_BUSY) -#define FFB_UCSR_READ_ERR 0x40000000 -#define FFB_UCSR_FIFO_OVFL 0x80000000 -#define FFB_UCSR_ALL_ERRORS (FFB_UCSR_READ_ERR|FFB_UCSR_FIFO_OVFL) - -/* Mode Enable Register */ -#define FFB_MER_EIRA 0x00000080 /* Enable read-ahead, increasing */ -#define FFB_MER_EDRA 0x000000c0 /* Enable read-ahead, decreasing */ -#define FFB_MER_DRA 0x00000040 /* No read-ahead */ - -/* FBram Config 0 */ -#define FFB_FBCFG0_RFTIME 0xff800000 -#define FFB_FBCFG0_XMAX 0x007c0000 -#define FFB_FBCFG0_YMAX 0x0003ffc0 -#define FFB_FBCFG0_RES_MASK 0x00000030 -#define FFB_FBCFG0_RES_HIGH 0x00000030 /* 1920x1360 */ -#define FFB_FBCFG0_RES_STD 0x00000020 /* 1280x1024 */ -#define FFB_FBCFG0_RES_STEREO 0x00000010 /* 960x580 */ -#define FFB_FBCFG0_RES_PRTRAIT 0x00000000 /* 1280x2048 */ -#define FFB_FBCFG0_ITRLACE 0x00000000 -#define FFB_FBCFG0_SEQUENTIAL 0x00000008 -#define FFB_FBCFG0_DRENA 0x00000004 -#define FFB_FBCFG0_BPMODE 0x00000002 -#define FFB_FBCFG0_RFRSH_RST 0x00000001 - -typedef struct _ffb_dac { - volatile unsigned int cfg; - volatile unsigned int cfgdata; - volatile unsigned int cur; - volatile unsigned int curdata; -} ffb_dac, *ffb_dacPtr; - -/* Writing 2 32-bit registers at a time using 64-bit stores. -DaveM */ -#if defined(__GNUC__) && defined(USE_VIS) -/* 64-bit register writing support. - * Note: "lo" means "low address". - */ -#define FFB_WRITE64_COMMON(__regp, __lo32, __hi32, REG0, REG1) \ -do { __extension__ register unsigned int __r0 __asm__(""#REG0); \ - __extension__ register unsigned int __r1 __asm__(""#REG1); \ - __r0 = (__lo32); \ - __r1 = (__hi32); \ - __asm__ __volatile__ ("sllx\t%0, 32, %%g1\n\t" \ - "srl\t%1, 0, %1\n\t" \ - "or\t%%g1, %1, %%g1\n\t" \ - "stx\t%%g1, %2" \ - : : "r" (__r0), "r" (__r1), "m" (*(__regp)) : "g1"); \ -} while(0) - -#define FFB_WRITE64P(__regp, __srcp) \ -do { __asm__ __volatile__ ("ldx\t%0, %%g2;" \ - "stx\t%%g2, %1" \ - : : "m" (*(__srcp)), "m" (*(__regp)) \ - : "g2"); \ -} while(0) - -#define FFB_WRITE64(__regp, __lo32, __hi32) \ - FFB_WRITE64_COMMON(__regp, __lo32, __hi32, g2, g3) -#define FFB_WRITE64_2(__regp, __lo32, __hi32) \ - FFB_WRITE64_COMMON(__regp, __lo32, __hi32, g4, g5) -#define FFB_WRITE64_3(__regp, __lo32, __hi32) \ - FFB_WRITE64_COMMON(__regp, __lo32, __hi32, o4, o5) - -#else /* Do not use 64-bit writes. */ - -#define FFB_WRITE64(__regp, __lo32, __hi32) \ -do { volatile unsigned int *__p = (__regp); \ - *__p = (__lo32); \ - *(__p + 1) = (__hi32); \ -} while(0) - -#define FFB_WRITE64P(__regp, __srcp) \ -do { volatile unsigned int *__p = (__regp); \ - unsigned int *__q = (__srcp); \ - *__p = *__q; \ - *(__p + 1) = *(__q + 1); \ -} while(0) - -#define FFB_WRITE64_2(__regp, __lo32, __hi32) \ - FFB_WRITE64(__regp, __lo32, __hi32) -#define FFB_WRITE64_3(__regp, __lo32, __hi32) \ - FFB_WRITE64(__regp, __lo32, __hi32) -#endif - -#endif /* FFBREGS_H */ |