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-rw-r--r--nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/Makefile42
-rw-r--r--nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_compat.c302
-rw-r--r--nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_context.c630
-rw-r--r--nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_context.h868
-rw-r--r--nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_ioctl.c1283
-rw-r--r--nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_ioctl.h217
-rw-r--r--nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_lighting.c682
-rw-r--r--nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_lock.c135
-rw-r--r--nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_lock.h108
-rw-r--r--nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_maos.c12
-rw-r--r--nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_maos.h44
-rw-r--r--nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c604
-rw-r--r--nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_maos_vbtmp.h284
-rw-r--r--nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_maos_verts.c367
-rw-r--r--nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_sanity.c1070
-rw-r--r--nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_sanity.h8
-rw-r--r--nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_screen.c656
-rw-r--r--nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_screen.h103
-rw-r--r--nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_span.c346
-rw-r--r--nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_span.h46
-rw-r--r--nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_state.c2295
-rw-r--r--nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_state.h74
-rw-r--r--nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_state_init.c572
-rw-r--r--nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_swtcl.c983
-rw-r--r--nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_swtcl.h69
-rw-r--r--nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_tcl.c489
-rw-r--r--nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_tcl.h66
-rw-r--r--nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_tex.c866
-rw-r--r--nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_tex.h50
-rw-r--r--nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_texmem.c404
-rw-r--r--nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_texstate.c1171
-rw-r--r--nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_vtxfmt.c1093
-rw-r--r--nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_vtxfmt.h120
-rw-r--r--nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_vtxfmt_c.c922
-rw-r--r--nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_vtxfmt_sse.c232
-rw-r--r--nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_vtxfmt_x86.c437
-rw-r--r--nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_vtxtmp_x86.S494
-rw-r--r--nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/server/radeon.h202
-rw-r--r--nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/server/radeon_dri.c1336
-rw-r--r--nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/server/radeon_dri.h116
-rw-r--r--nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/server/radeon_egl.c978
-rw-r--r--nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/server/radeon_macros.h129
-rw-r--r--nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/server/radeon_reg.h2142
43 files changed, 0 insertions, 23047 deletions
diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/Makefile b/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/Makefile
deleted file mode 100644
index b0ef17299..000000000
--- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/Makefile
+++ /dev/null
@@ -1,42 +0,0 @@
-# src/mesa/drivers/dri/radeon/Makefile
-# Note, this Makefile requires GNU make
-
-TOP = ../../../../..
-include $(TOP)/configs/current
-
-LIBNAME = radeon_dri.so
-
-MINIGLX_SOURCES = server/radeon_dri.c
-
-DRIVER_SOURCES = \
- radeon_context.c \
- radeon_ioctl.c \
- radeon_lock.c \
- radeon_screen.c \
- radeon_state.c \
- radeon_state_init.c \
- radeon_tex.c \
- radeon_texmem.c \
- radeon_texstate.c \
- radeon_tcl.c \
- radeon_swtcl.c \
- radeon_span.c \
- radeon_maos.c \
- radeon_sanity.c \
- radeon_compat.c \
- radeon_vtxfmt.c \
- radeon_vtxfmt_c.c \
- radeon_vtxfmt_sse.c \
- radeon_vtxfmt_x86.c
-
-C_SOURCES = \
- $(COMMON_SOURCES) \
- $(DRIVER_SOURCES)
-
-
-X86_SOURCES = \
- radeon_vtxtmp_x86.S
-
-include ../Makefile.template
-
-symlinks:
diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_compat.c b/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_compat.c
deleted file mode 100644
index 1cbe3407b..000000000
--- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_compat.c
+++ /dev/null
@@ -1,302 +0,0 @@
-/* $XFree86$ */
-/**************************************************************************
-
-Copyright 2002 ATI Technologies Inc., Ontario, Canada, and
- Tungsten Graphics Inc., Austin, Texas.
-
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining a
-copy of this software and associated documentation files (the "Software"),
-to deal in the Software without restriction, including without limitation
-on the rights to use, copy, modify, merge, publish, distribute, sub
-license, and/or sell copies of the Software, and to permit persons to whom
-the Software is furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice (including the next
-paragraph) shall be included in all copies or substantial portions of the
-Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
-ATI, TUNGSTEN GRAPHICS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
-DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/*
- * Authors:
- * Keith Whitwell <keith@tungstengraphics.com>
- *
- */
-
-#include "glheader.h"
-#include "imports.h"
-
-#include "radeon_context.h"
-#include "radeon_state.h"
-#include "radeon_ioctl.h"
-
-
-static struct {
- int start;
- int len;
- const char *name;
-} packet[RADEON_MAX_STATE_PACKETS] = {
- { RADEON_PP_MISC,7,"RADEON_PP_MISC" },
- { RADEON_PP_CNTL,3,"RADEON_PP_CNTL" },
- { RADEON_RB3D_COLORPITCH,1,"RADEON_RB3D_COLORPITCH" },
- { RADEON_RE_LINE_PATTERN,2,"RADEON_RE_LINE_PATTERN" },
- { RADEON_SE_LINE_WIDTH,1,"RADEON_SE_LINE_WIDTH" },
- { RADEON_PP_LUM_MATRIX,1,"RADEON_PP_LUM_MATRIX" },
- { RADEON_PP_ROT_MATRIX_0,2,"RADEON_PP_ROT_MATRIX_0" },
- { RADEON_RB3D_STENCILREFMASK,3,"RADEON_RB3D_STENCILREFMASK" },
- { RADEON_SE_VPORT_XSCALE,6,"RADEON_SE_VPORT_XSCALE" },
- { RADEON_SE_CNTL,2,"RADEON_SE_CNTL" },
- { RADEON_SE_CNTL_STATUS,1,"RADEON_SE_CNTL_STATUS" },
- { RADEON_RE_MISC,1,"RADEON_RE_MISC" },
- { RADEON_PP_TXFILTER_0,6,"RADEON_PP_TXFILTER_0" },
- { RADEON_PP_BORDER_COLOR_0,1,"RADEON_PP_BORDER_COLOR_0" },
- { RADEON_PP_TXFILTER_1,6,"RADEON_PP_TXFILTER_1" },
- { RADEON_PP_BORDER_COLOR_1,1,"RADEON_PP_BORDER_COLOR_1" },
- { RADEON_PP_TXFILTER_2,6,"RADEON_PP_TXFILTER_2" },
- { RADEON_PP_BORDER_COLOR_2,1,"RADEON_PP_BORDER_COLOR_2" },
- { RADEON_SE_ZBIAS_FACTOR,2,"RADEON_SE_ZBIAS_FACTOR" },
- { RADEON_SE_TCL_OUTPUT_VTX_FMT,11,"RADEON_SE_TCL_OUTPUT_VTX_FMT" },
- { RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED,17,"RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED" },
-};
-
-
-static void radeonCompatEmitPacket( radeonContextPtr rmesa,
- struct radeon_state_atom *state )
-{
- drm_radeon_sarea_t *sarea = rmesa->sarea;
- drm_radeon_context_regs_t *ctx = &sarea->context_state;
- drm_radeon_texture_regs_t *tex0 = &sarea->tex_state[0];
- drm_radeon_texture_regs_t *tex1 = &sarea->tex_state[1];
- int i;
- int *buf = state->cmd;
-
- for ( i = 0 ; i < state->cmd_size ; ) {
- drm_radeon_cmd_header_t *header = (drm_radeon_cmd_header_t *)&buf[i++];
-
- if (RADEON_DEBUG & DEBUG_STATE)
- fprintf(stderr, "%s %d: %s\n", __FUNCTION__, header->packet.packet_id,
- packet[(int)header->packet.packet_id].name);
-
- switch (header->packet.packet_id) {
- case RADEON_EMIT_PP_MISC:
- ctx->pp_misc = buf[i++];
- ctx->pp_fog_color = buf[i++];
- ctx->re_solid_color = buf[i++];
- ctx->rb3d_blendcntl = buf[i++];
- ctx->rb3d_depthoffset = buf[i++];
- ctx->rb3d_depthpitch = buf[i++];
- ctx->rb3d_zstencilcntl = buf[i++];
- sarea->dirty |= RADEON_UPLOAD_CONTEXT;
- break;
- case RADEON_EMIT_PP_CNTL:
- ctx->pp_cntl = buf[i++];
- ctx->rb3d_cntl = buf[i++];
- ctx->rb3d_coloroffset = buf[i++];
- sarea->dirty |= RADEON_UPLOAD_CONTEXT;
- break;
- case RADEON_EMIT_RB3D_COLORPITCH:
- ctx->rb3d_colorpitch = buf[i++];
- sarea->dirty |= RADEON_UPLOAD_CONTEXT;
- break;
- case RADEON_EMIT_RE_LINE_PATTERN:
- ctx->re_line_pattern = buf[i++];
- ctx->re_line_state = buf[i++];
- sarea->dirty |= RADEON_UPLOAD_LINE;
- break;
- case RADEON_EMIT_SE_LINE_WIDTH:
- ctx->se_line_width = buf[i++];
- sarea->dirty |= RADEON_UPLOAD_LINE;
- break;
- case RADEON_EMIT_PP_LUM_MATRIX:
- ctx->pp_lum_matrix = buf[i++];
- sarea->dirty |= RADEON_UPLOAD_BUMPMAP;
- break;
- case RADEON_EMIT_PP_ROT_MATRIX_0:
- ctx->pp_rot_matrix_0 = buf[i++];
- ctx->pp_rot_matrix_1 = buf[i++];
- sarea->dirty |= RADEON_UPLOAD_BUMPMAP;
- break;
- case RADEON_EMIT_RB3D_STENCILREFMASK:
- ctx->rb3d_stencilrefmask = buf[i++];
- ctx->rb3d_ropcntl = buf[i++];
- ctx->rb3d_planemask = buf[i++];
- sarea->dirty |= RADEON_UPLOAD_MASKS;
- break;
- case RADEON_EMIT_SE_VPORT_XSCALE:
- ctx->se_vport_xscale = buf[i++];
- ctx->se_vport_xoffset = buf[i++];
- ctx->se_vport_yscale = buf[i++];
- ctx->se_vport_yoffset = buf[i++];
- ctx->se_vport_zscale = buf[i++];
- ctx->se_vport_zoffset = buf[i++];
- sarea->dirty |= RADEON_UPLOAD_VIEWPORT;
- break;
- case RADEON_EMIT_SE_CNTL:
- ctx->se_cntl = buf[i++];
- ctx->se_coord_fmt = buf[i++];
- sarea->dirty |= RADEON_UPLOAD_CONTEXT | RADEON_UPLOAD_VERTFMT;
- break;
- case RADEON_EMIT_SE_CNTL_STATUS:
- ctx->se_cntl_status = buf[i++];
- sarea->dirty |= RADEON_UPLOAD_SETUP;
- break;
- case RADEON_EMIT_RE_MISC:
- ctx->re_misc = buf[i++];
- sarea->dirty |= RADEON_UPLOAD_MISC;
- break;
- case RADEON_EMIT_PP_TXFILTER_0:
- tex0->pp_txfilter = buf[i++];
- tex0->pp_txformat = buf[i++];
- tex0->pp_txoffset = buf[i++];
- tex0->pp_txcblend = buf[i++];
- tex0->pp_txablend = buf[i++];
- tex0->pp_tfactor = buf[i++];
- sarea->dirty |= RADEON_UPLOAD_TEX0;
- break;
- case RADEON_EMIT_PP_BORDER_COLOR_0:
- tex0->pp_border_color = buf[i++];
- sarea->dirty |= RADEON_UPLOAD_TEX0;
- break;
- case RADEON_EMIT_PP_TXFILTER_1:
- tex1->pp_txfilter = buf[i++];
- tex1->pp_txformat = buf[i++];
- tex1->pp_txoffset = buf[i++];
- tex1->pp_txcblend = buf[i++];
- tex1->pp_txablend = buf[i++];
- tex1->pp_tfactor = buf[i++];
- sarea->dirty |= RADEON_UPLOAD_TEX1;
- break;
- case RADEON_EMIT_PP_BORDER_COLOR_1:
- tex1->pp_border_color = buf[i++];
- sarea->dirty |= RADEON_UPLOAD_TEX1;
- break;
-
- case RADEON_EMIT_SE_ZBIAS_FACTOR:
- i++;
- i++;
- break;
-
- case RADEON_EMIT_PP_TXFILTER_2:
- case RADEON_EMIT_PP_BORDER_COLOR_2:
- case RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT:
- case RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED:
- default:
- /* These states aren't understood by radeon drm 1.1 */
- fprintf(stderr, "Tried to emit unsupported state\n");
- return;
- }
- }
-}
-
-
-
-static void radeonCompatEmitStateLocked( radeonContextPtr rmesa )
-{
- struct radeon_state_atom *atom;
-
- if (RADEON_DEBUG & (DEBUG_STATE|DEBUG_PRIMS))
- fprintf(stderr, "%s\n", __FUNCTION__);
-
- if (!rmesa->hw.is_dirty && !rmesa->hw.all_dirty)
- return;
-
- foreach(atom, &rmesa->hw.atomlist) {
- if (rmesa->hw.all_dirty)
- atom->dirty = GL_TRUE;
- if (atom->is_tcl)
- atom->dirty = GL_FALSE;
- if (atom->dirty)
- radeonCompatEmitPacket(rmesa, atom);
- }
-
- rmesa->hw.is_dirty = GL_FALSE;
- rmesa->hw.all_dirty = GL_FALSE;
-}
-
-
-static void radeonCompatEmitPrimitiveLocked( radeonContextPtr rmesa,
- GLuint hw_primitive,
- GLuint nverts,
- drm_clip_rect_t *pbox,
- GLuint nbox )
-{
- int i;
-
- for ( i = 0 ; i < nbox ; ) {
- int nr = MIN2( i + RADEON_NR_SAREA_CLIPRECTS, nbox );
- drm_clip_rect_t *b = rmesa->sarea->boxes;
- drm_radeon_vertex_t vtx;
-
- rmesa->sarea->dirty |= RADEON_UPLOAD_CLIPRECTS;
- rmesa->sarea->nbox = nr - i;
-
- for ( ; i < nr ; i++)
- *b++ = pbox[i];
-
- if (RADEON_DEBUG & DEBUG_IOCTL)
- fprintf(stderr,
- "RadeonFlushVertexBuffer: prim %x buf %d verts %d "
- "disc %d nbox %d\n",
- hw_primitive,
- rmesa->dma.current.buf->buf->idx,
- nverts,
- nr == nbox,
- rmesa->sarea->nbox );
-
- vtx.prim = hw_primitive;
- vtx.idx = rmesa->dma.current.buf->buf->idx;
- vtx.count = nverts;
- vtx.discard = (nr == nbox);
-
- drmCommandWrite( rmesa->dri.fd,
- DRM_RADEON_VERTEX,
- &vtx, sizeof(vtx));
- }
-}
-
-
-
-/* No 'start' for 1.1 vertices ioctl: only one vertex prim/buffer!
- */
-void radeonCompatEmitPrimitive( radeonContextPtr rmesa,
- GLuint vertex_format,
- GLuint hw_primitive,
- GLuint nrverts )
-{
- if (RADEON_DEBUG & DEBUG_IOCTL)
- fprintf(stderr, "%s\n", __FUNCTION__);
-
- LOCK_HARDWARE( rmesa );
-
- radeonCompatEmitStateLocked( rmesa );
- rmesa->sarea->vc_format = vertex_format;
-
- if (rmesa->state.scissor.enabled) {
- radeonCompatEmitPrimitiveLocked( rmesa,
- hw_primitive,
- nrverts,
- rmesa->state.scissor.pClipRects,
- rmesa->state.scissor.numClipRects );
- }
- else {
- radeonCompatEmitPrimitiveLocked( rmesa,
- hw_primitive,
- nrverts,
- rmesa->pClipRects,
- rmesa->numClipRects );
- }
-
-
- UNLOCK_HARDWARE( rmesa );
-}
-
diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_context.c b/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_context.c
deleted file mode 100644
index c96f38e0a..000000000
--- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_context.c
+++ /dev/null
@@ -1,630 +0,0 @@
-/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_context.c,v 1.9 2003/09/24 02:43:12 dawes Exp $ */
-/**************************************************************************
-
-Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
- VA Linux Systems Inc., Fremont, California.
-
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/*
- * Authors:
- * Kevin E. Martin <martin@valinux.com>
- * Gareth Hughes <gareth@valinux.com>
- * Keith Whitwell <keith@tungstengraphics.com>
- */
-
-#include "glheader.h"
-#include "api_arrayelt.h"
-#include "context.h"
-#include "simple_list.h"
-#include "imports.h"
-#include "matrix.h"
-#include "extensions.h"
-#include "framebuffer.h"
-
-#include "swrast/swrast.h"
-#include "swrast_setup/swrast_setup.h"
-#include "array_cache/acache.h"
-
-#include "tnl/tnl.h"
-#include "tnl/t_pipeline.h"
-
-#include "drivers/common/driverfuncs.h"
-
-#include "radeon_context.h"
-#include "radeon_ioctl.h"
-#include "radeon_state.h"
-#include "radeon_span.h"
-#include "radeon_tex.h"
-#include "radeon_swtcl.h"
-#include "radeon_tcl.h"
-#include "radeon_vtxfmt.h"
-#include "radeon_maos.h"
-
-#define need_GL_ARB_multisample
-#define need_GL_ARB_texture_compression
-#define need_GL_EXT_blend_minmax
-#define need_GL_EXT_secondary_color
-#include "extension_helper.h"
-
-#define DRIVER_DATE "20050528"
-
-#include "vblank.h"
-#include "utils.h"
-#include "xmlpool.h" /* for symbolic values of enum-type options */
-#ifndef RADEON_DEBUG
-int RADEON_DEBUG = (0);
-#endif
-
-
-/* Return the width and height of the given buffer.
- */
-static void radeonGetBufferSize( GLframebuffer *buffer,
- GLuint *width, GLuint *height )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-
- LOCK_HARDWARE( rmesa );
- *width = rmesa->dri.drawable->w;
- *height = rmesa->dri.drawable->h;
- UNLOCK_HARDWARE( rmesa );
-}
-
-/* Return various strings for glGetString().
- */
-static const GLubyte *radeonGetString( GLcontext *ctx, GLenum name )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- static char buffer[128];
- unsigned offset;
- GLuint agp_mode = rmesa->radeonScreen->IsPCI ? 0 :
- rmesa->radeonScreen->AGPMode;
-
- switch ( name ) {
- case GL_VENDOR:
- return (GLubyte *)"Tungsten Graphics, Inc.";
-
- case GL_RENDERER:
- offset = driGetRendererString( buffer, "Radeon", DRIVER_DATE,
- agp_mode );
-
- sprintf( & buffer[ offset ], " %sTCL",
- !(rmesa->TclFallback & RADEON_TCL_FALLBACK_TCL_DISABLE)
- ? "" : "NO-" );
-
- return (GLubyte *)buffer;
-
- default:
- return NULL;
- }
-}
-
-
-/* Extension strings exported by the R100 driver.
- */
-const struct dri_extension card_extensions[] =
-{
- { "GL_ARB_multisample", GL_ARB_multisample_functions },
- { "GL_ARB_multitexture", NULL },
- { "GL_ARB_texture_border_clamp", NULL },
- { "GL_ARB_texture_compression", GL_ARB_texture_compression_functions },
- { "GL_ARB_texture_env_add", NULL },
- { "GL_ARB_texture_env_combine", NULL },
- { "GL_ARB_texture_env_crossbar", NULL },
- { "GL_ARB_texture_env_dot3", NULL },
- { "GL_ARB_texture_mirrored_repeat", NULL },
- { "GL_EXT_blend_logic_op", NULL },
- { "GL_EXT_blend_subtract", GL_EXT_blend_minmax_functions },
- { "GL_EXT_secondary_color", GL_EXT_secondary_color_functions },
- { "GL_EXT_stencil_wrap", NULL },
- { "GL_EXT_texture_edge_clamp", NULL },
- { "GL_EXT_texture_env_combine", NULL },
- { "GL_EXT_texture_env_dot3", NULL },
- { "GL_EXT_texture_filter_anisotropic", NULL },
- { "GL_EXT_texture_lod_bias", NULL },
- { "GL_EXT_texture_mirror_clamp", NULL },
- { "GL_ATI_texture_env_combine3", NULL },
- { "GL_ATI_texture_mirror_once", NULL },
- { "GL_MESA_ycbcr_texture", NULL },
- { "GL_NV_blend_square", NULL },
- { "GL_SGIS_generate_mipmap", NULL },
- { NULL, NULL }
-};
-
-extern const struct tnl_pipeline_stage _radeon_texrect_stage;
-extern const struct tnl_pipeline_stage _radeon_render_stage;
-extern const struct tnl_pipeline_stage _radeon_tcl_stage;
-
-static const struct tnl_pipeline_stage *radeon_pipeline[] = {
-
- /* Try and go straight to t&l
- */
- &_radeon_tcl_stage,
-
- /* Catch any t&l fallbacks
- */
- &_tnl_vertex_transform_stage,
- &_tnl_normal_transform_stage,
- &_tnl_lighting_stage,
- &_tnl_fog_coordinate_stage,
- &_tnl_texgen_stage,
- &_tnl_texture_transform_stage,
-
- /* Scale texture rectangle to 0..1.
- */
- &_radeon_texrect_stage,
-
- &_radeon_render_stage,
- &_tnl_render_stage, /* FALLBACK: */
- NULL,
-};
-
-
-
-/* Initialize the driver's misc functions.
- */
-static void radeonInitDriverFuncs( struct dd_function_table *functions )
-{
- functions->GetBufferSize = radeonGetBufferSize;
- functions->ResizeBuffers = _mesa_resize_framebuffer;
- functions->GetString = radeonGetString;
-}
-
-static const struct dri_debug_control debug_control[] =
-{
- { "fall", DEBUG_FALLBACKS },
- { "tex", DEBUG_TEXTURE },
- { "ioctl", DEBUG_IOCTL },
- { "prim", DEBUG_PRIMS },
- { "vert", DEBUG_VERTS },
- { "state", DEBUG_STATE },
- { "code", DEBUG_CODEGEN },
- { "vfmt", DEBUG_VFMT },
- { "vtxf", DEBUG_VFMT },
- { "verb", DEBUG_VERBOSE },
- { "dri", DEBUG_DRI },
- { "dma", DEBUG_DMA },
- { "san", DEBUG_SANITY },
- { "sync", DEBUG_SYNC },
- { NULL, 0 }
-};
-
-
-/* Create the device specific context.
- */
-GLboolean
-radeonCreateContext( const __GLcontextModes *glVisual,
- __DRIcontextPrivate *driContextPriv,
- void *sharedContextPrivate)
-{
- __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
- radeonScreenPtr screen = (radeonScreenPtr)(sPriv->private);
- struct dd_function_table functions;
- radeonContextPtr rmesa;
- GLcontext *ctx, *shareCtx;
- int i;
- int tcl_mode, fthrottle_mode;
-
- assert(glVisual);
- assert(driContextPriv);
- assert(screen);
-
- /* Allocate the Radeon context */
- rmesa = (radeonContextPtr) CALLOC( sizeof(*rmesa) );
- if ( !rmesa )
- return GL_FALSE;
-
- /* Parse configuration files.
- * Do this here so that initialMaxAnisotropy is set before we create
- * the default textures.
- */
- driParseConfigFiles (&rmesa->optionCache, &screen->optionCache,
- screen->driScreen->myNum, "radeon");
- rmesa->initialMaxAnisotropy = driQueryOptionf(&rmesa->optionCache,
- "def_max_anisotropy");
-
- if ( driQueryOptionb( &rmesa->optionCache, "hyperz" ) ) {
- if ( sPriv->drmMinor < 13 )
- fprintf( stderr, "DRM version 1.%d too old to support HyperZ, "
- "disabling.\n",sPriv->drmMinor );
- else
- rmesa->using_hyperz = GL_TRUE;
- }
-
- if ( sPriv->drmMinor >= 15 )
- rmesa->texmicrotile = GL_TRUE;
-
- /* Init default driver functions then plug in our Radeon-specific functions
- * (the texture functions are especially important)
- */
- _mesa_init_driver_functions( &functions );
- radeonInitDriverFuncs( &functions );
- radeonInitTextureFuncs( &functions );
-
- /* Allocate the Mesa context */
- if (sharedContextPrivate)
- shareCtx = ((radeonContextPtr) sharedContextPrivate)->glCtx;
- else
- shareCtx = NULL;
- rmesa->glCtx = _mesa_create_context(glVisual, shareCtx,
- &functions, (void *) rmesa);
- if (!rmesa->glCtx) {
- FREE(rmesa);
- return GL_FALSE;
- }
- driContextPriv->driverPrivate = rmesa;
-
- /* Init radeon context data */
- rmesa->dri.context = driContextPriv;
- rmesa->dri.screen = sPriv;
- rmesa->dri.drawable = NULL; /* Set by XMesaMakeCurrent */
- rmesa->dri.hwContext = driContextPriv->hHWContext;
- rmesa->dri.hwLock = &sPriv->pSAREA->lock;
- rmesa->dri.fd = sPriv->fd;
- rmesa->dri.drmMinor = sPriv->drmMinor;
-
- rmesa->radeonScreen = screen;
- rmesa->sarea = (drm_radeon_sarea_t *)((GLubyte *)sPriv->pSAREA +
- screen->sarea_priv_offset);
-
-
- rmesa->dma.buf0_address = rmesa->radeonScreen->buffers->list[0].address;
-
- (void) memset( rmesa->texture_heaps, 0, sizeof( rmesa->texture_heaps ) );
- make_empty_list( & rmesa->swapped );
-
- rmesa->nr_heaps = screen->numTexHeaps;
- for ( i = 0 ; i < rmesa->nr_heaps ; i++ ) {
- rmesa->texture_heaps[i] = driCreateTextureHeap( i, rmesa,
- screen->texSize[i],
- 12,
- RADEON_NR_TEX_REGIONS,
- (drmTextureRegionPtr)rmesa->sarea->tex_list[i],
- & rmesa->sarea->tex_age[i],
- & rmesa->swapped,
- sizeof( radeonTexObj ),
- (destroy_texture_object_t *) radeonDestroyTexObj );
-
- driSetTextureSwapCounterLocation( rmesa->texture_heaps[i],
- & rmesa->c_textureSwaps );
- }
- rmesa->texture_depth = driQueryOptioni (&rmesa->optionCache,
- "texture_depth");
- if (rmesa->texture_depth == DRI_CONF_TEXTURE_DEPTH_FB)
- rmesa->texture_depth = ( screen->cpp == 4 ) ?
- DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16;
-
- rmesa->swtcl.RenderIndex = ~0;
- rmesa->hw.all_dirty = GL_TRUE;
-
- /* Set the maximum texture size small enough that we can guarentee that
- * all texture units can bind a maximal texture and have them both in
- * texturable memory at once.
- */
-
- ctx = rmesa->glCtx;
- ctx->Const.MaxTextureUnits = 2;
- ctx->Const.MaxTextureImageUnits = 2;
- ctx->Const.MaxTextureCoordUnits = 2;
-
- driCalculateMaxTextureLevels( rmesa->texture_heaps,
- rmesa->nr_heaps,
- & ctx->Const,
- 4,
- 11, /* max 2D texture size is 2048x2048 */
- 0, /* 3D textures unsupported. */
- 0, /* cube textures unsupported. */
- 11, /* max rect texture size is 2048x2048. */
- 12,
- GL_FALSE );
-
- /* adjust max texture size a bit. Hack, but I really want to use larger textures
- which will work just fine in 99.999999% of all cases, especially with texture compression... */
- if (driQueryOptionb( &rmesa->optionCache, "texture_level_hack" ))
- {
- if (ctx->Const.MaxTextureLevels < 12) ctx->Const.MaxTextureLevels += 1;
- }
-
- ctx->Const.MaxTextureMaxAnisotropy = 16.0;
-
- /* No wide points.
- */
- ctx->Const.MinPointSize = 1.0;
- ctx->Const.MinPointSizeAA = 1.0;
- ctx->Const.MaxPointSize = 1.0;
- ctx->Const.MaxPointSizeAA = 1.0;
-
- ctx->Const.MinLineWidth = 1.0;
- ctx->Const.MinLineWidthAA = 1.0;
- ctx->Const.MaxLineWidth = 10.0;
- ctx->Const.MaxLineWidthAA = 10.0;
- ctx->Const.LineWidthGranularity = 0.0625;
-
- /* Set maxlocksize (and hence vb size) small enough to avoid
- * fallbacks in radeon_tcl.c. ie. guarentee that all vertices can
- * fit in a single dma buffer for indexed rendering of quad strips,
- * etc.
- */
- ctx->Const.MaxArrayLockSize =
- MIN2( ctx->Const.MaxArrayLockSize,
- RADEON_BUFFER_SIZE / RADEON_MAX_TCL_VERTSIZE );
-
- rmesa->boxes = 0;
-
- /* Initialize the software rasterizer and helper modules.
- */
- _swrast_CreateContext( ctx );
- _ac_CreateContext( ctx );
- _tnl_CreateContext( ctx );
- _swsetup_CreateContext( ctx );
- _ae_create_context( ctx );
-
- /* Install the customized pipeline:
- */
- _tnl_destroy_pipeline( ctx );
- _tnl_install_pipeline( ctx, radeon_pipeline );
- ctx->Driver.FlushVertices = radeonFlushVertices;
-
- /* Try and keep materials and vertices separate:
- */
- _tnl_isolate_materials( ctx, GL_TRUE );
-
-/* _mesa_allow_light_in_model( ctx, GL_FALSE ); */
-
- /* Configure swrast and T&L to match hardware characteristics:
- */
- _swrast_allow_pixel_fog( ctx, GL_FALSE );
- _swrast_allow_vertex_fog( ctx, GL_TRUE );
- _tnl_allow_pixel_fog( ctx, GL_FALSE );
- _tnl_allow_vertex_fog( ctx, GL_TRUE );
-
-
- _math_matrix_ctr( &rmesa->TexGenMatrix[0] );
- _math_matrix_ctr( &rmesa->TexGenMatrix[1] );
- _math_matrix_ctr( &rmesa->tmpmat );
- _math_matrix_set_identity( &rmesa->TexGenMatrix[0] );
- _math_matrix_set_identity( &rmesa->TexGenMatrix[1] );
- _math_matrix_set_identity( &rmesa->tmpmat );
-
- driInitExtensions( ctx, card_extensions, GL_TRUE );
- if (rmesa->glCtx->Mesa_DXTn) {
- _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" );
- _mesa_enable_extension( ctx, "GL_S3_s3tc" );
- }
- else if (driQueryOptionb (&rmesa->optionCache, "force_s3tc_enable")) {
- _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" );
- }
-
- if (rmesa->dri.drmMinor >= 9)
- _mesa_enable_extension( ctx, "GL_NV_texture_rectangle");
-
- /* XXX these should really go right after _mesa_init_driver_functions() */
- radeonInitIoctlFuncs( ctx );
- radeonInitStateFuncs( ctx );
- radeonInitSpanFuncs( ctx );
- radeonInitState( rmesa );
- radeonInitSwtcl( ctx );
-
- _mesa_vector4f_alloc( &rmesa->tcl.ObjClean, 0,
- ctx->Const.MaxArrayLockSize, 32 );
-
- fthrottle_mode = driQueryOptioni(&rmesa->optionCache, "fthrottle_mode");
- rmesa->iw.irq_seq = -1;
- rmesa->irqsEmitted = 0;
- rmesa->do_irqs = (rmesa->radeonScreen->irq != 0 &&
- fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS);
-
- rmesa->do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
-
- rmesa->vblank_flags = (rmesa->radeonScreen->irq != 0)
- ? driGetDefaultVBlankFlags(&rmesa->optionCache) : VBLANK_FLAG_NO_IRQ;
-
- (*dri_interface->getUST)( & rmesa->swap_ust );
-
-
-#if DO_DEBUG
- RADEON_DEBUG = driParseDebugString( getenv( "RADEON_DEBUG" ),
- debug_control );
-#endif
-
- tcl_mode = driQueryOptioni(&rmesa->optionCache, "tcl_mode");
- if (driQueryOptionb(&rmesa->optionCache, "no_rast")) {
- fprintf(stderr, "disabling 3D acceleration\n");
- FALLBACK(rmesa, RADEON_FALLBACK_DISABLE, 1);
- } else if (tcl_mode == DRI_CONF_TCL_SW ||
- !(rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL)) {
- if (rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL) {
- rmesa->radeonScreen->chipset &= ~RADEON_CHIPSET_TCL;
- fprintf(stderr, "Disabling HW TCL support\n");
- }
- TCL_FALLBACK(rmesa->glCtx, RADEON_TCL_FALLBACK_TCL_DISABLE, 1);
- }
-
- if (rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL) {
- if (tcl_mode >= DRI_CONF_TCL_VTXFMT)
- radeonVtxfmtInit( ctx, tcl_mode >= DRI_CONF_TCL_CODEGEN );
-
- _tnl_need_dlist_norm_lengths( ctx, GL_FALSE );
- }
- return GL_TRUE;
-}
-
-
-/* Destroy the device specific context.
- */
-/* Destroy the Mesa and driver specific context data.
- */
-void radeonDestroyContext( __DRIcontextPrivate *driContextPriv )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = (radeonContextPtr) driContextPriv->driverPrivate;
- radeonContextPtr current = ctx ? RADEON_CONTEXT(ctx) : NULL;
-
- /* check if we're deleting the currently bound context */
- if (rmesa == current) {
- RADEON_FIREVERTICES( rmesa );
- _mesa_make_current(NULL, NULL, NULL);
- }
-
- /* Free radeon context resources */
- assert(rmesa); /* should never be null */
- if ( rmesa ) {
- GLboolean release_texture_heaps;
-
-
- release_texture_heaps = (rmesa->glCtx->Shared->RefCount == 1);
- _swsetup_DestroyContext( rmesa->glCtx );
- _tnl_DestroyContext( rmesa->glCtx );
- _ac_DestroyContext( rmesa->glCtx );
- _swrast_DestroyContext( rmesa->glCtx );
-
- radeonDestroySwtcl( rmesa->glCtx );
- radeonReleaseArrays( rmesa->glCtx, ~0 );
- if (rmesa->dma.current.buf) {
- radeonReleaseDmaRegion( rmesa, &rmesa->dma.current, __FUNCTION__ );
- radeonFlushCmdBuf( rmesa, __FUNCTION__ );
- }
-
- if (!(rmesa->TclFallback & RADEON_TCL_FALLBACK_TCL_DISABLE)) {
- int tcl_mode = driQueryOptioni(&rmesa->optionCache, "tcl_mode");
- if (tcl_mode >= DRI_CONF_TCL_VTXFMT)
- radeonVtxfmtDestroy( rmesa->glCtx );
- }
-
- /* free the Mesa context */
- rmesa->glCtx->DriverCtx = NULL;
- _mesa_destroy_context( rmesa->glCtx );
-
- _mesa_vector4f_free( &rmesa->tcl.ObjClean );
-
- if (rmesa->state.scissor.pClipRects) {
- FREE(rmesa->state.scissor.pClipRects);
- rmesa->state.scissor.pClipRects = NULL;
- }
-
- if ( release_texture_heaps ) {
- /* This share group is about to go away, free our private
- * texture object data.
- */
- int i;
-
- for ( i = 0 ; i < rmesa->nr_heaps ; i++ ) {
- driDestroyTextureHeap( rmesa->texture_heaps[ i ] );
- rmesa->texture_heaps[ i ] = NULL;
- }
-
- assert( is_empty_list( & rmesa->swapped ) );
- }
-
- /* free the option cache */
- driDestroyOptionCache (&rmesa->optionCache);
-
- FREE( rmesa );
- }
-}
-
-
-
-
-void
-radeonSwapBuffers( __DRIdrawablePrivate *dPriv )
-{
-
- if (dPriv->driContextPriv && dPriv->driContextPriv->driverPrivate) {
- radeonContextPtr rmesa;
- GLcontext *ctx;
- rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate;
- ctx = rmesa->glCtx;
- if (ctx->Visual.doubleBufferMode) {
- _mesa_notifySwapBuffers( ctx ); /* flush pending rendering comands */
-
- if ( rmesa->doPageFlip ) {
- radeonPageFlip( dPriv );
- }
- else {
- radeonCopyBuffer( dPriv );
- }
- }
- }
- else {
- /* XXX this shouldn't be an error but we can't handle it for now */
- _mesa_problem(NULL, "%s: drawable has no context!", __FUNCTION__);
- }
-}
-
-
-/* Force the context `c' to be the current context and associate with it
- * buffer `b'.
- */
-GLboolean
-radeonMakeCurrent( __DRIcontextPrivate *driContextPriv,
- __DRIdrawablePrivate *driDrawPriv,
- __DRIdrawablePrivate *driReadPriv )
-{
- if ( driContextPriv ) {
- radeonContextPtr newCtx =
- (radeonContextPtr) driContextPriv->driverPrivate;
-
- if (RADEON_DEBUG & DEBUG_DRI)
- fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *) newCtx->glCtx);
-
- if ( newCtx->dri.drawable != driDrawPriv ) {
- driDrawableInitVBlank( driDrawPriv, newCtx->vblank_flags );
- newCtx->dri.drawable = driDrawPriv;
- radeonUpdateWindow( newCtx->glCtx );
- radeonUpdateViewportOffset( newCtx->glCtx );
- }
-
- _mesa_make_current( newCtx->glCtx,
- (GLframebuffer *) driDrawPriv->driverPrivate,
- (GLframebuffer *) driReadPriv->driverPrivate );
-
- if (newCtx->vb.enabled)
- radeonVtxfmtMakeCurrent( newCtx->glCtx );
-
- } else {
- if (RADEON_DEBUG & DEBUG_DRI)
- fprintf(stderr, "%s ctx is null\n", __FUNCTION__);
- _mesa_make_current( NULL, NULL, NULL );
- }
-
- if (RADEON_DEBUG & DEBUG_DRI)
- fprintf(stderr, "End %s\n", __FUNCTION__);
- return GL_TRUE;
-}
-
-/* Force the context `c' to be unbound from its buffer.
- */
-GLboolean
-radeonUnbindContext( __DRIcontextPrivate *driContextPriv )
-{
- radeonContextPtr rmesa = (radeonContextPtr) driContextPriv->driverPrivate;
-
- if (RADEON_DEBUG & DEBUG_DRI)
- fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *) rmesa->glCtx);
-
- return GL_TRUE;
-}
diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_context.h b/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_context.h
deleted file mode 100644
index 621a4c655..000000000
--- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_context.h
+++ /dev/null
@@ -1,868 +0,0 @@
-/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_context.h,v 1.6 2002/12/16 16:18:58 dawes Exp $ */
-/**************************************************************************
-
-Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
- VA Linux Systems Inc., Fremont, California.
-
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/*
- * Authors:
- * Kevin E. Martin <martin@valinux.com>
- * Gareth Hughes <gareth@valinux.com>
- * Keith Whitwell <keith@tungstengraphics.com>
- */
-
-#ifndef __RADEON_CONTEXT_H__
-#define __RADEON_CONTEXT_H__
-
-#include "tnl/t_vertex.h"
-#include "dri_util.h"
-#include "drm.h"
-#include "radeon_drm.h"
-#include "texmem.h"
-
-#include "macros.h"
-#include "mtypes.h"
-#include "colormac.h"
-
-struct radeon_context;
-typedef struct radeon_context radeonContextRec;
-typedef struct radeon_context *radeonContextPtr;
-
-#include "radeon_lock.h"
-#include "radeon_screen.h"
-#include "mm.h"
-
-#include "math/m_vector.h"
-
-/* Flags for software fallback cases */
-/* See correponding strings in radeon_swtcl.c */
-#define RADEON_FALLBACK_TEXTURE 0x0001
-#define RADEON_FALLBACK_DRAW_BUFFER 0x0002
-#define RADEON_FALLBACK_STENCIL 0x0004
-#define RADEON_FALLBACK_RENDER_MODE 0x0008
-#define RADEON_FALLBACK_BLEND_EQ 0x0010
-#define RADEON_FALLBACK_BLEND_FUNC 0x0020
-#define RADEON_FALLBACK_DISABLE 0x0040
-#define RADEON_FALLBACK_BORDER_MODE 0x0080
-
-/* The blit width for texture uploads
- */
-#define BLIT_WIDTH_BYTES 1024
-
-/* Use the templated vertex format:
- */
-#define COLOR_IS_RGBA
-#define TAG(x) radeon##x
-#include "tnl_dd/t_dd_vertex.h"
-#undef TAG
-
-typedef void (*radeon_tri_func)( radeonContextPtr,
- radeonVertex *,
- radeonVertex *,
- radeonVertex * );
-
-typedef void (*radeon_line_func)( radeonContextPtr,
- radeonVertex *,
- radeonVertex * );
-
-typedef void (*radeon_point_func)( radeonContextPtr,
- radeonVertex * );
-
-
-struct radeon_colorbuffer_state {
- GLuint clear;
- GLint drawOffset, drawPitch;
- int roundEnable;
-};
-
-
-struct radeon_depthbuffer_state {
- GLuint clear;
- GLfloat scale;
-};
-
-struct radeon_pixel_state {
- GLint readOffset, readPitch;
-};
-
-struct radeon_scissor_state {
- drm_clip_rect_t rect;
- GLboolean enabled;
-
- GLuint numClipRects; /* Cliprects active */
- GLuint numAllocedClipRects; /* Cliprects available */
- drm_clip_rect_t *pClipRects;
-};
-
-struct radeon_stencilbuffer_state {
- GLboolean hwBuffer;
- GLuint clear; /* rb3d_stencilrefmask value */
-};
-
-struct radeon_stipple_state {
- GLuint mask[32];
-};
-
-
-
-#define TEX_0 0x1
-#define TEX_1 0x2
-#define TEX_ALL 0x3
-
-typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr;
-
-/* Texture object in locally shared texture space.
- */
-struct radeon_tex_obj {
- driTextureObject base;
-
- GLuint bufAddr; /* Offset to start of locally
- shared texture block */
-
- GLuint dirty_state; /* Flags (1 per texunit) for
- whether or not this texobj
- has dirty hardware state
- (pp_*) that needs to be
- brought into the
- texunit. */
-
- drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS];
- /* Six, for the cube faces */
-
- GLuint pp_txfilter; /* hardware register values */
- GLuint pp_txformat;
- GLuint pp_txoffset; /* Image location in texmem.
- All cube faces follow. */
- GLuint pp_txsize; /* npot only */
- GLuint pp_txpitch; /* npot only */
- GLuint pp_border_color;
- GLuint pp_cubic_faces; /* cube face 1,2,3,4 log2 sizes */
-
- GLboolean border_fallback;
-
- GLuint tile_bits; /* hw texture tile bits used on this texture */
-};
-
-
-struct radeon_texture_env_state {
- radeonTexObjPtr texobj;
- GLenum format;
- GLenum envMode;
-};
-
-struct radeon_texture_state {
- struct radeon_texture_env_state unit[RADEON_MAX_TEXTURE_UNITS];
-};
-
-
-struct radeon_state_atom {
- struct radeon_state_atom *next, *prev;
- const char *name; /* for debug */
- int cmd_size; /* size in bytes */
- GLuint is_tcl;
- int *cmd; /* one or more cmd's */
- int *lastcmd; /* one or more cmd's */
- GLboolean dirty; /* dirty-mark in emit_state_list */
- GLboolean (*check)( GLcontext * ); /* is this state active? */
-};
-
-
-
-/* Trying to keep these relatively short as the variables are becoming
- * extravagently long. Drop the driver name prefix off the front of
- * everything - I think we know which driver we're in by now, and keep the
- * prefix to 3 letters unless absolutely impossible.
- */
-
-#define CTX_CMD_0 0
-#define CTX_PP_MISC 1
-#define CTX_PP_FOG_COLOR 2
-#define CTX_RE_SOLID_COLOR 3
-#define CTX_RB3D_BLENDCNTL 4
-#define CTX_RB3D_DEPTHOFFSET 5
-#define CTX_RB3D_DEPTHPITCH 6
-#define CTX_RB3D_ZSTENCILCNTL 7
-#define CTX_CMD_1 8
-#define CTX_PP_CNTL 9
-#define CTX_RB3D_CNTL 10
-#define CTX_RB3D_COLOROFFSET 11
-#define CTX_CMD_2 12
-#define CTX_RB3D_COLORPITCH 13
-#define CTX_STATE_SIZE 14
-
-#define SET_CMD_0 0
-#define SET_SE_CNTL 1
-#define SET_SE_COORDFMT 2
-#define SET_CMD_1 3
-#define SET_SE_CNTL_STATUS 4
-#define SET_STATE_SIZE 5
-
-#define LIN_CMD_0 0
-#define LIN_RE_LINE_PATTERN 1
-#define LIN_RE_LINE_STATE 2
-#define LIN_CMD_1 3
-#define LIN_SE_LINE_WIDTH 4
-#define LIN_STATE_SIZE 5
-
-#define MSK_CMD_0 0
-#define MSK_RB3D_STENCILREFMASK 1
-#define MSK_RB3D_ROPCNTL 2
-#define MSK_RB3D_PLANEMASK 3
-#define MSK_STATE_SIZE 4
-
-#define VPT_CMD_0 0
-#define VPT_SE_VPORT_XSCALE 1
-#define VPT_SE_VPORT_XOFFSET 2
-#define VPT_SE_VPORT_YSCALE 3
-#define VPT_SE_VPORT_YOFFSET 4
-#define VPT_SE_VPORT_ZSCALE 5
-#define VPT_SE_VPORT_ZOFFSET 6
-#define VPT_STATE_SIZE 7
-
-#define MSC_CMD_0 0
-#define MSC_RE_MISC 1
-#define MSC_STATE_SIZE 2
-
-#define TEX_CMD_0 0
-#define TEX_PP_TXFILTER 1
-#define TEX_PP_TXFORMAT 2
-#define TEX_PP_TXOFFSET 3
-#define TEX_PP_TXCBLEND 4
-#define TEX_PP_TXABLEND 5
-#define TEX_PP_TFACTOR 6
-#define TEX_CMD_1 7
-#define TEX_PP_BORDER_COLOR 8
-#define TEX_STATE_SIZE 9
-
-#define TXR_CMD_0 0 /* rectangle textures */
-#define TXR_PP_TEX_SIZE 1 /* 0x1d04, 0x1d0c for NPOT! */
-#define TXR_PP_TEX_PITCH 2 /* 0x1d08, 0x1d10 for NPOT! */
-#define TXR_STATE_SIZE 3
-
-#define ZBS_CMD_0 0
-#define ZBS_SE_ZBIAS_FACTOR 1
-#define ZBS_SE_ZBIAS_CONSTANT 2
-#define ZBS_STATE_SIZE 3
-
-#define TCL_CMD_0 0
-#define TCL_OUTPUT_VTXFMT 1
-#define TCL_OUTPUT_VTXSEL 2
-#define TCL_MATRIX_SELECT_0 3
-#define TCL_MATRIX_SELECT_1 4
-#define TCL_UCP_VERT_BLEND_CTL 5
-#define TCL_TEXTURE_PROC_CTL 6
-#define TCL_LIGHT_MODEL_CTL 7
-#define TCL_PER_LIGHT_CTL_0 8
-#define TCL_PER_LIGHT_CTL_1 9
-#define TCL_PER_LIGHT_CTL_2 10
-#define TCL_PER_LIGHT_CTL_3 11
-#define TCL_STATE_SIZE 12
-
-#define MTL_CMD_0 0
-#define MTL_EMMISSIVE_RED 1
-#define MTL_EMMISSIVE_GREEN 2
-#define MTL_EMMISSIVE_BLUE 3
-#define MTL_EMMISSIVE_ALPHA 4
-#define MTL_AMBIENT_RED 5
-#define MTL_AMBIENT_GREEN 6
-#define MTL_AMBIENT_BLUE 7
-#define MTL_AMBIENT_ALPHA 8
-#define MTL_DIFFUSE_RED 9
-#define MTL_DIFFUSE_GREEN 10
-#define MTL_DIFFUSE_BLUE 11
-#define MTL_DIFFUSE_ALPHA 12
-#define MTL_SPECULAR_RED 13
-#define MTL_SPECULAR_GREEN 14
-#define MTL_SPECULAR_BLUE 15
-#define MTL_SPECULAR_ALPHA 16
-#define MTL_SHININESS 17
-#define MTL_STATE_SIZE 18
-
-#define VTX_CMD_0 0
-#define VTX_SE_COORD_FMT 1
-#define VTX_STATE_SIZE 2
-
-#define MAT_CMD_0 0
-#define MAT_ELT_0 1
-#define MAT_STATE_SIZE 17
-
-#define GRD_CMD_0 0
-#define GRD_VERT_GUARD_CLIP_ADJ 1
-#define GRD_VERT_GUARD_DISCARD_ADJ 2
-#define GRD_HORZ_GUARD_CLIP_ADJ 3
-#define GRD_HORZ_GUARD_DISCARD_ADJ 4
-#define GRD_STATE_SIZE 5
-
-/* position changes frequently when lighting in modelpos - separate
- * out to new state item?
- */
-#define LIT_CMD_0 0
-#define LIT_AMBIENT_RED 1
-#define LIT_AMBIENT_GREEN 2
-#define LIT_AMBIENT_BLUE 3
-#define LIT_AMBIENT_ALPHA 4
-#define LIT_DIFFUSE_RED 5
-#define LIT_DIFFUSE_GREEN 6
-#define LIT_DIFFUSE_BLUE 7
-#define LIT_DIFFUSE_ALPHA 8
-#define LIT_SPECULAR_RED 9
-#define LIT_SPECULAR_GREEN 10
-#define LIT_SPECULAR_BLUE 11
-#define LIT_SPECULAR_ALPHA 12
-#define LIT_POSITION_X 13
-#define LIT_POSITION_Y 14
-#define LIT_POSITION_Z 15
-#define LIT_POSITION_W 16
-#define LIT_DIRECTION_X 17
-#define LIT_DIRECTION_Y 18
-#define LIT_DIRECTION_Z 19
-#define LIT_DIRECTION_W 20
-#define LIT_ATTEN_QUADRATIC 21
-#define LIT_ATTEN_LINEAR 22
-#define LIT_ATTEN_CONST 23
-#define LIT_ATTEN_XXX 24
-#define LIT_CMD_1 25
-#define LIT_SPOT_DCD 26
-#define LIT_SPOT_EXPONENT 27
-#define LIT_SPOT_CUTOFF 28
-#define LIT_SPECULAR_THRESH 29
-#define LIT_RANGE_CUTOFF 30 /* ? */
-#define LIT_ATTEN_CONST_INV 31
-#define LIT_STATE_SIZE 32
-
-/* Fog
- */
-#define FOG_CMD_0 0
-#define FOG_R 1
-#define FOG_C 2
-#define FOG_D 3
-#define FOG_PAD 4
-#define FOG_STATE_SIZE 5
-
-/* UCP
- */
-#define UCP_CMD_0 0
-#define UCP_X 1
-#define UCP_Y 2
-#define UCP_Z 3
-#define UCP_W 4
-#define UCP_STATE_SIZE 5
-
-/* GLT - Global ambient
- */
-#define GLT_CMD_0 0
-#define GLT_RED 1
-#define GLT_GREEN 2
-#define GLT_BLUE 3
-#define GLT_ALPHA 4
-#define GLT_STATE_SIZE 5
-
-/* EYE
- */
-#define EYE_CMD_0 0
-#define EYE_X 1
-#define EYE_Y 2
-#define EYE_Z 3
-#define EYE_RESCALE_FACTOR 4
-#define EYE_STATE_SIZE 5
-
-#define SHN_CMD_0 0
-#define SHN_SHININESS 1
-#define SHN_STATE_SIZE 2
-
-
-
-
-
-struct radeon_hw_state {
- /* Head of the linked list of state atoms. */
- struct radeon_state_atom atomlist;
-
- /* Hardware state, stored as cmdbuf commands:
- * -- Need to doublebuffer for
- * - eliding noop statechange loops? (except line stipple count)
- */
- struct radeon_state_atom ctx;
- struct radeon_state_atom set;
- struct radeon_state_atom lin;
- struct radeon_state_atom msk;
- struct radeon_state_atom vpt;
- struct radeon_state_atom tcl;
- struct radeon_state_atom msc;
- struct radeon_state_atom tex[2];
- struct radeon_state_atom zbs;
- struct radeon_state_atom mtl;
- struct radeon_state_atom mat[5];
- struct radeon_state_atom lit[8]; /* includes vec, scl commands */
- struct radeon_state_atom ucp[6];
- struct radeon_state_atom eye; /* eye pos */
- struct radeon_state_atom grd; /* guard band clipping */
- struct radeon_state_atom fog;
- struct radeon_state_atom glt;
- struct radeon_state_atom txr[2]; /* for NPOT */
-
- int max_state_size; /* Number of bytes necessary for a full state emit. */
- GLboolean is_dirty, all_dirty;
-};
-
-struct radeon_state {
- /* Derived state for internal purposes:
- */
- struct radeon_colorbuffer_state color;
- struct radeon_depthbuffer_state depth;
- struct radeon_pixel_state pixel;
- struct radeon_scissor_state scissor;
- struct radeon_stencilbuffer_state stencil;
- struct radeon_stipple_state stipple;
- struct radeon_texture_state texture;
-};
-
-
-/* Need refcounting on dma buffers:
- */
-struct radeon_dma_buffer {
- int refcount; /* the number of retained regions in buf */
- drmBufPtr buf;
-};
-
-#define GET_START(rvb) (rmesa->radeonScreen->gart_buffer_offset + \
- (rvb)->address - rmesa->dma.buf0_address + \
- (rvb)->start)
-
-/* A retained region, eg vertices for indexed vertices.
- */
-struct radeon_dma_region {
- struct radeon_dma_buffer *buf;
- char *address; /* == buf->address */
- int start, end, ptr; /* offsets from start of buf */
- int aos_start;
- int aos_stride;
- int aos_size;
-};
-
-
-struct radeon_dma {
- /* Active dma region. Allocations for vertices and retained
- * regions come from here. Also used for emitting random vertices,
- * these may be flushed by calling flush_current();
- */
- struct radeon_dma_region current;
-
- void (*flush)( radeonContextPtr );
-
- char *buf0_address; /* start of buf[0], for index calcs */
- GLuint nr_released_bufs; /* flush after so many buffers released */
-};
-
-struct radeon_dri_mirror {
- __DRIcontextPrivate *context; /* DRI context */
- __DRIscreenPrivate *screen; /* DRI screen */
- __DRIdrawablePrivate *drawable; /* DRI drawable bound to this ctx */
-
- drm_context_t hwContext;
- drm_hw_lock_t *hwLock;
- int fd;
- int drmMinor;
-};
-
-
-#define RADEON_CMD_BUF_SZ (8*1024)
-
-struct radeon_store {
- GLuint statenr;
- GLuint primnr;
- char cmd_buf[RADEON_CMD_BUF_SZ];
- int cmd_used;
- int elts_start;
-};
-
-
-/* radeon_tcl.c
- */
-struct radeon_tcl_info {
- GLuint vertex_format;
- GLint last_offset;
- GLuint hw_primitive;
-
- /* Temporary for cases where incoming vertex data is incompatible
- * with maos code.
- */
- GLvector4f ObjClean;
-
- struct radeon_dma_region *aos_components[8];
- GLuint nr_aos_components;
-
- GLuint *Elts;
-
- struct radeon_dma_region indexed_verts;
- struct radeon_dma_region obj;
- struct radeon_dma_region rgba;
- struct radeon_dma_region spec;
- struct radeon_dma_region fog;
- struct radeon_dma_region tex[RADEON_MAX_TEXTURE_UNITS];
- struct radeon_dma_region norm;
-};
-
-
-/* radeon_swtcl.c
- */
-struct radeon_swtcl_info {
- GLuint RenderIndex;
- GLuint vertex_size;
- GLuint vertex_format;
-
- struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX];
- GLuint vertex_attr_count;
-
- GLubyte *verts;
-
- /* Fallback rasterization functions
- */
- radeon_point_func draw_point;
- radeon_line_func draw_line;
- radeon_tri_func draw_tri;
-
- GLuint hw_primitive;
- GLenum render_primitive;
- GLuint numverts;
-
- /**
- * Offset of the 4UB color data within a hardware (swtcl) vertex.
- */
- GLuint coloroffset;
-
- /**
- * Offset of the 3UB specular color data within a hardware (swtcl) vertex.
- */
- GLuint specoffset;
-
- GLboolean needproj;
-
- struct radeon_dma_region indexed_verts;
-};
-
-
-struct radeon_ioctl {
- GLuint vertex_offset;
- GLuint vertex_size;
-};
-
-
-
-#define RADEON_MAX_PRIMS 64
-
-
-/* Want to keep a cache of these around. Each is parameterized by
- * only a single value which has only a small range. Only expect a
- * few, so just rescan the list each time?
- */
-struct dynfn {
- struct dynfn *next, *prev;
- int key;
- char *code;
-};
-
-struct dfn_lists {
- struct dynfn Vertex2f;
- struct dynfn Vertex2fv;
- struct dynfn Vertex3f;
- struct dynfn Vertex3fv;
- struct dynfn Color4ub;
- struct dynfn Color4ubv;
- struct dynfn Color3ub;
- struct dynfn Color3ubv;
- struct dynfn Color4f;
- struct dynfn Color4fv;
- struct dynfn Color3f;
- struct dynfn Color3fv;
- struct dynfn SecondaryColor3ubEXT;
- struct dynfn SecondaryColor3ubvEXT;
- struct dynfn SecondaryColor3fEXT;
- struct dynfn SecondaryColor3fvEXT;
- struct dynfn Normal3f;
- struct dynfn Normal3fv;
- struct dynfn TexCoord2f;
- struct dynfn TexCoord2fv;
- struct dynfn TexCoord1f;
- struct dynfn TexCoord1fv;
- struct dynfn MultiTexCoord2fARB;
- struct dynfn MultiTexCoord2fvARB;
- struct dynfn MultiTexCoord1fARB;
- struct dynfn MultiTexCoord1fvARB;
-};
-
-struct dfn_generators {
- struct dynfn *(*Vertex2f)( GLcontext *, int );
- struct dynfn *(*Vertex2fv)( GLcontext *, int );
- struct dynfn *(*Vertex3f)( GLcontext *, int );
- struct dynfn *(*Vertex3fv)( GLcontext *, int );
- struct dynfn *(*Color4ub)( GLcontext *, int );
- struct dynfn *(*Color4ubv)( GLcontext *, int );
- struct dynfn *(*Color3ub)( GLcontext *, int );
- struct dynfn *(*Color3ubv)( GLcontext *, int );
- struct dynfn *(*Color4f)( GLcontext *, int );
- struct dynfn *(*Color4fv)( GLcontext *, int );
- struct dynfn *(*Color3f)( GLcontext *, int );
- struct dynfn *(*Color3fv)( GLcontext *, int );
- struct dynfn *(*SecondaryColor3ubEXT)( GLcontext *, int );
- struct dynfn *(*SecondaryColor3ubvEXT)( GLcontext *, int );
- struct dynfn *(*SecondaryColor3fEXT)( GLcontext *, int );
- struct dynfn *(*SecondaryColor3fvEXT)( GLcontext *, int );
- struct dynfn *(*Normal3f)( GLcontext *, int );
- struct dynfn *(*Normal3fv)( GLcontext *, int );
- struct dynfn *(*TexCoord2f)( GLcontext *, int );
- struct dynfn *(*TexCoord2fv)( GLcontext *, int );
- struct dynfn *(*TexCoord1f)( GLcontext *, int );
- struct dynfn *(*TexCoord1fv)( GLcontext *, int );
- struct dynfn *(*MultiTexCoord2fARB)( GLcontext *, int );
- struct dynfn *(*MultiTexCoord2fvARB)( GLcontext *, int );
- struct dynfn *(*MultiTexCoord1fARB)( GLcontext *, int );
- struct dynfn *(*MultiTexCoord1fvARB)( GLcontext *, int );
-};
-
-
-
-struct radeon_prim {
- GLuint start;
- GLuint end;
- GLuint prim;
-};
-
-struct radeon_vbinfo {
- GLint counter, initial_counter;
- GLint *dmaptr;
- void (*notify)( void );
- GLint vertex_size;
-
- /* A maximum total of 15 elements per vertex: 3 floats for position, 3
- * floats for normal, 4 floats for color, 4 bytes for secondary color,
- * 2 floats for each texture unit (4 floats total).
- *
- * As soon as the 3rd TMU is supported or cube maps (or 3D textures) are
- * supported, this value will grow.
- *
- * The position data is never actually stored here, so 3 elements could be
- * trimmed out of the buffer.
- */
- union { float f; int i; radeon_color_t color; } vertex[15];
-
- GLfloat *normalptr;
- GLfloat *floatcolorptr;
- radeon_color_t *colorptr;
- GLfloat *floatspecptr;
- radeon_color_t *specptr;
- GLfloat *texcoordptr[2];
-
- GLenum *prim; /* &ctx->Driver.CurrentExecPrimitive */
- GLuint primflags;
- GLboolean enabled; /* *_NO_VTXFMT / *_NO_TCL env vars */
- GLboolean installed;
- GLboolean fell_back;
- GLboolean recheck;
- GLint nrverts;
- GLuint vertex_format;
-
- GLuint installed_vertex_format;
- GLuint installed_color_3f_sz;
-
- struct radeon_prim primlist[RADEON_MAX_PRIMS];
- int nrprims;
-
- struct dfn_lists dfn_cache;
- struct dfn_generators codegen;
- GLvertexformat vtxfmt;
-};
-
-
-
-
-struct radeon_context {
- GLcontext *glCtx; /* Mesa context */
-
- /* Driver and hardware state management
- */
- struct radeon_hw_state hw;
- struct radeon_state state;
-
- /* Texture object bookkeeping
- */
- unsigned nr_heaps;
- driTexHeap * texture_heaps[ RADEON_NR_TEX_HEAPS ];
- driTextureObject swapped;
- int texture_depth;
- float initialMaxAnisotropy;
-
- /* Rasterization and vertex state:
- */
- GLuint TclFallback;
- GLuint Fallback;
- GLuint NewGLState;
- GLuint tnl_index; /* index of bits for last tnl_install_attrs */
-
- /* Vertex buffers
- */
- struct radeon_ioctl ioctl;
- struct radeon_dma dma;
- struct radeon_store store;
- /* A full state emit as of the first state emit in the main store, in case
- * the context is lost.
- */
- struct radeon_store backup_store;
-
- /* Page flipping
- */
- GLuint doPageFlip;
-
- /* Busy waiting
- */
- GLuint do_usleeps;
- GLuint do_irqs;
- GLuint irqsEmitted;
- drm_radeon_irq_wait_t iw;
-
- /* Drawable, cliprect and scissor information
- */
- GLuint numClipRects; /* Cliprects for the draw buffer */
- drm_clip_rect_t *pClipRects;
- unsigned int lastStamp;
- GLboolean lost_context;
- GLboolean save_on_next_emit;
- radeonScreenPtr radeonScreen; /* Screen private DRI data */
- drm_radeon_sarea_t *sarea; /* Private SAREA data */
-
- /* TCL stuff
- */
- GLmatrix TexGenMatrix[RADEON_MAX_TEXTURE_UNITS];
- GLboolean recheck_texgen[RADEON_MAX_TEXTURE_UNITS];
- GLboolean TexGenNeedNormals[RADEON_MAX_TEXTURE_UNITS];
- GLuint TexMatEnabled;
- GLuint TexGenEnabled;
- GLmatrix tmpmat;
- GLuint last_ReallyEnabled;
-
- /* VBI
- */
- GLuint vbl_seq;
- GLuint vblank_flags;
-
- int64_t swap_ust;
- int64_t swap_missed_ust;
-
- GLuint swap_count;
- GLuint swap_missed_count;
-
-
- /* radeon_tcl.c
- */
- struct radeon_tcl_info tcl;
-
- /* radeon_swtcl.c
- */
- struct radeon_swtcl_info swtcl;
-
- /* radeon_vtxfmt.c
- */
- struct radeon_vbinfo vb;
-
- /* Mirrors of some DRI state
- */
- struct radeon_dri_mirror dri;
-
- /* Configuration cache
- */
- driOptionCache optionCache;
-
- GLboolean using_hyperz;
- GLboolean texmicrotile;
-
- /* Performance counters
- */
- GLuint boxes; /* Draw performance boxes */
- GLuint hardwareWentIdle;
- GLuint c_clears;
- GLuint c_drawWaits;
- GLuint c_textureSwaps;
- GLuint c_textureBytes;
- GLuint c_vertexBuffers;
-};
-
-#define RADEON_CONTEXT(ctx) ((radeonContextPtr)(ctx->DriverCtx))
-
-
-static __inline GLuint radeonPackColor( GLuint cpp,
- GLubyte r, GLubyte g,
- GLubyte b, GLubyte a )
-{
- switch ( cpp ) {
- case 2:
- return PACK_COLOR_565( r, g, b );
- case 4:
- return PACK_COLOR_8888( a, r, g, b );
- default:
- return 0;
- }
-}
-
-#define RADEON_OLD_PACKETS 1
-
-
-extern void radeonDestroyContext( __DRIcontextPrivate *driContextPriv );
-extern GLboolean radeonCreateContext(const __GLcontextModes *glVisual,
- __DRIcontextPrivate *driContextPriv,
- void *sharedContextPrivate);
-extern void radeonSwapBuffers( __DRIdrawablePrivate *dPriv );
-extern GLboolean radeonMakeCurrent( __DRIcontextPrivate *driContextPriv,
- __DRIdrawablePrivate *driDrawPriv,
- __DRIdrawablePrivate *driReadPriv );
-extern GLboolean radeonUnbindContext( __DRIcontextPrivate *driContextPriv );
-
-/* ================================================================
- * Debugging:
- */
-#define DO_DEBUG 1
-
-#if DO_DEBUG
-extern int RADEON_DEBUG;
-#else
-#define RADEON_DEBUG 0
-#endif
-
-#define DEBUG_TEXTURE 0x001
-#define DEBUG_STATE 0x002
-#define DEBUG_IOCTL 0x004
-#define DEBUG_PRIMS 0x008
-#define DEBUG_VERTS 0x010
-#define DEBUG_FALLBACKS 0x020
-#define DEBUG_VFMT 0x040
-#define DEBUG_CODEGEN 0x080
-#define DEBUG_VERBOSE 0x100
-#define DEBUG_DRI 0x200
-#define DEBUG_DMA 0x400
-#define DEBUG_SANITY 0x800
-#define DEBUG_SYNC 0x1000
-
-#endif /* __RADEON_CONTEXT_H__ */
diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_ioctl.c
deleted file mode 100644
index 53c5d5ca5..000000000
--- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_ioctl.c
+++ /dev/null
@@ -1,1283 +0,0 @@
-/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_ioctl.c,v 1.11 2003/01/29 22:04:59 dawes Exp $ */
-/**************************************************************************
-
-Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
- VA Linux Systems Inc., Fremont, California.
-
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/*
- * Authors:
- * Kevin E. Martin <martin@valinux.com>
- * Gareth Hughes <gareth@valinux.com>
- * Keith Whitwell <keith@tungstengraphics.com>
- */
-
-#include <sched.h>
-#include <errno.h>
-
-#include "glheader.h"
-#include "imports.h"
-#include "simple_list.h"
-#include "swrast/swrast.h"
-
-#include "radeon_context.h"
-#include "radeon_state.h"
-#include "radeon_ioctl.h"
-#include "radeon_tcl.h"
-#include "radeon_sanity.h"
-
-#define STANDALONE_MMIO
-#include "radeon_macros.h" /* for INREG() */
-
-#include "vblank.h"
-
-#define RADEON_TIMEOUT 512
-#define RADEON_IDLE_RETRY 16
-
-
-static void radeonWaitForIdle( radeonContextPtr rmesa );
-static int radeonFlushCmdBufLocked( radeonContextPtr rmesa,
- const char * caller );
-
-static void print_state_atom( struct radeon_state_atom *state )
-{
- int i;
-
- fprintf(stderr, "emit %s/%d\n", state->name, state->cmd_size);
-
- if (RADEON_DEBUG & DEBUG_VERBOSE)
- for (i = 0 ; i < state->cmd_size ; i++)
- fprintf(stderr, "\t%s[%d]: %x\n", state->name, i, state->cmd[i]);
-
-}
-
-static void radeonSaveHwState( radeonContextPtr rmesa )
-{
- struct radeon_state_atom *atom;
- char * dest = rmesa->backup_store.cmd_buf;
-
- if (RADEON_DEBUG & DEBUG_STATE)
- fprintf(stderr, "%s\n", __FUNCTION__);
-
- rmesa->backup_store.cmd_used = 0;
-
- foreach( atom, &rmesa->hw.atomlist ) {
- if ( atom->check( rmesa->glCtx ) ) {
- int size = atom->cmd_size * 4;
- memcpy( dest, atom->cmd, size);
- dest += size;
- rmesa->backup_store.cmd_used += size;
- if (RADEON_DEBUG & DEBUG_STATE)
- print_state_atom( atom );
- }
- }
-
- assert( rmesa->backup_store.cmd_used <= RADEON_CMD_BUF_SZ );
- if (RADEON_DEBUG & DEBUG_STATE)
- fprintf(stderr, "Returning to radeonEmitState\n");
-}
-
-/* At this point we were in FlushCmdBufLocked but we had lost our context, so
- * we need to unwire our current cmdbuf, hook the one with the saved state in
- * it, flush it, and then put the current one back. This is so commands at the
- * start of a cmdbuf can rely on the state being kept from the previous one.
- */
-static void radeonBackUpAndEmitLostStateLocked( radeonContextPtr rmesa )
-{
- GLuint nr_released_bufs;
- struct radeon_store saved_store;
-
- if (rmesa->backup_store.cmd_used == 0)
- return;
-
- if (RADEON_DEBUG & DEBUG_STATE)
- fprintf(stderr, "Emitting backup state on lost context\n");
-
- rmesa->lost_context = GL_FALSE;
-
- nr_released_bufs = rmesa->dma.nr_released_bufs;
- saved_store = rmesa->store;
- rmesa->dma.nr_released_bufs = 0;
- rmesa->store = rmesa->backup_store;
- radeonFlushCmdBufLocked( rmesa, __FUNCTION__ );
- rmesa->dma.nr_released_bufs = nr_released_bufs;
- rmesa->store = saved_store;
-}
-
-/* =============================================================
- * Kernel command buffer handling
- */
-
-/* The state atoms will be emitted in the order they appear in the atom list,
- * so this step is important.
- */
-void radeonSetUpAtomList( radeonContextPtr rmesa )
-{
- int i, mtu = rmesa->glCtx->Const.MaxTextureUnits;
-
- make_empty_list(&rmesa->hw.atomlist);
- rmesa->hw.atomlist.name = "atom-list";
-
- insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.ctx);
- insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.set);
- insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.lin);
- insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.msk);
- insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.vpt);
- insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.tcl);
- insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.msc);
- for (i = 0; i < mtu; ++i) {
- insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.tex[i]);
- insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.txr[i]);
- }
- insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.zbs);
- insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.mtl);
- for (i = 0; i < 3 + mtu; ++i)
- insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.mat[i]);
- for (i = 0; i < 8; ++i)
- insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.lit[i]);
- for (i = 0; i < 6; ++i)
- insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.ucp[i]);
- insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.eye);
- insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.grd);
- insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.fog);
- insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.glt);
-}
-
-void radeonEmitState( radeonContextPtr rmesa )
-{
- struct radeon_state_atom *atom;
- char *dest;
-
- if (RADEON_DEBUG & (DEBUG_STATE|DEBUG_PRIMS))
- fprintf(stderr, "%s\n", __FUNCTION__);
-
- if (rmesa->save_on_next_emit) {
- radeonSaveHwState(rmesa);
- rmesa->save_on_next_emit = GL_FALSE;
- }
-
- /* this code used to return here but now it emits zbs */
-
- /* To avoid going across the entire set of states multiple times, just check
- * for enough space for the case of emitting all state, and inline the
- * radeonAllocCmdBuf code here without all the checks.
- */
- radeonEnsureCmdBufSpace(rmesa, rmesa->hw.max_state_size);
- dest = rmesa->store.cmd_buf + rmesa->store.cmd_used;
-
- /* We always always emit zbs, this is due to a bug found by keithw in
- the hardware and rediscovered after Erics changes by me.
- if you ever touch this code make sure you emit zbs otherwise
- you get tcl lockups on at least M7/7500 class of chips - airlied */
- rmesa->hw.zbs.dirty=1;
-
- if (RADEON_DEBUG & DEBUG_STATE) {
- foreach(atom, &rmesa->hw.atomlist) {
- if (atom->dirty || rmesa->hw.all_dirty) {
- if (atom->check(rmesa->glCtx))
- print_state_atom(atom);
- else
- fprintf(stderr, "skip state %s\n", atom->name);
- }
- }
- }
-
- foreach(atom, &rmesa->hw.atomlist) {
- if (rmesa->hw.all_dirty)
- atom->dirty = GL_TRUE;
- if (!(rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL) &&
- atom->is_tcl)
- atom->dirty = GL_FALSE;
- if (atom->dirty) {
- if (atom->check(rmesa->glCtx)) {
- int size = atom->cmd_size * 4;
- memcpy(dest, atom->cmd, size);
- dest += size;
- rmesa->store.cmd_used += size;
- atom->dirty = GL_FALSE;
- }
- }
- }
-
- assert(rmesa->store.cmd_used <= RADEON_CMD_BUF_SZ);
-
- rmesa->hw.is_dirty = GL_FALSE;
- rmesa->hw.all_dirty = GL_FALSE;
-}
-
-/* Fire a section of the retained (indexed_verts) buffer as a regular
- * primtive.
- */
-extern void radeonEmitVbufPrim( radeonContextPtr rmesa,
- GLuint vertex_format,
- GLuint primitive,
- GLuint vertex_nr )
-{
- drm_radeon_cmd_header_t *cmd;
-
-
- assert(!(primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND));
-
- radeonEmitState( rmesa );
-
- if (RADEON_DEBUG & DEBUG_IOCTL)
- fprintf(stderr, "%s cmd_used/4: %d\n", __FUNCTION__,
- rmesa->store.cmd_used/4);
-
- cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa, VBUF_BUFSZ,
- __FUNCTION__ );
-#if RADEON_OLD_PACKETS
- cmd[0].i = 0;
- cmd[0].header.cmd_type = RADEON_CMD_PACKET3_CLIP;
- cmd[1].i = RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM | (3 << 16);
- cmd[2].i = rmesa->ioctl.vertex_offset;
- cmd[3].i = vertex_nr;
- cmd[4].i = vertex_format;
- cmd[5].i = (primitive |
- RADEON_CP_VC_CNTL_PRIM_WALK_LIST |
- RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA |
- RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE |
- (vertex_nr << RADEON_CP_VC_CNTL_NUM_SHIFT));
-
- if (RADEON_DEBUG & DEBUG_PRIMS)
- fprintf(stderr, "%s: header 0x%x offt 0x%x vfmt 0x%x vfcntl %x \n",
- __FUNCTION__,
- cmd[1].i, cmd[2].i, cmd[4].i, cmd[5].i);
-#else
- cmd[0].i = 0;
- cmd[0].header.cmd_type = RADEON_CMD_PACKET3_CLIP;
- cmd[1].i = RADEON_CP_PACKET3_3D_DRAW_VBUF | (1 << 16);
- cmd[2].i = vertex_format;
- cmd[3].i = (primitive |
- RADEON_CP_VC_CNTL_PRIM_WALK_LIST |
- RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA |
- RADEON_CP_VC_CNTL_MAOS_ENABLE |
- RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE |
- (vertex_nr << RADEON_CP_VC_CNTL_NUM_SHIFT));
-
-
- if (RADEON_DEBUG & DEBUG_PRIMS)
- fprintf(stderr, "%s: header 0x%x vfmt 0x%x vfcntl %x \n",
- __FUNCTION__,
- cmd[1].i, cmd[2].i, cmd[3].i);
-#endif
-}
-
-
-void radeonFlushElts( radeonContextPtr rmesa )
-{
- int *cmd = (int *)(rmesa->store.cmd_buf + rmesa->store.elts_start);
- int dwords;
-#if RADEON_OLD_PACKETS
- int nr = (rmesa->store.cmd_used - (rmesa->store.elts_start + 24)) / 2;
-#else
- int nr = (rmesa->store.cmd_used - (rmesa->store.elts_start + 16)) / 2;
-#endif
-
- if (RADEON_DEBUG & DEBUG_IOCTL)
- fprintf(stderr, "%s\n", __FUNCTION__);
-
- assert( rmesa->dma.flush == radeonFlushElts );
- rmesa->dma.flush = NULL;
-
- /* Cope with odd number of elts:
- */
- rmesa->store.cmd_used = (rmesa->store.cmd_used + 2) & ~2;
- dwords = (rmesa->store.cmd_used - rmesa->store.elts_start) / 4;
-
-#if RADEON_OLD_PACKETS
- cmd[1] |= (dwords - 3) << 16;
- cmd[5] |= nr << RADEON_CP_VC_CNTL_NUM_SHIFT;
-#else
- cmd[1] |= (dwords - 3) << 16;
- cmd[3] |= nr << RADEON_CP_VC_CNTL_NUM_SHIFT;
-#endif
-
- if (RADEON_DEBUG & DEBUG_SYNC) {
- fprintf(stderr, "%s: Syncing\n", __FUNCTION__);
- radeonFinish( rmesa->glCtx );
- }
-}
-
-
-GLushort *radeonAllocEltsOpenEnded( radeonContextPtr rmesa,
- GLuint vertex_format,
- GLuint primitive,
- GLuint min_nr )
-{
- drm_radeon_cmd_header_t *cmd;
- GLushort *retval;
-
- if (RADEON_DEBUG & DEBUG_IOCTL)
- fprintf(stderr, "%s %d\n", __FUNCTION__, min_nr);
-
- assert((primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND));
-
- radeonEmitState( rmesa );
-
- cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa,
- ELTS_BUFSZ(min_nr),
- __FUNCTION__ );
-#if RADEON_OLD_PACKETS
- cmd[0].i = 0;
- cmd[0].header.cmd_type = RADEON_CMD_PACKET3_CLIP;
- cmd[1].i = RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM;
- cmd[2].i = rmesa->ioctl.vertex_offset;
- cmd[3].i = 0xffff;
- cmd[4].i = vertex_format;
- cmd[5].i = (primitive |
- RADEON_CP_VC_CNTL_PRIM_WALK_IND |
- RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA |
- RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE);
-
- retval = (GLushort *)(cmd+6);
-#else
- cmd[0].i = 0;
- cmd[0].header.cmd_type = RADEON_CMD_PACKET3_CLIP;
- cmd[1].i = RADEON_CP_PACKET3_3D_DRAW_INDX;
- cmd[2].i = vertex_format;
- cmd[3].i = (primitive |
- RADEON_CP_VC_CNTL_PRIM_WALK_IND |
- RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA |
- RADEON_CP_VC_CNTL_MAOS_ENABLE |
- RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE);
-
- retval = (GLushort *)(cmd+4);
-#endif
-
- if (RADEON_DEBUG & DEBUG_PRIMS)
- fprintf(stderr, "%s: header 0x%x vfmt 0x%x prim %x \n",
- __FUNCTION__,
- cmd[1].i, vertex_format, primitive);
-
- assert(!rmesa->dma.flush);
- rmesa->glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES;
- rmesa->dma.flush = radeonFlushElts;
-
- rmesa->store.elts_start = ((char *)cmd) - rmesa->store.cmd_buf;
-
- return retval;
-}
-
-
-
-void radeonEmitVertexAOS( radeonContextPtr rmesa,
- GLuint vertex_size,
- GLuint offset )
-{
-#if RADEON_OLD_PACKETS
- rmesa->ioctl.vertex_size = vertex_size;
- rmesa->ioctl.vertex_offset = offset;
-#else
- drm_radeon_cmd_header_t *cmd;
-
- if (RADEON_DEBUG & (DEBUG_PRIMS|DEBUG_IOCTL))
- fprintf(stderr, "%s: vertex_size 0x%x offset 0x%x \n",
- __FUNCTION__, vertex_size, offset);
-
- cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa, VERT_AOS_BUFSZ,
- __FUNCTION__ );
-
- cmd[0].i = 0;
- cmd[0].header.cmd_type = RADEON_CMD_PACKET3;
- cmd[1].i = RADEON_CP_PACKET3_3D_LOAD_VBPNTR | (2 << 16);
- cmd[2].i = 1;
- cmd[3].i = vertex_size | (vertex_size << 8);
- cmd[4].i = offset;
-#endif
-}
-
-
-void radeonEmitAOS( radeonContextPtr rmesa,
- struct radeon_dma_region **component,
- GLuint nr,
- GLuint offset )
-{
-#if RADEON_OLD_PACKETS
- assert( nr == 1 );
- assert( component[0]->aos_size == component[0]->aos_stride );
- rmesa->ioctl.vertex_size = component[0]->aos_size;
- rmesa->ioctl.vertex_offset =
- (component[0]->aos_start + offset * component[0]->aos_stride * 4);
-#else
- drm_radeon_cmd_header_t *cmd;
- int sz = AOS_BUFSZ(nr);
- int i;
- int *tmp;
-
- if (RADEON_DEBUG & DEBUG_IOCTL)
- fprintf(stderr, "%s\n", __FUNCTION__);
-
-
- cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa, sz,
- __FUNCTION__ );
- cmd[0].i = 0;
- cmd[0].header.cmd_type = RADEON_CMD_PACKET3;
- cmd[1].i = RADEON_CP_PACKET3_3D_LOAD_VBPNTR | (((sz / sizeof(int))-3) << 16);
- cmd[2].i = nr;
- tmp = &cmd[0].i;
- cmd += 3;
-
- for (i = 0 ; i < nr ; i++) {
- if (i & 1) {
- cmd[0].i |= ((component[i]->aos_stride << 24) |
- (component[i]->aos_size << 16));
- cmd[2].i = (component[i]->aos_start +
- offset * component[i]->aos_stride * 4);
- cmd += 3;
- }
- else {
- cmd[0].i = ((component[i]->aos_stride << 8) |
- (component[i]->aos_size << 0));
- cmd[1].i = (component[i]->aos_start +
- offset * component[i]->aos_stride * 4);
- }
- }
-
- if (RADEON_DEBUG & DEBUG_VERTS) {
- fprintf(stderr, "%s:\n", __FUNCTION__);
- for (i = 0 ; i < sz ; i++)
- fprintf(stderr, " %d: %x\n", i, tmp[i]);
- }
-#endif
-}
-
-/* using already shifted color_fmt! */
-void radeonEmitBlit( radeonContextPtr rmesa, /* FIXME: which drmMinor is required? */
- GLuint color_fmt,
- GLuint src_pitch,
- GLuint src_offset,
- GLuint dst_pitch,
- GLuint dst_offset,
- GLint srcx, GLint srcy,
- GLint dstx, GLint dsty,
- GLuint w, GLuint h )
-{
- drm_radeon_cmd_header_t *cmd;
-
- if (RADEON_DEBUG & DEBUG_IOCTL)
- fprintf(stderr, "%s src %x/%x %d,%d dst: %x/%x %d,%d sz: %dx%d\n",
- __FUNCTION__,
- src_pitch, src_offset, srcx, srcy,
- dst_pitch, dst_offset, dstx, dsty,
- w, h);
-
- assert( (src_pitch & 63) == 0 );
- assert( (dst_pitch & 63) == 0 );
- assert( (src_offset & 1023) == 0 );
- assert( (dst_offset & 1023) == 0 );
- assert( w < (1<<16) );
- assert( h < (1<<16) );
-
- cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa, 8 * sizeof(int),
- __FUNCTION__ );
-
-
- cmd[0].i = 0;
- cmd[0].header.cmd_type = RADEON_CMD_PACKET3;
- cmd[1].i = RADEON_CP_PACKET3_CNTL_BITBLT_MULTI | (5 << 16);
- cmd[2].i = (RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
- RADEON_GMC_DST_PITCH_OFFSET_CNTL |
- RADEON_GMC_BRUSH_NONE |
- color_fmt |
- RADEON_GMC_SRC_DATATYPE_COLOR |
- RADEON_ROP3_S |
- RADEON_DP_SRC_SOURCE_MEMORY |
- RADEON_GMC_CLR_CMP_CNTL_DIS |
- RADEON_GMC_WR_MSK_DIS );
-
- cmd[3].i = ((src_pitch/64)<<22) | (src_offset >> 10);
- cmd[4].i = ((dst_pitch/64)<<22) | (dst_offset >> 10);
- cmd[5].i = (srcx << 16) | srcy;
- cmd[6].i = (dstx << 16) | dsty; /* dst */
- cmd[7].i = (w << 16) | h;
-}
-
-
-void radeonEmitWait( radeonContextPtr rmesa, GLuint flags )
-{
- if (rmesa->dri.drmMinor >= 6) {
- drm_radeon_cmd_header_t *cmd;
-
- assert( !(flags & ~(RADEON_WAIT_2D|RADEON_WAIT_3D)) );
-
- cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa, 1 * sizeof(int),
- __FUNCTION__ );
- cmd[0].i = 0;
- cmd[0].wait.cmd_type = RADEON_CMD_WAIT;
- cmd[0].wait.flags = flags;
- }
-}
-
-
-static int radeonFlushCmdBufLocked( radeonContextPtr rmesa,
- const char * caller )
-{
- int ret, i;
- drm_radeon_cmd_buffer_t cmd;
-
- if (rmesa->lost_context)
- radeonBackUpAndEmitLostStateLocked(rmesa);
-
- if (RADEON_DEBUG & DEBUG_IOCTL) {
- fprintf(stderr, "%s from %s\n", __FUNCTION__, caller);
-
- if (RADEON_DEBUG & DEBUG_VERBOSE)
- for (i = 0 ; i < rmesa->store.cmd_used ; i += 4 )
- fprintf(stderr, "%d: %x\n", i/4,
- *(int *)(&rmesa->store.cmd_buf[i]));
- }
-
- if (RADEON_DEBUG & DEBUG_DMA)
- fprintf(stderr, "%s: Releasing %d buffers\n", __FUNCTION__,
- rmesa->dma.nr_released_bufs);
-
-
- if (RADEON_DEBUG & DEBUG_SANITY) {
- if (rmesa->state.scissor.enabled)
- ret = radeonSanityCmdBuffer( rmesa,
- rmesa->state.scissor.numClipRects,
- rmesa->state.scissor.pClipRects);
- else
- ret = radeonSanityCmdBuffer( rmesa,
- rmesa->numClipRects,
- rmesa->pClipRects);
- if (ret) {
- fprintf(stderr, "drmSanityCommandWrite: %d\n", ret);
- goto out;
- }
- }
-
-
- cmd.bufsz = rmesa->store.cmd_used;
- cmd.buf = rmesa->store.cmd_buf;
-
- if (rmesa->state.scissor.enabled) {
- cmd.nbox = rmesa->state.scissor.numClipRects;
- cmd.boxes = rmesa->state.scissor.pClipRects;
- } else {
- cmd.nbox = rmesa->numClipRects;
- cmd.boxes = rmesa->pClipRects;
- }
-
- ret = drmCommandWrite( rmesa->dri.fd,
- DRM_RADEON_CMDBUF,
- &cmd, sizeof(cmd) );
-
- if (ret)
- fprintf(stderr, "drmCommandWrite: %d\n", ret);
-
- if (RADEON_DEBUG & DEBUG_SYNC) {
- fprintf(stderr, "\nSyncing in %s\n\n", __FUNCTION__);
- radeonWaitForIdleLocked( rmesa );
- }
-
- out:
- rmesa->store.primnr = 0;
- rmesa->store.statenr = 0;
- rmesa->store.cmd_used = 0;
- rmesa->dma.nr_released_bufs = 0;
- rmesa->save_on_next_emit = 1;
-
- return ret;
-}
-
-
-/* Note: does not emit any commands to avoid recursion on
- * radeonAllocCmdBuf.
- */
-void radeonFlushCmdBuf( radeonContextPtr rmesa, const char *caller )
-{
- int ret;
-
-
- LOCK_HARDWARE( rmesa );
-
- ret = radeonFlushCmdBufLocked( rmesa, caller );
-
- UNLOCK_HARDWARE( rmesa );
-
- if (ret) {
- fprintf(stderr, "drm_radeon_cmd_buffer_t: %d (exiting)\n", ret);
- exit(ret);
- }
-}
-
-/* =============================================================
- * Hardware vertex buffer handling
- */
-
-
-void radeonRefillCurrentDmaRegion( radeonContextPtr rmesa )
-{
- struct radeon_dma_buffer *dmabuf;
- int fd = rmesa->dri.fd;
- int index = 0;
- int size = 0;
- drmDMAReq dma;
- int ret;
-
- if (RADEON_DEBUG & (DEBUG_IOCTL|DEBUG_DMA))
- fprintf(stderr, "%s\n", __FUNCTION__);
-
- if (rmesa->dma.flush) {
- rmesa->dma.flush( rmesa );
- }
-
- if (rmesa->dma.current.buf)
- radeonReleaseDmaRegion( rmesa, &rmesa->dma.current, __FUNCTION__ );
-
- if (rmesa->dma.nr_released_bufs > 4)
- radeonFlushCmdBuf( rmesa, __FUNCTION__ );
-
- dma.context = rmesa->dri.hwContext;
- dma.send_count = 0;
- dma.send_list = NULL;
- dma.send_sizes = NULL;
- dma.flags = 0;
- dma.request_count = 1;
- dma.request_size = RADEON_BUFFER_SIZE;
- dma.request_list = &index;
- dma.request_sizes = &size;
- dma.granted_count = 0;
-
- LOCK_HARDWARE(rmesa); /* no need to validate */
-
- ret = drmDMA( fd, &dma );
-
- if (ret != 0) {
- /* Free some up this way?
- */
- if (rmesa->dma.nr_released_bufs) {
- radeonFlushCmdBufLocked( rmesa, __FUNCTION__ );
- }
-
- if (RADEON_DEBUG & DEBUG_DMA)
- fprintf(stderr, "Waiting for buffers\n");
-
- radeonWaitForIdleLocked( rmesa );
- ret = drmDMA( fd, &dma );
-
- if ( ret != 0 ) {
- UNLOCK_HARDWARE( rmesa );
- fprintf( stderr, "Error: Could not get dma buffer... exiting\n" );
- exit( -1 );
- }
- }
-
- UNLOCK_HARDWARE(rmesa);
-
- if (RADEON_DEBUG & DEBUG_DMA)
- fprintf(stderr, "Allocated buffer %d\n", index);
-
- dmabuf = CALLOC_STRUCT( radeon_dma_buffer );
- dmabuf->buf = &rmesa->radeonScreen->buffers->list[index];
- dmabuf->refcount = 1;
-
- rmesa->dma.current.buf = dmabuf;
- rmesa->dma.current.address = dmabuf->buf->address;
- rmesa->dma.current.end = dmabuf->buf->total;
- rmesa->dma.current.start = 0;
- rmesa->dma.current.ptr = 0;
-
- rmesa->c_vertexBuffers++;
-}
-
-void radeonReleaseDmaRegion( radeonContextPtr rmesa,
- struct radeon_dma_region *region,
- const char *caller )
-{
- if (RADEON_DEBUG & DEBUG_IOCTL)
- fprintf(stderr, "%s from %s\n", __FUNCTION__, caller);
-
- if (!region->buf)
- return;
-
- if (rmesa->dma.flush)
- rmesa->dma.flush( rmesa );
-
- if (--region->buf->refcount == 0) {
- drm_radeon_cmd_header_t *cmd;
-
- if (RADEON_DEBUG & (DEBUG_IOCTL|DEBUG_DMA))
- fprintf(stderr, "%s -- DISCARD BUF %d\n", __FUNCTION__,
- region->buf->buf->idx);
-
- cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa, sizeof(*cmd),
- __FUNCTION__ );
- cmd->dma.cmd_type = RADEON_CMD_DMA_DISCARD;
- cmd->dma.buf_idx = region->buf->buf->idx;
- FREE(region->buf);
- rmesa->dma.nr_released_bufs++;
- }
-
- region->buf = NULL;
- region->start = 0;
-}
-
-/* Allocates a region from rmesa->dma.current. If there isn't enough
- * space in current, grab a new buffer (and discard what was left of current)
- */
-void radeonAllocDmaRegion( radeonContextPtr rmesa,
- struct radeon_dma_region *region,
- int bytes,
- int alignment )
-{
- if (RADEON_DEBUG & DEBUG_IOCTL)
- fprintf(stderr, "%s %d\n", __FUNCTION__, bytes);
-
- if (rmesa->dma.flush)
- rmesa->dma.flush( rmesa );
-
- if (region->buf)
- radeonReleaseDmaRegion( rmesa, region, __FUNCTION__ );
-
- alignment--;
- rmesa->dma.current.start = rmesa->dma.current.ptr =
- (rmesa->dma.current.ptr + alignment) & ~alignment;
-
- if ( rmesa->dma.current.ptr + bytes > rmesa->dma.current.end )
- radeonRefillCurrentDmaRegion( rmesa );
-
- region->start = rmesa->dma.current.start;
- region->ptr = rmesa->dma.current.start;
- region->end = rmesa->dma.current.start + bytes;
- region->address = rmesa->dma.current.address;
- region->buf = rmesa->dma.current.buf;
- region->buf->refcount++;
-
- rmesa->dma.current.ptr += bytes; /* bug - if alignment > 7 */
- rmesa->dma.current.start =
- rmesa->dma.current.ptr = (rmesa->dma.current.ptr + 0x7) & ~0x7;
-}
-
-void radeonAllocDmaRegionVerts( radeonContextPtr rmesa,
- struct radeon_dma_region *region,
- int numverts,
- int vertsize,
- int alignment )
-{
- radeonAllocDmaRegion( rmesa, region, vertsize * numverts, alignment );
-}
-
-/* ================================================================
- * SwapBuffers with client-side throttling
- */
-
-static u_int32_t radeonGetLastFrame (radeonContextPtr rmesa)
-{
- unsigned char *RADEONMMIO = rmesa->radeonScreen->mmio.map;
- int ret;
- u_int32_t frame;
-
- if (rmesa->dri.screen->drmMinor >= 4) {
- drm_radeon_getparam_t gp;
-
- gp.param = RADEON_PARAM_LAST_FRAME;
- gp.value = (int *)&frame;
- ret = drmCommandWriteRead( rmesa->dri.fd, DRM_RADEON_GETPARAM,
- &gp, sizeof(gp) );
- }
- else
- ret = -EINVAL;
-
- if ( ret == -EINVAL ) {
- frame = INREG( RADEON_LAST_FRAME_REG );
- ret = 0;
- }
- if ( ret ) {
- fprintf( stderr, "%s: drm_radeon_getparam_t: %d\n", __FUNCTION__, ret );
- exit(1);
- }
-
- return frame;
-}
-
-static void radeonEmitIrqLocked( radeonContextPtr rmesa )
-{
- drm_radeon_irq_emit_t ie;
- int ret;
-
- ie.irq_seq = &rmesa->iw.irq_seq;
- ret = drmCommandWriteRead( rmesa->dri.fd, DRM_RADEON_IRQ_EMIT,
- &ie, sizeof(ie) );
- if ( ret ) {
- fprintf( stderr, "%s: drm_radeon_irq_emit_t: %d\n", __FUNCTION__, ret );
- exit(1);
- }
-}
-
-
-static void radeonWaitIrq( radeonContextPtr rmesa )
-{
- int ret;
-
- do {
- ret = drmCommandWrite( rmesa->dri.fd, DRM_RADEON_IRQ_WAIT,
- &rmesa->iw, sizeof(rmesa->iw) );
- } while (ret && (errno == EINTR || errno == EAGAIN));
-
- if ( ret ) {
- fprintf( stderr, "%s: drmRadeonIrqWait: %d\n", __FUNCTION__, ret );
- exit(1);
- }
-}
-
-
-static void radeonWaitForFrameCompletion( radeonContextPtr rmesa )
-{
- drm_radeon_sarea_t *sarea = rmesa->sarea;
-
- if (rmesa->do_irqs) {
- if (radeonGetLastFrame(rmesa) < sarea->last_frame) {
- if (!rmesa->irqsEmitted) {
- while (radeonGetLastFrame (rmesa) < sarea->last_frame)
- ;
- }
- else {
- UNLOCK_HARDWARE( rmesa );
- radeonWaitIrq( rmesa );
- LOCK_HARDWARE( rmesa );
- }
- rmesa->irqsEmitted = 10;
- }
-
- if (rmesa->irqsEmitted) {
- radeonEmitIrqLocked( rmesa );
- rmesa->irqsEmitted--;
- }
- }
- else {
- while (radeonGetLastFrame (rmesa) < sarea->last_frame) {
- UNLOCK_HARDWARE( rmesa );
- if (rmesa->do_usleeps)
- DO_USLEEP( 1 );
- LOCK_HARDWARE( rmesa );
- }
- }
-}
-
-/* Copy the back color buffer to the front color buffer.
- */
-void radeonCopyBuffer( const __DRIdrawablePrivate *dPriv )
-{
- radeonContextPtr rmesa;
- GLint nbox, i, ret;
- GLboolean missed_target;
- int64_t ust;
-
- assert(dPriv);
- assert(dPriv->driContextPriv);
- assert(dPriv->driContextPriv->driverPrivate);
-
- rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate;
-
- if ( RADEON_DEBUG & DEBUG_IOCTL ) {
- fprintf( stderr, "\n%s( %p )\n\n", __FUNCTION__, (void *) rmesa->glCtx );
- }
-
- RADEON_FIREVERTICES( rmesa );
- LOCK_HARDWARE( rmesa );
-
- /* Throttle the frame rate -- only allow one pending swap buffers
- * request at a time.
- */
- radeonWaitForFrameCompletion( rmesa );
- UNLOCK_HARDWARE( rmesa );
- driWaitForVBlank( dPriv, & rmesa->vbl_seq, rmesa->vblank_flags, & missed_target );
- LOCK_HARDWARE( rmesa );
-
- nbox = dPriv->numClipRects; /* must be in locked region */
-
- for ( i = 0 ; i < nbox ; ) {
- GLint nr = MIN2( i + RADEON_NR_SAREA_CLIPRECTS , nbox );
- drm_clip_rect_t *box = dPriv->pClipRects;
- drm_clip_rect_t *b = rmesa->sarea->boxes;
- GLint n = 0;
-
- for ( ; i < nr ; i++ ) {
- *b++ = box[i];
- n++;
- }
- rmesa->sarea->nbox = n;
-
- ret = drmCommandNone( rmesa->dri.fd, DRM_RADEON_SWAP );
-
- if ( ret ) {
- fprintf( stderr, "DRM_RADEON_SWAP_BUFFERS: return = %d\n", ret );
- UNLOCK_HARDWARE( rmesa );
- exit( 1 );
- }
- }
-
- UNLOCK_HARDWARE( rmesa );
- rmesa->swap_count++;
- (*dri_interface->getUST)( & ust );
- if ( missed_target ) {
- rmesa->swap_missed_count++;
- rmesa->swap_missed_ust = ust - rmesa->swap_ust;
- }
-
- rmesa->swap_ust = ust;
- rmesa->hw.all_dirty = GL_TRUE;
-}
-
-void radeonPageFlip( const __DRIdrawablePrivate *dPriv )
-{
- radeonContextPtr rmesa;
- GLint ret;
- GLboolean missed_target;
-
- assert(dPriv);
- assert(dPriv->driContextPriv);
- assert(dPriv->driContextPriv->driverPrivate);
-
- rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate;
-
- if ( RADEON_DEBUG & DEBUG_IOCTL ) {
- fprintf(stderr, "%s: pfCurrentPage: %d\n", __FUNCTION__,
- rmesa->sarea->pfCurrentPage);
- }
-
- RADEON_FIREVERTICES( rmesa );
- LOCK_HARDWARE( rmesa );
-
- /* Need to do this for the perf box placement:
- */
- if (dPriv->numClipRects)
- {
- drm_clip_rect_t *box = dPriv->pClipRects;
- drm_clip_rect_t *b = rmesa->sarea->boxes;
- b[0] = box[0];
- rmesa->sarea->nbox = 1;
- }
-
- /* Throttle the frame rate -- only allow a few pending swap buffers
- * request at a time.
- */
- radeonWaitForFrameCompletion( rmesa );
- UNLOCK_HARDWARE( rmesa );
- driWaitForVBlank( dPriv, & rmesa->vbl_seq, rmesa->vblank_flags, & missed_target );
- if ( missed_target ) {
- rmesa->swap_missed_count++;
- (void) (*dri_interface->getUST)( & rmesa->swap_missed_ust );
- }
- LOCK_HARDWARE( rmesa );
-
- ret = drmCommandNone( rmesa->dri.fd, DRM_RADEON_FLIP );
-
- UNLOCK_HARDWARE( rmesa );
-
- if ( ret ) {
- fprintf( stderr, "DRM_RADEON_FLIP: return = %d\n", ret );
- exit( 1 );
- }
-
- rmesa->swap_count++;
- (void) (*dri_interface->getUST)( & rmesa->swap_ust );
-
- if ( rmesa->sarea->pfCurrentPage == 1 ) {
- rmesa->state.color.drawOffset = rmesa->radeonScreen->frontOffset;
- rmesa->state.color.drawPitch = rmesa->radeonScreen->frontPitch;
- } else {
- rmesa->state.color.drawOffset = rmesa->radeonScreen->backOffset;
- rmesa->state.color.drawPitch = rmesa->radeonScreen->backPitch;
- }
-
- RADEON_STATECHANGE( rmesa, ctx );
- rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = rmesa->state.color.drawOffset
- + rmesa->radeonScreen->fbLocation;
- rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = rmesa->state.color.drawPitch;
- if (rmesa->sarea->tiling_enabled) {
- rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= RADEON_COLOR_TILE_ENABLE;
- }
-}
-
-
-/* ================================================================
- * Buffer clear
- */
-#define RADEON_MAX_CLEARS 256
-
-static void radeonClear( GLcontext *ctx, GLbitfield mask, GLboolean all,
- GLint cx, GLint cy, GLint cw, GLint ch )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- __DRIdrawablePrivate *dPriv = rmesa->dri.drawable;
- drm_radeon_sarea_t *sarea = rmesa->sarea;
- unsigned char *RADEONMMIO = rmesa->radeonScreen->mmio.map;
- u_int32_t clear;
- GLuint flags = 0;
- GLuint color_mask = 0;
- GLint ret, i;
-
- if ( RADEON_DEBUG & DEBUG_IOCTL ) {
- fprintf( stderr, "%s: all=%d cx=%d cy=%d cw=%d ch=%d\n",
- __FUNCTION__, all, cx, cy, cw, ch );
- }
-
- {
- LOCK_HARDWARE( rmesa );
- UNLOCK_HARDWARE( rmesa );
- if ( dPriv->numClipRects == 0 )
- return;
- }
-
- radeonFlush( ctx );
-
- if ( mask & BUFFER_BIT_FRONT_LEFT ) {
- flags |= RADEON_FRONT;
- color_mask = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK];
- mask &= ~BUFFER_BIT_FRONT_LEFT;
- }
-
- if ( mask & BUFFER_BIT_BACK_LEFT ) {
- flags |= RADEON_BACK;
- color_mask = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK];
- mask &= ~BUFFER_BIT_BACK_LEFT;
- }
-
- if ( mask & BUFFER_BIT_DEPTH ) {
- flags |= RADEON_DEPTH;
- mask &= ~BUFFER_BIT_DEPTH;
- }
-
- if ( (mask & BUFFER_BIT_STENCIL) && rmesa->state.stencil.hwBuffer ) {
- flags |= RADEON_STENCIL;
- mask &= ~BUFFER_BIT_STENCIL;
- }
-
- if ( mask ) {
- if (RADEON_DEBUG & DEBUG_FALLBACKS)
- fprintf(stderr, "%s: swrast clear, mask: %x\n", __FUNCTION__, mask);
- _swrast_Clear( ctx, mask, all, cx, cy, cw, ch );
- }
-
- if ( !flags )
- return;
-
- if (rmesa->using_hyperz) {
- flags |= RADEON_USE_COMP_ZBUF;
-/* if (rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL)
- flags |= RADEON_USE_HIERZ; */
- if (!(rmesa->state.stencil.hwBuffer) ||
- ((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) &&
- ((rmesa->state.stencil.clear & RADEON_STENCIL_WRITE_MASK) == RADEON_STENCIL_WRITE_MASK))) {
- flags |= RADEON_CLEAR_FASTZ;
- }
- }
-
- /* Flip top to bottom */
- cx += dPriv->x;
- cy = dPriv->y + dPriv->h - cy - ch;
-
- LOCK_HARDWARE( rmesa );
-
- /* Throttle the number of clear ioctls we do.
- */
- while ( 1 ) {
- int ret;
-
- if (rmesa->dri.screen->drmMinor >= 4) {
- drm_radeon_getparam_t gp;
-
- gp.param = RADEON_PARAM_LAST_CLEAR;
- gp.value = (int *)&clear;
- ret = drmCommandWriteRead( rmesa->dri.fd,
- DRM_RADEON_GETPARAM, &gp, sizeof(gp) );
- } else
- ret = -EINVAL;
-
- if ( ret == -EINVAL ) {
- clear = INREG( RADEON_LAST_CLEAR_REG );
- ret = 0;
- }
- if ( ret ) {
- fprintf( stderr, "%s: drm_radeon_getparam_t: %d\n", __FUNCTION__, ret );
- exit(1);
- }
- if ( RADEON_DEBUG & DEBUG_IOCTL ) {
- fprintf( stderr, "%s( %d )\n", __FUNCTION__, (int)clear );
- if ( ret ) fprintf( stderr, " ( RADEON_LAST_CLEAR register read directly )\n" );
- }
-
- if ( sarea->last_clear - clear <= RADEON_MAX_CLEARS ) {
- break;
- }
-
- if ( rmesa->do_usleeps ) {
- UNLOCK_HARDWARE( rmesa );
- DO_USLEEP( 1 );
- LOCK_HARDWARE( rmesa );
- }
- }
-
- /* Send current state to the hardware */
- radeonFlushCmdBufLocked( rmesa, __FUNCTION__ );
-
- for ( i = 0 ; i < dPriv->numClipRects ; ) {
- GLint nr = MIN2( i + RADEON_NR_SAREA_CLIPRECTS, dPriv->numClipRects );
- drm_clip_rect_t *box = dPriv->pClipRects;
- drm_clip_rect_t *b = rmesa->sarea->boxes;
- drm_radeon_clear_t clear;
- drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS];
- GLint n = 0;
-
- if ( !all ) {
- for ( ; i < nr ; i++ ) {
- GLint x = box[i].x1;
- GLint y = box[i].y1;
- GLint w = box[i].x2 - x;
- GLint h = box[i].y2 - y;
-
- if ( x < cx ) w -= cx - x, x = cx;
- if ( y < cy ) h -= cy - y, y = cy;
- if ( x + w > cx + cw ) w = cx + cw - x;
- if ( y + h > cy + ch ) h = cy + ch - y;
- if ( w <= 0 ) continue;
- if ( h <= 0 ) continue;
-
- b->x1 = x;
- b->y1 = y;
- b->x2 = x + w;
- b->y2 = y + h;
- b++;
- n++;
- }
- } else {
- for ( ; i < nr ; i++ ) {
- *b++ = box[i];
- n++;
- }
- }
-
- rmesa->sarea->nbox = n;
-
- clear.flags = flags;
- clear.clear_color = rmesa->state.color.clear;
- clear.clear_depth = rmesa->state.depth.clear;
- clear.color_mask = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK];
- clear.depth_mask = rmesa->state.stencil.clear;
- clear.depth_boxes = depth_boxes;
-
- n--;
- b = rmesa->sarea->boxes;
- for ( ; n >= 0 ; n-- ) {
- depth_boxes[n].f[CLEAR_X1] = (float)b[n].x1;
- depth_boxes[n].f[CLEAR_Y1] = (float)b[n].y1;
- depth_boxes[n].f[CLEAR_X2] = (float)b[n].x2;
- depth_boxes[n].f[CLEAR_Y2] = (float)b[n].y2;
- depth_boxes[n].f[CLEAR_DEPTH] =
- (float)rmesa->state.depth.clear;
- }
-
- ret = drmCommandWrite( rmesa->dri.fd, DRM_RADEON_CLEAR,
- &clear, sizeof(drm_radeon_clear_t));
-
- if ( ret ) {
- UNLOCK_HARDWARE( rmesa );
- fprintf( stderr, "DRM_RADEON_CLEAR: return = %d\n", ret );
- exit( 1 );
- }
- }
-
- UNLOCK_HARDWARE( rmesa );
- rmesa->hw.all_dirty = GL_TRUE;
-}
-
-
-void radeonWaitForIdleLocked( radeonContextPtr rmesa )
-{
- int fd = rmesa->dri.fd;
- int to = 0;
- int ret, i = 0;
-
- rmesa->c_drawWaits++;
-
- do {
- do {
- ret = drmCommandNone( fd, DRM_RADEON_CP_IDLE);
- } while ( ret && errno == EBUSY && i++ < RADEON_IDLE_RETRY );
- } while ( ( ret == -EBUSY ) && ( to++ < RADEON_TIMEOUT ) );
-
- if ( ret < 0 ) {
- UNLOCK_HARDWARE( rmesa );
- fprintf( stderr, "Error: Radeon timed out... exiting\n" );
- exit( -1 );
- }
-}
-
-
-static void radeonWaitForIdle( radeonContextPtr rmesa )
-{
- LOCK_HARDWARE(rmesa);
- radeonWaitForIdleLocked( rmesa );
- UNLOCK_HARDWARE(rmesa);
-}
-
-
-void radeonFlush( GLcontext *ctx )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
-
- if (RADEON_DEBUG & DEBUG_IOCTL)
- fprintf(stderr, "%s\n", __FUNCTION__);
-
- if (rmesa->dma.flush)
- rmesa->dma.flush( rmesa );
-
- radeonEmitState( rmesa );
-
- if (rmesa->store.cmd_used)
- radeonFlushCmdBuf( rmesa, __FUNCTION__ );
-}
-
-/* Make sure all commands have been sent to the hardware and have
- * completed processing.
- */
-void radeonFinish( GLcontext *ctx )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- radeonFlush( ctx );
-
- if (rmesa->do_irqs) {
- LOCK_HARDWARE( rmesa );
- radeonEmitIrqLocked( rmesa );
- UNLOCK_HARDWARE( rmesa );
- radeonWaitIrq( rmesa );
- }
- else
- radeonWaitForIdle( rmesa );
-}
-
-
-void radeonInitIoctlFuncs( GLcontext *ctx )
-{
- ctx->Driver.Clear = radeonClear;
- ctx->Driver.Finish = radeonFinish;
- ctx->Driver.Flush = radeonFlush;
-}
-
diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_ioctl.h b/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_ioctl.h
deleted file mode 100644
index 8b21920c5..000000000
--- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_ioctl.h
+++ /dev/null
@@ -1,217 +0,0 @@
-/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_ioctl.h,v 1.6 2002/12/16 16:18:58 dawes Exp $ */
-/**************************************************************************
-
-Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
- VA Linux Systems Inc., Fremont, California.
-
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/*
- * Authors:
- * Kevin E. Martin <martin@valinux.com>
- * Gareth Hughes <gareth@valinux.com>
- */
-
-#ifndef __RADEON_IOCTL_H__
-#define __RADEON_IOCTL_H__
-
-#include "simple_list.h"
-#include "radeon_lock.h"
-
-
-extern void radeonEmitState( radeonContextPtr rmesa );
-extern void radeonEmitVertexAOS( radeonContextPtr rmesa,
- GLuint vertex_size,
- GLuint offset );
-
-extern void radeonEmitVbufPrim( radeonContextPtr rmesa,
- GLuint vertex_format,
- GLuint primitive,
- GLuint vertex_nr );
-
-extern void radeonFlushElts( radeonContextPtr rmesa );
-
-extern GLushort *radeonAllocEltsOpenEnded( radeonContextPtr rmesa,
- GLuint vertex_format,
- GLuint primitive,
- GLuint min_nr );
-
-extern void radeonEmitAOS( radeonContextPtr rmesa,
- struct radeon_dma_region **regions,
- GLuint n,
- GLuint offset );
-
-extern void radeonEmitBlit( radeonContextPtr rmesa,
- GLuint color_fmt,
- GLuint src_pitch,
- GLuint src_offset,
- GLuint dst_pitch,
- GLuint dst_offset,
- GLint srcx, GLint srcy,
- GLint dstx, GLint dsty,
- GLuint w, GLuint h );
-
-extern void radeonEmitWait( radeonContextPtr rmesa, GLuint flags );
-
-extern void radeonFlushCmdBuf( radeonContextPtr rmesa, const char * );
-extern void radeonRefillCurrentDmaRegion( radeonContextPtr rmesa );
-
-extern void radeonAllocDmaRegion( radeonContextPtr rmesa,
- struct radeon_dma_region *region,
- int bytes,
- int alignment );
-
-extern void radeonAllocDmaRegionVerts( radeonContextPtr rmesa,
- struct radeon_dma_region *region,
- int numverts,
- int vertsize,
- int alignment );
-
-extern void radeonReleaseDmaRegion( radeonContextPtr rmesa,
- struct radeon_dma_region *region,
- const char *caller );
-
-extern void radeonCopyBuffer( const __DRIdrawablePrivate *drawable );
-extern void radeonPageFlip( const __DRIdrawablePrivate *drawable );
-extern void radeonFlush( GLcontext *ctx );
-extern void radeonFinish( GLcontext *ctx );
-extern void radeonWaitForIdleLocked( radeonContextPtr rmesa );
-extern void radeonWaitForVBlank( radeonContextPtr rmesa );
-extern void radeonInitIoctlFuncs( GLcontext *ctx );
-extern void radeonGetAllParams( radeonContextPtr rmesa );
-extern void radeonSetUpAtomList( radeonContextPtr rmesa );
-
-/* radeon_compat.c:
- */
-extern void radeonCompatEmitPrimitive( radeonContextPtr rmesa,
- GLuint vertex_format,
- GLuint hw_primitive,
- GLuint nrverts );
-
-/* ================================================================
- * Helper macros:
- */
-
-/* Close off the last primitive, if it exists.
- */
-#define RADEON_NEWPRIM( rmesa ) \
-do { \
- if ( rmesa->dma.flush ) \
- rmesa->dma.flush( rmesa ); \
-} while (0)
-
-/* Can accomodate several state changes and primitive changes without
- * actually firing the buffer.
- */
-#define RADEON_STATECHANGE( rmesa, ATOM ) \
-do { \
- RADEON_NEWPRIM( rmesa ); \
- rmesa->hw.ATOM.dirty = GL_TRUE; \
- rmesa->hw.is_dirty = GL_TRUE; \
-} while (0)
-
-#define RADEON_DB_STATE( ATOM ) \
- memcpy( rmesa->hw.ATOM.lastcmd, rmesa->hw.ATOM.cmd, \
- rmesa->hw.ATOM.cmd_size * 4)
-
-static __inline int RADEON_DB_STATECHANGE(
- radeonContextPtr rmesa,
- struct radeon_state_atom *atom )
-{
- if (memcmp(atom->cmd, atom->lastcmd, atom->cmd_size*4)) {
- int *tmp;
- RADEON_NEWPRIM( rmesa );
- atom->dirty = GL_TRUE;
- rmesa->hw.is_dirty = GL_TRUE;
- tmp = atom->cmd;
- atom->cmd = atom->lastcmd;
- atom->lastcmd = tmp;
- return 1;
- }
- else
- return 0;
-}
-
-
-/* Fire the buffered vertices no matter what.
- */
-#define RADEON_FIREVERTICES( rmesa ) \
-do { \
- if ( rmesa->store.cmd_used || rmesa->dma.flush ) { \
- radeonFlush( rmesa->glCtx ); \
- } \
-} while (0)
-
-/* Command lengths. Note that any time you ensure ELTS_BUFSZ or VBUF_BUFSZ
- * are available, you will also be adding an rmesa->state.max_state_size because
- * r200EmitState is called from within r200EmitVbufPrim and r200FlushElts.
- */
-#if RADEON_OLD_PACKETS
-#define AOS_BUFSZ(nr) ((3 + ((nr / 2) * 3) + ((nr & 1) * 2)) * sizeof(int))
-#define VERT_AOS_BUFSZ (0)
-#define ELTS_BUFSZ(nr) (24 + nr * 2)
-#define VBUF_BUFSZ (6 * sizeof(int))
-#else
-#define AOS_BUFSZ(nr) ((3 + ((nr / 2) * 3) + ((nr & 1) * 2)) * sizeof(int))
-#define VERT_AOS_BUFSZ (5 * sizeof(int))
-#define ELTS_BUFSZ(nr) (16 + nr * 2)
-#define VBUF_BUFSZ (4 * sizeof(int))
-#endif
-
-/* Ensure that a minimum amount of space is available in the command buffer.
- * This is used to ensure atomicity of state updates with the rendering requests
- * that rely on them.
- *
- * An alternative would be to implement a "soft lock" such that when the buffer
- * wraps at an inopportune time, we grab the lock, flush the current buffer,
- * and hang on to the lock until the critical section is finished and we flush
- * the buffer again and unlock.
- */
-static __inline void radeonEnsureCmdBufSpace( radeonContextPtr rmesa,
- int bytes )
-{
- if (rmesa->store.cmd_used + bytes > RADEON_CMD_BUF_SZ)
- radeonFlushCmdBuf( rmesa, __FUNCTION__ );
- assert( bytes <= RADEON_CMD_BUF_SZ );
-}
-
-/* Alloc space in the command buffer
- */
-static __inline char *radeonAllocCmdBuf( radeonContextPtr rmesa,
- int bytes, const char *where )
-{
- if (rmesa->store.cmd_used + bytes > RADEON_CMD_BUF_SZ)
- radeonFlushCmdBuf( rmesa, __FUNCTION__ );
-
- assert(rmesa->dri.drmMinor >= 3);
-
- {
- char *head = rmesa->store.cmd_buf + rmesa->store.cmd_used;
- rmesa->store.cmd_used += bytes;
- return head;
- }
-}
-
-#endif /* __RADEON_IOCTL_H__ */
diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_lighting.c b/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_lighting.c
deleted file mode 100644
index 44e00af0e..000000000
--- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_lighting.c
+++ /dev/null
@@ -1,682 +0,0 @@
-/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_state.c,v 1.5 2002/09/16 18:05:20 eich Exp $ */
-/*
- * Copyright 2000, 2001 VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * on the rights to use, copy, modify, merge, publish, distribute, sub
- * license, and/or sell copies of the Software, and to permit persons to whom
- * the Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Gareth Hughes <gareth@valinux.com>
- * Keith Whitwell <keith@tungstengraphics.com>
- */
-
-#include "glheader.h"
-#include "imports.h"
-#include "api_arrayelt.h"
-/* #include "mmath.h" */
-#include "enums.h"
-#include "colormac.h"
-
-
-#include "radeon_context.h"
-#include "radeon_ioctl.h"
-#include "radeon_state.h"
-#include "radeon_tcl.h"
-#include "radeon_tex.h"
-#include "radeon_vtxfmt.h"
-
-
-
-/* =============================================================
- * Materials
- */
-
-
-/* Update on colormaterial, material emmissive/ambient,
- * lightmodel.globalambient
- */
-void update_global_ambient( GLcontext *ctx )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- float *fcmd = (float *)RADEON_DB_STATE( glt );
-
- /* Need to do more if both emmissive & ambient are PREMULT:
- */
- if ((rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] &
- ((3 << RADEON_EMISSIVE_SOURCE_SHIFT) |
- (3 << RADEON_AMBIENT_SOURCE_SHIFT))) == 0)
- {
- COPY_3V( &fcmd[GLT_RED],
- ctx->Light.Material[0].Emission);
- ACC_SCALE_3V( &fcmd[GLT_RED],
- ctx->Light.Model.Ambient,
- ctx->Light.Material[0].Ambient);
- }
- else
- {
- COPY_3V( &fcmd[GLT_RED], ctx->Light.Model.Ambient );
- }
-
- RADEON_DB_STATECHANGE(rmesa, &rmesa->hw.glt);
-}
-
-/* Update on change to
- * - light[p].colors
- * - light[p].enabled
- * - material,
- * - colormaterial enabled
- * - colormaterial bitmask
- */
-void update_light_colors( GLcontext *ctx, GLuint p )
-{
- struct gl_light *l = &ctx->Light.Light[p];
-
-/* fprintf(stderr, "%s\n", __FUNCTION__); */
-
- if (l->Enabled) {
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- float *fcmd = (float *)RADEON_DB_STATE( lit[p] );
- GLuint bitmask = ctx->Light.ColorMaterialBitmask;
- struct gl_material *mat = &ctx->Light.Material[0];
-
- COPY_4V( &fcmd[LIT_AMBIENT_RED], l->Ambient );
- COPY_4V( &fcmd[LIT_DIFFUSE_RED], l->Diffuse );
- COPY_4V( &fcmd[LIT_SPECULAR_RED], l->Specular );
-
- if (!ctx->Light.ColorMaterialEnabled)
- bitmask = 0;
-
- if ((bitmask & FRONT_AMBIENT_BIT) == 0)
- SELF_SCALE_3V( &fcmd[LIT_AMBIENT_RED], mat->Ambient );
-
- if ((bitmask & FRONT_DIFFUSE_BIT) == 0)
- SELF_SCALE_3V( &fcmd[LIT_DIFFUSE_RED], mat->Diffuse );
-
- if ((bitmask & FRONT_SPECULAR_BIT) == 0)
- SELF_SCALE_3V( &fcmd[LIT_SPECULAR_RED], mat->Specular );
-
- RADEON_DB_STATECHANGE( rmesa, &rmesa->hw.lit[p] );
- }
-}
-
-/* Also fallback for asym colormaterial mode in twoside lighting...
- */
-void check_twoside_fallback( GLcontext *ctx )
-{
- GLboolean fallback = GL_FALSE;
-
- if (ctx->Light.Enabled && ctx->Light.Model.TwoSide) {
- if (memcmp( &ctx->Light.Material[0],
- &ctx->Light.Material[1],
- sizeof(struct gl_material)) != 0)
- fallback = GL_TRUE;
- else if (ctx->Light.ColorMaterialEnabled &&
- (ctx->Light.ColorMaterialBitmask & BACK_MATERIAL_BITS) !=
- ((ctx->Light.ColorMaterialBitmask & FRONT_MATERIAL_BITS)<<1))
- fallback = GL_TRUE;
- }
-
- TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_LIGHT_TWOSIDE, fallback );
-}
-
-void radeonColorMaterial( GLcontext *ctx, GLenum face, GLenum mode )
-{
- if (ctx->Light.ColorMaterialEnabled) {
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLuint light_model_ctl = rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL];
- GLuint mask = ctx->Light.ColorMaterialBitmask;
-
- /* Default to PREMULT:
- */
- light_model_ctl &= ~((3 << RADEON_EMISSIVE_SOURCE_SHIFT) |
- (3 << RADEON_AMBIENT_SOURCE_SHIFT) |
- (3 << RADEON_DIFFUSE_SOURCE_SHIFT) |
- (3 << RADEON_SPECULAR_SOURCE_SHIFT));
-
- if (mask & FRONT_EMISSION_BIT) {
- light_model_ctl |= (RADEON_LM_SOURCE_VERTEX_DIFFUSE <<
- RADEON_EMISSIVE_SOURCE_SHIFT);
- }
-
- if (mask & FRONT_AMBIENT_BIT) {
- light_model_ctl |= (RADEON_LM_SOURCE_VERTEX_DIFFUSE <<
- RADEON_AMBIENT_SOURCE_SHIFT);
- }
-
- if (mask & FRONT_DIFFUSE_BIT) {
- light_model_ctl |= (RADEON_LM_SOURCE_VERTEX_DIFFUSE <<
- RADEON_DIFFUSE_SOURCE_SHIFT);
- }
-
- if (mask & FRONT_SPECULAR_BIT) {
- light_model_ctl |= (RADEON_LM_SOURCE_VERTEX_DIFFUSE <<
- RADEON_SPECULAR_SOURCE_SHIFT);
- }
-
- if (light_model_ctl != rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL]) {
- GLuint p;
-
- RADEON_STATECHANGE( rmesa, tcl );
- rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] = light_model_ctl;
-
- for (p = 0 ; p < MAX_LIGHTS; p++)
- update_light_colors( ctx, p );
- update_global_ambient( ctx );
- }
- }
-
- check_twoside_fallback( ctx );
-}
-
-void radeonUpdateMaterial( GLcontext *ctx )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLfloat *fcmd = (GLfloat *)RADEON_DB_STATE( mtl );
- GLuint p;
- GLuint mask = ~0;
-
- if (ctx->Light.ColorMaterialEnabled)
- mask &= ~ctx->Light.ColorMaterialBitmask;
-
- if (RADEON_DEBUG & DEBUG_STATE)
- fprintf(stderr, "%s\n", __FUNCTION__);
-
-
- if (mask & FRONT_EMISSION_BIT) {
- fcmd[MTL_EMMISSIVE_RED] = ctx->Light.Material[0].Emission[0];
- fcmd[MTL_EMMISSIVE_GREEN] = ctx->Light.Material[0].Emission[1];
- fcmd[MTL_EMMISSIVE_BLUE] = ctx->Light.Material[0].Emission[2];
- fcmd[MTL_EMMISSIVE_ALPHA] = ctx->Light.Material[0].Emission[3];
- }
- if (mask & FRONT_AMBIENT_BIT) {
- fcmd[MTL_AMBIENT_RED] = ctx->Light.Material[0].Ambient[0];
- fcmd[MTL_AMBIENT_GREEN] = ctx->Light.Material[0].Ambient[1];
- fcmd[MTL_AMBIENT_BLUE] = ctx->Light.Material[0].Ambient[2];
- fcmd[MTL_AMBIENT_ALPHA] = ctx->Light.Material[0].Ambient[3];
- }
- if (mask & FRONT_DIFFUSE_BIT) {
- fcmd[MTL_DIFFUSE_RED] = ctx->Light.Material[0].Diffuse[0];
- fcmd[MTL_DIFFUSE_GREEN] = ctx->Light.Material[0].Diffuse[1];
- fcmd[MTL_DIFFUSE_BLUE] = ctx->Light.Material[0].Diffuse[2];
- fcmd[MTL_DIFFUSE_ALPHA] = ctx->Light.Material[0].Diffuse[3];
- }
- if (mask & FRONT_SPECULAR_BIT) {
- fcmd[MTL_SPECULAR_RED] = ctx->Light.Material[0].Specular[0];
- fcmd[MTL_SPECULAR_GREEN] = ctx->Light.Material[0].Specular[1];
- fcmd[MTL_SPECULAR_BLUE] = ctx->Light.Material[0].Specular[2];
- fcmd[MTL_SPECULAR_ALPHA] = ctx->Light.Material[0].Specular[3];
- }
- if (mask & FRONT_SHININESS_BIT) {
- fcmd[MTL_SHININESS] = ctx->Light.Material[0].Shininess;
- }
-
- if (RADEON_DB_STATECHANGE( rmesa, &rmesa->hw.mtl )) {
- for (p = 0 ; p < MAX_LIGHTS; p++)
- update_light_colors( ctx, p );
-
- check_twoside_fallback( ctx );
- update_global_ambient( ctx );
- }
- else if (RADEON_DEBUG & (DEBUG_PRIMS|DEBUG_STATE))
- fprintf(stderr, "%s: Elided noop material call\n", __FUNCTION__);
-}
-
-/* _NEW_LIGHT
- * _NEW_MODELVIEW
- * _MESA_NEW_NEED_EYE_COORDS
- *
- * Uses derived state from mesa:
- * _VP_inf_norm
- * _h_inf_norm
- * _Position
- * _NormDirection
- * _ModelViewInvScale
- * _NeedEyeCoords
- * _EyeZDir
- *
- * which are calculated in light.c and are correct for the current
- * lighting space (model or eye), hence dependencies on _NEW_MODELVIEW
- * and _MESA_NEW_NEED_EYE_COORDS.
- */
-void radeonUpdateLighting( GLcontext *ctx )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-
- /* Have to check these, or have an automatic shortcircuit mechanism
- * to remove noop statechanges. (Or just do a better job on the
- * front end).
- */
- {
- GLuint tmp = rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL];
-
- if (ctx->_NeedEyeCoords)
- tmp &= ~RADEON_LIGHT_IN_MODELSPACE;
- else
- tmp |= RADEON_LIGHT_IN_MODELSPACE;
-
-
- /* Leave this test disabled: (unexplained q3 lockup) (even with
- new packets)
- */
- if (tmp != rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL])
- {
- RADEON_STATECHANGE( rmesa, tcl );
- rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] = tmp;
- }
- }
-
- {
- GLfloat *fcmd = (GLfloat *)RADEON_DB_STATE( eye );
- fcmd[EYE_X] = ctx->_EyeZDir[0];
- fcmd[EYE_Y] = ctx->_EyeZDir[1];
- fcmd[EYE_Z] = - ctx->_EyeZDir[2];
- fcmd[EYE_RESCALE_FACTOR] = ctx->_ModelViewInvScale;
- RADEON_DB_STATECHANGE( rmesa, &rmesa->hw.eye );
- }
-
-
-/* RADEON_STATECHANGE( rmesa, glt ); */
-
- if (ctx->Light.Enabled) {
- GLint p;
- for (p = 0 ; p < MAX_LIGHTS; p++) {
- if (ctx->Light.Light[p].Enabled) {
- struct gl_light *l = &ctx->Light.Light[p];
- GLfloat *fcmd = (GLfloat *)RADEON_DB_STATE( lit[p] );
-
- if (l->EyePosition[3] == 0.0) {
- COPY_3FV( &fcmd[LIT_POSITION_X], l->_VP_inf_norm );
- COPY_3FV( &fcmd[LIT_DIRECTION_X], l->_h_inf_norm );
- fcmd[LIT_POSITION_W] = 0;
- fcmd[LIT_DIRECTION_W] = 0;
- } else {
- COPY_4V( &fcmd[LIT_POSITION_X], l->_Position );
- fcmd[LIT_DIRECTION_X] = -l->_NormDirection[0];
- fcmd[LIT_DIRECTION_Y] = -l->_NormDirection[1];
- fcmd[LIT_DIRECTION_Z] = -l->_NormDirection[2];
- fcmd[LIT_DIRECTION_W] = 0;
- }
-
- RADEON_DB_STATECHANGE( rmesa, &rmesa->hw.lit[p] );
- }
- }
- }
-}
-
-
-void radeonLightfv( GLcontext *ctx, GLenum light,
- GLenum pname, const GLfloat *params )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLint p = light - GL_LIGHT0;
- struct gl_light *l = &ctx->Light.Light[p];
- GLfloat *fcmd = (GLfloat *)rmesa->hw.lit[p].cmd;
-
-
- switch (pname) {
- case GL_AMBIENT:
- case GL_DIFFUSE:
- case GL_SPECULAR:
- update_light_colors( ctx, p );
- break;
-
- case GL_SPOT_DIRECTION:
- /* picked up in update_light */
- break;
-
- case GL_POSITION: {
- /* positions picked up in update_light, but can do flag here */
- GLuint flag = (p&1)? RADEON_LIGHT_1_IS_LOCAL : RADEON_LIGHT_0_IS_LOCAL;
- GLuint idx = TCL_PER_LIGHT_CTL_0 + p/2;
-
- RADEON_STATECHANGE(rmesa, tcl);
- if (l->EyePosition[3] != 0.0F)
- rmesa->hw.tcl.cmd[idx] |= flag;
- else
- rmesa->hw.tcl.cmd[idx] &= ~flag;
- break;
- }
-
- case GL_SPOT_EXPONENT:
- RADEON_STATECHANGE(rmesa, lit[p]);
- fcmd[LIT_SPOT_EXPONENT] = params[0];
- break;
-
- case GL_SPOT_CUTOFF: {
- GLuint flag = (p&1) ? RADEON_LIGHT_1_IS_SPOT : RADEON_LIGHT_0_IS_SPOT;
- GLuint idx = TCL_PER_LIGHT_CTL_0 + p/2;
-
- RADEON_STATECHANGE(rmesa, lit[p]);
- fcmd[LIT_SPOT_CUTOFF] = l->_CosCutoff;
-
- RADEON_STATECHANGE(rmesa, tcl);
- if (l->SpotCutoff != 180.0F)
- rmesa->hw.tcl.cmd[idx] |= flag;
- else
- rmesa->hw.tcl.cmd[idx] &= ~flag;
- break;
- }
-
- case GL_CONSTANT_ATTENUATION:
- RADEON_STATECHANGE(rmesa, lit[p]);
- fcmd[LIT_ATTEN_CONST] = params[0];
- break;
- case GL_LINEAR_ATTENUATION:
- RADEON_STATECHANGE(rmesa, lit[p]);
- fcmd[LIT_ATTEN_LINEAR] = params[0];
- break;
- case GL_QUADRATIC_ATTENUATION:
- RADEON_STATECHANGE(rmesa, lit[p]);
- fcmd[LIT_ATTEN_QUADRATIC] = params[0];
- break;
- default:
- return;
- }
-
-}
-
-
-
-
-void radeonLightModelfv( GLcontext *ctx, GLenum pname,
- const GLfloat *param )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-
- switch (pname) {
- case GL_LIGHT_MODEL_AMBIENT:
- update_global_ambient( ctx );
- break;
-
- case GL_LIGHT_MODEL_LOCAL_VIEWER:
- RADEON_STATECHANGE( rmesa, tcl );
- if (ctx->Light.Model.LocalViewer)
- rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] |= RADEON_LOCAL_VIEWER;
- else
- rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] &= ~RADEON_LOCAL_VIEWER;
- break;
-
- case GL_LIGHT_MODEL_TWO_SIDE:
- RADEON_STATECHANGE( rmesa, tcl );
- if (ctx->Light.Model.TwoSide)
- rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= RADEON_LIGHT_TWOSIDE;
- else
- rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~RADEON_LIGHT_TWOSIDE;
-
- check_twoside_fallback( ctx );
-
-#if _HAVE_SWTNL
- if (rmesa->TclFallback) {
- radeonChooseRenderState( ctx );
- radeonChooseVertexState( ctx );
- }
-#endif
- break;
-
- case GL_LIGHT_MODEL_COLOR_CONTROL:
- radeonUpdateSpecular(ctx);
-
- RADEON_STATECHANGE( rmesa, tcl );
- if (ctx->Light.Model.ColorControl == GL_SEPARATE_SPECULAR_COLOR)
- rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] &=
- ~RADEON_DIFFUSE_SPECULAR_COMBINE;
- else
- rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] |=
- RADEON_DIFFUSE_SPECULAR_COMBINE;
- break;
-
- default:
- break;
- }
-}
-
-
-/* =============================================================
- * Fog
- */
-
-
-static void radeonFogfv( GLcontext *ctx, GLenum pname, const GLfloat *param )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- union { int i; float f; } c, d;
- GLchan col[4];
-
- c.i = rmesa->hw.fog.cmd[FOG_C];
- d.i = rmesa->hw.fog.cmd[FOG_D];
-
- switch (pname) {
- case GL_FOG_MODE:
- if (!ctx->Fog.Enabled)
- return;
- RADEON_STATECHANGE(rmesa, tcl);
- rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~RADEON_TCL_FOG_MASK;
- switch (ctx->Fog.Mode) {
- case GL_LINEAR:
- rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= RADEON_TCL_FOG_LINEAR;
- if (ctx->Fog.Start == ctx->Fog.End) {
- c.f = 1.0F;
- d.f = 1.0F;
- }
- else {
- c.f = ctx->Fog.End/(ctx->Fog.End-ctx->Fog.Start);
- d.f = 1.0/(ctx->Fog.End-ctx->Fog.Start);
- }
- break;
- case GL_EXP:
- rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= RADEON_TCL_FOG_EXP;
- c.f = 0.0;
- d.f = ctx->Fog.Density;
- break;
- case GL_EXP2:
- rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= RADEON_TCL_FOG_EXP2;
- c.f = 0.0;
- d.f = -(ctx->Fog.Density * ctx->Fog.Density);
- break;
- default:
- return;
- }
- break;
- case GL_FOG_DENSITY:
- switch (ctx->Fog.Mode) {
- case GL_EXP:
- c.f = 0.0;
- d.f = ctx->Fog.Density;
- break;
- case GL_EXP2:
- c.f = 0.0;
- d.f = -(ctx->Fog.Density * ctx->Fog.Density);
- break;
- default:
- break;
- }
- break;
- case GL_FOG_START:
- case GL_FOG_END:
- if (ctx->Fog.Mode == GL_LINEAR) {
- if (ctx->Fog.Start == ctx->Fog.End) {
- c.f = 1.0F;
- d.f = 1.0F;
- } else {
- c.f = ctx->Fog.End/(ctx->Fog.End-ctx->Fog.Start);
- d.f = 1.0/(ctx->Fog.End-ctx->Fog.Start);
- }
- }
- break;
- case GL_FOG_COLOR:
- RADEON_STATECHANGE( rmesa, ctx );
- UNCLAMPED_FLOAT_TO_RGB_CHAN( col, ctx->Fog.Color );
- rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] =
- radeonPackColor( 4, col[0], col[1], col[2], 0 );
- break;
- case GL_FOG_COORDINATE_SOURCE_EXT:
- /* What to do?
- */
- break;
- default:
- return;
- }
-
- if (c.i != rmesa->hw.fog.cmd[FOG_C] || d.i != rmesa->hw.fog.cmd[FOG_D]) {
- RADEON_STATECHANGE( rmesa, fog );
- rmesa->hw.fog.cmd[FOG_C] = c.i;
- rmesa->hw.fog.cmd[FOG_D] = d.i;
- }
-}
-
-/* Examine lighting and texture state to determine if separate specular
- * should be enabled.
- */
-void radeonUpdateSpecular( GLcontext *ctx )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLuint p = rmesa->hw.ctx.cmd[CTX_PP_CNTL];
-
- if (NEED_SECONDARY_COLOR(ctx)) {
- p |= RADEON_SPECULAR_ENABLE;
- } else {
- p &= ~RADEON_SPECULAR_ENABLE;
- }
-
- if ( rmesa->hw.ctx.cmd[CTX_PP_CNTL] != p ) {
- RADEON_STATECHANGE( rmesa, ctx );
- rmesa->hw.ctx.cmd[CTX_PP_CNTL] = p;
- }
-
- /* Bizzare: have to leave lighting enabled to get fog.
- */
- RADEON_STATECHANGE( rmesa, tcl );
- if ((ctx->Light.Enabled &&
- ctx->Light.Model.ColorControl == GL_SEPARATE_SPECULAR_COLOR)) {
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] |= RADEON_TCL_COMPUTE_SPECULAR;
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] |= RADEON_TCL_COMPUTE_DIFFUSE;
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_TCL_VTX_PK_SPEC;
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_TCL_VTX_PK_DIFFUSE;
- rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] |= RADEON_LIGHTING_ENABLE;
- }
- else if (ctx->Fog.Enabled) {
- if (ctx->Light.Enabled) {
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] |= RADEON_TCL_COMPUTE_SPECULAR;
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] |= RADEON_TCL_COMPUTE_DIFFUSE;
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_TCL_VTX_PK_SPEC;
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_TCL_VTX_PK_DIFFUSE;
- rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] |= RADEON_LIGHTING_ENABLE;
- } else {
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] |= RADEON_TCL_COMPUTE_SPECULAR;
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] &= ~RADEON_TCL_COMPUTE_DIFFUSE;
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_TCL_VTX_PK_SPEC;
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_TCL_VTX_PK_DIFFUSE;
- rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] |= RADEON_LIGHTING_ENABLE;
- }
- }
- else if (ctx->Light.Enabled) {
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] &= ~RADEON_TCL_COMPUTE_SPECULAR;
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] |= RADEON_TCL_COMPUTE_DIFFUSE;
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] &= ~RADEON_TCL_VTX_PK_SPEC;
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_TCL_VTX_PK_DIFFUSE;
- rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] |= RADEON_LIGHTING_ENABLE;
- } else if (ctx->Fog.ColorSumEnabled ) {
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] &= ~RADEON_TCL_COMPUTE_SPECULAR;
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] &= ~RADEON_TCL_COMPUTE_DIFFUSE;
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_TCL_VTX_PK_SPEC;
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_TCL_VTX_PK_DIFFUSE;
- rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] &= ~RADEON_LIGHTING_ENABLE;
- } else {
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] &= ~RADEON_TCL_COMPUTE_SPECULAR;
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] &= ~RADEON_TCL_COMPUTE_DIFFUSE;
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] &= ~RADEON_TCL_VTX_PK_SPEC;
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_TCL_VTX_PK_DIFFUSE;
- rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] &= ~RADEON_LIGHTING_ENABLE;
- }
-
-#if _HAVE_SWTNL
- /* Update vertex/render formats
- */
- if (rmesa->TclFallback) {
- radeonChooseRenderState( ctx );
- radeonChooseVertexState( ctx );
- }
-#endif
-}
-
-
-
-static void radeonLightingSpaceChange( GLcontext *ctx )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLboolean tmp;
- RADEON_STATECHANGE( rmesa, tcl );
-
- if (RADEON_DEBUG & DEBUG_STATE)
- fprintf(stderr, "%s %d\n", __FUNCTION__, ctx->_NeedEyeCoords);
-
- if (ctx->_NeedEyeCoords)
- tmp = ctx->Transform.RescaleNormals;
- else
- tmp = !ctx->Transform.RescaleNormals;
-
- if ( tmp ) {
- rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] |= RADEON_RESCALE_NORMALS;
- } else {
- rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] &= ~RADEON_RESCALE_NORMALS;
- }
-}
-
-void radeonInitLightStateFuncs( GLcontext *ctx )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- int i;
-
- ctx->Driver.LightModelfv = radeonLightModelfv;
- ctx->Driver.Lightfv = radeonLightfv;
- ctx->Driver.Fogfv = radeonFogfv;
- ctx->Driver.LightingSpaceChange = radeonLightingSpaceChange;
-
- for (i = 0 ; i < 8; i++) {
- struct gl_light *l = &ctx->Light.Light[i];
- GLenum p = GL_LIGHT0 + i;
- *(float *)&(rmesa->hw.lit[i].cmd[LIT_RANGE_CUTOFF]) = FLT_MAX;
-
- ctx->Driver.Lightfv( ctx, p, GL_AMBIENT, l->Ambient );
- ctx->Driver.Lightfv( ctx, p, GL_DIFFUSE, l->Diffuse );
- ctx->Driver.Lightfv( ctx, p, GL_SPECULAR, l->Specular );
- ctx->Driver.Lightfv( ctx, p, GL_POSITION, 0 );
- ctx->Driver.Lightfv( ctx, p, GL_SPOT_DIRECTION, 0 );
- ctx->Driver.Lightfv( ctx, p, GL_SPOT_EXPONENT, &l->SpotExponent );
- ctx->Driver.Lightfv( ctx, p, GL_SPOT_CUTOFF, &l->SpotCutoff );
- ctx->Driver.Lightfv( ctx, p, GL_CONSTANT_ATTENUATION,
- &l->ConstantAttenuation );
- ctx->Driver.Lightfv( ctx, p, GL_LINEAR_ATTENUATION,
- &l->LinearAttenuation );
- ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION,
- &l->QuadraticAttenuation );
- }
-
- ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT,
- ctx->Light.Model.Ambient );
-
- ctx->Driver.Fogfv( ctx, GL_FOG_MODE, 0 );
- ctx->Driver.Fogfv( ctx, GL_FOG_DENSITY, &ctx->Fog.Density );
- ctx->Driver.Fogfv( ctx, GL_FOG_START, &ctx->Fog.Start );
- ctx->Driver.Fogfv( ctx, GL_FOG_END, &ctx->Fog.End );
- ctx->Driver.Fogfv( ctx, GL_FOG_COLOR, ctx->Fog.Color );
- ctx->Driver.Fogfv( ctx, GL_FOG_COORDINATE_SOURCE_EXT, 0 );
-}
diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_lock.c b/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_lock.c
deleted file mode 100644
index bb121fc58..000000000
--- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_lock.c
+++ /dev/null
@@ -1,135 +0,0 @@
-/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_lock.c,v 1.5 2002/10/30 12:51:55 alanh Exp $ */
-/**************************************************************************
-
-Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
- VA Linux Systems Inc., Fremont, California.
-
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/*
- * Authors:
- * Kevin E. Martin <martin@valinux.com>
- * Gareth Hughes <gareth@valinux.com>
- */
-
-#include "glheader.h"
-#include "radeon_context.h"
-#include "radeon_lock.h"
-#include "radeon_tex.h"
-#include "radeon_state.h"
-#include "radeon_ioctl.h"
-
-#if DEBUG_LOCKING
-char *prevLockFile = NULL;
-int prevLockLine = 0;
-#endif
-
-/* Turn on/off page flipping according to the flags in the sarea:
- */
-static void
-radeonUpdatePageFlipping( radeonContextPtr rmesa )
-{
- int use_back;
-
-
- rmesa->doPageFlip = rmesa->sarea->pfState;
-
- use_back = (rmesa->glCtx->DrawBuffer->_ColorDrawBufferMask[0] == BUFFER_BIT_BACK_LEFT);
- use_back ^= (rmesa->sarea->pfCurrentPage == 1);
-
- if ( RADEON_DEBUG & DEBUG_VERBOSE )
- fprintf(stderr, "%s allow %d current %d\n", __FUNCTION__,
- rmesa->doPageFlip,
- rmesa->sarea->pfCurrentPage );
-
- if ( use_back ) {
- rmesa->state.color.drawOffset = rmesa->radeonScreen->backOffset;
- rmesa->state.color.drawPitch = rmesa->radeonScreen->backPitch;
- } else {
- rmesa->state.color.drawOffset = rmesa->radeonScreen->frontOffset;
- rmesa->state.color.drawPitch = rmesa->radeonScreen->frontPitch;
- }
-
- RADEON_STATECHANGE( rmesa, ctx );
- rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = rmesa->state.color.drawOffset
- + rmesa->radeonScreen->fbLocation;
- rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = rmesa->state.color.drawPitch;
-}
-
-
-
-/* Update the hardware state. This is called if another context has
- * grabbed the hardware lock, which includes the X server. This
- * function also updates the driver's window state after the X server
- * moves, resizes or restacks a window -- the change will be reflected
- * in the drawable position and clip rects. Since the X server grabs
- * the hardware lock when it changes the window state, this routine will
- * automatically be called after such a change.
- */
-void radeonGetLock( radeonContextPtr rmesa, GLuint flags )
-{
- __DRIdrawablePrivate *dPriv = rmesa->dri.drawable;
- __DRIscreenPrivate *sPriv = rmesa->dri.screen;
- drm_radeon_sarea_t *sarea = rmesa->sarea;
-
- drmGetLock( rmesa->dri.fd, rmesa->dri.hwContext, flags );
-
- /* The window might have moved, so we might need to get new clip
- * rects.
- *
- * NOTE: This releases and regrabs the hw lock to allow the X server
- * to respond to the DRI protocol request for new drawable info.
- * Since the hardware state depends on having the latest drawable
- * clip rects, all state checking must be done _after_ this call.
- */
- DRI_VALIDATE_DRAWABLE_INFO( sPriv, dPriv );
-
- if ( rmesa->lastStamp != dPriv->lastStamp ) {
- radeonUpdatePageFlipping( rmesa );
- if (rmesa->glCtx->DrawBuffer->_ColorDrawBufferMask[0] == BUFFER_BIT_BACK_LEFT)
- radeonSetCliprects( rmesa, GL_BACK_LEFT );
- else
- radeonSetCliprects( rmesa, GL_FRONT_LEFT );
- radeonUpdateViewportOffset( rmesa->glCtx );
- rmesa->lastStamp = dPriv->lastStamp;
- }
-
- RADEON_STATECHANGE( rmesa, ctx );
- if (rmesa->sarea->tiling_enabled) {
- rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= RADEON_COLOR_TILE_ENABLE;
- }
- else rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] &= ~RADEON_COLOR_TILE_ENABLE;
-
- if ( sarea->ctx_owner != rmesa->dri.hwContext ) {
- int i;
- sarea->ctx_owner = rmesa->dri.hwContext;
-
- for ( i = 0 ; i < rmesa->nr_heaps ; i++ ) {
- DRI_AGE_TEXTURES( rmesa->texture_heaps[ i ] );
- }
- }
-
- rmesa->lost_context = GL_TRUE;
-}
diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_lock.h b/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_lock.h
deleted file mode 100644
index 4e8617eb8..000000000
--- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_lock.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_lock.h,v 1.3 2002/10/30 12:51:55 alanh Exp $ */
-/**************************************************************************
-
-Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
- VA Linux Systems Inc., Fremont, California.
-
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/*
- * Authors:
- * Kevin E. Martin <martin@valinux.com>
- * Gareth Hughes <gareth@valinux.com>
- */
-
-#ifndef __RADEON_LOCK_H__
-#define __RADEON_LOCK_H__
-
-extern void radeonGetLock( radeonContextPtr rmesa, GLuint flags );
-
-/* Turn DEBUG_LOCKING on to find locking conflicts.
- */
-#define DEBUG_LOCKING 0
-
-#if DEBUG_LOCKING
-extern char *prevLockFile;
-extern int prevLockLine;
-
-#define DEBUG_LOCK() \
- do { \
- prevLockFile = (__FILE__); \
- prevLockLine = (__LINE__); \
- } while (0)
-
-#define DEBUG_RESET() \
- do { \
- prevLockFile = 0; \
- prevLockLine = 0; \
- } while (0)
-
-#define DEBUG_CHECK_LOCK() \
- do { \
- if ( prevLockFile ) { \
- fprintf( stderr, \
- "LOCK SET!\n\tPrevious %s:%d\n\tCurrent: %s:%d\n", \
- prevLockFile, prevLockLine, __FILE__, __LINE__ ); \
- exit( 1 ); \
- } \
- } while (0)
-
-#else
-
-#define DEBUG_LOCK()
-#define DEBUG_RESET()
-#define DEBUG_CHECK_LOCK()
-
-#endif
-
-/*
- * !!! We may want to separate locks from locks with validation. This
- * could be used to improve performance for those things commands that
- * do not do any drawing !!!
- */
-
-
-/* Lock the hardware and validate our state.
- */
-#define LOCK_HARDWARE( rmesa ) \
- do { \
- char __ret = 0; \
- DEBUG_CHECK_LOCK(); \
- DRM_CAS( rmesa->dri.hwLock, rmesa->dri.hwContext, \
- (DRM_LOCK_HELD | rmesa->dri.hwContext), __ret ); \
- if ( __ret ) \
- radeonGetLock( rmesa, 0 ); \
- DEBUG_LOCK(); \
- } while (0)
-
-#define UNLOCK_HARDWARE( rmesa ) \
- do { \
- DRM_UNLOCK( rmesa->dri.fd, \
- rmesa->dri.hwLock, \
- rmesa->dri.hwContext ); \
- DEBUG_RESET(); \
- } while (0)
-
-#endif /* __RADEON_LOCK_H__ */
diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_maos.c b/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_maos.c
deleted file mode 100644
index c62edd715..000000000
--- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_maos.c
+++ /dev/null
@@ -1,12 +0,0 @@
-
-
-/* If using new packets, can choose either verts or arrays.
- * Otherwise, must use verts.
- */
-#include "radeon_context.h"
-#define RADEON_MAOS_VERTS 1
-#if (RADEON_MAOS_VERTS) || (RADEON_OLD_PACKETS)
-#include "radeon_maos_verts.c"
-#else
-#include "radeon_maos_arrays.c"
-#endif
diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_maos.h b/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_maos.h
deleted file mode 100644
index 09039d684..000000000
--- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_maos.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_maos.h,v 1.1 2002/10/30 12:51:55 alanh Exp $ */
-/**************************************************************************
-
-Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
- Tungsten Grahpics Inc., Austin, Texas.
-
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/*
- * Authors:
- * Keith Whitwell <keith@tungstengraphics.com>
- */
-
-#ifndef __RADEON_MAOS_H__
-#define __RADEON_MAOS_H__
-
-#include "radeon_context.h"
-
-extern void radeonEmitArrays( GLcontext *ctx, GLuint inputs );
-extern void radeonReleaseArrays( GLcontext *ctx, GLuint newinputs );
-
-#endif
diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c b/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c
deleted file mode 100644
index 98f66898c..000000000
--- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_maos_arrays.c
+++ /dev/null
@@ -1,604 +0,0 @@
-/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_maos_arrays.c,v 1.1 2002/10/30 12:51:55 alanh Exp $ */
-/**************************************************************************
-
-Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
- Tungsten Graphics Inc., Cedar Park, Texas.
-
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/*
- * Authors:
- * Keith Whitwell <keith@tungstengraphics.com>
- */
-
-#include "glheader.h"
-#include "imports.h"
-#include "mtypes.h"
-#include "macros.h"
-
-#include "swrast_setup/swrast_setup.h"
-#include "math/m_translate.h"
-#include "tnl/tnl.h"
-#include "tnl/t_context.h"
-
-#include "radeon_context.h"
-#include "radeon_ioctl.h"
-#include "radeon_state.h"
-#include "radeon_swtcl.h"
-#include "radeon_maos.h"
-
-#if 0
-/* Usage:
- * - from radeon_tcl_render
- * - call radeonEmitArrays to ensure uptodate arrays in dma
- * - emit primitives (new type?) which reference the data
- * -- need to use elts for lineloop, quads, quadstrip/flat
- * -- other primitives are all well-formed (need tristrip-1,fake-poly)
- *
- */
-static void emit_ubyte_rgba3( GLcontext *ctx,
- struct radeon_dma_region *rvb,
- char *data,
- int stride,
- int count )
-{
- int i;
- radeon_color_t *out = (radeon_color_t *)(rvb->start + rvb->address);
-
- if (RADEON_DEBUG & DEBUG_VERTS)
- fprintf(stderr, "%s count %d stride %d out %p\n",
- __FUNCTION__, count, stride, (void *)out);
-
- for (i = 0; i < count; i++) {
- out->red = *data;
- out->green = *(data+1);
- out->blue = *(data+2);
- out->alpha = 0xFF;
- out++;
- data += stride;
- }
-}
-
-static void emit_ubyte_rgba4( GLcontext *ctx,
- struct radeon_dma_region *rvb,
- char *data,
- int stride,
- int count )
-{
- int i;
- int *out = (int *)(rvb->address + rvb->start);
-
- if (RADEON_DEBUG & DEBUG_VERTS)
- fprintf(stderr, "%s count %d stride %d\n",
- __FUNCTION__, count, stride);
-
- if (stride == 4)
- COPY_DWORDS( out, data, count );
- else
- for (i = 0; i < count; i++) {
- *out++ = LE32_TO_CPU(*(int *)data);
- data += stride;
- }
-}
-
-
-static void emit_ubyte_rgba( GLcontext *ctx,
- struct radeon_dma_region *rvb,
- char *data,
- int size,
- int stride,
- int count )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-
- if (RADEON_DEBUG & DEBUG_VERTS)
- fprintf(stderr, "%s %d/%d\n", __FUNCTION__, count, size);
-
- assert (!rvb->buf);
-
- if (stride == 0) {
- radeonAllocDmaRegion( rmesa, rvb, 4, 4 );
- count = 1;
- rvb->aos_start = GET_START(rvb);
- rvb->aos_stride = 0;
- rvb->aos_size = 1;
- }
- else {
- radeonAllocDmaRegion( rmesa, rvb, 4 * count, 4 ); /* alignment? */
- rvb->aos_start = GET_START(rvb);
- rvb->aos_stride = 1;
- rvb->aos_size = 1;
- }
-
- /* Emit the data
- */
- switch (size) {
- case 3:
- emit_ubyte_rgba3( ctx, rvb, data, stride, count );
- break;
- case 4:
- emit_ubyte_rgba4( ctx, rvb, data, stride, count );
- break;
- default:
- assert(0);
- exit(1);
- break;
- }
-}
-#endif
-
-#if defined(USE_X86_ASM)
-#define COPY_DWORDS( dst, src, nr ) \
-do { \
- int __tmp; \
- __asm__ __volatile__( "rep ; movsl" \
- : "=%c" (__tmp), "=D" (dst), "=S" (__tmp) \
- : "0" (nr), \
- "D" ((long)dst), \
- "S" ((long)src) ); \
-} while (0)
-#else
-#define COPY_DWORDS( dst, src, nr ) \
-do { \
- int j; \
- for ( j = 0 ; j < nr ; j++ ) \
- dst[j] = ((int *)src)[j]; \
- dst += nr; \
-} while (0)
-#endif
-
-
-static void emit_vec4( GLcontext *ctx,
- struct radeon_dma_region *rvb,
- char *data,
- int stride,
- int count )
-{
- int i;
- int *out = (int *)(rvb->address + rvb->start);
-
- if (RADEON_DEBUG & DEBUG_VERTS)
- fprintf(stderr, "%s count %d stride %d\n",
- __FUNCTION__, count, stride);
-
- if (stride == 4)
- COPY_DWORDS( out, data, count );
- else
- for (i = 0; i < count; i++) {
- out[0] = *(int *)data;
- out++;
- data += stride;
- }
-}
-
-
-static void emit_vec8( GLcontext *ctx,
- struct radeon_dma_region *rvb,
- char *data,
- int stride,
- int count )
-{
- int i;
- int *out = (int *)(rvb->address + rvb->start);
-
- if (RADEON_DEBUG & DEBUG_VERTS)
- fprintf(stderr, "%s count %d stride %d\n",
- __FUNCTION__, count, stride);
-
- if (stride == 8)
- COPY_DWORDS( out, data, count*2 );
- else
- for (i = 0; i < count; i++) {
- out[0] = *(int *)data;
- out[1] = *(int *)(data+4);
- out += 2;
- data += stride;
- }
-}
-
-static void emit_vec12( GLcontext *ctx,
- struct radeon_dma_region *rvb,
- char *data,
- int stride,
- int count )
-{
- int i;
- int *out = (int *)(rvb->address + rvb->start);
-
- if (RADEON_DEBUG & DEBUG_VERTS)
- fprintf(stderr, "%s count %d stride %d out %p data %p\n",
- __FUNCTION__, count, stride, (void *)out, (void *)data);
-
- if (stride == 12)
- COPY_DWORDS( out, data, count*3 );
- else
- for (i = 0; i < count; i++) {
- out[0] = *(int *)data;
- out[1] = *(int *)(data+4);
- out[2] = *(int *)(data+8);
- out += 3;
- data += stride;
- }
-}
-
-static void emit_vec16( GLcontext *ctx,
- struct radeon_dma_region *rvb,
- char *data,
- int stride,
- int count )
-{
- int i;
- int *out = (int *)(rvb->address + rvb->start);
-
- if (RADEON_DEBUG & DEBUG_VERTS)
- fprintf(stderr, "%s count %d stride %d\n",
- __FUNCTION__, count, stride);
-
- if (stride == 16)
- COPY_DWORDS( out, data, count*4 );
- else
- for (i = 0; i < count; i++) {
- out[0] = *(int *)data;
- out[1] = *(int *)(data+4);
- out[2] = *(int *)(data+8);
- out[3] = *(int *)(data+12);
- out += 4;
- data += stride;
- }
-}
-
-
-static void emit_vector( GLcontext *ctx,
- struct radeon_dma_region *rvb,
- char *data,
- int size,
- int stride,
- int count )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-
- if (RADEON_DEBUG & DEBUG_VERTS)
- fprintf(stderr, "%s count %d size %d stride %d\n",
- __FUNCTION__, count, size, stride);
-
- assert (!rvb->buf);
-
- if (stride == 0) {
- radeonAllocDmaRegion( rmesa, rvb, size * 4, 4 );
- count = 1;
- rvb->aos_start = GET_START(rvb);
- rvb->aos_stride = 0;
- rvb->aos_size = size;
- }
- else {
- radeonAllocDmaRegion( rmesa, rvb, size * count * 4, 4 ); /* alignment? */
- rvb->aos_start = GET_START(rvb);
- rvb->aos_stride = size;
- rvb->aos_size = size;
- }
-
- /* Emit the data
- */
- switch (size) {
- case 1:
- emit_vec4( ctx, rvb, data, stride, count );
- break;
- case 2:
- emit_vec8( ctx, rvb, data, stride, count );
- break;
- case 3:
- emit_vec12( ctx, rvb, data, stride, count );
- break;
- case 4:
- emit_vec16( ctx, rvb, data, stride, count );
- break;
- default:
- assert(0);
- exit(1);
- break;
- }
-
-}
-
-
-
-static void emit_s0_vec( GLcontext *ctx,
- struct radeon_dma_region *rvb,
- char *data,
- int stride,
- int count )
-{
- int i;
- int *out = (int *)(rvb->address + rvb->start);
-
- if (RADEON_DEBUG & DEBUG_VERTS)
- fprintf(stderr, "%s count %d stride %d\n",
- __FUNCTION__, count, stride);
-
- for (i = 0; i < count; i++) {
- out[0] = *(int *)data;
- out[1] = 0;
- out += 2;
- data += stride;
- }
-}
-
-static void emit_stq_vec( GLcontext *ctx,
- struct radeon_dma_region *rvb,
- char *data,
- int stride,
- int count )
-{
- int i;
- int *out = (int *)(rvb->address + rvb->start);
-
- if (RADEON_DEBUG & DEBUG_VERTS)
- fprintf(stderr, "%s count %d stride %d\n",
- __FUNCTION__, count, stride);
-
- for (i = 0; i < count; i++) {
- out[0] = *(int *)data;
- out[1] = *(int *)(data+4);
- out[2] = *(int *)(data+12);
- out += 3;
- data += stride;
- }
-}
-
-
-
-
-static void emit_tex_vector( GLcontext *ctx,
- struct radeon_dma_region *rvb,
- char *data,
- int size,
- int stride,
- int count )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- int emitsize;
-
- if (RADEON_DEBUG & DEBUG_VERTS)
- fprintf(stderr, "%s %d/%d\n", __FUNCTION__, count, size);
-
- assert (!rvb->buf);
-
- switch (size) {
- case 4: emitsize = 3; break;
- default: emitsize = 2; break;
- }
-
-
- if (stride == 0) {
- radeonAllocDmaRegion( rmesa, rvb, 4 * emitsize, 4 );
- count = 1;
- rvb->aos_start = GET_START(rvb);
- rvb->aos_stride = 0;
- rvb->aos_size = emitsize;
- }
- else {
- radeonAllocDmaRegion( rmesa, rvb, 4 * emitsize * count, 4 );
- rvb->aos_start = GET_START(rvb);
- rvb->aos_stride = emitsize;
- rvb->aos_size = emitsize;
- }
-
-
- /* Emit the data
- */
- switch (size) {
- case 1:
- emit_s0_vec( ctx, rvb, data, stride, count );
- break;
- case 2:
- emit_vec8( ctx, rvb, data, stride, count );
- break;
- case 3:
- emit_vec8( ctx, rvb, data, stride, count );
- break;
- case 4:
- emit_stq_vec( ctx, rvb, data, stride, count );
- break;
- default:
- assert(0);
- exit(1);
- break;
- }
-}
-
-
-
-
-/* Emit any changed arrays to new GART memory, re-emit a packet to
- * update the arrays.
- */
-void radeonEmitArrays( GLcontext *ctx, GLuint inputs )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
- struct vertex_buffer *VB = &TNL_CONTEXT( ctx )->vb;
- struct radeon_dma_region **component = rmesa->tcl.aos_components;
- GLuint nr = 0;
- GLuint vfmt = 0;
- GLuint count = VB->Count;
- GLuint vtx;
-
-#if 0
- if (RADEON_DEBUG & DEBUG_VERTS)
- _tnl_print_vert_flags( __FUNCTION__, inputs );
-#endif
-
- if (1) {
- if (!rmesa->tcl.obj.buf)
- emit_vector( ctx,
- &rmesa->tcl.obj,
- (char *)VB->ObjPtr->data,
- VB->ObjPtr->size,
- VB->ObjPtr->stride,
- count);
-
- switch( VB->ObjPtr->size ) {
- case 4: vfmt |= RADEON_CP_VC_FRMT_W0;
- case 3: vfmt |= RADEON_CP_VC_FRMT_Z;
- case 2: vfmt |= RADEON_CP_VC_FRMT_XY;
- default:
- break;
- }
- component[nr++] = &rmesa->tcl.obj;
- }
-
-
- if (inputs & VERT_BIT_NORMAL) {
- if (!rmesa->tcl.norm.buf)
- emit_vector( ctx,
- &(rmesa->tcl.norm),
- (char *)VB->NormalPtr->data,
- 3,
- VB->NormalPtr->stride,
- count);
-
- vfmt |= RADEON_CP_VC_FRMT_N0;
- component[nr++] = &rmesa->tcl.norm;
- }
-
- if (inputs & VERT_BIT_COLOR0) {
- int emitsize;
- if (VB->ColorPtr[0]->size == 4 &&
- (VB->ColorPtr[0]->stride != 0 ||
- VB->ColorPtr[0]->data[0][3] != 1.0)) {
- vfmt |= RADEON_CP_VC_FRMT_FPCOLOR | RADEON_CP_VC_FRMT_FPALPHA;
- emitsize = 4;
- }
-
- else {
- vfmt |= RADEON_CP_VC_FRMT_FPCOLOR;
- emitsize = 3;
- }
-
- if (!rmesa->tcl.rgba.buf)
- emit_vector( ctx,
- &(rmesa->tcl.rgba),
- (char *)VB->ColorPtr[0]->data,
- emitsize,
- VB->ColorPtr[0]->stride,
- count);
-
-
- component[nr++] = &rmesa->tcl.rgba;
- }
-
-
- if (inputs & VERT_BIT_COLOR1) {
- if (!rmesa->tcl.spec.buf) {
-
- emit_vector( ctx,
- &rmesa->tcl.spec,
- (char *)VB->SecondaryColorPtr[0]->data,
- 3,
- VB->SecondaryColorPtr[0]->stride,
- count);
- }
-
- vfmt |= RADEON_CP_VC_FRMT_FPSPEC;
- component[nr++] = &rmesa->tcl.spec;
- }
-
- vtx = (rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] &
- ~(RADEON_TCL_VTX_Q0|RADEON_TCL_VTX_Q1));
-
- if (inputs & VERT_BIT_TEX0) {
- if (!rmesa->tcl.tex[0].buf)
- emit_tex_vector( ctx,
- &(rmesa->tcl.tex[0]),
- (char *)VB->TexCoordPtr[0]->data,
- VB->TexCoordPtr[0]->size,
- VB->TexCoordPtr[0]->stride,
- count );
-
- switch( VB->TexCoordPtr[0]->size ) {
- case 4:
- vtx |= RADEON_TCL_VTX_Q0;
- vfmt |= RADEON_CP_VC_FRMT_Q0;
- default:
- vfmt |= RADEON_CP_VC_FRMT_ST0;
- }
- component[nr++] = &rmesa->tcl.tex[0];
- }
-
- if (inputs & VERT_BIT_TEX1) {
- if (!rmesa->tcl.tex[1].buf)
- emit_tex_vector( ctx,
- &(rmesa->tcl.tex[1]),
- (char *)VB->TexCoordPtr[1]->data,
- VB->TexCoordPtr[1]->size,
- VB->TexCoordPtr[1]->stride,
- count );
-
- switch( VB->TexCoordPtr[1]->size ) {
- case 4:
- vtx |= RADEON_TCL_VTX_Q1;
- vfmt |= RADEON_CP_VC_FRMT_Q1;
- default:
- vfmt |= RADEON_CP_VC_FRMT_ST1;
- }
- component[nr++] = &rmesa->tcl.tex[1];
- }
-
- if (vtx != rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT]) {
- RADEON_STATECHANGE( rmesa, tcl );
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] = vtx;
- }
-
- rmesa->tcl.nr_aos_components = nr;
- rmesa->tcl.vertex_format = vfmt;
-}
-
-
-void radeonReleaseArrays( GLcontext *ctx, GLuint newinputs )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
-
-#if 0
- if (RADEON_DEBUG & DEBUG_VERTS)
- _tnl_print_vert_flags( __FUNCTION__, newinputs );
-#endif
-
- if (newinputs & VERT_BIT_POS)
- radeonReleaseDmaRegion( rmesa, &rmesa->tcl.obj, __FUNCTION__ );
-
- if (newinputs & VERT_BIT_NORMAL)
- radeonReleaseDmaRegion( rmesa, &rmesa->tcl.norm, __FUNCTION__ );
-
- if (newinputs & VERT_BIT_COLOR0)
- radeonReleaseDmaRegion( rmesa, &rmesa->tcl.rgba, __FUNCTION__ );
-
- if (newinputs & VERT_BIT_COLOR1)
- radeonReleaseDmaRegion( rmesa, &rmesa->tcl.spec, __FUNCTION__ );
-
- if (newinputs & VERT_BIT_TEX0)
- radeonReleaseDmaRegion( rmesa, &rmesa->tcl.tex[0], __FUNCTION__ );
-
- if (newinputs & VERT_BIT_TEX1)
- radeonReleaseDmaRegion( rmesa, &rmesa->tcl.tex[1], __FUNCTION__ );
-}
diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_maos_vbtmp.h b/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_maos_vbtmp.h
deleted file mode 100644
index c16234a94..000000000
--- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_maos_vbtmp.h
+++ /dev/null
@@ -1,284 +0,0 @@
-/*
- * Mesa 3-D graphics library
- * Version: 4.1
- *
- * Copyright (C) 1999-2002 Brian Paul All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * BRIAN PAUL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Keith Whitwell <keith@tungstengraphics.com>
- */
-
-#ifndef LOCALVARS
-#define LOCALVARS
-#endif
-
-#undef TCL_DEBUG
-#ifndef TCL_DEBUG
-#define TCL_DEBUG 0
-#endif
-
-static void TAG(emit)( GLcontext *ctx,
- GLuint start, GLuint end,
- void *dest )
-{
- LOCALVARS
- struct vertex_buffer *VB = &TNL_CONTEXT(ctx)->vb;
- GLuint (*tc0)[4], (*tc1)[4], (*tc2)[4];
- GLfloat (*col)[4], (*spec)[4];
- GLfloat (*fog)[4];
- GLuint (*norm)[4];
- GLuint tc0_stride, tc1_stride, col_stride, spec_stride, fog_stride;
- GLuint tc2_stride, norm_stride;
- GLuint fill_tex = 0;
- GLuint (*coord)[4];
- GLuint coord_stride; /* object coordinates */
- GLubyte dummy[4];
- int i;
-
- union emit_union *v = (union emit_union *)dest;
-
- if (RADEON_DEBUG & DEBUG_VERTS)
- fprintf(stderr, "%s\n", __FUNCTION__);
-
- coord = (GLuint (*)[4])VB->ObjPtr->data;
- coord_stride = VB->ObjPtr->stride;
-
- if (DO_TEX2) {
- if (VB->TexCoordPtr[2]) {
- const GLuint t2 = GET_TEXSOURCE(2);
- tc2 = (GLuint (*)[4])VB->TexCoordPtr[t2]->data;
- tc2_stride = VB->TexCoordPtr[t2]->stride;
- if (DO_PTEX && VB->TexCoordPtr[t2]->size < 4) {
- fill_tex |= (1<<2);
- }
- } else {
- tc2 = (GLuint (*)[4])&ctx->Current.Attrib[VERT_ATTRIB_TEX2];
- tc2_stride = 0;
- }
- }
-
- if (DO_TEX1) {
- if (VB->TexCoordPtr[1]) {
- const GLuint t1 = GET_TEXSOURCE(1);
- tc1 = (GLuint (*)[4])VB->TexCoordPtr[t1]->data;
- tc1_stride = VB->TexCoordPtr[t1]->stride;
- if (DO_PTEX && VB->TexCoordPtr[t1]->size < 4) {
- fill_tex |= (1<<1);
- }
- } else {
- tc1 = (GLuint (*)[4])&ctx->Current.Attrib[VERT_ATTRIB_TEX1];
- tc1_stride = 0;
- }
- }
-
- if (DO_TEX0) {
- if (VB->TexCoordPtr[0]) {
- const GLuint t0 = GET_TEXSOURCE(0);
- tc0_stride = VB->TexCoordPtr[t0]->stride;
- tc0 = (GLuint (*)[4])VB->TexCoordPtr[t0]->data;
- if (DO_PTEX && VB->TexCoordPtr[t0]->size < 4) {
- fill_tex |= (1<<0);
- }
- } else {
- tc0 = (GLuint (*)[4])&ctx->Current.Attrib[VERT_ATTRIB_TEX0];
- tc0_stride = 0;
- }
-
- }
-
- if (DO_NORM) {
- if (VB->NormalPtr) {
- norm_stride = VB->NormalPtr->stride;
- norm = (GLuint (*)[4])VB->NormalPtr->data;
- } else {
- norm_stride = 0;
- norm = (GLuint (*)[4])&ctx->Current.Attrib[VERT_ATTRIB_NORMAL];
- }
- }
-
- if (DO_RGBA) {
- if (VB->ColorPtr[0]) {
- col = VB->ColorPtr[0]->data;
- col_stride = VB->ColorPtr[0]->stride;
- } else {
- col = (GLfloat (*)[4])ctx->Current.Attrib[VERT_ATTRIB_COLOR0];
- col_stride = 0;
- }
- }
-
- if (DO_SPEC) {
- if (VB->SecondaryColorPtr[0]) {
- spec = VB->SecondaryColorPtr[0]->data;
- spec_stride = VB->SecondaryColorPtr[0]->stride;
- } else {
- spec = (GLfloat (*)[4])ctx->Current.Attrib[VERT_ATTRIB_COLOR1];
- spec_stride = 0;
- }
- }
-
- if (DO_FOG) {
- if (VB->FogCoordPtr) {
- fog = VB->FogCoordPtr->data;
- fog_stride = VB->FogCoordPtr->stride;
- } else {
- fog = (GLfloat (*)[4])&dummy; fog[0][0] = 0.0F;
- fog_stride = 0;
- }
- }
-
-
- if (start) {
- coord = (GLuint (*)[4])((GLubyte *)coord + start * coord_stride);
- if (DO_TEX0)
- tc0 = (GLuint (*)[4])((GLubyte *)tc0 + start * tc0_stride);
- if (DO_TEX1)
- tc1 = (GLuint (*)[4])((GLubyte *)tc1 + start * tc1_stride);
- if (DO_TEX2)
- tc2 = (GLuint (*)[4])((GLubyte *)tc2 + start * tc2_stride);
- if (DO_NORM)
- norm = (GLuint (*)[4])((GLubyte *)norm + start * norm_stride);
- if (DO_RGBA)
- STRIDE_4F(col, start * col_stride);
- if (DO_SPEC)
- STRIDE_4F(spec, start * spec_stride);
- if (DO_FOG)
- STRIDE_4F(fog, start * fog_stride);
- }
-
-
- {
- for (i=start; i < end; i++) {
-
- v[0].ui = coord[0][0];
- v[1].ui = coord[0][1];
- v[2].ui = coord[0][2];
- if (DO_W) {
- v[3].ui = coord[0][3];
- v += 4;
- }
- else
- v += 3;
- coord = (GLuint (*)[4])((GLubyte *)coord + coord_stride);
-
- if (DO_NORM) {
- v[0].ui = norm[0][0];
- v[1].ui = norm[0][1];
- v[2].ui = norm[0][2];
- v += 3;
- norm = (GLuint (*)[4])((GLubyte *)norm + norm_stride);
- }
- if (DO_RGBA) {
- UNCLAMPED_FLOAT_TO_UBYTE(v[0].rgba.red, col[0][0]);
- UNCLAMPED_FLOAT_TO_UBYTE(v[0].rgba.green, col[0][1]);
- UNCLAMPED_FLOAT_TO_UBYTE(v[0].rgba.blue, col[0][2]);
- UNCLAMPED_FLOAT_TO_UBYTE(v[0].rgba.alpha, col[0][3]);
- STRIDE_4F(col, col_stride);
- v++;
- }
- if (DO_SPEC || DO_FOG) {
- if (DO_SPEC) {
- UNCLAMPED_FLOAT_TO_UBYTE(v[0].rgba.red, spec[0][0]);
- UNCLAMPED_FLOAT_TO_UBYTE(v[0].rgba.green, spec[0][1]);
- UNCLAMPED_FLOAT_TO_UBYTE(v[0].rgba.blue, spec[0][2]);
- STRIDE_4F(spec, spec_stride);
- }
- if (DO_FOG) {
- UNCLAMPED_FLOAT_TO_UBYTE(v[0].rgba.alpha, fog[0][0]);
- fog = (GLfloat (*)[4])((GLubyte *)fog + fog_stride);
- }
- if (TCL_DEBUG) fprintf(stderr, "%x ", v[0].ui);
- v++;
- }
- if (DO_TEX0) {
- v[0].ui = tc0[0][0];
- v[1].ui = tc0[0][1];
- if (TCL_DEBUG) fprintf(stderr, "t0: %.2f %.2f ", v[0].f, v[1].f);
- if (DO_PTEX) {
- if (fill_tex & (1<<0))
- v[2].f = 1.0;
- else
- v[2].ui = tc0[0][3];
- if (TCL_DEBUG) fprintf(stderr, "%.2f ", v[2].f);
- v += 3;
- }
- else
- v += 2;
- tc0 = (GLuint (*)[4])((GLubyte *)tc0 + tc0_stride);
- }
- if (DO_TEX1) {
- v[0].ui = tc1[0][0];
- v[1].ui = tc1[0][1];
- if (TCL_DEBUG) fprintf(stderr, "t1: %.2f %.2f ", v[0].f, v[1].f);
- if (DO_PTEX) {
- if (fill_tex & (1<<1))
- v[2].f = 1.0;
- else
- v[2].ui = tc1[0][3];
- if (TCL_DEBUG) fprintf(stderr, "%.2f ", v[2].f);
- v += 3;
- }
- else
- v += 2;
- tc1 = (GLuint (*)[4])((GLubyte *)tc1 + tc1_stride);
- }
- if (DO_TEX2) {
- v[0].ui = tc2[0][0];
- v[1].ui = tc2[0][1];
- if (DO_PTEX) {
- if (fill_tex & (1<<2))
- v[2].f = 1.0;
- else
- v[2].ui = tc2[0][3];
- v += 3;
- }
- else
- v += 2;
- tc2 = (GLuint (*)[4])((GLubyte *)tc2 + tc2_stride);
- }
- if (TCL_DEBUG) fprintf(stderr, "\n");
- }
- }
-}
-
-
-
-static void TAG(init)( void )
-{
- int sz = 3;
- if (DO_W) sz++;
- if (DO_NORM) sz += 3;
- if (DO_RGBA) sz++;
- if (DO_SPEC || DO_FOG) sz++;
- if (DO_TEX0) sz += 2;
- if (DO_TEX0 && DO_PTEX) sz++;
- if (DO_TEX1) sz += 2;
- if (DO_TEX1 && DO_PTEX) sz++;
- if (DO_TEX2) sz += 2;
- if (DO_TEX2 && DO_PTEX) sz++;
-
- setup_tab[IDX].emit = TAG(emit);
- setup_tab[IDX].vertex_format = IND;
- setup_tab[IDX].vertex_size = sz;
-}
-
-
-#undef IND
-#undef TAG
-#undef IDX
diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_maos_verts.c b/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_maos_verts.c
deleted file mode 100644
index 8cb08a812..000000000
--- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_maos_verts.c
+++ /dev/null
@@ -1,367 +0,0 @@
-/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_maos_verts.c,v 1.1 2002/10/30 12:51:55 alanh Exp $ */
-/**************************************************************************
-
-Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
- Tungsten Graphics Inc., Austin, Texas.
-
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/*
- * Authors:
- * Keith Whitwell <keith@tungstengraphics.com>
- */
-
-#include "glheader.h"
-#include "imports.h"
-#include "mtypes.h"
-
-#include "array_cache/acache.h"
-#include "math/m_translate.h"
-#include "tnl/tnl.h"
-#include "tnl/t_pipeline.h"
-#include "math/m_translate.h"
-#include "radeon_context.h"
-#include "radeon_state.h"
-#include "radeon_ioctl.h"
-#include "radeon_tex.h"
-#include "radeon_tcl.h"
-#include "radeon_swtcl.h"
-#include "radeon_maos.h"
-
-
-#define RADEON_TCL_MAX_SETUP 13
-
-union emit_union { float f; GLuint ui; radeon_color_t rgba; };
-
-static struct {
- void (*emit)( GLcontext *, GLuint, GLuint, void * );
- GLuint vertex_size;
- GLuint vertex_format;
-} setup_tab[RADEON_TCL_MAX_SETUP];
-
-#define DO_W (IND & RADEON_CP_VC_FRMT_W0)
-#define DO_RGBA (IND & RADEON_CP_VC_FRMT_PKCOLOR)
-#define DO_SPEC (IND & RADEON_CP_VC_FRMT_PKSPEC)
-#define DO_FOG (IND & RADEON_CP_VC_FRMT_PKSPEC)
-#define DO_TEX0 (IND & RADEON_CP_VC_FRMT_ST0)
-#define DO_TEX1 (IND & RADEON_CP_VC_FRMT_ST1)
-#define DO_PTEX (IND & RADEON_CP_VC_FRMT_Q0)
-#define DO_NORM (IND & RADEON_CP_VC_FRMT_N0)
-
-#define DO_TEX2 0
-#define DO_TEX3 0
-
-#define GET_TEXSOURCE(n) n
-
-/***********************************************************************
- * Generate vertex emit functions *
- ***********************************************************************/
-
-
-/* Defined in order of increasing vertex size:
- */
-#define IDX 0
-#define IND (RADEON_CP_VC_FRMT_XY| \
- RADEON_CP_VC_FRMT_Z| \
- RADEON_CP_VC_FRMT_PKCOLOR)
-#define TAG(x) x##_rgba
-#include "radeon_maos_vbtmp.h"
-
-#define IDX 1
-#define IND (RADEON_CP_VC_FRMT_XY| \
- RADEON_CP_VC_FRMT_Z| \
- RADEON_CP_VC_FRMT_N0)
-#define TAG(x) x##_n
-#include "radeon_maos_vbtmp.h"
-
-#define IDX 2
-#define IND (RADEON_CP_VC_FRMT_XY| \
- RADEON_CP_VC_FRMT_Z| \
- RADEON_CP_VC_FRMT_PKCOLOR| \
- RADEON_CP_VC_FRMT_ST0)
-#define TAG(x) x##_rgba_st
-#include "radeon_maos_vbtmp.h"
-
-#define IDX 3
-#define IND (RADEON_CP_VC_FRMT_XY| \
- RADEON_CP_VC_FRMT_Z| \
- RADEON_CP_VC_FRMT_PKCOLOR| \
- RADEON_CP_VC_FRMT_N0)
-#define TAG(x) x##_rgba_n
-#include "radeon_maos_vbtmp.h"
-
-#define IDX 4
-#define IND (RADEON_CP_VC_FRMT_XY| \
- RADEON_CP_VC_FRMT_Z| \
- RADEON_CP_VC_FRMT_ST0| \
- RADEON_CP_VC_FRMT_N0)
-#define TAG(x) x##_st_n
-#include "radeon_maos_vbtmp.h"
-
-#define IDX 5
-#define IND (RADEON_CP_VC_FRMT_XY| \
- RADEON_CP_VC_FRMT_Z| \
- RADEON_CP_VC_FRMT_PKCOLOR| \
- RADEON_CP_VC_FRMT_ST0| \
- RADEON_CP_VC_FRMT_ST1)
-#define TAG(x) x##_rgba_st_st
-#include "radeon_maos_vbtmp.h"
-
-#define IDX 6
-#define IND (RADEON_CP_VC_FRMT_XY| \
- RADEON_CP_VC_FRMT_Z| \
- RADEON_CP_VC_FRMT_PKCOLOR| \
- RADEON_CP_VC_FRMT_ST0| \
- RADEON_CP_VC_FRMT_N0)
-#define TAG(x) x##_rgba_st_n
-#include "radeon_maos_vbtmp.h"
-
-#define IDX 7
-#define IND (RADEON_CP_VC_FRMT_XY| \
- RADEON_CP_VC_FRMT_Z| \
- RADEON_CP_VC_FRMT_PKCOLOR| \
- RADEON_CP_VC_FRMT_PKSPEC| \
- RADEON_CP_VC_FRMT_ST0| \
- RADEON_CP_VC_FRMT_ST1)
-#define TAG(x) x##_rgba_spec_st_st
-#include "radeon_maos_vbtmp.h"
-
-#define IDX 8
-#define IND (RADEON_CP_VC_FRMT_XY| \
- RADEON_CP_VC_FRMT_Z| \
- RADEON_CP_VC_FRMT_ST0| \
- RADEON_CP_VC_FRMT_ST1| \
- RADEON_CP_VC_FRMT_N0)
-#define TAG(x) x##_st_st_n
-#include "radeon_maos_vbtmp.h"
-
-#define IDX 9
-#define IND (RADEON_CP_VC_FRMT_XY| \
- RADEON_CP_VC_FRMT_Z| \
- RADEON_CP_VC_FRMT_PKCOLOR| \
- RADEON_CP_VC_FRMT_PKSPEC| \
- RADEON_CP_VC_FRMT_ST0| \
- RADEON_CP_VC_FRMT_ST1| \
- RADEON_CP_VC_FRMT_N0)
-#define TAG(x) x##_rgba_spec_st_st_n
-#include "radeon_maos_vbtmp.h"
-
-#define IDX 10
-#define IND (RADEON_CP_VC_FRMT_XY| \
- RADEON_CP_VC_FRMT_Z| \
- RADEON_CP_VC_FRMT_PKCOLOR| \
- RADEON_CP_VC_FRMT_ST0| \
- RADEON_CP_VC_FRMT_Q0)
-#define TAG(x) x##_rgba_stq
-#include "radeon_maos_vbtmp.h"
-
-#define IDX 11
-#define IND (RADEON_CP_VC_FRMT_XY| \
- RADEON_CP_VC_FRMT_Z| \
- RADEON_CP_VC_FRMT_PKCOLOR| \
- RADEON_CP_VC_FRMT_ST1| \
- RADEON_CP_VC_FRMT_Q1| \
- RADEON_CP_VC_FRMT_ST0| \
- RADEON_CP_VC_FRMT_Q0)
-#define TAG(x) x##_rgba_stq_stq
-#include "radeon_maos_vbtmp.h"
-
-#define IDX 12
-#define IND (RADEON_CP_VC_FRMT_XY| \
- RADEON_CP_VC_FRMT_Z| \
- RADEON_CP_VC_FRMT_W0| \
- RADEON_CP_VC_FRMT_PKCOLOR| \
- RADEON_CP_VC_FRMT_PKSPEC| \
- RADEON_CP_VC_FRMT_ST0| \
- RADEON_CP_VC_FRMT_Q0| \
- RADEON_CP_VC_FRMT_ST1| \
- RADEON_CP_VC_FRMT_Q1| \
- RADEON_CP_VC_FRMT_N0)
-#define TAG(x) x##_w_rgba_spec_stq_stq_n
-#include "radeon_maos_vbtmp.h"
-
-
-
-
-
-/***********************************************************************
- * Initialization
- ***********************************************************************/
-
-
-static void init_tcl_verts( void )
-{
- init_rgba();
- init_n();
- init_rgba_n();
- init_rgba_st();
- init_st_n();
- init_rgba_st_st();
- init_rgba_st_n();
- init_rgba_spec_st_st();
- init_st_st_n();
- init_rgba_spec_st_st_n();
- init_rgba_stq();
- init_rgba_stq_stq();
- init_w_rgba_spec_stq_stq_n();
-}
-
-
-void radeonEmitArrays( GLcontext *ctx, GLuint inputs )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- struct vertex_buffer *VB = &TNL_CONTEXT(ctx)->vb;
- GLuint req = 0;
- GLuint vtx = (rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] &
- ~(RADEON_TCL_VTX_Q0|RADEON_TCL_VTX_Q1));
- int i;
- static int firsttime = 1;
-
- if (firsttime) {
- init_tcl_verts();
- firsttime = 0;
- }
-
- if (1) {
- req |= RADEON_CP_VC_FRMT_Z;
- if (VB->ObjPtr->size == 4) {
- req |= RADEON_CP_VC_FRMT_W0;
- }
- }
-
- if (inputs & VERT_BIT_NORMAL) {
- req |= RADEON_CP_VC_FRMT_N0;
- }
-
- if (inputs & VERT_BIT_COLOR0) {
- req |= RADEON_CP_VC_FRMT_PKCOLOR;
- }
-
- if (inputs & VERT_BIT_COLOR1) {
- req |= RADEON_CP_VC_FRMT_PKSPEC;
- }
-
- if (inputs & VERT_BIT_TEX0) {
- req |= RADEON_CP_VC_FRMT_ST0;
-
- if (VB->TexCoordPtr[0]->size == 4) {
- req |= RADEON_CP_VC_FRMT_Q0;
- vtx |= RADEON_TCL_VTX_Q0;
- }
- }
-
- if (inputs & VERT_BIT_TEX1) {
- req |= RADEON_CP_VC_FRMT_ST1;
-
- if (VB->TexCoordPtr[1]->size == 4) {
- req |= RADEON_CP_VC_FRMT_Q1;
- vtx |= RADEON_TCL_VTX_Q1;
- }
- }
-
- if (vtx != rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT]) {
- RADEON_STATECHANGE( rmesa, tcl );
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] = vtx;
- }
-
- for (i = 0 ; i < RADEON_TCL_MAX_SETUP ; i++)
- if ((setup_tab[i].vertex_format & req) == req)
- break;
-
- if (rmesa->tcl.vertex_format == setup_tab[i].vertex_format &&
- rmesa->tcl.indexed_verts.buf)
- return;
-
- if (rmesa->tcl.indexed_verts.buf)
- radeonReleaseArrays( ctx, ~0 );
-
- radeonAllocDmaRegionVerts( rmesa,
- &rmesa->tcl.indexed_verts,
- VB->Count,
- setup_tab[i].vertex_size * 4,
- 4);
-
- /* The vertex code expects Obj to be clean to element 3. To fix
- * this, add more vertex code (for obj-2, obj-3) or preferably move
- * to maos.
- */
- if (VB->ObjPtr->size < 3 ||
- (VB->ObjPtr->size == 3 &&
- (setup_tab[i].vertex_format & RADEON_CP_VC_FRMT_W0))) {
-
- _math_trans_4f( rmesa->tcl.ObjClean.data,
- VB->ObjPtr->data,
- VB->ObjPtr->stride,
- GL_FLOAT,
- VB->ObjPtr->size,
- 0,
- VB->Count );
-
- switch (VB->ObjPtr->size) {
- case 1:
- _mesa_vector4f_clean_elem(&rmesa->tcl.ObjClean, VB->Count, 1);
- case 2:
- _mesa_vector4f_clean_elem(&rmesa->tcl.ObjClean, VB->Count, 2);
- case 3:
- if (setup_tab[i].vertex_format & RADEON_CP_VC_FRMT_W0) {
- _mesa_vector4f_clean_elem(&rmesa->tcl.ObjClean, VB->Count, 3);
- }
- case 4:
- default:
- break;
- }
-
- VB->ObjPtr = &rmesa->tcl.ObjClean;
- }
-
-
-
- setup_tab[i].emit( ctx, 0, VB->Count,
- rmesa->tcl.indexed_verts.address +
- rmesa->tcl.indexed_verts.start );
-
- rmesa->tcl.vertex_format = setup_tab[i].vertex_format;
- rmesa->tcl.indexed_verts.aos_start = GET_START( &rmesa->tcl.indexed_verts );
- rmesa->tcl.indexed_verts.aos_size = setup_tab[i].vertex_size;
- rmesa->tcl.indexed_verts.aos_stride = setup_tab[i].vertex_size;
-
- rmesa->tcl.aos_components[0] = &rmesa->tcl.indexed_verts;
- rmesa->tcl.nr_aos_components = 1;
-}
-
-
-
-void radeonReleaseArrays( GLcontext *ctx, GLuint newinputs )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
-
-#if 0
- if (RADEON_DEBUG & DEBUG_VERTS)
- _tnl_print_vert_flags( __FUNCTION__, newinputs );
-#endif
-
- if (newinputs)
- radeonReleaseDmaRegion( rmesa, &rmesa->tcl.indexed_verts, __FUNCTION__ );
-}
diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_sanity.c b/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_sanity.c
deleted file mode 100644
index 84112464e..000000000
--- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_sanity.c
+++ /dev/null
@@ -1,1070 +0,0 @@
-/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_sanity.c,v 1.1 2002/10/30 12:51:55 alanh Exp $ */
-/**************************************************************************
-
-Copyright 2002 ATI Technologies Inc., Ontario, Canada, and
- Tungsten Graphics Inc, Cedar Park, TX.
-
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining a
-copy of this software and associated documentation files (the "Software"),
-to deal in the Software without restriction, including without limitation
-on the rights to use, copy, modify, merge, publish, distribute, sub
-license, and/or sell copies of the Software, and to permit persons to whom
-the Software is furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice (including the next
-paragraph) shall be included in all copies or substantial portions of the
-Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
-ATI, TUNGSTEN GRAPHICS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
-DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/*
- * Authors:
- * Keith Whitwell <keith@tungstengraphics.com>
- *
- */
-#include <errno.h>
-
-#include "glheader.h"
-
-#include "radeon_context.h"
-#include "radeon_ioctl.h"
-#include "radeon_sanity.h"
-
-/* Set this '1' to get more verbiage.
- */
-#define MORE_VERBOSE 1
-
-#if MORE_VERBOSE
-#define VERBOSE (RADEON_DEBUG & DEBUG_VERBOSE)
-#define NORMAL (1)
-#else
-#define VERBOSE 0
-#define NORMAL (RADEON_DEBUG & DEBUG_VERBOSE)
-#endif
-
-
-/* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in
- * 1.3 cmdbuffers allow all previous state to be updated as well as
- * the tcl scalar and vector areas.
- */
-static struct {
- int start;
- int len;
- const char *name;
-} packet[RADEON_MAX_STATE_PACKETS] = {
- { RADEON_PP_MISC,7,"RADEON_PP_MISC" },
- { RADEON_PP_CNTL,3,"RADEON_PP_CNTL" },
- { RADEON_RB3D_COLORPITCH,1,"RADEON_RB3D_COLORPITCH" },
- { RADEON_RE_LINE_PATTERN,2,"RADEON_RE_LINE_PATTERN" },
- { RADEON_SE_LINE_WIDTH,1,"RADEON_SE_LINE_WIDTH" },
- { RADEON_PP_LUM_MATRIX,1,"RADEON_PP_LUM_MATRIX" },
- { RADEON_PP_ROT_MATRIX_0,2,"RADEON_PP_ROT_MATRIX_0" },
- { RADEON_RB3D_STENCILREFMASK,3,"RADEON_RB3D_STENCILREFMASK" },
- { RADEON_SE_VPORT_XSCALE,6,"RADEON_SE_VPORT_XSCALE" },
- { RADEON_SE_CNTL,2,"RADEON_SE_CNTL" },
- { RADEON_SE_CNTL_STATUS,1,"RADEON_SE_CNTL_STATUS" },
- { RADEON_RE_MISC,1,"RADEON_RE_MISC" },
- { RADEON_PP_TXFILTER_0,6,"RADEON_PP_TXFILTER_0" },
- { RADEON_PP_BORDER_COLOR_0,1,"RADEON_PP_BORDER_COLOR_0" },
- { RADEON_PP_TXFILTER_1,6,"RADEON_PP_TXFILTER_1" },
- { RADEON_PP_BORDER_COLOR_1,1,"RADEON_PP_BORDER_COLOR_1" },
- { RADEON_PP_TXFILTER_2,6,"RADEON_PP_TXFILTER_2" },
- { RADEON_PP_BORDER_COLOR_2,1,"RADEON_PP_BORDER_COLOR_2" },
- { RADEON_SE_ZBIAS_FACTOR,2,"RADEON_SE_ZBIAS_FACTOR" },
- { RADEON_SE_TCL_OUTPUT_VTX_FMT,11,"RADEON_SE_TCL_OUTPUT_VTX_FMT" },
- { RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED,17,"RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED" },
- { 0, 4, "R200_PP_TXCBLEND_0" },
- { 0, 4, "R200_PP_TXCBLEND_1" },
- { 0, 4, "R200_PP_TXCBLEND_2" },
- { 0, 4, "R200_PP_TXCBLEND_3" },
- { 0, 4, "R200_PP_TXCBLEND_4" },
- { 0, 4, "R200_PP_TXCBLEND_5" },
- { 0, 4, "R200_PP_TXCBLEND_6" },
- { 0, 4, "R200_PP_TXCBLEND_7" },
- { 0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0" },
- { 0, 6, "R200_PP_TFACTOR_0" },
- { 0, 4, "R200_SE_VTX_FMT_0" },
- { 0, 1, "R200_SE_VAP_CNTL" },
- { 0, 5, "R200_SE_TCL_MATRIX_SEL_0" },
- { 0, 5, "R200_SE_TCL_TEX_PROC_CTL_2" },
- { 0, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL" },
- { 0, 6, "R200_PP_TXFILTER_0" },
- { 0, 6, "R200_PP_TXFILTER_1" },
- { 0, 6, "R200_PP_TXFILTER_2" },
- { 0, 6, "R200_PP_TXFILTER_3" },
- { 0, 6, "R200_PP_TXFILTER_4" },
- { 0, 6, "R200_PP_TXFILTER_5" },
- { 0, 1, "R200_PP_TXOFFSET_0" },
- { 0, 1, "R200_PP_TXOFFSET_1" },
- { 0, 1, "R200_PP_TXOFFSET_2" },
- { 0, 1, "R200_PP_TXOFFSET_3" },
- { 0, 1, "R200_PP_TXOFFSET_4" },
- { 0, 1, "R200_PP_TXOFFSET_5" },
- { 0, 1, "R200_SE_VTE_CNTL" },
- { 0, 1, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" },
- { 0, 1, "R200_PP_TAM_DEBUG3" },
- { 0, 1, "R200_PP_CNTL_X" },
- { 0, 1, "R200_RB3D_DEPTHXY_OFFSET" },
- { 0, 1, "R200_RE_AUX_SCISSOR_CNTL" },
- { 0, 2, "R200_RE_SCISSOR_TL_0" },
- { 0, 2, "R200_RE_SCISSOR_TL_1" },
- { 0, 2, "R200_RE_SCISSOR_TL_2" },
- { 0, 1, "R200_SE_VAP_CNTL_STATUS" },
- { 0, 1, "R200_SE_VTX_STATE_CNTL" },
- { 0, 1, "R200_RE_POINTSIZE" },
- { 0, 4, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0" },
- { 0, 1, "R200_PP_CUBIC_FACES_0" }, /* 61 */
- { 0, 5, "R200_PP_CUBIC_OFFSET_F1_0" }, /* 62 */
- { 0, 1, "R200_PP_CUBIC_FACES_1" },
- { 0, 5, "R200_PP_CUBIC_OFFSET_F1_1" },
- { 0, 1, "R200_PP_CUBIC_FACES_2" },
- { 0, 5, "R200_PP_CUBIC_OFFSET_F1_2" },
- { 0, 1, "R200_PP_CUBIC_FACES_3" },
- { 0, 5, "R200_PP_CUBIC_OFFSET_F1_3" },
- { 0, 1, "R200_PP_CUBIC_FACES_4" },
- { 0, 5, "R200_PP_CUBIC_OFFSET_F1_4" },
- { 0, 1, "R200_PP_CUBIC_FACES_5" },
- { 0, 5, "R200_PP_CUBIC_OFFSET_F1_5" },
- { RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" },
- { RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" },
- { RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2" },
- { 0, 3, "R200_RB3D_BLENDCOLOR" },
- { 0, 1, "R200_SE_TCL_POINT_SPRITE_CNTL" },
- { RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0" },
- { RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0" },
- { RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1" },
- { RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0" },
- { RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2" },
- { RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0" },
- { 0, 2, "R200_PP_TRI_PERF" },
-};
-
-struct reg_names {
- int idx;
- const char *name;
-};
-
-static struct reg_names reg_names[] = {
- { RADEON_PP_MISC, "RADEON_PP_MISC" },
- { RADEON_PP_FOG_COLOR, "RADEON_PP_FOG_COLOR" },
- { RADEON_RE_SOLID_COLOR, "RADEON_RE_SOLID_COLOR" },
- { RADEON_RB3D_BLENDCNTL, "RADEON_RB3D_BLENDCNTL" },
- { RADEON_RB3D_DEPTHOFFSET, "RADEON_RB3D_DEPTHOFFSET" },
- { RADEON_RB3D_DEPTHPITCH, "RADEON_RB3D_DEPTHPITCH" },
- { RADEON_RB3D_ZSTENCILCNTL, "RADEON_RB3D_ZSTENCILCNTL" },
- { RADEON_PP_CNTL, "RADEON_PP_CNTL" },
- { RADEON_RB3D_CNTL, "RADEON_RB3D_CNTL" },
- { RADEON_RB3D_COLOROFFSET, "RADEON_RB3D_COLOROFFSET" },
- { RADEON_RB3D_COLORPITCH, "RADEON_RB3D_COLORPITCH" },
- { RADEON_SE_CNTL, "RADEON_SE_CNTL" },
- { RADEON_SE_COORD_FMT, "RADEON_SE_COORDFMT" },
- { RADEON_SE_CNTL_STATUS, "RADEON_SE_CNTL_STATUS" },
- { RADEON_RE_LINE_PATTERN, "RADEON_RE_LINE_PATTERN" },
- { RADEON_RE_LINE_STATE, "RADEON_RE_LINE_STATE" },
- { RADEON_SE_LINE_WIDTH, "RADEON_SE_LINE_WIDTH" },
- { RADEON_RB3D_STENCILREFMASK, "RADEON_RB3D_STENCILREFMASK" },
- { RADEON_RB3D_ROPCNTL, "RADEON_RB3D_ROPCNTL" },
- { RADEON_RB3D_PLANEMASK, "RADEON_RB3D_PLANEMASK" },
- { RADEON_SE_VPORT_XSCALE, "RADEON_SE_VPORT_XSCALE" },
- { RADEON_SE_VPORT_XOFFSET, "RADEON_SE_VPORT_XOFFSET" },
- { RADEON_SE_VPORT_YSCALE, "RADEON_SE_VPORT_YSCALE" },
- { RADEON_SE_VPORT_YOFFSET, "RADEON_SE_VPORT_YOFFSET" },
- { RADEON_SE_VPORT_ZSCALE, "RADEON_SE_VPORT_ZSCALE" },
- { RADEON_SE_VPORT_ZOFFSET, "RADEON_SE_VPORT_ZOFFSET" },
- { RADEON_RE_MISC, "RADEON_RE_MISC" },
- { RADEON_PP_TXFILTER_0, "RADEON_PP_TXFILTER_0" },
- { RADEON_PP_TXFILTER_1, "RADEON_PP_TXFILTER_1" },
- { RADEON_PP_TXFILTER_2, "RADEON_PP_TXFILTER_2" },
- { RADEON_PP_TXFORMAT_0, "RADEON_PP_TXFORMAT_0" },
- { RADEON_PP_TXFORMAT_1, "RADEON_PP_TXFORMAT_1" },
- { RADEON_PP_TXFORMAT_2, "RADEON_PP_TXFORMAT_2" },
- { RADEON_PP_TXOFFSET_0, "RADEON_PP_TXOFFSET_0" },
- { RADEON_PP_TXOFFSET_1, "RADEON_PP_TXOFFSET_1" },
- { RADEON_PP_TXOFFSET_2, "RADEON_PP_TXOFFSET_2" },
- { RADEON_PP_TXCBLEND_0, "RADEON_PP_TXCBLEND_0" },
- { RADEON_PP_TXCBLEND_1, "RADEON_PP_TXCBLEND_1" },
- { RADEON_PP_TXCBLEND_2, "RADEON_PP_TXCBLEND_2" },
- { RADEON_PP_TXABLEND_0, "RADEON_PP_TXABLEND_0" },
- { RADEON_PP_TXABLEND_1, "RADEON_PP_TXABLEND_1" },
- { RADEON_PP_TXABLEND_2, "RADEON_PP_TXABLEND_2" },
- { RADEON_PP_TFACTOR_0, "RADEON_PP_TFACTOR_0" },
- { RADEON_PP_TFACTOR_1, "RADEON_PP_TFACTOR_1" },
- { RADEON_PP_TFACTOR_2, "RADEON_PP_TFACTOR_2" },
- { RADEON_PP_BORDER_COLOR_0, "RADEON_PP_BORDER_COLOR_0" },
- { RADEON_PP_BORDER_COLOR_1, "RADEON_PP_BORDER_COLOR_1" },
- { RADEON_PP_BORDER_COLOR_2, "RADEON_PP_BORDER_COLOR_2" },
- { RADEON_SE_ZBIAS_FACTOR, "RADEON_SE_ZBIAS_FACTOR" },
- { RADEON_SE_ZBIAS_CONSTANT, "RADEON_SE_ZBIAS_CONSTANT" },
- { RADEON_SE_TCL_OUTPUT_VTX_FMT, "RADEON_SE_TCL_OUTPUT_VTXFMT" },
- { RADEON_SE_TCL_OUTPUT_VTX_SEL, "RADEON_SE_TCL_OUTPUT_VTXSEL" },
- { RADEON_SE_TCL_MATRIX_SELECT_0, "RADEON_SE_TCL_MATRIX_SELECT_0" },
- { RADEON_SE_TCL_MATRIX_SELECT_1, "RADEON_SE_TCL_MATRIX_SELECT_1" },
- { RADEON_SE_TCL_UCP_VERT_BLEND_CTL, "RADEON_SE_TCL_UCP_VERT_BLEND_CTL" },
- { RADEON_SE_TCL_TEXTURE_PROC_CTL, "RADEON_SE_TCL_TEXTURE_PROC_CTL" },
- { RADEON_SE_TCL_LIGHT_MODEL_CTL, "RADEON_SE_TCL_LIGHT_MODEL_CTL" },
- { RADEON_SE_TCL_PER_LIGHT_CTL_0, "RADEON_SE_TCL_PER_LIGHT_CTL_0" },
- { RADEON_SE_TCL_PER_LIGHT_CTL_1, "RADEON_SE_TCL_PER_LIGHT_CTL_1" },
- { RADEON_SE_TCL_PER_LIGHT_CTL_2, "RADEON_SE_TCL_PER_LIGHT_CTL_2" },
- { RADEON_SE_TCL_PER_LIGHT_CTL_3, "RADEON_SE_TCL_PER_LIGHT_CTL_3" },
- { RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, "RADEON_SE_TCL_EMMISSIVE_RED" },
- { RADEON_SE_TCL_MATERIAL_EMMISSIVE_GREEN, "RADEON_SE_TCL_EMMISSIVE_GREEN" },
- { RADEON_SE_TCL_MATERIAL_EMMISSIVE_BLUE, "RADEON_SE_TCL_EMMISSIVE_BLUE" },
- { RADEON_SE_TCL_MATERIAL_EMMISSIVE_ALPHA, "RADEON_SE_TCL_EMMISSIVE_ALPHA" },
- { RADEON_SE_TCL_MATERIAL_AMBIENT_RED, "RADEON_SE_TCL_AMBIENT_RED" },
- { RADEON_SE_TCL_MATERIAL_AMBIENT_GREEN, "RADEON_SE_TCL_AMBIENT_GREEN" },
- { RADEON_SE_TCL_MATERIAL_AMBIENT_BLUE, "RADEON_SE_TCL_AMBIENT_BLUE" },
- { RADEON_SE_TCL_MATERIAL_AMBIENT_ALPHA, "RADEON_SE_TCL_AMBIENT_ALPHA" },
- { RADEON_SE_TCL_MATERIAL_DIFFUSE_RED, "RADEON_SE_TCL_DIFFUSE_RED" },
- { RADEON_SE_TCL_MATERIAL_DIFFUSE_GREEN, "RADEON_SE_TCL_DIFFUSE_GREEN" },
- { RADEON_SE_TCL_MATERIAL_DIFFUSE_BLUE, "RADEON_SE_TCL_DIFFUSE_BLUE" },
- { RADEON_SE_TCL_MATERIAL_DIFFUSE_ALPHA, "RADEON_SE_TCL_DIFFUSE_ALPHA" },
- { RADEON_SE_TCL_MATERIAL_SPECULAR_RED, "RADEON_SE_TCL_SPECULAR_RED" },
- { RADEON_SE_TCL_MATERIAL_SPECULAR_GREEN, "RADEON_SE_TCL_SPECULAR_GREEN" },
- { RADEON_SE_TCL_MATERIAL_SPECULAR_BLUE, "RADEON_SE_TCL_SPECULAR_BLUE" },
- { RADEON_SE_TCL_MATERIAL_SPECULAR_ALPHA, "RADEON_SE_TCL_SPECULAR_ALPHA" },
- { RADEON_SE_TCL_SHININESS, "RADEON_SE_TCL_SHININESS" },
- { RADEON_SE_COORD_FMT, "RADEON_SE_COORD_FMT" },
- { RADEON_PP_TEX_SIZE_0, "RADEON_PP_TEX_SIZE_0" },
- { RADEON_PP_TEX_SIZE_1, "RADEON_PP_TEX_SIZE_1" },
- { RADEON_PP_TEX_SIZE_2, "RADEON_PP_TEX_SIZE_2" },
- { RADEON_PP_TEX_SIZE_0+4, "RADEON_PP_TEX_PITCH_0" },
- { RADEON_PP_TEX_SIZE_1+4, "RADEON_PP_TEX_PITCH_1" },
- { RADEON_PP_TEX_SIZE_2+4, "RADEON_PP_TEX_PITCH_2" },
- { RADEON_PP_CUBIC_FACES_0, "RADEON_PP_CUBIC_FACES_0" },
- { RADEON_PP_CUBIC_FACES_1, "RADEON_PP_CUBIC_FACES_1" },
- { RADEON_PP_CUBIC_FACES_2, "RADEON_PP_CUBIC_FACES_2" },
- { RADEON_PP_CUBIC_OFFSET_T0_0, "RADEON_PP_CUBIC_OFFSET_T0_0" },
- { RADEON_PP_CUBIC_OFFSET_T0_1, "RADEON_PP_CUBIC_OFFSET_T0_1" },
- { RADEON_PP_CUBIC_OFFSET_T0_2, "RADEON_PP_CUBIC_OFFSET_T0_2" },
- { RADEON_PP_CUBIC_OFFSET_T0_3, "RADEON_PP_CUBIC_OFFSET_T0_3" },
- { RADEON_PP_CUBIC_OFFSET_T0_4, "RADEON_PP_CUBIC_OFFSET_T0_4" },
- { RADEON_PP_CUBIC_OFFSET_T1_0, "RADEON_PP_CUBIC_OFFSET_T1_0" },
- { RADEON_PP_CUBIC_OFFSET_T1_1, "RADEON_PP_CUBIC_OFFSET_T1_1" },
- { RADEON_PP_CUBIC_OFFSET_T1_2, "RADEON_PP_CUBIC_OFFSET_T1_2" },
- { RADEON_PP_CUBIC_OFFSET_T1_3, "RADEON_PP_CUBIC_OFFSET_T1_3" },
- { RADEON_PP_CUBIC_OFFSET_T1_4, "RADEON_PP_CUBIC_OFFSET_T1_4" },
- { RADEON_PP_CUBIC_OFFSET_T2_0, "RADEON_PP_CUBIC_OFFSET_T2_0" },
- { RADEON_PP_CUBIC_OFFSET_T2_1, "RADEON_PP_CUBIC_OFFSET_T2_1" },
- { RADEON_PP_CUBIC_OFFSET_T2_2, "RADEON_PP_CUBIC_OFFSET_T2_2" },
- { RADEON_PP_CUBIC_OFFSET_T2_3, "RADEON_PP_CUBIC_OFFSET_T2_3" },
- { RADEON_PP_CUBIC_OFFSET_T2_4, "RADEON_PP_CUBIC_OFFSET_T2_4" },
-};
-
-static struct reg_names scalar_names[] = {
- { RADEON_SS_LIGHT_DCD_ADDR, "LIGHT_DCD" },
- { RADEON_SS_LIGHT_SPOT_EXPONENT_ADDR, "LIGHT_SPOT_EXPONENT" },
- { RADEON_SS_LIGHT_SPOT_CUTOFF_ADDR, "LIGHT_SPOT_CUTOFF" },
- { RADEON_SS_LIGHT_SPECULAR_THRESH_ADDR, "LIGHT_SPECULAR_THRESH" },
- { RADEON_SS_LIGHT_RANGE_CUTOFF_ADDR, "LIGHT_RANGE_CUTOFF" },
- { RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR, "VERT_GUARD_CLIP" },
- { RADEON_SS_VERT_GUARD_DISCARD_ADJ_ADDR, "VERT_GUARD_DISCARD" },
- { RADEON_SS_HORZ_GUARD_CLIP_ADJ_ADDR, "HORZ_GUARD_CLIP" },
- { RADEON_SS_HORZ_GUARD_DISCARD_ADJ_ADDR, "HORZ_GUARD_DISCARD" },
- { RADEON_SS_SHININESS, "SHININESS" },
- { 1000, "" },
-};
-
-/* Puff these out to make them look like normal (dword) registers.
- */
-static struct reg_names vector_names[] = {
- { RADEON_VS_MATRIX_0_ADDR * 4, "MATRIX_0" },
- { RADEON_VS_MATRIX_1_ADDR * 4, "MATRIX_1" },
- { RADEON_VS_MATRIX_2_ADDR * 4, "MATRIX_2" },
- { RADEON_VS_MATRIX_3_ADDR * 4, "MATRIX_3" },
- { RADEON_VS_MATRIX_4_ADDR * 4, "MATRIX_4" },
- { RADEON_VS_MATRIX_5_ADDR * 4, "MATRIX_5" },
- { RADEON_VS_MATRIX_6_ADDR * 4, "MATRIX_6" },
- { RADEON_VS_MATRIX_7_ADDR * 4, "MATRIX_7" },
- { RADEON_VS_MATRIX_8_ADDR * 4, "MATRIX_8" },
- { RADEON_VS_MATRIX_9_ADDR * 4, "MATRIX_9" },
- { RADEON_VS_MATRIX_10_ADDR * 4, "MATRIX_10" },
- { RADEON_VS_MATRIX_11_ADDR * 4, "MATRIX_11" },
- { RADEON_VS_MATRIX_12_ADDR * 4, "MATRIX_12" },
- { RADEON_VS_MATRIX_13_ADDR * 4, "MATRIX_13" },
- { RADEON_VS_MATRIX_14_ADDR * 4, "MATRIX_14" },
- { RADEON_VS_MATRIX_15_ADDR * 4, "MATRIX_15" },
- { RADEON_VS_LIGHT_AMBIENT_ADDR * 4, "LIGHT_AMBIENT" },
- { RADEON_VS_LIGHT_DIFFUSE_ADDR * 4, "LIGHT_DIFFUSE" },
- { RADEON_VS_LIGHT_SPECULAR_ADDR * 4, "LIGHT_SPECULAR" },
- { RADEON_VS_LIGHT_DIRPOS_ADDR * 4, "LIGHT_DIRPOS" },
- { RADEON_VS_LIGHT_HWVSPOT_ADDR * 4, "LIGHT_HWVSPOT" },
- { RADEON_VS_LIGHT_ATTENUATION_ADDR * 4, "LIGHT_ATTENUATION" },
- { RADEON_VS_MATRIX_EYE2CLIP_ADDR * 4, "MATRIX_EYE2CLIP" },
- { RADEON_VS_UCP_ADDR * 4, "UCP" },
- { RADEON_VS_GLOBAL_AMBIENT_ADDR * 4, "GLOBAL_AMBIENT" },
- { RADEON_VS_FOG_PARAM_ADDR * 4, "FOG_PARAM" },
- { RADEON_VS_EYE_VECTOR_ADDR * 4, "EYE_VECTOR" },
- { 1000, "" },
-};
-
-union fi { float f; int i; };
-
-#define ISVEC 1
-#define ISFLOAT 2
-#define TOUCHED 4
-
-struct reg {
- int idx;
- struct reg_names *closest;
- int flags;
- union fi current;
- union fi *values;
- int nvalues;
- int nalloc;
- float vmin, vmax;
-};
-
-
-static struct reg regs[Elements(reg_names)+1];
-static struct reg scalars[512+1];
-static struct reg vectors[512*4+1];
-
-static int total, total_changed, bufs;
-
-static void init_regs( void )
-{
- struct reg_names *tmp;
- int i;
-
- for (i = 0 ; i < Elements(regs) ; i++) {
- regs[i].idx = reg_names[i].idx;
- regs[i].closest = &reg_names[i];
- regs[i].flags = 0;
- }
-
- for (i = 0, tmp = scalar_names ; i < Elements(scalars) ; i++) {
- if (tmp[1].idx == i) tmp++;
- scalars[i].idx = i;
- scalars[i].closest = tmp;
- scalars[i].flags = ISFLOAT;
- }
-
- for (i = 0, tmp = vector_names ; i < Elements(vectors) ; i++) {
- if (tmp[1].idx*4 == i) tmp++;
- vectors[i].idx = i;
- vectors[i].closest = tmp;
- vectors[i].flags = ISFLOAT|ISVEC;
- }
-
- regs[Elements(regs)-1].idx = -1;
- scalars[Elements(scalars)-1].idx = -1;
- vectors[Elements(vectors)-1].idx = -1;
-}
-
-static int find_or_add_value( struct reg *reg, int val )
-{
- int j;
-
- for ( j = 0 ; j < reg->nvalues ; j++)
- if ( val == reg->values[j].i )
- return 1;
-
- if (j == reg->nalloc) {
- reg->nalloc += 5;
- reg->nalloc *= 2;
- reg->values = (union fi *) realloc( reg->values,
- reg->nalloc * sizeof(union fi) );
- }
-
- reg->values[reg->nvalues++].i = val;
- return 0;
-}
-
-static struct reg *lookup_reg( struct reg *tab, int reg )
-{
- int i;
-
- for (i = 0 ; tab[i].idx != -1 ; i++) {
- if (tab[i].idx == reg)
- return &tab[i];
- }
-
- fprintf(stderr, "*** unknown reg 0x%x\n", reg);
- return NULL;
-}
-
-
-static const char *get_reg_name( struct reg *reg )
-{
- static char tmp[80];
-
- if (reg->idx == reg->closest->idx)
- return reg->closest->name;
-
-
- if (reg->flags & ISVEC) {
- if (reg->idx/4 != reg->closest->idx)
- sprintf(tmp, "%s+%d[%d]",
- reg->closest->name,
- (reg->idx/4) - reg->closest->idx,
- reg->idx%4);
- else
- sprintf(tmp, "%s[%d]", reg->closest->name, reg->idx%4);
- }
- else {
- if (reg->idx != reg->closest->idx)
- sprintf(tmp, "%s+%d", reg->closest->name, reg->idx - reg->closest->idx);
- else
- sprintf(tmp, "%s", reg->closest->name);
- }
-
- return tmp;
-}
-
-static int print_int_reg_assignment( struct reg *reg, int data )
-{
- int changed = (reg->current.i != data);
- int ever_seen = find_or_add_value( reg, data );
-
- if (VERBOSE || (NORMAL && (changed || !ever_seen)))
- fprintf(stderr, " %s <-- 0x%x", get_reg_name(reg), data);
-
- if (NORMAL) {
- if (!ever_seen)
- fprintf(stderr, " *** BRAND NEW VALUE");
- else if (changed)
- fprintf(stderr, " *** CHANGED");
- }
-
- reg->current.i = data;
-
- if (VERBOSE || (NORMAL && (changed || !ever_seen)))
- fprintf(stderr, "\n");
-
- return changed;
-}
-
-
-static int print_float_reg_assignment( struct reg *reg, float data )
-{
- int changed = (reg->current.f != data);
- int newmin = (data < reg->vmin);
- int newmax = (data > reg->vmax);
-
- if (VERBOSE || (NORMAL && (newmin || newmax || changed)))
- fprintf(stderr, " %s <-- %.3f", get_reg_name(reg), data);
-
- if (NORMAL) {
- if (newmin) {
- fprintf(stderr, " *** NEW MIN (prev %.3f)", reg->vmin);
- reg->vmin = data;
- }
- else if (newmax) {
- fprintf(stderr, " *** NEW MAX (prev %.3f)", reg->vmax);
- reg->vmax = data;
- }
- else if (changed) {
- fprintf(stderr, " *** CHANGED");
- }
- }
-
- reg->current.f = data;
-
- if (VERBOSE || (NORMAL && (newmin || newmax || changed)))
- fprintf(stderr, "\n");
-
- return changed;
-}
-
-static int print_reg_assignment( struct reg *reg, int data )
-{
- reg->flags |= TOUCHED;
- if (reg->flags & ISFLOAT)
- return print_float_reg_assignment( reg, *(float *)&data );
- else
- return print_int_reg_assignment( reg, data );
-}
-
-static void print_reg( struct reg *reg )
-{
- if (reg->flags & TOUCHED) {
- if (reg->flags & ISFLOAT) {
- fprintf(stderr, " %s == %f\n", get_reg_name(reg), reg->current.f);
- } else {
- fprintf(stderr, " %s == 0x%x\n", get_reg_name(reg), reg->current.i);
- }
- }
-}
-
-
-static void dump_state( void )
-{
- int i;
-
- for (i = 0 ; i < Elements(regs) ; i++)
- print_reg( &regs[i] );
-
- for (i = 0 ; i < Elements(scalars) ; i++)
- print_reg( &scalars[i] );
-
- for (i = 0 ; i < Elements(vectors) ; i++)
- print_reg( &vectors[i] );
-}
-
-
-
-static int radeon_emit_packets(
- drm_radeon_cmd_header_t header,
- drm_radeon_cmd_buffer_t *cmdbuf )
-{
- int id = (int)header.packet.packet_id;
- int sz = packet[id].len;
- int *data = (int *)cmdbuf->buf;
- int i;
-
- if (sz * sizeof(int) > cmdbuf->bufsz) {
- fprintf(stderr, "Packet overflows cmdbuf\n");
- return -EINVAL;
- }
-
- if (!packet[id].name) {
- fprintf(stderr, "*** Unknown packet 0 nr %d\n", id );
- return -EINVAL;
- }
-
-
- if (VERBOSE)
- fprintf(stderr, "Packet 0 reg %s nr %d\n", packet[id].name, sz );
-
- for ( i = 0 ; i < sz ; i++) {
- struct reg *reg = lookup_reg( regs, packet[id].start + i*4 );
- if (print_reg_assignment( reg, data[i] ))
- total_changed++;
- total++;
- }
-
- cmdbuf->buf += sz * sizeof(int);
- cmdbuf->bufsz -= sz * sizeof(int);
- return 0;
-}
-
-
-static int radeon_emit_scalars(
- drm_radeon_cmd_header_t header,
- drm_radeon_cmd_buffer_t *cmdbuf )
-{
- int sz = header.scalars.count;
- int *data = (int *)cmdbuf->buf;
- int start = header.scalars.offset;
- int stride = header.scalars.stride;
- int i;
-
- if (VERBOSE)
- fprintf(stderr, "emit scalars, start %d stride %d nr %d (end %d)\n",
- start, stride, sz, start + stride * sz);
-
-
- for (i = 0 ; i < sz ; i++, start += stride) {
- struct reg *reg = lookup_reg( scalars, start );
- if (print_reg_assignment( reg, data[i] ))
- total_changed++;
- total++;
- }
-
- cmdbuf->buf += sz * sizeof(int);
- cmdbuf->bufsz -= sz * sizeof(int);
- return 0;
-}
-
-
-static int radeon_emit_scalars2(
- drm_radeon_cmd_header_t header,
- drm_radeon_cmd_buffer_t *cmdbuf )
-{
- int sz = header.scalars.count;
- int *data = (int *)cmdbuf->buf;
- int start = header.scalars.offset + 0x100;
- int stride = header.scalars.stride;
- int i;
-
- if (VERBOSE)
- fprintf(stderr, "emit scalars2, start %d stride %d nr %d (end %d)\n",
- start, stride, sz, start + stride * sz);
-
- if (start + stride * sz > 257) {
- fprintf(stderr, "emit scalars OVERFLOW %d/%d/%d\n", start, stride, sz);
- return -1;
- }
-
- for (i = 0 ; i < sz ; i++, start += stride) {
- struct reg *reg = lookup_reg( scalars, start );
- if (print_reg_assignment( reg, data[i] ))
- total_changed++;
- total++;
- }
-
- cmdbuf->buf += sz * sizeof(int);
- cmdbuf->bufsz -= sz * sizeof(int);
- return 0;
-}
-
-/* Check: inf/nan/extreme-size?
- * Check: table start, end, nr, etc.
- */
-static int radeon_emit_vectors(
- drm_radeon_cmd_header_t header,
- drm_radeon_cmd_buffer_t *cmdbuf )
-{
- int sz = header.vectors.count;
- int *data = (int *)cmdbuf->buf;
- int start = header.vectors.offset;
- int stride = header.vectors.stride;
- int i,j;
-
- if (VERBOSE)
- fprintf(stderr, "emit vectors, start %d stride %d nr %d (end %d) (0x%x)\n",
- start, stride, sz, start + stride * sz, header.i);
-
-/* if (start + stride * (sz/4) > 128) { */
-/* fprintf(stderr, "emit vectors OVERFLOW %d/%d/%d\n", start, stride, sz); */
-/* return -1; */
-/* } */
-
- for (i = 0 ; i < sz ; start += stride) {
- int changed = 0;
- for (j = 0 ; j < 4 ; i++,j++) {
- struct reg *reg = lookup_reg( vectors, start*4+j );
- if (print_reg_assignment( reg, data[i] ))
- changed = 1;
- }
- if (changed)
- total_changed += 4;
- total += 4;
- }
-
-
- cmdbuf->buf += sz * sizeof(int);
- cmdbuf->bufsz -= sz * sizeof(int);
- return 0;
-}
-
-
-static int print_vertex_format( int vfmt )
-{
- if (NORMAL) {
- fprintf(stderr, " %s(%x): %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
- "vertex format",
- vfmt,
- "xy,",
- (vfmt & RADEON_CP_VC_FRMT_Z) ? "z," : "",
- (vfmt & RADEON_CP_VC_FRMT_W0) ? "w0," : "",
- (vfmt & RADEON_CP_VC_FRMT_FPCOLOR) ? "fpcolor," : "",
- (vfmt & RADEON_CP_VC_FRMT_FPALPHA) ? "fpalpha," : "",
- (vfmt & RADEON_CP_VC_FRMT_PKCOLOR) ? "pkcolor," : "",
- (vfmt & RADEON_CP_VC_FRMT_FPSPEC) ? "fpspec," : "",
- (vfmt & RADEON_CP_VC_FRMT_FPFOG) ? "fpfog," : "",
- (vfmt & RADEON_CP_VC_FRMT_PKSPEC) ? "pkspec," : "",
- (vfmt & RADEON_CP_VC_FRMT_ST0) ? "st0," : "",
- (vfmt & RADEON_CP_VC_FRMT_ST1) ? "st1," : "",
- (vfmt & RADEON_CP_VC_FRMT_Q1) ? "q1," : "",
- (vfmt & RADEON_CP_VC_FRMT_ST2) ? "st2," : "",
- (vfmt & RADEON_CP_VC_FRMT_Q2) ? "q2," : "",
- (vfmt & RADEON_CP_VC_FRMT_ST3) ? "st3," : "",
- (vfmt & RADEON_CP_VC_FRMT_Q3) ? "q3," : "",
- (vfmt & RADEON_CP_VC_FRMT_Q0) ? "q0," : "",
- (vfmt & RADEON_CP_VC_FRMT_N0) ? "n0," : "",
- (vfmt & RADEON_CP_VC_FRMT_XY1) ? "xy1," : "",
- (vfmt & RADEON_CP_VC_FRMT_Z1) ? "z1," : "",
- (vfmt & RADEON_CP_VC_FRMT_W1) ? "w1," : "",
- (vfmt & RADEON_CP_VC_FRMT_N1) ? "n1," : "");
-
-
-/* if (!find_or_add_value( &others[V_VTXFMT], vfmt )) */
-/* fprintf(stderr, " *** NEW VALUE"); */
-
- fprintf(stderr, "\n");
- }
-
- return 0;
-}
-
-static char *primname[0xf] = {
- "NONE",
- "POINTS",
- "LINES",
- "LINE_STRIP",
- "TRIANGLES",
- "TRIANGLE_FAN",
- "TRIANGLE_STRIP",
- "TRI_TYPE_2",
- "RECT_LIST",
- "3VRT_POINTS",
- "3VRT_LINES",
-};
-
-static int print_prim_and_flags( int prim )
-{
- int numverts;
-
- if (NORMAL)
- fprintf(stderr, " %s(%x): %s%s%s%s%s%s%s\n",
- "prim flags",
- prim,
- ((prim & 0x30) == RADEON_CP_VC_CNTL_PRIM_WALK_IND) ? "IND," : "",
- ((prim & 0x30) == RADEON_CP_VC_CNTL_PRIM_WALK_LIST) ? "LIST," : "",
- ((prim & 0x30) == RADEON_CP_VC_CNTL_PRIM_WALK_RING) ? "RING," : "",
- (prim & RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA) ? "RGBA," : "BGRA, ",
- (prim & RADEON_CP_VC_CNTL_MAOS_ENABLE) ? "MAOS," : "",
- (prim & RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE) ? "RADEON," : "",
- (prim & RADEON_CP_VC_CNTL_TCL_ENABLE) ? "TCL," : "");
-
- if ((prim & 0xf) > RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST) {
- fprintf(stderr, " *** Bad primitive: %x\n", prim & 0xf);
- return -1;
- }
-
- numverts = prim>>16;
-
- if (NORMAL)
- fprintf(stderr, " prim: %s numverts %d\n", primname[prim&0xf], numverts);
-
- switch (prim & 0xf) {
- case RADEON_CP_VC_CNTL_PRIM_TYPE_NONE:
- case RADEON_CP_VC_CNTL_PRIM_TYPE_POINT:
- if (numverts < 1) {
- fprintf(stderr, "Bad nr verts for line %d\n", numverts);
- return -1;
- }
- break;
- case RADEON_CP_VC_CNTL_PRIM_TYPE_LINE:
- if ((numverts & 1) || numverts == 0) {
- fprintf(stderr, "Bad nr verts for line %d\n", numverts);
- return -1;
- }
- break;
- case RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP:
- if (numverts < 2) {
- fprintf(stderr, "Bad nr verts for line_strip %d\n", numverts);
- return -1;
- }
- break;
- case RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST:
- case RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST:
- case RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST:
- case RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST:
- if (numverts % 3 || numverts == 0) {
- fprintf(stderr, "Bad nr verts for tri %d\n", numverts);
- return -1;
- }
- break;
- case RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN:
- case RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP:
- if (numverts < 3) {
- fprintf(stderr, "Bad nr verts for strip/fan %d\n", numverts);
- return -1;
- }
- break;
- default:
- fprintf(stderr, "Bad primitive\n");
- return -1;
- }
- return 0;
-}
-
-/* build in knowledge about each packet type
- */
-static int radeon_emit_packet3( drm_radeon_cmd_buffer_t *cmdbuf )
-{
- int cmdsz;
- int *cmd = (int *)cmdbuf->buf;
- int *tmp;
- int i, stride, size, start;
-
- cmdsz = 2 + ((cmd[0] & RADEON_CP_PACKET_COUNT_MASK) >> 16);
-
- if ((cmd[0] & RADEON_CP_PACKET_MASK) != RADEON_CP_PACKET3 ||
- cmdsz * 4 > cmdbuf->bufsz ||
- cmdsz > RADEON_CP_PACKET_MAX_DWORDS) {
- fprintf(stderr, "Bad packet\n");
- return -EINVAL;
- }
-
- switch( cmd[0] & ~RADEON_CP_PACKET_COUNT_MASK ) {
- case RADEON_CP_PACKET3_NOP:
- if (NORMAL)
- fprintf(stderr, "PACKET3_NOP, %d dwords\n", cmdsz);
- break;
- case RADEON_CP_PACKET3_NEXT_CHAR:
- if (NORMAL)
- fprintf(stderr, "PACKET3_NEXT_CHAR, %d dwords\n", cmdsz);
- break;
- case RADEON_CP_PACKET3_PLY_NEXTSCAN:
- if (NORMAL)
- fprintf(stderr, "PACKET3_PLY_NEXTSCAN, %d dwords\n", cmdsz);
- break;
- case RADEON_CP_PACKET3_SET_SCISSORS:
- if (NORMAL)
- fprintf(stderr, "PACKET3_SET_SCISSORS, %d dwords\n", cmdsz);
- break;
- case RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM:
- if (NORMAL)
- fprintf(stderr, "PACKET3_3D_RNDR_GEN_INDX_PRIM, %d dwords\n",
- cmdsz);
- break;
- case RADEON_CP_PACKET3_LOAD_MICROCODE:
- if (NORMAL)
- fprintf(stderr, "PACKET3_LOAD_MICROCODE, %d dwords\n", cmdsz);
- break;
- case RADEON_CP_PACKET3_WAIT_FOR_IDLE:
- if (NORMAL)
- fprintf(stderr, "PACKET3_WAIT_FOR_IDLE, %d dwords\n", cmdsz);
- break;
-
- case RADEON_CP_PACKET3_3D_DRAW_VBUF:
- if (NORMAL)
- fprintf(stderr, "PACKET3_3D_DRAW_VBUF, %d dwords\n", cmdsz);
- print_vertex_format(cmd[1]);
- print_prim_and_flags(cmd[2]);
- break;
-
- case RADEON_CP_PACKET3_3D_DRAW_IMMD:
- if (NORMAL)
- fprintf(stderr, "PACKET3_3D_DRAW_IMMD, %d dwords\n", cmdsz);
- break;
- case RADEON_CP_PACKET3_3D_DRAW_INDX: {
- int neltdwords;
- if (NORMAL)
- fprintf(stderr, "PACKET3_3D_DRAW_INDX, %d dwords\n", cmdsz);
- print_vertex_format(cmd[1]);
- print_prim_and_flags(cmd[2]);
- neltdwords = cmd[2]>>16;
- neltdwords += neltdwords & 1;
- neltdwords /= 2;
- if (neltdwords + 3 != cmdsz)
- fprintf(stderr, "Mismatch in DRAW_INDX, %d vs cmdsz %d\n",
- neltdwords, cmdsz);
- break;
- }
- case RADEON_CP_PACKET3_LOAD_PALETTE:
- if (NORMAL)
- fprintf(stderr, "PACKET3_LOAD_PALETTE, %d dwords\n", cmdsz);
- break;
- case RADEON_CP_PACKET3_3D_LOAD_VBPNTR:
- if (NORMAL) {
- fprintf(stderr, "PACKET3_3D_LOAD_VBPNTR, %d dwords\n", cmdsz);
- fprintf(stderr, " nr arrays: %d\n", cmd[1]);
- }
-
- if (cmd[1]/2 + cmd[1]%2 != cmdsz - 3) {
- fprintf(stderr, " ****** MISMATCH %d/%d *******\n",
- cmd[1]/2 + cmd[1]%2 + 3, cmdsz);
- return -EINVAL;
- }
-
- if (NORMAL) {
- tmp = cmd+2;
- for (i = 0 ; i < cmd[1] ; i++) {
- if (i & 1) {
- stride = (tmp[0]>>24) & 0xff;
- size = (tmp[0]>>16) & 0xff;
- start = tmp[2];
- tmp += 3;
- }
- else {
- stride = (tmp[0]>>8) & 0xff;
- size = (tmp[0]) & 0xff;
- start = tmp[1];
- }
- fprintf(stderr, " array %d: start 0x%x vsize %d vstride %d\n",
- i, start, size, stride );
- }
- }
- break;
- case RADEON_CP_PACKET3_CNTL_PAINT:
- if (NORMAL)
- fprintf(stderr, "PACKET3_CNTL_PAINT, %d dwords\n", cmdsz);
- break;
- case RADEON_CP_PACKET3_CNTL_BITBLT:
- if (NORMAL)
- fprintf(stderr, "PACKET3_CNTL_BITBLT, %d dwords\n", cmdsz);
- break;
- case RADEON_CP_PACKET3_CNTL_SMALLTEXT:
- if (NORMAL)
- fprintf(stderr, "PACKET3_CNTL_SMALLTEXT, %d dwords\n", cmdsz);
- break;
- case RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT:
- if (NORMAL)
- fprintf(stderr, "PACKET3_CNTL_HOSTDATA_BLT, %d dwords\n",
- cmdsz);
- break;
- case RADEON_CP_PACKET3_CNTL_POLYLINE:
- if (NORMAL)
- fprintf(stderr, "PACKET3_CNTL_POLYLINE, %d dwords\n", cmdsz);
- break;
- case RADEON_CP_PACKET3_CNTL_POLYSCANLINES:
- if (NORMAL)
- fprintf(stderr, "PACKET3_CNTL_POLYSCANLINES, %d dwords\n",
- cmdsz);
- break;
- case RADEON_CP_PACKET3_CNTL_PAINT_MULTI:
- if (NORMAL)
- fprintf(stderr, "PACKET3_CNTL_PAINT_MULTI, %d dwords\n",
- cmdsz);
- break;
- case RADEON_CP_PACKET3_CNTL_BITBLT_MULTI:
- if (NORMAL)
- fprintf(stderr, "PACKET3_CNTL_BITBLT_MULTI, %d dwords\n",
- cmdsz);
- break;
- case RADEON_CP_PACKET3_CNTL_TRANS_BITBLT:
- if (NORMAL)
- fprintf(stderr, "PACKET3_CNTL_TRANS_BITBLT, %d dwords\n",
- cmdsz);
- break;
- default:
- fprintf(stderr, "UNKNOWN PACKET, %d dwords\n", cmdsz);
- break;
- }
-
- cmdbuf->buf += cmdsz * 4;
- cmdbuf->bufsz -= cmdsz * 4;
- return 0;
-}
-
-
-/* Check cliprects for bounds, then pass on to above:
- */
-static int radeon_emit_packet3_cliprect( drm_radeon_cmd_buffer_t *cmdbuf )
-{
- drm_clip_rect_t *boxes = cmdbuf->boxes;
- int i = 0;
-
- if (VERBOSE && total_changed) {
- dump_state();
- total_changed = 0;
- }
- else fprintf(stderr, "total_changed zero\n");
-
- if (NORMAL) {
- do {
- if ( i < cmdbuf->nbox ) {
- fprintf(stderr, "Emit box %d/%d %d,%d %d,%d\n",
- i, cmdbuf->nbox,
- boxes[i].x1, boxes[i].y1, boxes[i].x2, boxes[i].y2);
- }
- } while ( ++i < cmdbuf->nbox );
- }
-
- if (cmdbuf->nbox == 1)
- cmdbuf->nbox = 0;
-
- return radeon_emit_packet3( cmdbuf );
-}
-
-
-int radeonSanityCmdBuffer( radeonContextPtr rmesa,
- int nbox,
- drm_clip_rect_t *boxes )
-{
- int idx;
- drm_radeon_cmd_buffer_t cmdbuf;
- drm_radeon_cmd_header_t header;
- static int inited = 0;
-
- if (!inited) {
- init_regs();
- inited = 1;
- }
-
- cmdbuf.buf = rmesa->store.cmd_buf;
- cmdbuf.bufsz = rmesa->store.cmd_used;
- cmdbuf.boxes = boxes;
- cmdbuf.nbox = nbox;
-
- while ( cmdbuf.bufsz >= sizeof(header) ) {
-
- header.i = *(int *)cmdbuf.buf;
- cmdbuf.buf += sizeof(header);
- cmdbuf.bufsz -= sizeof(header);
-
- switch (header.header.cmd_type) {
- case RADEON_CMD_PACKET:
- if (radeon_emit_packets( header, &cmdbuf )) {
- fprintf(stderr,"radeon_emit_packets failed\n");
- return -EINVAL;
- }
- break;
-
- case RADEON_CMD_SCALARS:
- if (radeon_emit_scalars( header, &cmdbuf )) {
- fprintf(stderr,"radeon_emit_scalars failed\n");
- return -EINVAL;
- }
- break;
-
- case RADEON_CMD_SCALARS2:
- if (radeon_emit_scalars2( header, &cmdbuf )) {
- fprintf(stderr,"radeon_emit_scalars failed\n");
- return -EINVAL;
- }
- break;
-
- case RADEON_CMD_VECTORS:
- if (radeon_emit_vectors( header, &cmdbuf )) {
- fprintf(stderr,"radeon_emit_vectors failed\n");
- return -EINVAL;
- }
- break;
-
- case RADEON_CMD_DMA_DISCARD:
- idx = header.dma.buf_idx;
- if (NORMAL)
- fprintf(stderr, "RADEON_CMD_DMA_DISCARD buf %d\n", idx);
- bufs++;
- break;
-
- case RADEON_CMD_PACKET3:
- if (radeon_emit_packet3( &cmdbuf )) {
- fprintf(stderr,"radeon_emit_packet3 failed\n");
- return -EINVAL;
- }
- break;
-
- case RADEON_CMD_PACKET3_CLIP:
- if (radeon_emit_packet3_cliprect( &cmdbuf )) {
- fprintf(stderr,"radeon_emit_packet3_clip failed\n");
- return -EINVAL;
- }
- break;
-
- case RADEON_CMD_WAIT:
- break;
-
- default:
- fprintf(stderr,"bad cmd_type %d at %p\n",
- header.header.cmd_type,
- cmdbuf.buf - sizeof(header));
- return -EINVAL;
- }
- }
-
- if (0)
- {
- static int n = 0;
- n++;
- if (n == 10) {
- fprintf(stderr, "Bufs %d Total emitted %d real changes %d (%.2f%%)\n",
- bufs,
- total, total_changed,
- ((float)total_changed/(float)total*100.0));
- fprintf(stderr, "Total emitted per buf: %.2f\n",
- (float)total/(float)bufs);
- fprintf(stderr, "Real changes per buf: %.2f\n",
- (float)total_changed/(float)bufs);
-
- bufs = n = total = total_changed = 0;
- }
- }
-
- return 0;
-}
diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_sanity.h b/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_sanity.h
deleted file mode 100644
index 1ec06bc58..000000000
--- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_sanity.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef RADEON_SANITY_H
-#define RADEON_SANITY_H
-
-extern int radeonSanityCmdBuffer( radeonContextPtr rmesa,
- int nbox,
- drm_clip_rect_t *boxes );
-
-#endif
diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_screen.c b/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_screen.c
deleted file mode 100644
index 80710294c..000000000
--- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ /dev/null
@@ -1,656 +0,0 @@
-/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_screen.c,v 1.7 2003/03/26 20:43:51 tsi Exp $ */
-/**************************************************************************
-
-Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
- VA Linux Systems Inc., Fremont, California.
-
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/**
- * \file radeon_screen.c
- * Screen initialization functions for the Radeon driver.
- *
- * \author Kevin E. Martin <martin@valinux.com>
- * \author Gareth Hughes <gareth@valinux.com>
- */
-
-#include "glheader.h"
-#include "imports.h"
-#include "mtypes.h"
-#include "framebuffer.h"
-#include "renderbuffer.h"
-
-#define STANDALONE_MMIO
-#include "radeon_context.h"
-#include "radeon_screen.h"
-#include "radeon_macros.h"
-#include "radeon_span.h"
-
-#include "utils.h"
-#include "context.h"
-#include "vblank.h"
-#include "drirenderbuffer.h"
-
-#include "GL/internal/dri_interface.h"
-
-/* Radeon configuration
- */
-#include "xmlpool.h"
-
-PUBLIC const char __driConfigOptions[] =
-DRI_CONF_BEGIN
- DRI_CONF_SECTION_PERFORMANCE
- DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
- DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
- DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
- DRI_CONF_HYPERZ(false)
- DRI_CONF_SECTION_END
- DRI_CONF_SECTION_QUALITY
- DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
- DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
- DRI_CONF_NO_NEG_LOD_BIAS(false)
- DRI_CONF_FORCE_S3TC_ENABLE(false)
- DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
- DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
- DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
- DRI_CONF_TEXTURE_LEVEL_HACK(false)
- DRI_CONF_SECTION_END
- DRI_CONF_SECTION_DEBUG
- DRI_CONF_NO_RAST(false)
- DRI_CONF_SECTION_END
-DRI_CONF_END;
-static const GLuint __driNConfigOptions = 13;
-
-extern const struct dri_extension card_extensions[];
-
-#if 1
-/* Including xf86PciInfo.h introduces a bunch of errors...
- */
-#define PCI_CHIP_RADEON_QD 0x5144
-#define PCI_CHIP_RADEON_QE 0x5145
-#define PCI_CHIP_RADEON_QF 0x5146
-#define PCI_CHIP_RADEON_QG 0x5147
-
-#define PCI_CHIP_RADEON_QY 0x5159
-#define PCI_CHIP_RADEON_QZ 0x515A
-
-#define PCI_CHIP_RN50_515E 0x515E
-#define PCI_CHIP_RN50_5969 0x5969
-
-#define PCI_CHIP_RADEON_LW 0x4C57 /* mobility 7 - has tcl */
-#define PCI_CHIP_RADEON_LX 0x4C58 /* mobility FireGL 7800 m7 */
-
-#define PCI_CHIP_RADEON_LY 0x4C59
-#define PCI_CHIP_RADEON_LZ 0x4C5A
-
-#define PCI_CHIP_RV200_QW 0x5157 /* Radeon 7500 - not an R200 at all */
-#define PCI_CHIP_RV200_QX 0x5158
-
-/* IGP Chipsets */
-#define PCI_CHIP_RS100_4136 0x4136
-#define PCI_CHIP_RS200_4137 0x4137
-#define PCI_CHIP_RS250_4237 0x4237
-#define PCI_CHIP_RS100_4336 0x4336
-#define PCI_CHIP_RS200_4337 0x4337
-#define PCI_CHIP_RS250_4437 0x4437
-#endif
-
-
-static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo );
-
-static __GLcontextModes *
-radeonFillInModes( unsigned pixel_bits, unsigned depth_bits,
- unsigned stencil_bits, GLboolean have_back_buffer )
-{
- __GLcontextModes * modes;
- __GLcontextModes * m;
- unsigned num_modes;
- unsigned depth_buffer_factor;
- unsigned back_buffer_factor;
- GLenum fb_format;
- GLenum fb_type;
-
- /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
- * enough to add support. Basically, if a context is created with an
- * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
- * will never be used.
- */
- static const GLenum back_buffer_modes[] = {
- GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
- };
-
- u_int8_t depth_bits_array[2];
- u_int8_t stencil_bits_array[2];
-
-
- depth_bits_array[0] = depth_bits;
- depth_bits_array[1] = depth_bits;
-
- /* Just like with the accumulation buffer, always provide some modes
- * with a stencil buffer. It will be a sw fallback, but some apps won't
- * care about that.
- */
- stencil_bits_array[0] = 0;
- stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits;
-
- depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1;
- back_buffer_factor = (have_back_buffer) ? 2 : 1;
-
- num_modes = depth_buffer_factor * back_buffer_factor * 4;
-
- if ( pixel_bits == 16 ) {
- fb_format = GL_RGB;
- fb_type = GL_UNSIGNED_SHORT_5_6_5;
- }
- else {
- fb_format = GL_BGRA;
- fb_type = GL_UNSIGNED_INT_8_8_8_8_REV;
- }
-
- modes = (*dri_interface->createContextModes)( num_modes, sizeof( __GLcontextModes ) );
- m = modes;
- if ( ! driFillInModes( & m, fb_format, fb_type,
- depth_bits_array, stencil_bits_array, depth_buffer_factor,
- back_buffer_modes, back_buffer_factor,
- GLX_TRUE_COLOR ) ) {
- fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
- __func__, __LINE__ );
- return NULL;
- }
-
- if ( ! driFillInModes( & m, fb_format, fb_type,
- depth_bits_array, stencil_bits_array, depth_buffer_factor,
- back_buffer_modes, back_buffer_factor,
- GLX_DIRECT_COLOR ) ) {
- fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
- __func__, __LINE__ );
- return NULL;
- }
-
- /* Mark the visual as slow if there are "fake" stencil bits.
- */
- for ( m = modes ; m != NULL ; m = m->next ) {
- if ( (m->stencilBits != 0) && (m->stencilBits != stencil_bits) ) {
- m->visualRating = GLX_SLOW_CONFIG;
- }
- }
-
- return modes;
-}
-
-
-/* Create the device specific screen private data struct.
- */
-radeonScreenPtr radeonCreateScreen( __DRIscreenPrivate *sPriv )
-{
- radeonScreenPtr screen;
- RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv;
- unsigned char *RADEONMMIO;
- PFNGLXSCRENABLEEXTENSIONPROC glx_enable_extension =
- (PFNGLXSCRENABLEEXTENSIONPROC) (*dri_interface->getProcAddress("glxEnableExtension"));
- void * const psc = sPriv->psc->screenConfigs;
-
- if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) {
- fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n");
- return GL_FALSE;
- }
-
- /* Allocate the private area */
- screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
- if ( !screen ) {
- __driUtilMessage("%s: Could not allocate memory for screen structure",
- __FUNCTION__);
- return NULL;
- }
-
- /* parse information in __driConfigOptions */
- driParseOptionInfo (&screen->optionCache,
- __driConfigOptions, __driNConfigOptions);
-
- /* This is first since which regions we map depends on whether or
- * not we are using a PCI card.
- */
- screen->IsPCI = dri_priv->IsPCI;
-
- {
- int ret;
- drm_radeon_getparam_t gp;
-
- gp.param = RADEON_PARAM_GART_BUFFER_OFFSET;
- gp.value = &screen->gart_buffer_offset;
-
- ret = drmCommandWriteRead( sPriv->fd, DRM_RADEON_GETPARAM,
- &gp, sizeof(gp));
- if (ret) {
- FREE( screen );
- fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret);
- return NULL;
- }
-
- if (sPriv->drmMinor >= 6) {
- gp.param = RADEON_PARAM_IRQ_NR;
- gp.value = &screen->irq;
-
- ret = drmCommandWriteRead( sPriv->fd, DRM_RADEON_GETPARAM,
- &gp, sizeof(gp));
- if (ret) {
- FREE( screen );
- fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret);
- return NULL;
- }
- }
- }
-
- screen->mmio.handle = dri_priv->registerHandle;
- screen->mmio.size = dri_priv->registerSize;
- if ( drmMap( sPriv->fd,
- screen->mmio.handle,
- screen->mmio.size,
- &screen->mmio.map ) ) {
- FREE( screen );
- __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ );
- return NULL;
- }
-
- RADEONMMIO = screen->mmio.map;
-
- screen->status.handle = dri_priv->statusHandle;
- screen->status.size = dri_priv->statusSize;
- if ( drmMap( sPriv->fd,
- screen->status.handle,
- screen->status.size,
- &screen->status.map ) ) {
- drmUnmap( screen->mmio.map, screen->mmio.size );
- FREE( screen );
- __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ );
- return NULL;
- }
- screen->scratch = (__volatile__ u_int32_t *)
- ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET);
-
- screen->buffers = drmMapBufs( sPriv->fd );
- if ( !screen->buffers ) {
- drmUnmap( screen->status.map, screen->status.size );
- drmUnmap( screen->mmio.map, screen->mmio.size );
- FREE( screen );
- __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ );
- return NULL;
- }
-
- if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) {
- screen->gartTextures.handle = dri_priv->gartTexHandle;
- screen->gartTextures.size = dri_priv->gartTexMapSize;
- if ( drmMap( sPriv->fd,
- screen->gartTextures.handle,
- screen->gartTextures.size,
- (drmAddressPtr)&screen->gartTextures.map ) ) {
- drmUnmapBufs( screen->buffers );
- drmUnmap( screen->status.map, screen->status.size );
- drmUnmap( screen->mmio.map, screen->mmio.size );
- FREE( screen );
- __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__);
- return NULL;
- }
-
- screen->gart_texture_offset = dri_priv->gartTexOffset + ( screen->IsPCI
- ? INREG( RADEON_AIC_LO_ADDR )
- : ( ( INREG( RADEON_MC_AGP_LOCATION ) & 0x0ffffU ) << 16 ) );
- }
-
- screen->chipset = 0;
- switch ( dri_priv->deviceID ) {
- default:
- fprintf(stderr, "unknown chip id, assuming full radeon support\n");
- case PCI_CHIP_RADEON_QD:
- case PCI_CHIP_RADEON_QE:
- case PCI_CHIP_RADEON_QF:
- case PCI_CHIP_RADEON_QG:
- /* all original radeons (7200) presumably have a stencil op bug */
- screen->chipset |= RADEON_CHIPSET_BROKEN_STENCIL;
- case PCI_CHIP_RV200_QW:
- case PCI_CHIP_RV200_QX:
- case PCI_CHIP_RADEON_LW:
- case PCI_CHIP_RADEON_LX:
- screen->chipset |= RADEON_CHIPSET_TCL;
- case PCI_CHIP_RADEON_QY:
- case PCI_CHIP_RADEON_QZ:
- case PCI_CHIP_RN50_515E:
- case PCI_CHIP_RN50_5969:
- case PCI_CHIP_RADEON_LY:
- case PCI_CHIP_RADEON_LZ:
- case PCI_CHIP_RS100_4136: /* IGPs don't have TCL */
- case PCI_CHIP_RS200_4137:
- case PCI_CHIP_RS250_4237:
- case PCI_CHIP_RS100_4336:
- case PCI_CHIP_RS200_4337:
- case PCI_CHIP_RS250_4437:
- break;
- }
-
- screen->cpp = dri_priv->bpp / 8;
- screen->AGPMode = dri_priv->AGPMode;
-
- screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff ) << 16;
-
- if ( sPriv->drmMinor >= 10 ) {
- drm_radeon_setparam_t sp;
-
- sp.param = RADEON_SETPARAM_FB_LOCATION;
- sp.value = screen->fbLocation;
-
- drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM,
- &sp, sizeof( sp ) );
- }
-
- screen->frontOffset = dri_priv->frontOffset;
- screen->frontPitch = dri_priv->frontPitch;
- screen->backOffset = dri_priv->backOffset;
- screen->backPitch = dri_priv->backPitch;
- screen->depthOffset = dri_priv->depthOffset;
- screen->depthPitch = dri_priv->depthPitch;
-
- /* Check if ddx has set up a surface reg to cover depth buffer */
- screen->depthHasSurface = ((sPriv->ddxMajor > 4) &&
- (screen->chipset & RADEON_CHIPSET_TCL));
-
- if ( dri_priv->textureSize == 0 ) {
- screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset;
- screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize;
- screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
- dri_priv->log2GARTTexGran;
- } else {
- screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset
- + screen->fbLocation;
- screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize;
- screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
- dri_priv->log2TexGran;
- }
-
- if ( !screen->gartTextures.map || dri_priv->textureSize == 0
- || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
- screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1;
- screen->texOffset[RADEON_GART_TEX_HEAP] = 0;
- screen->texSize[RADEON_GART_TEX_HEAP] = 0;
- screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0;
- } else {
- screen->numTexHeaps = RADEON_NR_TEX_HEAPS;
- screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset;
- screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize;
- screen->logTexGranularity[RADEON_GART_TEX_HEAP] =
- dri_priv->log2GARTTexGran;
- }
-
- if ( glx_enable_extension != NULL ) {
- if ( screen->irq != 0 ) {
- (*glx_enable_extension)( psc, "GLX_SGI_swap_control" );
- (*glx_enable_extension)( psc, "GLX_SGI_video_sync" );
- (*glx_enable_extension)( psc, "GLX_MESA_swap_control" );
- }
-
- (*glx_enable_extension)( psc, "GLX_MESA_swap_frame_usage" );
- }
-
- screen->driScreen = sPriv;
- screen->sarea_priv_offset = dri_priv->sarea_priv_offset;
- return screen;
-}
-
-/* Destroy the device specific screen private data struct.
- */
-void radeonDestroyScreen( __DRIscreenPrivate *sPriv )
-{
- radeonScreenPtr screen = (radeonScreenPtr)sPriv->private;
-
- if (!screen)
- return;
-
- if ( screen->gartTextures.map ) {
- drmUnmap( screen->gartTextures.map, screen->gartTextures.size );
- }
- drmUnmapBufs( screen->buffers );
- drmUnmap( screen->status.map, screen->status.size );
- drmUnmap( screen->mmio.map, screen->mmio.size );
-
- /* free all option information */
- driDestroyOptionInfo (&screen->optionCache);
-
- FREE( screen );
- sPriv->private = NULL;
-}
-
-
-/* Initialize the driver specific screen private data.
- */
-static GLboolean
-radeonInitDriver( __DRIscreenPrivate *sPriv )
-{
- sPriv->private = (void *) radeonCreateScreen( sPriv );
- if ( !sPriv->private ) {
- radeonDestroyScreen( sPriv );
- return GL_FALSE;
- }
-
- return GL_TRUE;
-}
-
-
-/**
- * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
- *
- * \todo This function (and its interface) will need to be updated to support
- * pbuffers.
- */
-static GLboolean
-radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv,
- __DRIdrawablePrivate *driDrawPriv,
- const __GLcontextModes *mesaVis,
- GLboolean isPixmap )
-{
- radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private;
-
- if (isPixmap) {
- return GL_FALSE; /* not implemented */
- }
- else {
- const GLboolean swDepth = GL_FALSE;
- const GLboolean swAlpha = GL_FALSE;
- const GLboolean swAccum = mesaVis->accumRedBits > 0;
- const GLboolean swStencil = mesaVis->stencilBits > 0 &&
- mesaVis->depthBits != 24;
-#if 0
- driDrawPriv->driverPrivate = (void *)
- _mesa_create_framebuffer( mesaVis,
- swDepth,
- swStencil,
- swAccum,
- swAlpha );
-#else
- struct gl_framebuffer *fb = _mesa_create_framebuffer(mesaVis);
-
- {
- driRenderbuffer *frontRb
- = driNewRenderbuffer(GL_RGBA, screen->cpp,
- screen->frontOffset, screen->frontPitch);
- radeonSetSpanFunctions(frontRb, mesaVis);
- _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &frontRb->Base);
- }
-
- if (mesaVis->doubleBufferMode) {
- driRenderbuffer *backRb
- = driNewRenderbuffer(GL_RGBA, screen->cpp,
- screen->backOffset, screen->backPitch);
- radeonSetSpanFunctions(backRb, mesaVis);
- _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &backRb->Base);
- }
-
- if (mesaVis->depthBits == 16) {
- driRenderbuffer *depthRb
- = driNewRenderbuffer(GL_DEPTH_COMPONENT16, screen->cpp,
- screen->depthOffset, screen->depthPitch);
- radeonSetSpanFunctions(depthRb, mesaVis);
- _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base);
- }
- else if (mesaVis->depthBits == 24) {
- driRenderbuffer *depthRb
- = driNewRenderbuffer(GL_DEPTH_COMPONENT24, screen->cpp,
- screen->depthOffset, screen->depthPitch);
- radeonSetSpanFunctions(depthRb, mesaVis);
- _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base);
- }
-
- if (mesaVis->stencilBits > 0 && !swStencil) {
- driRenderbuffer *stencilRb
- = driNewRenderbuffer(GL_STENCIL_INDEX8_EXT, screen->cpp,
- screen->depthOffset, screen->depthPitch);
- radeonSetSpanFunctions(stencilRb, mesaVis);
- _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencilRb->Base);
- }
-
- _mesa_add_soft_renderbuffers(fb,
- GL_FALSE, /* color */
- swDepth,
- swStencil,
- swAccum,
- swAlpha,
- GL_FALSE /* aux */);
- driDrawPriv->driverPrivate = (void *) fb;
-#endif
- return (driDrawPriv->driverPrivate != NULL);
- }
-}
-
-
-static void
-radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv)
-{
- _mesa_destroy_framebuffer((GLframebuffer *) (driDrawPriv->driverPrivate));
-}
-
-static struct __DriverAPIRec radeonAPI = {
- .InitDriver = radeonInitDriver,
- .DestroyScreen = radeonDestroyScreen,
- .CreateContext = radeonCreateContext,
- .DestroyContext = radeonDestroyContext,
- .CreateBuffer = radeonCreateBuffer,
- .DestroyBuffer = radeonDestroyBuffer,
- .SwapBuffers = radeonSwapBuffers,
- .MakeCurrent = radeonMakeCurrent,
- .UnbindContext = radeonUnbindContext,
- .GetSwapInfo = getSwapInfo,
- .GetMSC = driGetMSC32,
- .WaitForMSC = driWaitForMSC32,
- .WaitForSBC = NULL,
- .SwapBuffersMSC = NULL
-};
-
-
-/**
- * This is the bootstrap function for the driver. libGL supplies all of the
- * requisite information about the system, and the driver initializes itself.
- * This routine also fills in the linked list pointed to by \c driver_modes
- * with the \c __GLcontextModes that the driver can support for windows or
- * pbuffers.
- *
- * \return A pointer to a \c __DRIscreenPrivate on success, or \c NULL on
- * failure.
- */
-PUBLIC
-void * __driCreateNewScreen_20050727( __DRInativeDisplay *dpy, int scrn, __DRIscreen *psc,
- const __GLcontextModes * modes,
- const __DRIversion * ddx_version,
- const __DRIversion * dri_version,
- const __DRIversion * drm_version,
- const __DRIframebuffer * frame_buffer,
- drmAddress pSAREA, int fd,
- int internal_api_version,
- const __DRIinterfaceMethods * interface,
- __GLcontextModes ** driver_modes )
-
-{
- __DRIscreenPrivate *psp;
- static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
- static const __DRIversion dri_expected = { 4, 0, 0 };
- static const __DRIversion drm_expected = { 1, 3, 0 };
-
- dri_interface = interface;
-
- if ( ! driCheckDriDdxDrmVersions3( "Radeon",
- dri_version, & dri_expected,
- ddx_version, & ddx_expected,
- drm_version, & drm_expected ) ) {
- return NULL;
- }
-
- psp = __driUtilCreateNewScreen(dpy, scrn, psc, NULL,
- ddx_version, dri_version, drm_version,
- frame_buffer, pSAREA, fd,
- internal_api_version, &radeonAPI);
- if ( psp != NULL ) {
- RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv;
- *driver_modes = radeonFillInModes( dri_priv->bpp,
- (dri_priv->bpp == 16) ? 16 : 24,
- (dri_priv->bpp == 16) ? 0 : 8,
- (dri_priv->backOffset != dri_priv->depthOffset) );
-
- /* Calling driInitExtensions here, with a NULL context pointer, does not actually
- * enable the extensions. It just makes sure that all the dispatch offsets for all
- * the extensions that *might* be enables are known. This is needed because the
- * dispatch offsets need to be known when _mesa_context_create is called, but we can't
- * enable the extensions until we have a context pointer.
- *
- * Hello chicken. Hello egg. How are you two today?
- */
- driInitExtensions( NULL, card_extensions, GL_FALSE );
- }
-
- return (void *) psp;
-}
-
-
-/**
- * Get information about previous buffer swaps.
- */
-static int
-getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo )
-{
- radeonContextPtr rmesa;
-
- if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL)
- || (dPriv->driContextPriv->driverPrivate == NULL)
- || (sInfo == NULL) ) {
- return -1;
- }
-
- rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate;
- sInfo->swap_count = rmesa->swap_count;
- sInfo->swap_ust = rmesa->swap_ust;
- sInfo->swap_missed_count = rmesa->swap_missed_count;
-
- sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0)
- ? driCalculateSwapUsage( dPriv, 0, rmesa->swap_missed_ust )
- : 0.0;
-
- return 0;
-}
diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_screen.h b/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_screen.h
deleted file mode 100644
index b9cbeaac3..000000000
--- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_screen.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_screen.h,v 1.5 2002/12/16 16:18:58 dawes Exp $ */
-/**************************************************************************
-
-Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
- VA Linux Systems Inc., Fremont, California.
-
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/*
- * Authors:
- * Kevin E. Martin <martin@valinux.com>
- * Gareth Hughes <gareth@valinux.com>
- */
-
-#ifndef __RADEON_SCREEN_H__
-#define __RADEON_SCREEN_H__
-
-/*
- * IMPORTS: these headers contain all the DRI, X and kernel-related
- * definitions that we need.
- */
-/* #include "dri_util.h" */
-#include "radeon_dri.h"
-#include "radeon_reg.h"
-#include "drm_sarea.h"
-#include "xmlconfig.h"
-
-
-typedef struct {
- drm_handle_t handle; /* Handle to the DRM region */
- drmSize size; /* Size of the DRM region */
- drmAddress map; /* Mapping of the DRM region */
-} radeonRegionRec, *radeonRegionPtr;
-
-/* chipset features */
-#define RADEON_CHIPSET_TCL (1 << 0)
-#define RADEON_CHIPSET_BROKEN_STENCIL (1 << 1)
-
-typedef struct {
-
- int chipset;
- int cpp;
- int IsPCI; /* Current card is a PCI card */
- int AGPMode;
- unsigned int irq; /* IRQ number (0 means none) */
-
- unsigned int fbLocation;
- unsigned int frontOffset;
- unsigned int frontPitch;
- unsigned int backOffset;
- unsigned int backPitch;
-
- unsigned int depthOffset;
- unsigned int depthPitch;
-
- /* Shared texture data */
- int numTexHeaps;
- int texOffset[RADEON_NR_TEX_HEAPS];
- int texSize[RADEON_NR_TEX_HEAPS];
- int logTexGranularity[RADEON_NR_TEX_HEAPS];
-
- radeonRegionRec mmio;
- radeonRegionRec status;
- radeonRegionRec gartTextures;
-
- drmBufMapPtr buffers;
-
- __volatile__ u_int32_t *scratch;
-
- __DRIscreenPrivate *driScreen;
- unsigned int sarea_priv_offset;
- unsigned int gart_buffer_offset; /* offset in card memory space */
- unsigned int gart_texture_offset; /* offset in card memory space */
-
- GLboolean depthHasSurface;
-
- /* Configuration cache with default values for all contexts */
- driOptionCache optionCache;
-} radeonScreenRec, *radeonScreenPtr;
-
-#endif /* __RADEON_SCREEN_H__ */
diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_span.c b/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_span.c
deleted file mode 100644
index 2d15078d6..000000000
--- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_span.c
+++ /dev/null
@@ -1,346 +0,0 @@
-/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_span.c,v 1.6 2002/10/30 12:51:56 alanh Exp $ */
-/**************************************************************************
-
-Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
- VA Linux Systems Inc., Fremont, California.
-
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/*
- * Authors:
- * Kevin E. Martin <martin@valinux.com>
- * Gareth Hughes <gareth@valinux.com>
- * Keith Whitwell <keith@tungstengraphics.com>
- *
- */
-
-#include "glheader.h"
-#include "swrast/swrast.h"
-
-#include "radeon_context.h"
-#include "radeon_ioctl.h"
-#include "radeon_state.h"
-#include "radeon_span.h"
-#include "radeon_tex.h"
-
-#define DBG 0
-
-#define LOCAL_VARS \
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx); \
- radeonScreenPtr radeonScreen = rmesa->radeonScreen; \
- __DRIscreenPrivate *sPriv = rmesa->dri.screen; \
- __DRIdrawablePrivate *dPriv = rmesa->dri.drawable; \
- GLuint pitch = radeonScreen->frontPitch * radeonScreen->cpp; \
- GLuint height = dPriv->h; \
- char *buf = (char *)(sPriv->pFB + \
- rmesa->state.color.drawOffset + \
- (dPriv->x * radeonScreen->cpp) + \
- (dPriv->y * pitch)); \
- char *read_buf = (char *)(sPriv->pFB + \
- rmesa->state.pixel.readOffset + \
- (dPriv->x * radeonScreen->cpp) + \
- (dPriv->y * pitch)); \
- GLuint p; \
- (void) read_buf; (void) buf; (void) p
-
-#define LOCAL_DEPTH_VARS \
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx); \
- radeonScreenPtr radeonScreen = rmesa->radeonScreen; \
- __DRIscreenPrivate *sPriv = rmesa->dri.screen; \
- __DRIdrawablePrivate *dPriv = rmesa->dri.drawable; \
- GLuint height = dPriv->h; \
- GLuint xo = dPriv->x; \
- GLuint yo = dPriv->y; \
- char *buf = (char *)(sPriv->pFB + radeonScreen->depthOffset); \
- (void) buf
-
-#define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
-
-#define Y_FLIP( _y ) (height - _y - 1)
-
-#define HW_LOCK()
-
-#define HW_UNLOCK()
-
-
-
-/* ================================================================
- * Color buffer
- */
-
-/* 16 bit, RGB565 color spanline and pixel functions
- */
-#define SPANTMP_PIXEL_FMT GL_RGB
-#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
-
-#define TAG(x) radeon##x##_RGB565
-#define TAG2(x,y) radeon##x##_RGB565##y
-#include "spantmp2.h"
-
-/* 32 bit, ARGB8888 color spanline and pixel functions
- */
-#define SPANTMP_PIXEL_FMT GL_BGRA
-#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
-
-#define TAG(x) radeon##x##_ARGB8888
-#define TAG2(x,y) radeon##x##_ARGB8888##y
-#include "spantmp2.h"
-
-
-/* ================================================================
- * Depth buffer
- */
-
-/* The Radeon family has depth tiling on all the time, so we have to convert
- * the x,y coordinates into the memory bus address (mba) in the same
- * manner as the engine. In each case, the linear block address (ba)
- * is calculated, and then wired with x and y to produce the final
- * memory address.
- * The chip will do address translation on its own if the surface registers
- * are set up correctly. It is not quite enough to get it working with hyperz too...
- */
-
-static GLuint radeon_mba_z32( radeonContextPtr rmesa,
- GLint x, GLint y )
-{
- GLuint pitch = rmesa->radeonScreen->frontPitch;
- if (rmesa->radeonScreen->depthHasSurface) {
- return 4*(x + y*pitch);
- }
- else {
- GLuint ba, address = 0; /* a[0..1] = 0 */
-
- ba = (y / 16) * (pitch / 16) + (x / 16);
-
- address |= (x & 0x7) << 2; /* a[2..4] = x[0..2] */
- address |= (y & 0x3) << 5; /* a[5..6] = y[0..1] */
- address |=
- (((x & 0x10) >> 2) ^ (y & 0x4)) << 5; /* a[7] = x[4] ^ y[2] */
- address |= (ba & 0x3) << 8; /* a[8..9] = ba[0..1] */
-
- address |= (y & 0x8) << 7; /* a[10] = y[3] */
- address |=
- (((x & 0x8) << 1) ^ (y & 0x10)) << 7; /* a[11] = x[3] ^ y[4] */
- address |= (ba & ~0x3) << 10; /* a[12..] = ba[2..] */
-
- return address;
- }
-}
-
-static __inline GLuint radeon_mba_z16( radeonContextPtr rmesa, GLint x, GLint y )
-{
- GLuint pitch = rmesa->radeonScreen->frontPitch;
- if (rmesa->radeonScreen->depthHasSurface) {
- return 2*(x + y*pitch);
- }
- else {
- GLuint ba, address = 0; /* a[0] = 0 */
-
- ba = (y / 16) * (pitch / 32) + (x / 32);
-
- address |= (x & 0x7) << 1; /* a[1..3] = x[0..2] */
- address |= (y & 0x7) << 4; /* a[4..6] = y[0..2] */
- address |= (x & 0x8) << 4; /* a[7] = x[3] */
- address |= (ba & 0x3) << 8; /* a[8..9] = ba[0..1] */
- address |= (y & 0x8) << 7; /* a[10] = y[3] */
- address |= ((x & 0x10) ^ (y & 0x10)) << 7; /* a[11] = x[4] ^ y[4] */
- address |= (ba & ~0x3) << 10; /* a[12..] = ba[2..] */
-
- return address;
- }
-}
-
-
-/* 16-bit depth buffer functions
- */
-#define WRITE_DEPTH( _x, _y, d ) \
- *(GLushort *)(buf + radeon_mba_z16( rmesa, _x + xo, _y + yo )) = d;
-
-#define READ_DEPTH( d, _x, _y ) \
- d = *(GLushort *)(buf + radeon_mba_z16( rmesa, _x + xo, _y + yo ));
-
-#define TAG(x) radeon##x##_16
-#include "depthtmp.h"
-
-/* 24 bit depth, 8 bit stencil depthbuffer functions
- */
-#define WRITE_DEPTH( _x, _y, d ) \
-do { \
- GLuint offset = radeon_mba_z32( rmesa, _x + xo, _y + yo ); \
- GLuint tmp = *(GLuint *)(buf + offset); \
- tmp &= 0xff000000; \
- tmp |= ((d) & 0x00ffffff); \
- *(GLuint *)(buf + offset) = tmp; \
-} while (0)
-
-#define READ_DEPTH( d, _x, _y ) \
- d = *(GLuint *)(buf + radeon_mba_z32( rmesa, _x + xo, \
- _y + yo )) & 0x00ffffff;
-
-#define TAG(x) radeon##x##_24_8
-#include "depthtmp.h"
-
-
-/* ================================================================
- * Stencil buffer
- */
-
-/* 24 bit depth, 8 bit stencil depthbuffer functions
- */
-#define WRITE_STENCIL( _x, _y, d ) \
-do { \
- GLuint offset = radeon_mba_z32( rmesa, _x + xo, _y + yo ); \
- GLuint tmp = *(GLuint *)(buf + offset); \
- tmp &= 0x00ffffff; \
- tmp |= (((d) & 0xff) << 24); \
- *(GLuint *)(buf + offset) = tmp; \
-} while (0)
-
-#define READ_STENCIL( d, _x, _y ) \
-do { \
- GLuint offset = radeon_mba_z32( rmesa, _x + xo, _y + yo ); \
- GLuint tmp = *(GLuint *)(buf + offset); \
- tmp &= 0xff000000; \
- d = tmp >> 24; \
-} while (0)
-
-#define TAG(x) radeon##x##_24_8
-#include "stenciltmp.h"
-
-
-/*
- * This function is called to specify which buffer to read and write
- * for software rasterization (swrast) fallbacks. This doesn't necessarily
- * correspond to glDrawBuffer() or glReadBuffer() calls.
- */
-static void radeonSetBuffer( GLcontext *ctx,
- GLframebuffer *colorBuffer,
- GLuint bufferBit )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-
- switch ( bufferBit ) {
- case BUFFER_BIT_FRONT_LEFT:
- if ( rmesa->sarea->pfCurrentPage == 1 ) {
- rmesa->state.pixel.readOffset = rmesa->radeonScreen->backOffset;
- rmesa->state.pixel.readPitch = rmesa->radeonScreen->backPitch;
- rmesa->state.color.drawOffset = rmesa->radeonScreen->backOffset;
- rmesa->state.color.drawPitch = rmesa->radeonScreen->backPitch;
- } else {
- rmesa->state.pixel.readOffset = rmesa->radeonScreen->frontOffset;
- rmesa->state.pixel.readPitch = rmesa->radeonScreen->frontPitch;
- rmesa->state.color.drawOffset = rmesa->radeonScreen->frontOffset;
- rmesa->state.color.drawPitch = rmesa->radeonScreen->frontPitch;
- }
- break;
- case BUFFER_BIT_BACK_LEFT:
- if ( rmesa->sarea->pfCurrentPage == 1 ) {
- rmesa->state.pixel.readOffset = rmesa->radeonScreen->frontOffset;
- rmesa->state.pixel.readPitch = rmesa->radeonScreen->frontPitch;
- rmesa->state.color.drawOffset = rmesa->radeonScreen->frontOffset;
- rmesa->state.color.drawPitch = rmesa->radeonScreen->frontPitch;
- } else {
- rmesa->state.pixel.readOffset = rmesa->radeonScreen->backOffset;
- rmesa->state.pixel.readPitch = rmesa->radeonScreen->backPitch;
- rmesa->state.color.drawOffset = rmesa->radeonScreen->backOffset;
- rmesa->state.color.drawPitch = rmesa->radeonScreen->backPitch;
- }
- break;
- default:
- assert(0);
- break;
- }
-}
-
-/* Move locking out to get reasonable span performance (10x better
- * than doing this in HW_LOCK above). WaitForIdle() is the main
- * culprit.
- */
-
-static void radeonSpanRenderStart( GLcontext *ctx )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
-
- RADEON_FIREVERTICES( rmesa );
- LOCK_HARDWARE( rmesa );
- radeonWaitForIdleLocked( rmesa );
-}
-
-static void radeonSpanRenderFinish( GLcontext *ctx )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
- _swrast_flush( ctx );
- UNLOCK_HARDWARE( rmesa );
-}
-
-void radeonInitSpanFuncs( GLcontext *ctx )
-{
- struct swrast_device_driver *swdd = _swrast_GetDeviceDriverReference(ctx);
-
- swdd->SetBuffer = radeonSetBuffer;
- swdd->SpanRenderStart = radeonSpanRenderStart;
- swdd->SpanRenderFinish = radeonSpanRenderFinish;
-}
-
-
-/**
- * Plug in the Get/Put routines for the given driRenderbuffer.
- */
-void
-radeonSetSpanFunctions(driRenderbuffer *drb, const GLvisual *vis)
-{
- if (drb->Base.InternalFormat == GL_RGBA) {
- if (vis->redBits == 5 && vis->greenBits == 6 && vis->blueBits == 5) {
- radeonInitPointers_RGB565(&drb->Base);
- }
- else {
- radeonInitPointers_ARGB8888(&drb->Base);
- }
- }
- else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT16) {
- drb->Base.GetRow = radeonReadDepthSpan_16;
- drb->Base.GetValues = radeonReadDepthPixels_16;
- drb->Base.PutRow = radeonWriteDepthSpan_16;
- drb->Base.PutMonoRow = radeonWriteMonoDepthSpan_16;
- drb->Base.PutValues = radeonWriteDepthPixels_16;
- drb->Base.PutMonoValues = NULL;
- }
- else if (drb->Base.InternalFormat == GL_DEPTH_COMPONENT24) {
- drb->Base.GetRow = radeonReadDepthSpan_24_8;
- drb->Base.GetValues = radeonReadDepthPixels_24_8;
- drb->Base.PutRow = radeonWriteDepthSpan_24_8;
- drb->Base.PutMonoRow = radeonWriteMonoDepthSpan_24_8;
- drb->Base.PutValues = radeonWriteDepthPixels_24_8;
- drb->Base.PutMonoValues = NULL;
- }
- else if (drb->Base.InternalFormat == GL_STENCIL_INDEX8_EXT) {
- drb->Base.GetRow = radeonReadStencilSpan_24_8;
- drb->Base.GetValues = radeonReadStencilPixels_24_8;
- drb->Base.PutRow = radeonWriteStencilSpan_24_8;
- drb->Base.PutMonoRow = radeonWriteMonoStencilSpan_24_8;
- drb->Base.PutValues = radeonWriteStencilPixels_24_8;
- drb->Base.PutMonoValues = NULL;
- }
-}
diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_span.h b/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_span.h
deleted file mode 100644
index 13b308e1c..000000000
--- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_span.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_span.h,v 1.2 2002/02/22 21:45:01 dawes Exp $ */
-/**************************************************************************
-
-Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
- VA Linux Systems Inc., Fremont, California.
-
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/*
- * Authors:
- * Kevin E. Martin <martin@valinux.com>
- * Gareth Hughes <gareth@valinux.com>
- */
-
-#ifndef __RADEON_SPAN_H__
-#define __RADEON_SPAN_H__
-
-#include "drirenderbuffer.h"
-
-extern void radeonInitSpanFuncs( GLcontext *ctx );
-
-extern void radeonSetSpanFunctions(driRenderbuffer *rb, const GLvisual *vis);
-
-#endif
diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_state.c b/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_state.c
deleted file mode 100644
index 3a491f5de..000000000
--- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_state.c
+++ /dev/null
@@ -1,2295 +0,0 @@
-/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_state.c,v 1.8 2002/12/16 16:18:58 dawes Exp $ */
-/**************************************************************************
-
-Copyright 2000, 2001 VA Linux Systems Inc., Fremont, California.
-
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/*
- * Authors:
- * Gareth Hughes <gareth@valinux.com>
- * Keith Whitwell <keith@tungstengraphics.com>
- */
-
-#include "glheader.h"
-#include "imports.h"
-#include "api_arrayelt.h"
-#include "enums.h"
-#include "colormac.h"
-#include "state.h"
-#include "buffers.h"
-#include "context.h"
-
-#include "swrast/swrast.h"
-#include "array_cache/acache.h"
-#include "tnl/tnl.h"
-#include "tnl/t_pipeline.h"
-#include "main/light.h"
-#include "swrast_setup/swrast_setup.h"
-
-#include "radeon_context.h"
-#include "radeon_ioctl.h"
-#include "radeon_state.h"
-#include "radeon_tcl.h"
-#include "radeon_tex.h"
-#include "radeon_swtcl.h"
-#include "radeon_vtxfmt.h"
-
-/* =============================================================
- * Alpha blending
- */
-
-static void radeonAlphaFunc( GLcontext *ctx, GLenum func, GLfloat ref )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- int pp_misc = rmesa->hw.ctx.cmd[CTX_PP_MISC];
- GLubyte refByte;
-
- CLAMPED_FLOAT_TO_UBYTE(refByte, ref);
-
- RADEON_STATECHANGE( rmesa, ctx );
-
- pp_misc &= ~(RADEON_ALPHA_TEST_OP_MASK | RADEON_REF_ALPHA_MASK);
- pp_misc |= (refByte & RADEON_REF_ALPHA_MASK);
-
- switch ( func ) {
- case GL_NEVER:
- pp_misc |= RADEON_ALPHA_TEST_FAIL;
- break;
- case GL_LESS:
- pp_misc |= RADEON_ALPHA_TEST_LESS;
- break;
- case GL_EQUAL:
- pp_misc |= RADEON_ALPHA_TEST_EQUAL;
- break;
- case GL_LEQUAL:
- pp_misc |= RADEON_ALPHA_TEST_LEQUAL;
- break;
- case GL_GREATER:
- pp_misc |= RADEON_ALPHA_TEST_GREATER;
- break;
- case GL_NOTEQUAL:
- pp_misc |= RADEON_ALPHA_TEST_NEQUAL;
- break;
- case GL_GEQUAL:
- pp_misc |= RADEON_ALPHA_TEST_GEQUAL;
- break;
- case GL_ALWAYS:
- pp_misc |= RADEON_ALPHA_TEST_PASS;
- break;
- }
-
- rmesa->hw.ctx.cmd[CTX_PP_MISC] = pp_misc;
-}
-
-static void radeonBlendEquationSeparate( GLcontext *ctx,
- GLenum modeRGB, GLenum modeA )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLuint b = rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] & ~RADEON_COMB_FCN_MASK;
- GLboolean fallback = GL_FALSE;
-
- assert( modeRGB == modeA );
-
- switch ( modeRGB ) {
- case GL_FUNC_ADD:
- case GL_LOGIC_OP:
- b |= RADEON_COMB_FCN_ADD_CLAMP;
- break;
-
- case GL_FUNC_SUBTRACT:
- b |= RADEON_COMB_FCN_SUB_CLAMP;
- break;
-
- default:
- if (ctx->Color.BlendEnabled)
- fallback = GL_TRUE;
- else
- b |= RADEON_COMB_FCN_ADD_CLAMP;
- break;
- }
-
- FALLBACK( rmesa, RADEON_FALLBACK_BLEND_EQ, fallback );
- if ( !fallback ) {
- RADEON_STATECHANGE( rmesa, ctx );
- rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = b;
- if ( ctx->Color._LogicOpEnabled ) {
- rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_ROP_ENABLE;
- } else {
- rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_ROP_ENABLE;
- }
- }
-}
-
-static void radeonBlendFuncSeparate( GLcontext *ctx,
- GLenum sfactorRGB, GLenum dfactorRGB,
- GLenum sfactorA, GLenum dfactorA )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLuint b = rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] &
- ~(RADEON_SRC_BLEND_MASK | RADEON_DST_BLEND_MASK);
- GLboolean fallback = GL_FALSE;
-
- switch ( ctx->Color.BlendSrcRGB ) {
- case GL_ZERO:
- b |= RADEON_SRC_BLEND_GL_ZERO;
- break;
- case GL_ONE:
- b |= RADEON_SRC_BLEND_GL_ONE;
- break;
- case GL_DST_COLOR:
- b |= RADEON_SRC_BLEND_GL_DST_COLOR;
- break;
- case GL_ONE_MINUS_DST_COLOR:
- b |= RADEON_SRC_BLEND_GL_ONE_MINUS_DST_COLOR;
- break;
- case GL_SRC_COLOR:
- b |= RADEON_SRC_BLEND_GL_SRC_COLOR;
- break;
- case GL_ONE_MINUS_SRC_COLOR:
- b |= RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR;
- break;
- case GL_SRC_ALPHA:
- b |= RADEON_SRC_BLEND_GL_SRC_ALPHA;
- break;
- case GL_ONE_MINUS_SRC_ALPHA:
- b |= RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA;
- break;
- case GL_DST_ALPHA:
- b |= RADEON_SRC_BLEND_GL_DST_ALPHA;
- break;
- case GL_ONE_MINUS_DST_ALPHA:
- b |= RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA;
- break;
- case GL_SRC_ALPHA_SATURATE:
- b |= RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE;
- break;
- case GL_CONSTANT_COLOR:
- case GL_ONE_MINUS_CONSTANT_COLOR:
- case GL_CONSTANT_ALPHA:
- case GL_ONE_MINUS_CONSTANT_ALPHA:
- if (ctx->Color.BlendEnabled)
- fallback = GL_TRUE;
- else
- b |= RADEON_SRC_BLEND_GL_ONE;
- break;
- default:
- break;
- }
-
- switch ( ctx->Color.BlendDstRGB ) {
- case GL_ZERO:
- b |= RADEON_DST_BLEND_GL_ZERO;
- break;
- case GL_ONE:
- b |= RADEON_DST_BLEND_GL_ONE;
- break;
- case GL_SRC_COLOR:
- b |= RADEON_DST_BLEND_GL_SRC_COLOR;
- break;
- case GL_ONE_MINUS_SRC_COLOR:
- b |= RADEON_DST_BLEND_GL_ONE_MINUS_SRC_COLOR;
- break;
- case GL_SRC_ALPHA:
- b |= RADEON_DST_BLEND_GL_SRC_ALPHA;
- break;
- case GL_ONE_MINUS_SRC_ALPHA:
- b |= RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA;
- break;
- case GL_DST_COLOR:
- b |= RADEON_DST_BLEND_GL_DST_COLOR;
- break;
- case GL_ONE_MINUS_DST_COLOR:
- b |= RADEON_DST_BLEND_GL_ONE_MINUS_DST_COLOR;
- break;
- case GL_DST_ALPHA:
- b |= RADEON_DST_BLEND_GL_DST_ALPHA;
- break;
- case GL_ONE_MINUS_DST_ALPHA:
- b |= RADEON_DST_BLEND_GL_ONE_MINUS_DST_ALPHA;
- break;
- case GL_CONSTANT_COLOR:
- case GL_ONE_MINUS_CONSTANT_COLOR:
- case GL_CONSTANT_ALPHA:
- case GL_ONE_MINUS_CONSTANT_ALPHA:
- if (ctx->Color.BlendEnabled)
- fallback = GL_TRUE;
- else
- b |= RADEON_DST_BLEND_GL_ZERO;
- break;
- default:
- break;
- }
-
- FALLBACK( rmesa, RADEON_FALLBACK_BLEND_FUNC, fallback );
- if ( !fallback ) {
- RADEON_STATECHANGE( rmesa, ctx );
- rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = b;
- }
-}
-
-
-/* =============================================================
- * Depth testing
- */
-
-static void radeonDepthFunc( GLcontext *ctx, GLenum func )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-
- RADEON_STATECHANGE( rmesa, ctx );
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_Z_TEST_MASK;
-
- switch ( ctx->Depth.Func ) {
- case GL_NEVER:
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_TEST_NEVER;
- break;
- case GL_LESS:
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_TEST_LESS;
- break;
- case GL_EQUAL:
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_TEST_EQUAL;
- break;
- case GL_LEQUAL:
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_TEST_LEQUAL;
- break;
- case GL_GREATER:
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_TEST_GREATER;
- break;
- case GL_NOTEQUAL:
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_TEST_NEQUAL;
- break;
- case GL_GEQUAL:
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_TEST_GEQUAL;
- break;
- case GL_ALWAYS:
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_TEST_ALWAYS;
- break;
- }
-}
-
-
-static void radeonDepthMask( GLcontext *ctx, GLboolean flag )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- RADEON_STATECHANGE( rmesa, ctx );
-
- if ( ctx->Depth.Mask ) {
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_WRITE_ENABLE;
- } else {
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_Z_WRITE_ENABLE;
- }
-}
-
-static void radeonClearDepth( GLcontext *ctx, GLclampd d )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLuint format = (rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] &
- RADEON_DEPTH_FORMAT_MASK);
-
- switch ( format ) {
- case RADEON_DEPTH_FORMAT_16BIT_INT_Z:
- rmesa->state.depth.clear = d * 0x0000ffff;
- break;
- case RADEON_DEPTH_FORMAT_24BIT_INT_Z:
- rmesa->state.depth.clear = d * 0x00ffffff;
- break;
- }
-}
-
-
-/* =============================================================
- * Fog
- */
-
-
-static void radeonFogfv( GLcontext *ctx, GLenum pname, const GLfloat *param )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- union { int i; float f; } c, d;
- GLchan col[4];
-
- c.i = rmesa->hw.fog.cmd[FOG_C];
- d.i = rmesa->hw.fog.cmd[FOG_D];
-
- switch (pname) {
- case GL_FOG_MODE:
- if (!ctx->Fog.Enabled)
- return;
- RADEON_STATECHANGE(rmesa, tcl);
- rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~RADEON_TCL_FOG_MASK;
- switch (ctx->Fog.Mode) {
- case GL_LINEAR:
- rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= RADEON_TCL_FOG_LINEAR;
- if (ctx->Fog.Start == ctx->Fog.End) {
- c.f = 1.0F;
- d.f = 1.0F;
- }
- else {
- c.f = ctx->Fog.End/(ctx->Fog.End-ctx->Fog.Start);
- d.f = 1.0/(ctx->Fog.End-ctx->Fog.Start);
- }
- break;
- case GL_EXP:
- rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= RADEON_TCL_FOG_EXP;
- c.f = 0.0;
- d.f = ctx->Fog.Density;
- break;
- case GL_EXP2:
- rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= RADEON_TCL_FOG_EXP2;
- c.f = 0.0;
- d.f = -(ctx->Fog.Density * ctx->Fog.Density);
- break;
- default:
- return;
- }
- break;
- case GL_FOG_DENSITY:
- switch (ctx->Fog.Mode) {
- case GL_EXP:
- c.f = 0.0;
- d.f = ctx->Fog.Density;
- break;
- case GL_EXP2:
- c.f = 0.0;
- d.f = -(ctx->Fog.Density * ctx->Fog.Density);
- break;
- default:
- break;
- }
- break;
- case GL_FOG_START:
- case GL_FOG_END:
- if (ctx->Fog.Mode == GL_LINEAR) {
- if (ctx->Fog.Start == ctx->Fog.End) {
- c.f = 1.0F;
- d.f = 1.0F;
- } else {
- c.f = ctx->Fog.End/(ctx->Fog.End-ctx->Fog.Start);
- d.f = 1.0/(ctx->Fog.End-ctx->Fog.Start);
- }
- }
- break;
- case GL_FOG_COLOR:
- RADEON_STATECHANGE( rmesa, ctx );
- UNCLAMPED_FLOAT_TO_RGB_CHAN( col, ctx->Fog.Color );
- rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] =
- radeonPackColor( 4, col[0], col[1], col[2], 0 );
- break;
- case GL_FOG_COORDINATE_SOURCE_EXT:
- /* What to do?
- */
- break;
- default:
- return;
- }
-
- if (c.i != rmesa->hw.fog.cmd[FOG_C] || d.i != rmesa->hw.fog.cmd[FOG_D]) {
- RADEON_STATECHANGE( rmesa, fog );
- rmesa->hw.fog.cmd[FOG_C] = c.i;
- rmesa->hw.fog.cmd[FOG_D] = d.i;
- }
-}
-
-
-/* =============================================================
- * Scissoring
- */
-
-
-static GLboolean intersect_rect( drm_clip_rect_t *out,
- drm_clip_rect_t *a,
- drm_clip_rect_t *b )
-{
- *out = *a;
- if ( b->x1 > out->x1 ) out->x1 = b->x1;
- if ( b->y1 > out->y1 ) out->y1 = b->y1;
- if ( b->x2 < out->x2 ) out->x2 = b->x2;
- if ( b->y2 < out->y2 ) out->y2 = b->y2;
- if ( out->x1 >= out->x2 ) return GL_FALSE;
- if ( out->y1 >= out->y2 ) return GL_FALSE;
- return GL_TRUE;
-}
-
-
-void radeonRecalcScissorRects( radeonContextPtr rmesa )
-{
- drm_clip_rect_t *out;
- int i;
-
- /* Grow cliprect store?
- */
- if (rmesa->state.scissor.numAllocedClipRects < rmesa->numClipRects) {
- while (rmesa->state.scissor.numAllocedClipRects < rmesa->numClipRects) {
- rmesa->state.scissor.numAllocedClipRects += 1; /* zero case */
- rmesa->state.scissor.numAllocedClipRects *= 2;
- }
-
- if (rmesa->state.scissor.pClipRects)
- FREE(rmesa->state.scissor.pClipRects);
-
- rmesa->state.scissor.pClipRects =
- MALLOC( rmesa->state.scissor.numAllocedClipRects *
- sizeof(drm_clip_rect_t) );
-
- if ( rmesa->state.scissor.pClipRects == NULL ) {
- rmesa->state.scissor.numAllocedClipRects = 0;
- return;
- }
- }
-
- out = rmesa->state.scissor.pClipRects;
- rmesa->state.scissor.numClipRects = 0;
-
- for ( i = 0 ; i < rmesa->numClipRects ; i++ ) {
- if ( intersect_rect( out,
- &rmesa->pClipRects[i],
- &rmesa->state.scissor.rect ) ) {
- rmesa->state.scissor.numClipRects++;
- out++;
- }
- }
-}
-
-
-static void radeonUpdateScissor( GLcontext *ctx )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-
- if ( rmesa->dri.drawable ) {
- __DRIdrawablePrivate *dPriv = rmesa->dri.drawable;
-
- int x = ctx->Scissor.X;
- int y = dPriv->h - ctx->Scissor.Y - ctx->Scissor.Height;
- int w = ctx->Scissor.X + ctx->Scissor.Width - 1;
- int h = dPriv->h - ctx->Scissor.Y - 1;
-
- rmesa->state.scissor.rect.x1 = x + dPriv->x;
- rmesa->state.scissor.rect.y1 = y + dPriv->y;
- rmesa->state.scissor.rect.x2 = w + dPriv->x + 1;
- rmesa->state.scissor.rect.y2 = h + dPriv->y + 1;
-
- radeonRecalcScissorRects( rmesa );
- }
-}
-
-
-static void radeonScissor( GLcontext *ctx,
- GLint x, GLint y, GLsizei w, GLsizei h )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-
- if ( ctx->Scissor.Enabled ) {
- RADEON_FIREVERTICES( rmesa ); /* don't pipeline cliprect changes */
- radeonUpdateScissor( ctx );
- }
-
-}
-
-
-/* =============================================================
- * Culling
- */
-
-static void radeonCullFace( GLcontext *ctx, GLenum unused )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLuint s = rmesa->hw.set.cmd[SET_SE_CNTL];
- GLuint t = rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL];
-
- s |= RADEON_FFACE_SOLID | RADEON_BFACE_SOLID;
- t &= ~(RADEON_CULL_FRONT | RADEON_CULL_BACK);
-
- if ( ctx->Polygon.CullFlag ) {
- switch ( ctx->Polygon.CullFaceMode ) {
- case GL_FRONT:
- s &= ~RADEON_FFACE_SOLID;
- t |= RADEON_CULL_FRONT;
- break;
- case GL_BACK:
- s &= ~RADEON_BFACE_SOLID;
- t |= RADEON_CULL_BACK;
- break;
- case GL_FRONT_AND_BACK:
- s &= ~(RADEON_FFACE_SOLID | RADEON_BFACE_SOLID);
- t |= (RADEON_CULL_FRONT | RADEON_CULL_BACK);
- break;
- }
- }
-
- if ( rmesa->hw.set.cmd[SET_SE_CNTL] != s ) {
- RADEON_STATECHANGE(rmesa, set );
- rmesa->hw.set.cmd[SET_SE_CNTL] = s;
- }
-
- if ( rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] != t ) {
- RADEON_STATECHANGE(rmesa, tcl );
- rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] = t;
- }
-}
-
-static void radeonFrontFace( GLcontext *ctx, GLenum mode )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-
- RADEON_STATECHANGE( rmesa, set );
- rmesa->hw.set.cmd[SET_SE_CNTL] &= ~RADEON_FFACE_CULL_DIR_MASK;
-
- RADEON_STATECHANGE( rmesa, tcl );
- rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~RADEON_CULL_FRONT_IS_CCW;
-
- switch ( mode ) {
- case GL_CW:
- rmesa->hw.set.cmd[SET_SE_CNTL] |= RADEON_FFACE_CULL_CW;
- break;
- case GL_CCW:
- rmesa->hw.set.cmd[SET_SE_CNTL] |= RADEON_FFACE_CULL_CCW;
- rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= RADEON_CULL_FRONT_IS_CCW;
- break;
- }
-}
-
-
-/* =============================================================
- * Line state
- */
-static void radeonLineWidth( GLcontext *ctx, GLfloat widthf )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-
- RADEON_STATECHANGE( rmesa, lin );
- RADEON_STATECHANGE( rmesa, set );
-
- /* Line width is stored in U6.4 format.
- */
- rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (GLuint)(widthf * 16.0);
- if ( widthf > 1.0 ) {
- rmesa->hw.set.cmd[SET_SE_CNTL] |= RADEON_WIDELINE_ENABLE;
- } else {
- rmesa->hw.set.cmd[SET_SE_CNTL] &= ~RADEON_WIDELINE_ENABLE;
- }
-}
-
-static void radeonLineStipple( GLcontext *ctx, GLint factor, GLushort pattern )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-
- RADEON_STATECHANGE( rmesa, lin );
- rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] =
- ((((GLuint)factor & 0xff) << 16) | ((GLuint)pattern));
-}
-
-
-/* =============================================================
- * Masks
- */
-static void radeonColorMask( GLcontext *ctx,
- GLboolean r, GLboolean g,
- GLboolean b, GLboolean a )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLuint mask = radeonPackColor( rmesa->radeonScreen->cpp,
- ctx->Color.ColorMask[RCOMP],
- ctx->Color.ColorMask[GCOMP],
- ctx->Color.ColorMask[BCOMP],
- ctx->Color.ColorMask[ACOMP] );
-
- if ( rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] != mask ) {
- RADEON_STATECHANGE( rmesa, msk );
- rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = mask;
- }
-}
-
-
-/* =============================================================
- * Polygon state
- */
-
-static void radeonPolygonOffset( GLcontext *ctx,
- GLfloat factor, GLfloat units )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLfloat constant = units * rmesa->state.depth.scale;
-
- RADEON_STATECHANGE( rmesa, zbs );
- rmesa->hw.zbs.cmd[ZBS_SE_ZBIAS_FACTOR] = *(GLuint *)&factor;
- rmesa->hw.zbs.cmd[ZBS_SE_ZBIAS_CONSTANT] = *(GLuint *)&constant;
-}
-
-static void radeonPolygonStipple( GLcontext *ctx, const GLubyte *mask )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLuint i;
- drm_radeon_stipple_t stipple;
-
- /* Must flip pattern upside down.
- */
- for ( i = 0 ; i < 32 ; i++ ) {
- rmesa->state.stipple.mask[31 - i] = ((GLuint *) mask)[i];
- }
-
- /* TODO: push this into cmd mechanism
- */
- RADEON_FIREVERTICES( rmesa );
- LOCK_HARDWARE( rmesa );
-
- /* FIXME: Use window x,y offsets into stipple RAM.
- */
- stipple.mask = rmesa->state.stipple.mask;
- drmCommandWrite( rmesa->dri.fd, DRM_RADEON_STIPPLE,
- &stipple, sizeof(drm_radeon_stipple_t) );
- UNLOCK_HARDWARE( rmesa );
-}
-
-static void radeonPolygonMode( GLcontext *ctx, GLenum face, GLenum mode )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLboolean flag = (ctx->_TriangleCaps & DD_TRI_UNFILLED) != 0;
-
- /* Can't generally do unfilled via tcl, but some good special
- * cases work.
- */
- TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_UNFILLED, flag);
- if (rmesa->TclFallback) {
- radeonChooseRenderState( ctx );
- radeonChooseVertexState( ctx );
- }
-}
-
-
-/* =============================================================
- * Rendering attributes
- *
- * We really don't want to recalculate all this every time we bind a
- * texture. These things shouldn't change all that often, so it makes
- * sense to break them out of the core texture state update routines.
- */
-
-/* Examine lighting and texture state to determine if separate specular
- * should be enabled.
- */
-static void radeonUpdateSpecular( GLcontext *ctx )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- u_int32_t p = rmesa->hw.ctx.cmd[CTX_PP_CNTL];
-
- RADEON_STATECHANGE( rmesa, tcl );
-
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] &= ~RADEON_TCL_COMPUTE_SPECULAR;
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] &= ~RADEON_TCL_COMPUTE_DIFFUSE;
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] &= ~RADEON_TCL_VTX_PK_SPEC;
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] &= ~RADEON_TCL_VTX_PK_DIFFUSE;
- rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] &= ~RADEON_LIGHTING_ENABLE;
-
- p &= ~RADEON_SPECULAR_ENABLE;
-
- rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] |= RADEON_DIFFUSE_SPECULAR_COMBINE;
-
-
- if (ctx->Light.Enabled &&
- ctx->Light.Model.ColorControl == GL_SEPARATE_SPECULAR_COLOR) {
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] |= RADEON_TCL_COMPUTE_SPECULAR;
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] |= RADEON_TCL_COMPUTE_DIFFUSE;
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_TCL_VTX_PK_SPEC;
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_TCL_VTX_PK_DIFFUSE;
- rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] |= RADEON_LIGHTING_ENABLE;
- p |= RADEON_SPECULAR_ENABLE;
- rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] &=
- ~RADEON_DIFFUSE_SPECULAR_COMBINE;
- }
- else if (ctx->Light.Enabled) {
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] |= RADEON_TCL_COMPUTE_DIFFUSE;
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_TCL_VTX_PK_DIFFUSE;
- rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] |= RADEON_LIGHTING_ENABLE;
- } else if (ctx->Fog.ColorSumEnabled ) {
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_TCL_VTX_PK_SPEC;
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_TCL_VTX_PK_DIFFUSE;
- p |= RADEON_SPECULAR_ENABLE;
- } else {
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_TCL_VTX_PK_DIFFUSE;
- }
-
- if (ctx->Fog.Enabled) {
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] |= RADEON_TCL_COMPUTE_SPECULAR;
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_TCL_VTX_PK_SPEC;
-
- /* Bizzare: have to leave lighting enabled to get fog.
- */
- rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] |= RADEON_LIGHTING_ENABLE;
- }
-
- if (NEED_SECONDARY_COLOR(ctx)) {
- assert( (p & RADEON_SPECULAR_ENABLE) != 0 );
- } else {
- assert( (p & RADEON_SPECULAR_ENABLE) == 0 );
- }
-
- if ( rmesa->hw.ctx.cmd[CTX_PP_CNTL] != p ) {
- RADEON_STATECHANGE( rmesa, ctx );
- rmesa->hw.ctx.cmd[CTX_PP_CNTL] = p;
- }
-
- /* Update vertex/render formats
- */
- if (rmesa->TclFallback) {
- radeonChooseRenderState( ctx );
- radeonChooseVertexState( ctx );
- }
-}
-
-
-/* =============================================================
- * Materials
- */
-
-
-/* Update on colormaterial, material emmissive/ambient,
- * lightmodel.globalambient
- */
-static void update_global_ambient( GLcontext *ctx )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- float *fcmd = (float *)RADEON_DB_STATE( glt );
-
- /* Need to do more if both emmissive & ambient are PREMULT:
- * Hope this is not needed for MULT
- */
- if ((rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] &
- ((3 << RADEON_EMISSIVE_SOURCE_SHIFT) |
- (3 << RADEON_AMBIENT_SOURCE_SHIFT))) == 0)
- {
- COPY_3V( &fcmd[GLT_RED],
- ctx->Light.Material.Attrib[MAT_ATTRIB_FRONT_EMISSION]);
- ACC_SCALE_3V( &fcmd[GLT_RED],
- ctx->Light.Model.Ambient,
- ctx->Light.Material.Attrib[MAT_ATTRIB_FRONT_AMBIENT]);
- }
- else
- {
- COPY_3V( &fcmd[GLT_RED], ctx->Light.Model.Ambient );
- }
-
- RADEON_DB_STATECHANGE(rmesa, &rmesa->hw.glt);
-}
-
-/* Update on change to
- * - light[p].colors
- * - light[p].enabled
- */
-static void update_light_colors( GLcontext *ctx, GLuint p )
-{
- struct gl_light *l = &ctx->Light.Light[p];
-
-/* fprintf(stderr, "%s\n", __FUNCTION__); */
-
- if (l->Enabled) {
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- float *fcmd = (float *)RADEON_DB_STATE( lit[p] );
-
- COPY_4V( &fcmd[LIT_AMBIENT_RED], l->Ambient );
- COPY_4V( &fcmd[LIT_DIFFUSE_RED], l->Diffuse );
- COPY_4V( &fcmd[LIT_SPECULAR_RED], l->Specular );
-
- RADEON_DB_STATECHANGE( rmesa, &rmesa->hw.lit[p] );
- }
-}
-
-/* Also fallback for asym colormaterial mode in twoside lighting...
- */
-static void check_twoside_fallback( GLcontext *ctx )
-{
- GLboolean fallback = GL_FALSE;
- GLint i;
-
- if (ctx->Light.Enabled && ctx->Light.Model.TwoSide) {
- if (ctx->Light.ColorMaterialEnabled &&
- (ctx->Light.ColorMaterialBitmask & BACK_MATERIAL_BITS) !=
- ((ctx->Light.ColorMaterialBitmask & FRONT_MATERIAL_BITS)<<1))
- fallback = GL_TRUE;
- else {
- for (i = MAT_ATTRIB_FRONT_AMBIENT; i < MAT_ATTRIB_FRONT_INDEXES; i+=2)
- if (memcmp( ctx->Light.Material.Attrib[i],
- ctx->Light.Material.Attrib[i+1],
- sizeof(GLfloat)*4) != 0) {
- fallback = GL_TRUE;
- break;
- }
- }
- }
-
- TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_LIGHT_TWOSIDE, fallback );
-}
-
-
-static void radeonColorMaterial( GLcontext *ctx, GLenum face, GLenum mode )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLuint light_model_ctl1 = rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL];
-
- light_model_ctl1 &= ~((3 << RADEON_EMISSIVE_SOURCE_SHIFT) |
- (3 << RADEON_AMBIENT_SOURCE_SHIFT) |
- (3 << RADEON_DIFFUSE_SOURCE_SHIFT) |
- (3 << RADEON_SPECULAR_SOURCE_SHIFT));
-
- if (ctx->Light.ColorMaterialEnabled) {
- GLuint mask = ctx->Light.ColorMaterialBitmask;
-
- if (mask & MAT_BIT_FRONT_EMISSION) {
- light_model_ctl1 |= (RADEON_LM_SOURCE_VERTEX_DIFFUSE <<
- RADEON_EMISSIVE_SOURCE_SHIFT);
- }
- else {
- light_model_ctl1 |= (RADEON_LM_SOURCE_STATE_MULT <<
- RADEON_EMISSIVE_SOURCE_SHIFT);
- }
-
- if (mask & MAT_BIT_FRONT_AMBIENT) {
- light_model_ctl1 |= (RADEON_LM_SOURCE_VERTEX_DIFFUSE <<
- RADEON_AMBIENT_SOURCE_SHIFT);
- }
- else {
- light_model_ctl1 |= (RADEON_LM_SOURCE_STATE_MULT <<
- RADEON_AMBIENT_SOURCE_SHIFT);
- }
-
- if (mask & MAT_BIT_FRONT_DIFFUSE) {
- light_model_ctl1 |= (RADEON_LM_SOURCE_VERTEX_DIFFUSE <<
- RADEON_DIFFUSE_SOURCE_SHIFT);
- }
- else {
- light_model_ctl1 |= (RADEON_LM_SOURCE_STATE_MULT <<
- RADEON_DIFFUSE_SOURCE_SHIFT);
- }
-
- if (mask & MAT_BIT_FRONT_SPECULAR) {
- light_model_ctl1 |= (RADEON_LM_SOURCE_VERTEX_DIFFUSE <<
- RADEON_SPECULAR_SOURCE_SHIFT);
- }
- else {
- light_model_ctl1 |= (RADEON_LM_SOURCE_STATE_MULT <<
- RADEON_SPECULAR_SOURCE_SHIFT);
- }
- }
- else {
- /* Default to MULT:
- */
- light_model_ctl1 |= (RADEON_LM_SOURCE_STATE_MULT << RADEON_EMISSIVE_SOURCE_SHIFT) |
- (RADEON_LM_SOURCE_STATE_MULT << RADEON_AMBIENT_SOURCE_SHIFT) |
- (RADEON_LM_SOURCE_STATE_MULT << RADEON_DIFFUSE_SOURCE_SHIFT) |
- (RADEON_LM_SOURCE_STATE_MULT << RADEON_SPECULAR_SOURCE_SHIFT);
- }
-
- if (light_model_ctl1 != rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL]) {
- RADEON_STATECHANGE( rmesa, tcl );
- rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] = light_model_ctl1;
- }
-}
-
-void radeonUpdateMaterial( GLcontext *ctx )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLfloat (*mat)[4] = ctx->Light.Material.Attrib;
- GLfloat *fcmd = (GLfloat *)RADEON_DB_STATE( mtl );
- GLuint mask = ~0;
-
- if (ctx->Light.ColorMaterialEnabled)
- mask &= ~ctx->Light.ColorMaterialBitmask;
-
- if (RADEON_DEBUG & DEBUG_STATE)
- fprintf(stderr, "%s\n", __FUNCTION__);
-
-
- if (mask & MAT_BIT_FRONT_EMISSION) {
- fcmd[MTL_EMMISSIVE_RED] = mat[MAT_ATTRIB_FRONT_EMISSION][0];
- fcmd[MTL_EMMISSIVE_GREEN] = mat[MAT_ATTRIB_FRONT_EMISSION][1];
- fcmd[MTL_EMMISSIVE_BLUE] = mat[MAT_ATTRIB_FRONT_EMISSION][2];
- fcmd[MTL_EMMISSIVE_ALPHA] = mat[MAT_ATTRIB_FRONT_EMISSION][3];
- }
- if (mask & MAT_BIT_FRONT_AMBIENT) {
- fcmd[MTL_AMBIENT_RED] = mat[MAT_ATTRIB_FRONT_AMBIENT][0];
- fcmd[MTL_AMBIENT_GREEN] = mat[MAT_ATTRIB_FRONT_AMBIENT][1];
- fcmd[MTL_AMBIENT_BLUE] = mat[MAT_ATTRIB_FRONT_AMBIENT][2];
- fcmd[MTL_AMBIENT_ALPHA] = mat[MAT_ATTRIB_FRONT_AMBIENT][3];
- }
- if (mask & MAT_BIT_FRONT_DIFFUSE) {
- fcmd[MTL_DIFFUSE_RED] = mat[MAT_ATTRIB_FRONT_DIFFUSE][0];
- fcmd[MTL_DIFFUSE_GREEN] = mat[MAT_ATTRIB_FRONT_DIFFUSE][1];
- fcmd[MTL_DIFFUSE_BLUE] = mat[MAT_ATTRIB_FRONT_DIFFUSE][2];
- fcmd[MTL_DIFFUSE_ALPHA] = mat[MAT_ATTRIB_FRONT_DIFFUSE][3];
- }
- if (mask & MAT_BIT_FRONT_SPECULAR) {
- fcmd[MTL_SPECULAR_RED] = mat[MAT_ATTRIB_FRONT_SPECULAR][0];
- fcmd[MTL_SPECULAR_GREEN] = mat[MAT_ATTRIB_FRONT_SPECULAR][1];
- fcmd[MTL_SPECULAR_BLUE] = mat[MAT_ATTRIB_FRONT_SPECULAR][2];
- fcmd[MTL_SPECULAR_ALPHA] = mat[MAT_ATTRIB_FRONT_SPECULAR][3];
- }
- if (mask & MAT_BIT_FRONT_SHININESS) {
- fcmd[MTL_SHININESS] = mat[MAT_ATTRIB_FRONT_SHININESS][0];
- }
-
- RADEON_DB_STATECHANGE( rmesa, &rmesa->hw.mtl );
-
- check_twoside_fallback( ctx );
-/* update_global_ambient( ctx );*/
-}
-
-/* _NEW_LIGHT
- * _NEW_MODELVIEW
- * _MESA_NEW_NEED_EYE_COORDS
- *
- * Uses derived state from mesa:
- * _VP_inf_norm
- * _h_inf_norm
- * _Position
- * _NormDirection
- * _ModelViewInvScale
- * _NeedEyeCoords
- * _EyeZDir
- *
- * which are calculated in light.c and are correct for the current
- * lighting space (model or eye), hence dependencies on _NEW_MODELVIEW
- * and _MESA_NEW_NEED_EYE_COORDS.
- */
-static void update_light( GLcontext *ctx )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-
- /* Have to check these, or have an automatic shortcircuit mechanism
- * to remove noop statechanges. (Or just do a better job on the
- * front end).
- */
- {
- GLuint tmp = rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL];
-
- if (ctx->_NeedEyeCoords)
- tmp &= ~RADEON_LIGHT_IN_MODELSPACE;
- else
- tmp |= RADEON_LIGHT_IN_MODELSPACE;
-
-
- /* Leave this test disabled: (unexplained q3 lockup) (even with
- new packets)
- */
- if (tmp != rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL])
- {
- RADEON_STATECHANGE( rmesa, tcl );
- rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] = tmp;
- }
- }
-
- {
- GLfloat *fcmd = (GLfloat *)RADEON_DB_STATE( eye );
- fcmd[EYE_X] = ctx->_EyeZDir[0];
- fcmd[EYE_Y] = ctx->_EyeZDir[1];
- fcmd[EYE_Z] = - ctx->_EyeZDir[2];
- fcmd[EYE_RESCALE_FACTOR] = ctx->_ModelViewInvScale;
- RADEON_DB_STATECHANGE( rmesa, &rmesa->hw.eye );
- }
-
-
-
- if (ctx->Light.Enabled) {
- GLint p;
- for (p = 0 ; p < MAX_LIGHTS; p++) {
- if (ctx->Light.Light[p].Enabled) {
- struct gl_light *l = &ctx->Light.Light[p];
- GLfloat *fcmd = (GLfloat *)RADEON_DB_STATE( lit[p] );
-
- if (l->EyePosition[3] == 0.0) {
- COPY_3FV( &fcmd[LIT_POSITION_X], l->_VP_inf_norm );
- COPY_3FV( &fcmd[LIT_DIRECTION_X], l->_h_inf_norm );
- fcmd[LIT_POSITION_W] = 0;
- fcmd[LIT_DIRECTION_W] = 0;
- } else {
- COPY_4V( &fcmd[LIT_POSITION_X], l->_Position );
- fcmd[LIT_DIRECTION_X] = -l->_NormDirection[0];
- fcmd[LIT_DIRECTION_Y] = -l->_NormDirection[1];
- fcmd[LIT_DIRECTION_Z] = -l->_NormDirection[2];
- fcmd[LIT_DIRECTION_W] = 0;
- }
-
- RADEON_DB_STATECHANGE( rmesa, &rmesa->hw.lit[p] );
- }
- }
- }
-}
-
-static void radeonLightfv( GLcontext *ctx, GLenum light,
- GLenum pname, const GLfloat *params )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLint p = light - GL_LIGHT0;
- struct gl_light *l = &ctx->Light.Light[p];
- GLfloat *fcmd = (GLfloat *)rmesa->hw.lit[p].cmd;
-
-
- switch (pname) {
- case GL_AMBIENT:
- case GL_DIFFUSE:
- case GL_SPECULAR:
- update_light_colors( ctx, p );
- break;
-
- case GL_SPOT_DIRECTION:
- /* picked up in update_light */
- break;
-
- case GL_POSITION: {
- /* positions picked up in update_light, but can do flag here */
- GLuint flag;
- GLuint idx = TCL_PER_LIGHT_CTL_0 + p/2;
-
- /* FIXME: Set RANGE_ATTEN only when needed */
- if (p&1)
- flag = RADEON_LIGHT_1_IS_LOCAL;
- else
- flag = RADEON_LIGHT_0_IS_LOCAL;
-
- RADEON_STATECHANGE(rmesa, tcl);
- if (l->EyePosition[3] != 0.0F)
- rmesa->hw.tcl.cmd[idx] |= flag;
- else
- rmesa->hw.tcl.cmd[idx] &= ~flag;
- break;
- }
-
- case GL_SPOT_EXPONENT:
- RADEON_STATECHANGE(rmesa, lit[p]);
- fcmd[LIT_SPOT_EXPONENT] = params[0];
- break;
-
- case GL_SPOT_CUTOFF: {
- GLuint flag = (p&1) ? RADEON_LIGHT_1_IS_SPOT : RADEON_LIGHT_0_IS_SPOT;
- GLuint idx = TCL_PER_LIGHT_CTL_0 + p/2;
-
- RADEON_STATECHANGE(rmesa, lit[p]);
- fcmd[LIT_SPOT_CUTOFF] = l->_CosCutoff;
-
- RADEON_STATECHANGE(rmesa, tcl);
- if (l->SpotCutoff != 180.0F)
- rmesa->hw.tcl.cmd[idx] |= flag;
- else
- rmesa->hw.tcl.cmd[idx] &= ~flag;
-
- break;
- }
-
- case GL_CONSTANT_ATTENUATION:
- RADEON_STATECHANGE(rmesa, lit[p]);
- fcmd[LIT_ATTEN_CONST] = params[0];
- if ( params[0] == 0.0 )
- fcmd[LIT_ATTEN_CONST_INV] = FLT_MAX;
- else
- fcmd[LIT_ATTEN_CONST_INV] = 1.0 / params[0];
- break;
- case GL_LINEAR_ATTENUATION:
- RADEON_STATECHANGE(rmesa, lit[p]);
- fcmd[LIT_ATTEN_LINEAR] = params[0];
- break;
- case GL_QUADRATIC_ATTENUATION:
- RADEON_STATECHANGE(rmesa, lit[p]);
- fcmd[LIT_ATTEN_QUADRATIC] = params[0];
- break;
- default:
- return;
- }
-
- /* Set RANGE_ATTEN only when needed */
- switch (pname) {
- case GL_POSITION:
- case GL_CONSTANT_ATTENUATION:
- case GL_LINEAR_ATTENUATION:
- case GL_QUADRATIC_ATTENUATION:
- {
- GLuint *icmd = (GLuint *)RADEON_DB_STATE( tcl );
- GLuint idx = TCL_PER_LIGHT_CTL_0 + p/2;
- GLuint atten_flag = ( p&1 ) ? RADEON_LIGHT_1_ENABLE_RANGE_ATTEN
- : RADEON_LIGHT_0_ENABLE_RANGE_ATTEN;
- GLuint atten_const_flag = ( p&1 ) ? RADEON_LIGHT_1_CONSTANT_RANGE_ATTEN
- : RADEON_LIGHT_0_CONSTANT_RANGE_ATTEN;
-
- if ( l->EyePosition[3] == 0.0F ||
- ( ( fcmd[LIT_ATTEN_CONST] == 0.0 || fcmd[LIT_ATTEN_CONST] == 1.0 ) &&
- fcmd[LIT_ATTEN_QUADRATIC] == 0.0 && fcmd[LIT_ATTEN_LINEAR] == 0.0 ) ) {
- /* Disable attenuation */
- icmd[idx] &= ~atten_flag;
- } else {
- if ( fcmd[LIT_ATTEN_QUADRATIC] == 0.0 && fcmd[LIT_ATTEN_LINEAR] == 0.0 ) {
- /* Enable only constant portion of attenuation calculation */
- icmd[idx] |= ( atten_flag | atten_const_flag );
- } else {
- /* Enable full attenuation calculation */
- icmd[idx] &= ~atten_const_flag;
- icmd[idx] |= atten_flag;
- }
- }
-
- RADEON_DB_STATECHANGE( rmesa, &rmesa->hw.tcl );
- break;
- }
- default:
- break;
- }
-}
-
-
-
-
-static void radeonLightModelfv( GLcontext *ctx, GLenum pname,
- const GLfloat *param )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-
- switch (pname) {
- case GL_LIGHT_MODEL_AMBIENT:
- update_global_ambient( ctx );
- break;
-
- case GL_LIGHT_MODEL_LOCAL_VIEWER:
- RADEON_STATECHANGE( rmesa, tcl );
- if (ctx->Light.Model.LocalViewer)
- rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] |= RADEON_LOCAL_VIEWER;
- else
- rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] &= ~RADEON_LOCAL_VIEWER;
- break;
-
- case GL_LIGHT_MODEL_TWO_SIDE:
- RADEON_STATECHANGE( rmesa, tcl );
- if (ctx->Light.Model.TwoSide)
- rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= RADEON_LIGHT_TWOSIDE;
- else
- rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~RADEON_LIGHT_TWOSIDE;
-
- check_twoside_fallback( ctx );
-
- if (rmesa->TclFallback) {
- radeonChooseRenderState( ctx );
- radeonChooseVertexState( ctx );
- }
- break;
-
- case GL_LIGHT_MODEL_COLOR_CONTROL:
- radeonUpdateSpecular(ctx);
- break;
-
- default:
- break;
- }
-}
-
-static void radeonShadeModel( GLcontext *ctx, GLenum mode )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLuint s = rmesa->hw.set.cmd[SET_SE_CNTL];
-
- s &= ~(RADEON_DIFFUSE_SHADE_MASK |
- RADEON_ALPHA_SHADE_MASK |
- RADEON_SPECULAR_SHADE_MASK |
- RADEON_FOG_SHADE_MASK);
-
- switch ( mode ) {
- case GL_FLAT:
- s |= (RADEON_DIFFUSE_SHADE_FLAT |
- RADEON_ALPHA_SHADE_FLAT |
- RADEON_SPECULAR_SHADE_FLAT |
- RADEON_FOG_SHADE_FLAT);
- break;
- case GL_SMOOTH:
- s |= (RADEON_DIFFUSE_SHADE_GOURAUD |
- RADEON_ALPHA_SHADE_GOURAUD |
- RADEON_SPECULAR_SHADE_GOURAUD |
- RADEON_FOG_SHADE_GOURAUD);
- break;
- default:
- return;
- }
-
- if ( rmesa->hw.set.cmd[SET_SE_CNTL] != s ) {
- RADEON_STATECHANGE( rmesa, set );
- rmesa->hw.set.cmd[SET_SE_CNTL] = s;
- }
-}
-
-
-/* =============================================================
- * User clip planes
- */
-
-static void radeonClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq )
-{
- GLint p = (GLint) plane - (GLint) GL_CLIP_PLANE0;
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLint *ip = (GLint *)ctx->Transform._ClipUserPlane[p];
-
- RADEON_STATECHANGE( rmesa, ucp[p] );
- rmesa->hw.ucp[p].cmd[UCP_X] = ip[0];
- rmesa->hw.ucp[p].cmd[UCP_Y] = ip[1];
- rmesa->hw.ucp[p].cmd[UCP_Z] = ip[2];
- rmesa->hw.ucp[p].cmd[UCP_W] = ip[3];
-}
-
-static void radeonUpdateClipPlanes( GLcontext *ctx )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLuint p;
-
- for (p = 0; p < ctx->Const.MaxClipPlanes; p++) {
- if (ctx->Transform.ClipPlanesEnabled & (1 << p)) {
- GLint *ip = (GLint *)ctx->Transform._ClipUserPlane[p];
-
- RADEON_STATECHANGE( rmesa, ucp[p] );
- rmesa->hw.ucp[p].cmd[UCP_X] = ip[0];
- rmesa->hw.ucp[p].cmd[UCP_Y] = ip[1];
- rmesa->hw.ucp[p].cmd[UCP_Z] = ip[2];
- rmesa->hw.ucp[p].cmd[UCP_W] = ip[3];
- }
- }
-}
-
-
-/* =============================================================
- * Stencil
- */
-
-static void radeonStencilFunc( GLcontext *ctx, GLenum func,
- GLint ref, GLuint mask )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLuint refmask = ((ctx->Stencil.Ref[0] << RADEON_STENCIL_REF_SHIFT) |
- (ctx->Stencil.ValueMask[0] << RADEON_STENCIL_MASK_SHIFT));
-
- RADEON_STATECHANGE( rmesa, ctx );
- RADEON_STATECHANGE( rmesa, msk );
-
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_STENCIL_TEST_MASK;
- rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] &= ~(RADEON_STENCIL_REF_MASK|
- RADEON_STENCIL_VALUE_MASK);
-
- switch ( ctx->Stencil.Function[0] ) {
- case GL_NEVER:
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_TEST_NEVER;
- break;
- case GL_LESS:
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_TEST_LESS;
- break;
- case GL_EQUAL:
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_TEST_EQUAL;
- break;
- case GL_LEQUAL:
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_TEST_LEQUAL;
- break;
- case GL_GREATER:
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_TEST_GREATER;
- break;
- case GL_NOTEQUAL:
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_TEST_NEQUAL;
- break;
- case GL_GEQUAL:
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_TEST_GEQUAL;
- break;
- case GL_ALWAYS:
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_TEST_ALWAYS;
- break;
- }
-
- rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] |= refmask;
-}
-
-static void radeonStencilMask( GLcontext *ctx, GLuint mask )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-
- RADEON_STATECHANGE( rmesa, msk );
- rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] &= ~RADEON_STENCIL_WRITE_MASK;
- rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] |=
- (ctx->Stencil.WriteMask[0] << RADEON_STENCIL_WRITEMASK_SHIFT);
-}
-
-static void radeonStencilOp( GLcontext *ctx, GLenum fail,
- GLenum zfail, GLenum zpass )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-
- /* radeon 7200 have stencil bug, DEC and INC_WRAP will actually both do DEC_WRAP,
- and DEC_WRAP (and INVERT) will do INVERT. No way to get correct INC_WRAP and DEC,
- but DEC_WRAP can be fixed by using DEC and INC_WRAP at least use INC. */
-
- GLuint tempRADEON_STENCIL_FAIL_DEC_WRAP;
- GLuint tempRADEON_STENCIL_FAIL_INC_WRAP;
- GLuint tempRADEON_STENCIL_ZFAIL_DEC_WRAP;
- GLuint tempRADEON_STENCIL_ZFAIL_INC_WRAP;
- GLuint tempRADEON_STENCIL_ZPASS_DEC_WRAP;
- GLuint tempRADEON_STENCIL_ZPASS_INC_WRAP;
-
- if (rmesa->radeonScreen->chipset & RADEON_CHIPSET_BROKEN_STENCIL) {
- tempRADEON_STENCIL_FAIL_DEC_WRAP = RADEON_STENCIL_FAIL_DEC;
- tempRADEON_STENCIL_FAIL_INC_WRAP = RADEON_STENCIL_FAIL_INC;
- tempRADEON_STENCIL_ZFAIL_DEC_WRAP = RADEON_STENCIL_ZFAIL_DEC;
- tempRADEON_STENCIL_ZFAIL_INC_WRAP = RADEON_STENCIL_ZFAIL_INC;
- tempRADEON_STENCIL_ZPASS_DEC_WRAP = RADEON_STENCIL_ZPASS_DEC;
- tempRADEON_STENCIL_ZPASS_INC_WRAP = RADEON_STENCIL_ZPASS_INC;
- }
- else {
- tempRADEON_STENCIL_FAIL_DEC_WRAP = RADEON_STENCIL_FAIL_DEC_WRAP;
- tempRADEON_STENCIL_FAIL_INC_WRAP = RADEON_STENCIL_FAIL_INC_WRAP;
- tempRADEON_STENCIL_ZFAIL_DEC_WRAP = RADEON_STENCIL_ZFAIL_DEC_WRAP;
- tempRADEON_STENCIL_ZFAIL_INC_WRAP = RADEON_STENCIL_ZFAIL_INC_WRAP;
- tempRADEON_STENCIL_ZPASS_DEC_WRAP = RADEON_STENCIL_ZPASS_DEC_WRAP;
- tempRADEON_STENCIL_ZPASS_INC_WRAP = RADEON_STENCIL_ZPASS_INC_WRAP;
- }
-
- RADEON_STATECHANGE( rmesa, ctx );
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] &= ~(RADEON_STENCIL_FAIL_MASK |
- RADEON_STENCIL_ZFAIL_MASK |
- RADEON_STENCIL_ZPASS_MASK);
-
- switch ( ctx->Stencil.FailFunc[0] ) {
- case GL_KEEP:
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_FAIL_KEEP;
- break;
- case GL_ZERO:
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_FAIL_ZERO;
- break;
- case GL_REPLACE:
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_FAIL_REPLACE;
- break;
- case GL_INCR:
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_FAIL_INC;
- break;
- case GL_DECR:
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_FAIL_DEC;
- break;
- case GL_INCR_WRAP:
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= tempRADEON_STENCIL_FAIL_INC_WRAP;
- break;
- case GL_DECR_WRAP:
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= tempRADEON_STENCIL_FAIL_DEC_WRAP;
- break;
- case GL_INVERT:
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_FAIL_INVERT;
- break;
- }
-
- switch ( ctx->Stencil.ZFailFunc[0] ) {
- case GL_KEEP:
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_ZFAIL_KEEP;
- break;
- case GL_ZERO:
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_ZFAIL_ZERO;
- break;
- case GL_REPLACE:
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_ZFAIL_REPLACE;
- break;
- case GL_INCR:
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_ZFAIL_INC;
- break;
- case GL_DECR:
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_ZFAIL_DEC;
- break;
- case GL_INCR_WRAP:
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= tempRADEON_STENCIL_ZFAIL_INC_WRAP;
- break;
- case GL_DECR_WRAP:
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= tempRADEON_STENCIL_ZFAIL_DEC_WRAP;
- break;
- case GL_INVERT:
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_ZFAIL_INVERT;
- break;
- }
-
- switch ( ctx->Stencil.ZPassFunc[0] ) {
- case GL_KEEP:
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_ZPASS_KEEP;
- break;
- case GL_ZERO:
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_ZPASS_ZERO;
- break;
- case GL_REPLACE:
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_ZPASS_REPLACE;
- break;
- case GL_INCR:
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_ZPASS_INC;
- break;
- case GL_DECR:
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_ZPASS_DEC;
- break;
- case GL_INCR_WRAP:
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= tempRADEON_STENCIL_ZPASS_INC_WRAP;
- break;
- case GL_DECR_WRAP:
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= tempRADEON_STENCIL_ZPASS_DEC_WRAP;
- break;
- case GL_INVERT:
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_STENCIL_ZPASS_INVERT;
- break;
- }
-}
-
-static void radeonClearStencil( GLcontext *ctx, GLint s )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-
- rmesa->state.stencil.clear =
- ((GLuint) ctx->Stencil.Clear |
- (0xff << RADEON_STENCIL_MASK_SHIFT) |
- (ctx->Stencil.WriteMask[0] << RADEON_STENCIL_WRITEMASK_SHIFT));
-}
-
-
-/* =============================================================
- * Window position and viewport transformation
- */
-
-/*
- * To correctly position primitives:
- */
-#define SUBPIXEL_X 0.125
-#define SUBPIXEL_Y 0.125
-
-void radeonUpdateWindow( GLcontext *ctx )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- __DRIdrawablePrivate *dPriv = rmesa->dri.drawable;
- GLfloat xoffset = (GLfloat)dPriv->x;
- GLfloat yoffset = (GLfloat)dPriv->y + dPriv->h;
- const GLfloat *v = ctx->Viewport._WindowMap.m;
-
- GLfloat sx = v[MAT_SX];
- GLfloat tx = v[MAT_TX] + xoffset + SUBPIXEL_X;
- GLfloat sy = - v[MAT_SY];
- GLfloat ty = (- v[MAT_TY]) + yoffset + SUBPIXEL_Y;
- GLfloat sz = v[MAT_SZ] * rmesa->state.depth.scale;
- GLfloat tz = v[MAT_TZ] * rmesa->state.depth.scale;
- RADEON_FIREVERTICES( rmesa );
- RADEON_STATECHANGE( rmesa, vpt );
-
- rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = *(GLuint *)&sx;
- rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = *(GLuint *)&tx;
- rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = *(GLuint *)&sy;
- rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = *(GLuint *)&ty;
- rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = *(GLuint *)&sz;
- rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = *(GLuint *)&tz;
-}
-
-
-
-static void radeonViewport( GLcontext *ctx, GLint x, GLint y,
- GLsizei width, GLsizei height )
-{
- /* update size of Mesa/software ancillary buffers */
- _mesa_ResizeBuffersMESA();
- /* Don't pipeline viewport changes, conflict with window offset
- * setting below. Could apply deltas to rescue pipelined viewport
- * values, or keep the originals hanging around.
- */
- RADEON_FIREVERTICES( RADEON_CONTEXT(ctx) );
- radeonUpdateWindow( ctx );
-}
-
-static void radeonDepthRange( GLcontext *ctx, GLclampd nearval,
- GLclampd farval )
-{
- radeonUpdateWindow( ctx );
-}
-
-void radeonUpdateViewportOffset( GLcontext *ctx )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- __DRIdrawablePrivate *dPriv = rmesa->dri.drawable;
- GLfloat xoffset = (GLfloat)dPriv->x;
- GLfloat yoffset = (GLfloat)dPriv->y + dPriv->h;
- const GLfloat *v = ctx->Viewport._WindowMap.m;
-
- GLfloat tx = v[MAT_TX] + xoffset + SUBPIXEL_X;
- GLfloat ty = (- v[MAT_TY]) + yoffset + SUBPIXEL_Y;
-
- if ( rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] != *(GLuint *)&tx ||
- rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] != *(GLuint *)&ty )
- {
- /* Note: this should also modify whatever data the context reset
- * code uses...
- */
- rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = *(GLuint *)&tx;
- rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = *(GLuint *)&ty;
-
- /* update polygon stipple x/y screen offset */
- {
- GLuint stx, sty;
- GLuint m = rmesa->hw.msc.cmd[MSC_RE_MISC];
-
- m &= ~(RADEON_STIPPLE_X_OFFSET_MASK |
- RADEON_STIPPLE_Y_OFFSET_MASK);
-
- /* add magic offsets, then invert */
- stx = 31 - ((rmesa->dri.drawable->x - 1) & RADEON_STIPPLE_COORD_MASK);
- sty = 31 - ((rmesa->dri.drawable->y + rmesa->dri.drawable->h - 1)
- & RADEON_STIPPLE_COORD_MASK);
-
- m |= ((stx << RADEON_STIPPLE_X_OFFSET_SHIFT) |
- (sty << RADEON_STIPPLE_Y_OFFSET_SHIFT));
-
- if ( rmesa->hw.msc.cmd[MSC_RE_MISC] != m ) {
- RADEON_STATECHANGE( rmesa, msc );
- rmesa->hw.msc.cmd[MSC_RE_MISC] = m;
- }
- }
- }
-
- radeonUpdateScissor( ctx );
-}
-
-
-
-/* =============================================================
- * Miscellaneous
- */
-
-static void radeonClearColor( GLcontext *ctx, const GLfloat color[4] )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLubyte c[4];
- CLAMPED_FLOAT_TO_UBYTE(c[0], color[0]);
- CLAMPED_FLOAT_TO_UBYTE(c[1], color[1]);
- CLAMPED_FLOAT_TO_UBYTE(c[2], color[2]);
- CLAMPED_FLOAT_TO_UBYTE(c[3], color[3]);
- rmesa->state.color.clear = radeonPackColor( rmesa->radeonScreen->cpp,
- c[0], c[1], c[2], c[3] );
-}
-
-
-static void radeonRenderMode( GLcontext *ctx, GLenum mode )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- FALLBACK( rmesa, RADEON_FALLBACK_RENDER_MODE, (mode != GL_RENDER) );
-}
-
-
-static GLuint radeon_rop_tab[] = {
- RADEON_ROP_CLEAR,
- RADEON_ROP_AND,
- RADEON_ROP_AND_REVERSE,
- RADEON_ROP_COPY,
- RADEON_ROP_AND_INVERTED,
- RADEON_ROP_NOOP,
- RADEON_ROP_XOR,
- RADEON_ROP_OR,
- RADEON_ROP_NOR,
- RADEON_ROP_EQUIV,
- RADEON_ROP_INVERT,
- RADEON_ROP_OR_REVERSE,
- RADEON_ROP_COPY_INVERTED,
- RADEON_ROP_OR_INVERTED,
- RADEON_ROP_NAND,
- RADEON_ROP_SET,
-};
-
-static void radeonLogicOpCode( GLcontext *ctx, GLenum opcode )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLuint rop = (GLuint)opcode - GL_CLEAR;
-
- ASSERT( rop < 16 );
-
- RADEON_STATECHANGE( rmesa, msk );
- rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = radeon_rop_tab[rop];
-}
-
-
-void radeonSetCliprects( radeonContextPtr rmesa, GLenum mode )
-{
- __DRIdrawablePrivate *dPriv = rmesa->dri.drawable;
-
- switch ( mode ) {
- case GL_FRONT_LEFT:
- rmesa->numClipRects = dPriv->numClipRects;
- rmesa->pClipRects = dPriv->pClipRects;
- break;
- case GL_BACK_LEFT:
- /* Can't ignore 2d windows if we are page flipping.
- */
- if ( dPriv->numBackClipRects == 0 || rmesa->doPageFlip ) {
- rmesa->numClipRects = dPriv->numClipRects;
- rmesa->pClipRects = dPriv->pClipRects;
- }
- else {
- rmesa->numClipRects = dPriv->numBackClipRects;
- rmesa->pClipRects = dPriv->pBackClipRects;
- }
- break;
- default:
- fprintf(stderr, "bad mode in radeonSetCliprects\n");
- return;
- }
-
- if (rmesa->state.scissor.enabled)
- radeonRecalcScissorRects( rmesa );
-}
-
-
-static void radeonDrawBuffer( GLcontext *ctx, GLenum mode )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-
- if (RADEON_DEBUG & DEBUG_DRI)
- fprintf(stderr, "%s %s\n", __FUNCTION__,
- _mesa_lookup_enum_by_nr( mode ));
-
- RADEON_FIREVERTICES(rmesa); /* don't pipeline cliprect changes */
-
- /*
- * _DrawDestMask is easier to cope with than <mode>.
- */
- switch ( ctx->DrawBuffer->_ColorDrawBufferMask[0] ) {
- case BUFFER_BIT_FRONT_LEFT:
- FALLBACK( rmesa, RADEON_FALLBACK_DRAW_BUFFER, GL_FALSE );
- radeonSetCliprects( rmesa, GL_FRONT_LEFT );
- break;
- case BUFFER_BIT_BACK_LEFT:
- FALLBACK( rmesa, RADEON_FALLBACK_DRAW_BUFFER, GL_FALSE );
- radeonSetCliprects( rmesa, GL_BACK_LEFT );
- break;
- default:
- /* GL_NONE or GL_FRONT_AND_BACK or stereo left&right, etc */
- FALLBACK( rmesa, RADEON_FALLBACK_DRAW_BUFFER, GL_TRUE );
- return;
- }
-
- /* We want to update the s/w rast state too so that r200SetBuffer()
- * gets called.
- */
- _swrast_DrawBuffer(ctx, mode);
-
- RADEON_STATECHANGE( rmesa, ctx );
- rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((rmesa->state.color.drawOffset +
- rmesa->radeonScreen->fbLocation)
- & RADEON_COLOROFFSET_MASK);
- rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = rmesa->state.color.drawPitch;
- if (rmesa->sarea->tiling_enabled) {
- rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= RADEON_COLOR_TILE_ENABLE;
- }
-}
-
-static void radeonReadBuffer( GLcontext *ctx, GLenum mode )
-{
- /* nothing, until we implement h/w glRead/CopyPixels or CopyTexImage */
-}
-
-
-/* =============================================================
- * State enable/disable
- */
-
-static void radeonEnable( GLcontext *ctx, GLenum cap, GLboolean state )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLuint p, flag;
-
- if ( RADEON_DEBUG & DEBUG_STATE )
- fprintf( stderr, "%s( %s = %s )\n", __FUNCTION__,
- _mesa_lookup_enum_by_nr( cap ),
- state ? "GL_TRUE" : "GL_FALSE" );
-
- switch ( cap ) {
- /* Fast track this one...
- */
- case GL_TEXTURE_1D:
- case GL_TEXTURE_2D:
- case GL_TEXTURE_3D:
- break;
-
- case GL_ALPHA_TEST:
- RADEON_STATECHANGE( rmesa, ctx );
- if (state) {
- rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= RADEON_ALPHA_TEST_ENABLE;
- } else {
- rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~RADEON_ALPHA_TEST_ENABLE;
- }
- break;
-
- case GL_BLEND:
- RADEON_STATECHANGE( rmesa, ctx );
- if (state) {
- rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_ALPHA_BLEND_ENABLE;
- } else {
- rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_ALPHA_BLEND_ENABLE;
- }
- if ( ctx->Color._LogicOpEnabled ) {
- rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_ROP_ENABLE;
- } else {
- rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_ROP_ENABLE;
- }
-
- /* Catch a possible fallback:
- */
- if (state) {
- ctx->Driver.BlendEquationSeparate( ctx,
- ctx->Color.BlendEquationRGB,
- ctx->Color.BlendEquationA );
- ctx->Driver.BlendFuncSeparate( ctx, ctx->Color.BlendSrcRGB,
- ctx->Color.BlendDstRGB,
- ctx->Color.BlendSrcA,
- ctx->Color.BlendDstA );
- }
- else {
- FALLBACK( rmesa, RADEON_FALLBACK_BLEND_FUNC, GL_FALSE );
- FALLBACK( rmesa, RADEON_FALLBACK_BLEND_EQ, GL_FALSE );
- }
- break;
-
- case GL_CLIP_PLANE0:
- case GL_CLIP_PLANE1:
- case GL_CLIP_PLANE2:
- case GL_CLIP_PLANE3:
- case GL_CLIP_PLANE4:
- case GL_CLIP_PLANE5:
- p = cap-GL_CLIP_PLANE0;
- RADEON_STATECHANGE( rmesa, tcl );
- if (state) {
- rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= (RADEON_UCP_ENABLE_0<<p);
- radeonClipPlane( ctx, cap, NULL );
- }
- else {
- rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~(RADEON_UCP_ENABLE_0<<p);
- }
- break;
-
- case GL_COLOR_MATERIAL:
- radeonColorMaterial( ctx, 0, 0 );
- radeonUpdateMaterial( ctx );
- break;
-
- case GL_CULL_FACE:
- radeonCullFace( ctx, 0 );
- break;
-
- case GL_DEPTH_TEST:
- RADEON_STATECHANGE(rmesa, ctx );
- if ( state ) {
- rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_Z_ENABLE;
- } else {
- rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_Z_ENABLE;
- }
- break;
-
- case GL_DITHER:
- RADEON_STATECHANGE(rmesa, ctx );
- if ( state ) {
- rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_ENABLE;
- rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~rmesa->state.color.roundEnable;
- } else {
- rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_DITHER_ENABLE;
- rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->state.color.roundEnable;
- }
- break;
-
- case GL_FOG:
- RADEON_STATECHANGE(rmesa, ctx );
- if ( state ) {
- rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= RADEON_FOG_ENABLE;
- radeonFogfv( ctx, GL_FOG_MODE, NULL );
- } else {
- rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~RADEON_FOG_ENABLE;
- RADEON_STATECHANGE(rmesa, tcl);
- rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~RADEON_TCL_FOG_MASK;
- }
- radeonUpdateSpecular( ctx ); /* for PK_SPEC */
- if (rmesa->TclFallback)
- radeonChooseVertexState( ctx );
- _mesa_allow_light_in_model( ctx, !state );
- break;
-
- case GL_LIGHT0:
- case GL_LIGHT1:
- case GL_LIGHT2:
- case GL_LIGHT3:
- case GL_LIGHT4:
- case GL_LIGHT5:
- case GL_LIGHT6:
- case GL_LIGHT7:
- RADEON_STATECHANGE(rmesa, tcl);
- p = cap - GL_LIGHT0;
- if (p&1)
- flag = (RADEON_LIGHT_1_ENABLE |
- RADEON_LIGHT_1_ENABLE_AMBIENT |
- RADEON_LIGHT_1_ENABLE_SPECULAR);
- else
- flag = (RADEON_LIGHT_0_ENABLE |
- RADEON_LIGHT_0_ENABLE_AMBIENT |
- RADEON_LIGHT_0_ENABLE_SPECULAR);
-
- if (state)
- rmesa->hw.tcl.cmd[p/2 + TCL_PER_LIGHT_CTL_0] |= flag;
- else
- rmesa->hw.tcl.cmd[p/2 + TCL_PER_LIGHT_CTL_0] &= ~flag;
-
- /*
- */
- update_light_colors( ctx, p );
- break;
-
- case GL_LIGHTING:
- RADEON_STATECHANGE(rmesa, tcl);
- radeonUpdateSpecular(ctx);
- check_twoside_fallback( ctx );
- break;
-
- case GL_LINE_SMOOTH:
- RADEON_STATECHANGE( rmesa, ctx );
- if ( state ) {
- rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= RADEON_ANTI_ALIAS_LINE;
- } else {
- rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~RADEON_ANTI_ALIAS_LINE;
- }
- break;
-
- case GL_LINE_STIPPLE:
- RADEON_STATECHANGE( rmesa, ctx );
- if ( state ) {
- rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= RADEON_PATTERN_ENABLE;
- } else {
- rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~RADEON_PATTERN_ENABLE;
- }
- break;
-
- case GL_COLOR_LOGIC_OP:
- RADEON_STATECHANGE( rmesa, ctx );
- if ( ctx->Color._LogicOpEnabled ) {
- rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_ROP_ENABLE;
- } else {
- rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_ROP_ENABLE;
- }
- break;
-
- case GL_NORMALIZE:
- RADEON_STATECHANGE( rmesa, tcl );
- if ( state ) {
- rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] |= RADEON_NORMALIZE_NORMALS;
- } else {
- rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] &= ~RADEON_NORMALIZE_NORMALS;
- }
- break;
-
- case GL_POLYGON_OFFSET_POINT:
- if (rmesa->dri.drmMinor == 1) {
- radeonChooseRenderState( ctx );
- }
- else {
- RADEON_STATECHANGE( rmesa, set );
- if ( state ) {
- rmesa->hw.set.cmd[SET_SE_CNTL] |= RADEON_ZBIAS_ENABLE_POINT;
- } else {
- rmesa->hw.set.cmd[SET_SE_CNTL] &= ~RADEON_ZBIAS_ENABLE_POINT;
- }
- }
- break;
-
- case GL_POLYGON_OFFSET_LINE:
- if (rmesa->dri.drmMinor == 1) {
- radeonChooseRenderState( ctx );
- }
- else {
- RADEON_STATECHANGE( rmesa, set );
- if ( state ) {
- rmesa->hw.set.cmd[SET_SE_CNTL] |= RADEON_ZBIAS_ENABLE_LINE;
- } else {
- rmesa->hw.set.cmd[SET_SE_CNTL] &= ~RADEON_ZBIAS_ENABLE_LINE;
- }
- }
- break;
-
- case GL_POLYGON_OFFSET_FILL:
- if (rmesa->dri.drmMinor == 1) {
- radeonChooseRenderState( ctx );
- }
- else {
- RADEON_STATECHANGE( rmesa, set );
- if ( state ) {
- rmesa->hw.set.cmd[SET_SE_CNTL] |= RADEON_ZBIAS_ENABLE_TRI;
- } else {
- rmesa->hw.set.cmd[SET_SE_CNTL] &= ~RADEON_ZBIAS_ENABLE_TRI;
- }
- }
- break;
-
- case GL_POLYGON_SMOOTH:
- RADEON_STATECHANGE( rmesa, ctx );
- if ( state ) {
- rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= RADEON_ANTI_ALIAS_POLY;
- } else {
- rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~RADEON_ANTI_ALIAS_POLY;
- }
- break;
-
- case GL_POLYGON_STIPPLE:
- RADEON_STATECHANGE(rmesa, ctx );
- if ( state ) {
- rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= RADEON_STIPPLE_ENABLE;
- } else {
- rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~RADEON_STIPPLE_ENABLE;
- }
- break;
-
- case GL_RESCALE_NORMAL_EXT: {
- GLboolean tmp = ctx->_NeedEyeCoords ? state : !state;
- RADEON_STATECHANGE( rmesa, tcl );
- if ( tmp ) {
- rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] |= RADEON_RESCALE_NORMALS;
- } else {
- rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] &= ~RADEON_RESCALE_NORMALS;
- }
- break;
- }
-
- case GL_SCISSOR_TEST:
- RADEON_FIREVERTICES( rmesa );
- rmesa->state.scissor.enabled = state;
- radeonUpdateScissor( ctx );
- break;
-
- case GL_STENCIL_TEST:
- if ( rmesa->state.stencil.hwBuffer ) {
- RADEON_STATECHANGE( rmesa, ctx );
- if ( state ) {
- rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_STENCIL_ENABLE;
- } else {
- rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_STENCIL_ENABLE;
- }
- } else {
- FALLBACK( rmesa, RADEON_FALLBACK_STENCIL, state );
- }
- break;
-
- case GL_TEXTURE_GEN_Q:
- case GL_TEXTURE_GEN_R:
- case GL_TEXTURE_GEN_S:
- case GL_TEXTURE_GEN_T:
- /* Picked up in radeonUpdateTextureState.
- */
- rmesa->recheck_texgen[ctx->Texture.CurrentUnit] = GL_TRUE;
- break;
-
- case GL_COLOR_SUM_EXT:
- radeonUpdateSpecular ( ctx );
- break;
-
- default:
- return;
- }
-}
-
-
-static void radeonLightingSpaceChange( GLcontext *ctx )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLboolean tmp;
- RADEON_STATECHANGE( rmesa, tcl );
-
- if (RADEON_DEBUG & DEBUG_STATE)
- fprintf(stderr, "%s %d BEFORE %x\n", __FUNCTION__, ctx->_NeedEyeCoords,
- rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL]);
-
- if (ctx->_NeedEyeCoords)
- tmp = ctx->Transform.RescaleNormals;
- else
- tmp = !ctx->Transform.RescaleNormals;
-
- if ( tmp ) {
- rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] |= RADEON_RESCALE_NORMALS;
- } else {
- rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] &= ~RADEON_RESCALE_NORMALS;
- }
-
- if (RADEON_DEBUG & DEBUG_STATE)
- fprintf(stderr, "%s %d AFTER %x\n", __FUNCTION__, ctx->_NeedEyeCoords,
- rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL]);
-}
-
-/* =============================================================
- * Deferred state management - matrices, textures, other?
- */
-
-
-
-
-static void upload_matrix( radeonContextPtr rmesa, GLfloat *src, int idx )
-{
- float *dest = ((float *)RADEON_DB_STATE( mat[idx] ))+MAT_ELT_0;
- int i;
-
-
- for (i = 0 ; i < 4 ; i++) {
- *dest++ = src[i];
- *dest++ = src[i+4];
- *dest++ = src[i+8];
- *dest++ = src[i+12];
- }
-
- RADEON_DB_STATECHANGE( rmesa, &rmesa->hw.mat[idx] );
-}
-
-static void upload_matrix_t( radeonContextPtr rmesa, GLfloat *src, int idx )
-{
- float *dest = ((float *)RADEON_DB_STATE( mat[idx] ))+MAT_ELT_0;
- memcpy(dest, src, 16*sizeof(float));
- RADEON_DB_STATECHANGE( rmesa, &rmesa->hw.mat[idx] );
-}
-
-
-static void update_texturematrix( GLcontext *ctx )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
- GLuint tpc = rmesa->hw.tcl.cmd[TCL_TEXTURE_PROC_CTL];
- GLuint vs = rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL];
- int unit;
-
- rmesa->TexMatEnabled = 0;
-
- for (unit = 0 ; unit < 2; unit++) {
- if (!ctx->Texture.Unit[unit]._ReallyEnabled) {
- }
- else if (ctx->TextureMatrixStack[unit].Top->type != MATRIX_IDENTITY) {
- GLuint inputshift = RADEON_TEXGEN_0_INPUT_SHIFT + unit*4;
-
- rmesa->TexMatEnabled |= (RADEON_TEXGEN_TEXMAT_0_ENABLE|
- RADEON_TEXMAT_0_ENABLE) << unit;
-
- if (rmesa->TexGenEnabled & (RADEON_TEXMAT_0_ENABLE << unit)) {
- /* Need to preconcatenate any active texgen
- * obj/eyeplane matrices:
- */
- _math_matrix_mul_matrix( &rmesa->tmpmat,
- &rmesa->TexGenMatrix[unit],
- ctx->TextureMatrixStack[unit].Top );
- upload_matrix( rmesa, rmesa->tmpmat.m, TEXMAT_0+unit );
- }
- else {
- rmesa->TexMatEnabled |=
- (RADEON_TEXGEN_INPUT_TEXCOORD_0+unit) << inputshift;
- upload_matrix( rmesa, ctx->TextureMatrixStack[unit].Top->m,
- TEXMAT_0+unit );
- }
- }
- else if (rmesa->TexGenEnabled & (RADEON_TEXMAT_0_ENABLE << unit)) {
- upload_matrix( rmesa, rmesa->TexGenMatrix[unit].m,
- TEXMAT_0+unit );
- }
- }
-
-
- tpc = (rmesa->TexMatEnabled | rmesa->TexGenEnabled);
-
- vs &= ~((0xf << RADEON_TCL_TEX_0_OUTPUT_SHIFT) |
- (0xf << RADEON_TCL_TEX_1_OUTPUT_SHIFT));
-
- if (tpc & RADEON_TEXGEN_TEXMAT_0_ENABLE)
- vs |= RADEON_TCL_TEX_COMPUTED_TEX_0 << RADEON_TCL_TEX_0_OUTPUT_SHIFT;
- else
- vs |= RADEON_TCL_TEX_INPUT_TEX_0 << RADEON_TCL_TEX_0_OUTPUT_SHIFT;
-
- if (tpc & RADEON_TEXGEN_TEXMAT_1_ENABLE)
- vs |= RADEON_TCL_TEX_COMPUTED_TEX_1 << RADEON_TCL_TEX_1_OUTPUT_SHIFT;
- else
- vs |= RADEON_TCL_TEX_INPUT_TEX_1 << RADEON_TCL_TEX_1_OUTPUT_SHIFT;
-
- if (tpc != rmesa->hw.tcl.cmd[TCL_TEXTURE_PROC_CTL] ||
- vs != rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL]) {
-
- RADEON_STATECHANGE(rmesa, tcl);
- rmesa->hw.tcl.cmd[TCL_TEXTURE_PROC_CTL] = tpc;
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] = vs;
- }
-}
-
-
-
-void radeonValidateState( GLcontext *ctx )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLuint new_state = rmesa->NewGLState;
-
- if (new_state & _NEW_TEXTURE) {
- radeonUpdateTextureState( ctx );
- new_state |= rmesa->NewGLState; /* may add TEXTURE_MATRIX */
- }
-
- /* Need an event driven matrix update?
- */
- if (new_state & (_NEW_MODELVIEW|_NEW_PROJECTION))
- upload_matrix( rmesa, ctx->_ModelProjectMatrix.m, MODEL_PROJ );
-
- /* Need these for lighting (shouldn't upload otherwise)
- */
- if (new_state & (_NEW_MODELVIEW)) {
- upload_matrix( rmesa, ctx->ModelviewMatrixStack.Top->m, MODEL );
- upload_matrix_t( rmesa, ctx->ModelviewMatrixStack.Top->inv, MODEL_IT );
- }
-
- /* Does this need to be triggered on eg. modelview for
- * texgen-derived objplane/eyeplane matrices?
- */
- if (new_state & _NEW_TEXTURE_MATRIX) {
- update_texturematrix( ctx );
- }
-
- if (new_state & (_NEW_LIGHT|_NEW_MODELVIEW|_MESA_NEW_NEED_EYE_COORDS)) {
- update_light( ctx );
- }
-
- /* emit all active clip planes if projection matrix changes.
- */
- if (new_state & (_NEW_PROJECTION)) {
- if (ctx->Transform.ClipPlanesEnabled)
- radeonUpdateClipPlanes( ctx );
- }
-
-
- rmesa->NewGLState = 0;
-}
-
-
-static void radeonInvalidateState( GLcontext *ctx, GLuint new_state )
-{
- _swrast_InvalidateState( ctx, new_state );
- _swsetup_InvalidateState( ctx, new_state );
- _ac_InvalidateState( ctx, new_state );
- _tnl_InvalidateState( ctx, new_state );
- _ae_invalidate_state( ctx, new_state );
- RADEON_CONTEXT(ctx)->NewGLState |= new_state;
- radeonVtxfmtInvalidate( ctx );
-}
-
-
-/* A hack. Need a faster way to find this out.
- */
-static GLboolean check_material( GLcontext *ctx )
-{
- TNLcontext *tnl = TNL_CONTEXT(ctx);
- GLint i;
-
- for (i = _TNL_ATTRIB_MAT_FRONT_AMBIENT;
- i < _TNL_ATTRIB_MAT_BACK_INDEXES;
- i++)
- if (tnl->vb.AttribPtr[i] &&
- tnl->vb.AttribPtr[i]->stride)
- return GL_TRUE;
-
- return GL_FALSE;
-}
-
-
-static void radeonWrapRunPipeline( GLcontext *ctx )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLboolean has_material;
-
- if (0)
- fprintf(stderr, "%s, newstate: %x\n", __FUNCTION__, rmesa->NewGLState);
-
- /* Validate state:
- */
- if (rmesa->NewGLState)
- radeonValidateState( ctx );
-
- has_material = (ctx->Light.Enabled && check_material( ctx ));
-
- if (has_material) {
- TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_MATERIAL, GL_TRUE );
- }
-
- /* Run the pipeline.
- */
- _tnl_run_pipeline( ctx );
-
- if (has_material) {
- TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_MATERIAL, GL_FALSE );
- }
-}
-
-
-/* Initialize the driver's state functions.
- */
-void radeonInitStateFuncs( GLcontext *ctx )
-{
- ctx->Driver.UpdateState = radeonInvalidateState;
- ctx->Driver.LightingSpaceChange = radeonLightingSpaceChange;
-
- ctx->Driver.DrawBuffer = radeonDrawBuffer;
- ctx->Driver.ReadBuffer = radeonReadBuffer;
-
- ctx->Driver.AlphaFunc = radeonAlphaFunc;
- ctx->Driver.BlendEquationSeparate = radeonBlendEquationSeparate;
- ctx->Driver.BlendFuncSeparate = radeonBlendFuncSeparate;
- ctx->Driver.ClearColor = radeonClearColor;
- ctx->Driver.ClearDepth = radeonClearDepth;
- ctx->Driver.ClearIndex = NULL;
- ctx->Driver.ClearStencil = radeonClearStencil;
- ctx->Driver.ClipPlane = radeonClipPlane;
- ctx->Driver.ColorMask = radeonColorMask;
- ctx->Driver.CullFace = radeonCullFace;
- ctx->Driver.DepthFunc = radeonDepthFunc;
- ctx->Driver.DepthMask = radeonDepthMask;
- ctx->Driver.DepthRange = radeonDepthRange;
- ctx->Driver.Enable = radeonEnable;
- ctx->Driver.Fogfv = radeonFogfv;
- ctx->Driver.FrontFace = radeonFrontFace;
- ctx->Driver.Hint = NULL;
- ctx->Driver.IndexMask = NULL;
- ctx->Driver.LightModelfv = radeonLightModelfv;
- ctx->Driver.Lightfv = radeonLightfv;
- ctx->Driver.LineStipple = radeonLineStipple;
- ctx->Driver.LineWidth = radeonLineWidth;
- ctx->Driver.LogicOpcode = radeonLogicOpCode;
- ctx->Driver.PolygonMode = radeonPolygonMode;
-
- if (RADEON_CONTEXT(ctx)->dri.drmMinor > 1)
- ctx->Driver.PolygonOffset = radeonPolygonOffset;
-
- ctx->Driver.PolygonStipple = radeonPolygonStipple;
- ctx->Driver.RenderMode = radeonRenderMode;
- ctx->Driver.Scissor = radeonScissor;
- ctx->Driver.ShadeModel = radeonShadeModel;
- ctx->Driver.StencilFunc = radeonStencilFunc;
- ctx->Driver.StencilMask = radeonStencilMask;
- ctx->Driver.StencilOp = radeonStencilOp;
- ctx->Driver.Viewport = radeonViewport;
-
- /* Pixel path fallbacks
- */
- ctx->Driver.Accum = _swrast_Accum;
- ctx->Driver.Bitmap = _swrast_Bitmap;
- ctx->Driver.CopyPixels = _swrast_CopyPixels;
- ctx->Driver.DrawPixels = _swrast_DrawPixels;
- ctx->Driver.ReadPixels = _swrast_ReadPixels;
-
- /* Swrast hooks for imaging extensions:
- */
- ctx->Driver.CopyColorTable = _swrast_CopyColorTable;
- ctx->Driver.CopyColorSubTable = _swrast_CopyColorSubTable;
- ctx->Driver.CopyConvolutionFilter1D = _swrast_CopyConvolutionFilter1D;
- ctx->Driver.CopyConvolutionFilter2D = _swrast_CopyConvolutionFilter2D;
-
- TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange = radeonUpdateMaterial;
- TNL_CONTEXT(ctx)->Driver.RunPipeline = radeonWrapRunPipeline;
-}
diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_state.h b/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_state.h
deleted file mode 100644
index 07739be94..000000000
--- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_state.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_state.h,v 1.5 2002/11/05 17:46:09 tsi Exp $ */
-/**************************************************************************
-
-Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
- VA Linux Systems Inc., Fremont, California.
-
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/*
- * Authors:
- * Kevin E. Martin <martin@valinux.com>
- * Gareth Hughes <gareth@valinux.com>
- *
- */
-
-#ifndef __RADEON_STATE_H__
-#define __RADEON_STATE_H__
-
-#include "radeon_context.h"
-
-extern void radeonInitState( radeonContextPtr rmesa );
-extern void radeonInitStateFuncs( GLcontext *ctx );
-
-extern void radeonUpdateMaterial( GLcontext *ctx );
-
-extern void radeonSetCliprects( radeonContextPtr rmesa, GLenum mode );
-extern void radeonRecalcScissorRects( radeonContextPtr rmesa );
-extern void radeonUpdateViewportOffset( GLcontext *ctx );
-extern void radeonUpdateWindow( GLcontext *ctx );
-
-extern void radeonValidateState( GLcontext *ctx );
-
-extern void radeonPrintDirty( radeonContextPtr rmesa,
- const char *msg );
-
-
-extern void radeonFallback( GLcontext *ctx, GLuint bit, GLboolean mode );
-#define FALLBACK( rmesa, bit, mode ) do { \
- if ( 0 ) fprintf( stderr, "FALLBACK in %s: #%d=%d\n", \
- __FUNCTION__, bit, mode ); \
- radeonFallback( rmesa->glCtx, bit, mode ); \
-} while (0)
-
-
-#define MODEL_PROJ 0
-#define MODEL 1
-#define MODEL_IT 2
-#define TEXMAT_0 3
-#define TEXMAT_1 4
-#define TEXMAT_2 5
-
-#endif
diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_state_init.c b/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_state_init.c
deleted file mode 100644
index 1caffe132..000000000
--- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_state_init.c
+++ /dev/null
@@ -1,572 +0,0 @@
-/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_state_init.c,v 1.3 2003/02/22 06:21:11 dawes Exp $ */
-/*
- * Copyright 2000, 2001 VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * on the rights to use, copy, modify, merge, publish, distribute, sub
- * license, and/or sell copies of the Software, and to permit persons to whom
- * the Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Gareth Hughes <gareth@valinux.com>
- * Keith Whitwell <keith@tungstengraphics.com>
- */
-
-#include "glheader.h"
-#include "imports.h"
-#include "api_arrayelt.h"
-
-#include "swrast/swrast.h"
-#include "array_cache/acache.h"
-#include "tnl/tnl.h"
-#include "tnl/t_pipeline.h"
-#include "swrast_setup/swrast_setup.h"
-
-#include "radeon_context.h"
-#include "radeon_ioctl.h"
-#include "radeon_state.h"
-#include "radeon_tcl.h"
-#include "radeon_tex.h"
-#include "radeon_swtcl.h"
-#include "radeon_vtxfmt.h"
-
-#include "xmlpool.h"
-
-/* =============================================================
- * State initialization
- */
-
-void radeonPrintDirty( radeonContextPtr rmesa, const char *msg )
-{
- struct radeon_state_atom *l;
-
- fprintf(stderr, msg);
- fprintf(stderr, ": ");
-
- foreach(l, &rmesa->hw.atomlist) {
- if (l->dirty || rmesa->hw.all_dirty)
- fprintf(stderr, "%s, ", l->name);
- }
-
- fprintf(stderr, "\n");
-}
-
-static int cmdpkt( int id )
-{
- drm_radeon_cmd_header_t h;
- h.i = 0;
- h.packet.cmd_type = RADEON_CMD_PACKET;
- h.packet.packet_id = id;
- return h.i;
-}
-
-static int cmdvec( int offset, int stride, int count )
-{
- drm_radeon_cmd_header_t h;
- h.i = 0;
- h.vectors.cmd_type = RADEON_CMD_VECTORS;
- h.vectors.offset = offset;
- h.vectors.stride = stride;
- h.vectors.count = count;
- return h.i;
-}
-
-static int cmdscl( int offset, int stride, int count )
-{
- drm_radeon_cmd_header_t h;
- h.i = 0;
- h.scalars.cmd_type = RADEON_CMD_SCALARS;
- h.scalars.offset = offset;
- h.scalars.stride = stride;
- h.scalars.count = count;
- return h.i;
-}
-
-#define CHECK( NM, FLAG ) \
-static GLboolean check_##NM( GLcontext *ctx ) \
-{ \
- return FLAG; \
-}
-
-#define TCL_CHECK( NM, FLAG ) \
-static GLboolean check_##NM( GLcontext *ctx ) \
-{ \
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx); \
- return !rmesa->TclFallback && (FLAG); \
-}
-
-
-CHECK( always, GL_TRUE )
-CHECK( tex0, ctx->Texture.Unit[0]._ReallyEnabled )
-CHECK( tex1, ctx->Texture.Unit[1]._ReallyEnabled )
-CHECK( fog, ctx->Fog.Enabled )
-TCL_CHECK( tcl, GL_TRUE )
-TCL_CHECK( tcl_tex0, ctx->Texture.Unit[0]._ReallyEnabled )
-TCL_CHECK( tcl_tex1, ctx->Texture.Unit[1]._ReallyEnabled )
-TCL_CHECK( tcl_lighting, ctx->Light.Enabled )
-TCL_CHECK( tcl_eyespace_or_lighting, ctx->_NeedEyeCoords || ctx->Light.Enabled )
-TCL_CHECK( tcl_lit0, ctx->Light.Enabled && ctx->Light.Light[0].Enabled )
-TCL_CHECK( tcl_lit1, ctx->Light.Enabled && ctx->Light.Light[1].Enabled )
-TCL_CHECK( tcl_lit2, ctx->Light.Enabled && ctx->Light.Light[2].Enabled )
-TCL_CHECK( tcl_lit3, ctx->Light.Enabled && ctx->Light.Light[3].Enabled )
-TCL_CHECK( tcl_lit4, ctx->Light.Enabled && ctx->Light.Light[4].Enabled )
-TCL_CHECK( tcl_lit5, ctx->Light.Enabled && ctx->Light.Light[5].Enabled )
-TCL_CHECK( tcl_lit6, ctx->Light.Enabled && ctx->Light.Light[6].Enabled )
-TCL_CHECK( tcl_lit7, ctx->Light.Enabled && ctx->Light.Light[7].Enabled )
-TCL_CHECK( tcl_ucp0, (ctx->Transform.ClipPlanesEnabled & 0x1) )
-TCL_CHECK( tcl_ucp1, (ctx->Transform.ClipPlanesEnabled & 0x2) )
-TCL_CHECK( tcl_ucp2, (ctx->Transform.ClipPlanesEnabled & 0x4) )
-TCL_CHECK( tcl_ucp3, (ctx->Transform.ClipPlanesEnabled & 0x8) )
-TCL_CHECK( tcl_ucp4, (ctx->Transform.ClipPlanesEnabled & 0x10) )
-TCL_CHECK( tcl_ucp5, (ctx->Transform.ClipPlanesEnabled & 0x20) )
-TCL_CHECK( tcl_eyespace_or_fog, ctx->_NeedEyeCoords || ctx->Fog.Enabled )
-
-CHECK( txr0, (ctx->Texture.Unit[0]._ReallyEnabled & TEXTURE_RECT_BIT))
-CHECK( txr1, (ctx->Texture.Unit[1]._ReallyEnabled & TEXTURE_RECT_BIT))
-
-
-
-/* Initialize the context's hardware state.
- */
-void radeonInitState( radeonContextPtr rmesa )
-{
- GLcontext *ctx = rmesa->glCtx;
- GLuint color_fmt, depth_fmt, i;
-
- switch ( rmesa->radeonScreen->cpp ) {
- case 2:
- color_fmt = RADEON_COLOR_FORMAT_RGB565;
- break;
- case 4:
- color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
- break;
- default:
- fprintf( stderr, "Error: Unsupported pixel depth... exiting\n" );
- exit( -1 );
- }
-
- rmesa->state.color.clear = 0x00000000;
-
- switch ( ctx->Visual.depthBits ) {
- case 16:
- rmesa->state.depth.clear = 0x0000ffff;
- rmesa->state.depth.scale = 1.0 / (GLfloat)0xffff;
- depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
- rmesa->state.stencil.clear = 0x00000000;
- break;
- case 24:
- rmesa->state.depth.clear = 0x00ffffff;
- rmesa->state.depth.scale = 1.0 / (GLfloat)0xffffff;
- depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
- rmesa->state.stencil.clear = 0xffff0000;
- break;
- default:
- fprintf( stderr, "Error: Unsupported depth %d... exiting\n",
- ctx->Visual.depthBits );
- exit( -1 );
- }
-
- /* Only have hw stencil when depth buffer is 24 bits deep */
- rmesa->state.stencil.hwBuffer = ( ctx->Visual.stencilBits > 0 &&
- ctx->Visual.depthBits == 24 );
-
- rmesa->Fallback = 0;
-
- if ( ctx->Visual.doubleBufferMode && rmesa->sarea->pfCurrentPage == 0 ) {
- rmesa->state.color.drawOffset = rmesa->radeonScreen->backOffset;
- rmesa->state.color.drawPitch = rmesa->radeonScreen->backPitch;
- } else {
- rmesa->state.color.drawOffset = rmesa->radeonScreen->frontOffset;
- rmesa->state.color.drawPitch = rmesa->radeonScreen->frontPitch;
- }
- rmesa->state.pixel.readOffset = rmesa->state.color.drawOffset;
- rmesa->state.pixel.readPitch = rmesa->state.color.drawPitch;
-
- rmesa->hw.max_state_size = 0;
-
-#define ALLOC_STATE( ATOM, CHK, SZ, NM, FLAG ) \
- do { \
- rmesa->hw.ATOM.cmd_size = SZ; \
- rmesa->hw.ATOM.cmd = (int *)CALLOC(SZ * sizeof(int)); \
- rmesa->hw.ATOM.lastcmd = (int *)CALLOC(SZ * sizeof(int)); \
- rmesa->hw.ATOM.name = NM; \
- rmesa->hw.ATOM.is_tcl = FLAG; \
- rmesa->hw.ATOM.check = check_##CHK; \
- rmesa->hw.ATOM.dirty = GL_TRUE; \
- rmesa->hw.max_state_size += SZ * sizeof(int); \
- } while (0)
-
-
- /* Allocate state buffers:
- */
- ALLOC_STATE( ctx, always, CTX_STATE_SIZE, "CTX/context", 0 );
- ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 );
- ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 );
- ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 );
- ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 );
- ALLOC_STATE( msc, always, MSC_STATE_SIZE, "MSC/misc", 0 );
- ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 );
- ALLOC_STATE( tcl, always, TCL_STATE_SIZE, "TCL/tcl", 1 );
- ALLOC_STATE( mtl, tcl_lighting, MTL_STATE_SIZE, "MTL/material", 1 );
- ALLOC_STATE( grd, always, GRD_STATE_SIZE, "GRD/guard-band", 1 );
- ALLOC_STATE( fog, fog, FOG_STATE_SIZE, "FOG/fog", 1 );
- ALLOC_STATE( glt, tcl_lighting, GLT_STATE_SIZE, "GLT/light-global", 1 );
- ALLOC_STATE( eye, tcl_lighting, EYE_STATE_SIZE, "EYE/eye-vector", 1 );
- ALLOC_STATE( tex[0], tex0, TEX_STATE_SIZE, "TEX/tex-0", 0 );
- ALLOC_STATE( tex[1], tex1, TEX_STATE_SIZE, "TEX/tex-1", 0 );
- ALLOC_STATE( mat[0], tcl, MAT_STATE_SIZE, "MAT/modelproject", 1 );
- ALLOC_STATE( mat[1], tcl_eyespace_or_fog, MAT_STATE_SIZE, "MAT/modelview", 1 );
- ALLOC_STATE( mat[2], tcl_eyespace_or_lighting, MAT_STATE_SIZE, "MAT/it-modelview", 1 );
- ALLOC_STATE( mat[3], tcl_tex0, MAT_STATE_SIZE, "MAT/texmat0", 1 );
- ALLOC_STATE( mat[4], tcl_tex1, MAT_STATE_SIZE, "MAT/texmat1", 1 );
- ALLOC_STATE( ucp[0], tcl_ucp0, UCP_STATE_SIZE, "UCP/userclip-0", 1 );
- ALLOC_STATE( ucp[1], tcl_ucp1, UCP_STATE_SIZE, "UCP/userclip-1", 1 );
- ALLOC_STATE( ucp[2], tcl_ucp2, UCP_STATE_SIZE, "UCP/userclip-2", 1 );
- ALLOC_STATE( ucp[3], tcl_ucp3, UCP_STATE_SIZE, "UCP/userclip-3", 1 );
- ALLOC_STATE( ucp[4], tcl_ucp4, UCP_STATE_SIZE, "UCP/userclip-4", 1 );
- ALLOC_STATE( ucp[5], tcl_ucp5, UCP_STATE_SIZE, "UCP/userclip-5", 1 );
- ALLOC_STATE( lit[0], tcl_lit0, LIT_STATE_SIZE, "LIT/light-0", 1 );
- ALLOC_STATE( lit[1], tcl_lit1, LIT_STATE_SIZE, "LIT/light-1", 1 );
- ALLOC_STATE( lit[2], tcl_lit2, LIT_STATE_SIZE, "LIT/light-2", 1 );
- ALLOC_STATE( lit[3], tcl_lit3, LIT_STATE_SIZE, "LIT/light-3", 1 );
- ALLOC_STATE( lit[4], tcl_lit4, LIT_STATE_SIZE, "LIT/light-4", 1 );
- ALLOC_STATE( lit[5], tcl_lit5, LIT_STATE_SIZE, "LIT/light-5", 1 );
- ALLOC_STATE( lit[6], tcl_lit6, LIT_STATE_SIZE, "LIT/light-6", 1 );
- ALLOC_STATE( lit[7], tcl_lit7, LIT_STATE_SIZE, "LIT/light-7", 1 );
- ALLOC_STATE( txr[0], txr0, TXR_STATE_SIZE, "TXR/txr-0", 0 );
- ALLOC_STATE( txr[1], txr1, TXR_STATE_SIZE, "TXR/txr-1", 0 );
-
- radeonSetUpAtomList( rmesa );
-
- /* Fill in the packet headers:
- */
- rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(RADEON_EMIT_PP_MISC);
- rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(RADEON_EMIT_PP_CNTL);
- rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(RADEON_EMIT_RB3D_COLORPITCH);
- rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(RADEON_EMIT_RE_LINE_PATTERN);
- rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(RADEON_EMIT_SE_LINE_WIDTH);
- rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(RADEON_EMIT_RB3D_STENCILREFMASK);
- rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(RADEON_EMIT_SE_VPORT_XSCALE);
- rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(RADEON_EMIT_SE_CNTL);
- rmesa->hw.set.cmd[SET_CMD_1] = cmdpkt(RADEON_EMIT_SE_CNTL_STATUS);
- rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(RADEON_EMIT_RE_MISC);
- rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(RADEON_EMIT_PP_TXFILTER_0);
- rmesa->hw.tex[0].cmd[TEX_CMD_1] = cmdpkt(RADEON_EMIT_PP_BORDER_COLOR_0);
- rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(RADEON_EMIT_PP_TXFILTER_1);
- rmesa->hw.tex[1].cmd[TEX_CMD_1] = cmdpkt(RADEON_EMIT_PP_BORDER_COLOR_1);
- rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(RADEON_EMIT_SE_ZBIAS_FACTOR);
- rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT);
- rmesa->hw.mtl.cmd[MTL_CMD_0] =
- cmdpkt(RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED);
- rmesa->hw.txr[0].cmd[TXR_CMD_0] = cmdpkt(RADEON_EMIT_PP_TEX_SIZE_0);
- rmesa->hw.txr[1].cmd[TXR_CMD_0] = cmdpkt(RADEON_EMIT_PP_TEX_SIZE_1);
- rmesa->hw.grd.cmd[GRD_CMD_0] =
- cmdscl( RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 );
- rmesa->hw.fog.cmd[FOG_CMD_0] =
- cmdvec( RADEON_VS_FOG_PARAM_ADDR, 1, 4 );
- rmesa->hw.glt.cmd[GLT_CMD_0] =
- cmdvec( RADEON_VS_GLOBAL_AMBIENT_ADDR, 1, 4 );
- rmesa->hw.eye.cmd[EYE_CMD_0] =
- cmdvec( RADEON_VS_EYE_VECTOR_ADDR, 1, 4 );
-
- for (i = 0 ; i < 5; i++) {
- rmesa->hw.mat[i].cmd[MAT_CMD_0] =
- cmdvec( RADEON_VS_MATRIX_0_ADDR + i*4, 1, 16);
- }
-
- for (i = 0 ; i < 8; i++) {
- rmesa->hw.lit[i].cmd[LIT_CMD_0] =
- cmdvec( RADEON_VS_LIGHT_AMBIENT_ADDR + i, 8, 24 );
- rmesa->hw.lit[i].cmd[LIT_CMD_1] =
- cmdscl( RADEON_SS_LIGHT_DCD_ADDR + i, 8, 6 );
- }
-
- for (i = 0 ; i < 6; i++) {
- rmesa->hw.ucp[i].cmd[UCP_CMD_0] =
- cmdvec( RADEON_VS_UCP_ADDR + i, 1, 4 );
- }
-
- rmesa->last_ReallyEnabled = -1;
-
- /* Initial Harware state:
- */
- rmesa->hw.ctx.cmd[CTX_PP_MISC] = (RADEON_ALPHA_TEST_PASS |
- RADEON_CHROMA_FUNC_FAIL |
- RADEON_CHROMA_KEY_NEAREST |
- RADEON_SHADOW_FUNC_EQUAL |
- RADEON_SHADOW_PASS_1 |
- RADEON_RIGHT_HAND_CUBE_OGL);
-
- rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] = (RADEON_FOG_VERTEX |
- RADEON_FOG_USE_DEPTH);
-
- rmesa->hw.ctx.cmd[CTX_RE_SOLID_COLOR] = 0x00000000;
-
- rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = (RADEON_COMB_FCN_ADD_CLAMP |
- RADEON_SRC_BLEND_GL_ONE |
- RADEON_DST_BLEND_GL_ZERO );
-
- rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] =
- rmesa->radeonScreen->depthOffset + rmesa->radeonScreen->fbLocation;
-
- rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] =
- ((rmesa->radeonScreen->depthPitch &
- RADEON_DEPTHPITCH_MASK) |
- RADEON_DEPTH_ENDIAN_NO_SWAP);
-
- if (rmesa->using_hyperz)
- rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] |= RADEON_DEPTH_HYPERZ;
-
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (depth_fmt |
- RADEON_Z_TEST_LESS |
- RADEON_STENCIL_TEST_ALWAYS |
- RADEON_STENCIL_FAIL_KEEP |
- RADEON_STENCIL_ZPASS_KEEP |
- RADEON_STENCIL_ZFAIL_KEEP |
- RADEON_Z_WRITE_ENABLE);
-
- if (rmesa->using_hyperz) {
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_COMPRESSION_ENABLE |
- RADEON_Z_DECOMPRESSION_ENABLE;
- if (rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL) {
- /* works for q3, but slight rendering errors with glxgears ? */
-/* rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
- /* need this otherwise get lots of lockups with q3 ??? */
- rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_FORCE_Z_DIRTY;
- }
- }
-
- rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (RADEON_SCISSOR_ENABLE |
- RADEON_ANTI_ALIAS_NONE);
-
- rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = (RADEON_PLANE_MASK_ENABLE |
- color_fmt |
- RADEON_ZBLOCK16);
-
- switch ( driQueryOptioni( &rmesa->optionCache, "dither_mode" ) ) {
- case DRI_CONF_DITHER_XERRORDIFFRESET:
- rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_INIT;
- break;
- case DRI_CONF_DITHER_ORDERED:
- rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_SCALE_DITHER_ENABLE;
- break;
- }
- if ( driQueryOptioni( &rmesa->optionCache, "round_mode" ) ==
- DRI_CONF_ROUND_ROUND )
- rmesa->state.color.roundEnable = RADEON_ROUND_ENABLE;
- else
- rmesa->state.color.roundEnable = 0;
- if ( driQueryOptioni (&rmesa->optionCache, "color_reduction" ) ==
- DRI_CONF_COLOR_REDUCTION_DITHER )
- rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_ENABLE;
- else
- rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->state.color.roundEnable;
-
- rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((rmesa->state.color.drawOffset +
- rmesa->radeonScreen->fbLocation)
- & RADEON_COLOROFFSET_MASK);
-
- rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((rmesa->state.color.drawPitch &
- RADEON_COLORPITCH_MASK) |
- RADEON_COLOR_ENDIAN_NO_SWAP);
- /* (fixed size) sarea is initialized to zero afaics so can omit version check. Phew! */
- if (rmesa->sarea->tiling_enabled) {
- rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= RADEON_COLOR_TILE_ENABLE;
- }
-
- rmesa->hw.set.cmd[SET_SE_CNTL] = (RADEON_FFACE_CULL_CCW |
- RADEON_BFACE_SOLID |
- RADEON_FFACE_SOLID |
-/* RADEON_BADVTX_CULL_DISABLE | */
- RADEON_FLAT_SHADE_VTX_LAST |
- RADEON_DIFFUSE_SHADE_GOURAUD |
- RADEON_ALPHA_SHADE_GOURAUD |
- RADEON_SPECULAR_SHADE_GOURAUD |
- RADEON_FOG_SHADE_GOURAUD |
- RADEON_VPORT_XY_XFORM_ENABLE |
- RADEON_VPORT_Z_XFORM_ENABLE |
- RADEON_VTX_PIX_CENTER_OGL |
- RADEON_ROUND_MODE_TRUNC |
- RADEON_ROUND_PREC_8TH_PIX);
-
- rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] =
-#ifdef MESA_BIG_ENDIAN
- RADEON_VC_32BIT_SWAP;
-#else
- RADEON_VC_NO_SWAP;
-#endif
-
- if (!(rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL)) {
- rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] |= RADEON_TCL_BYPASS;
- }
-
- rmesa->hw.set.cmd[SET_SE_COORDFMT] = (
- RADEON_VTX_W0_IS_NOT_1_OVER_W0 |
- RADEON_TEX1_W_ROUTING_USE_Q1);
-
-
- rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((1 << 16) | 0xffff);
-
- rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] =
- ((0 << RADEON_LINE_CURRENT_PTR_SHIFT) |
- (1 << RADEON_LINE_CURRENT_COUNT_SHIFT));
-
- rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (1 << 4);
-
- rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] =
- ((0x00 << RADEON_STENCIL_REF_SHIFT) |
- (0xff << RADEON_STENCIL_MASK_SHIFT) |
- (0xff << RADEON_STENCIL_WRITEMASK_SHIFT));
-
- rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = RADEON_ROP_COPY;
- rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = 0xffffffff;
-
- rmesa->hw.msc.cmd[MSC_RE_MISC] =
- ((0 << RADEON_STIPPLE_X_OFFSET_SHIFT) |
- (0 << RADEON_STIPPLE_Y_OFFSET_SHIFT) |
- RADEON_STIPPLE_BIG_BIT_ORDER);
-
- rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = 0x00000000;
- rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000;
- rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = 0x00000000;
- rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000;
- rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = 0x00000000;
- rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000;
-
- for ( i = 0 ; i < ctx->Const.MaxTextureUnits ; i++ ) {
- rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] = RADEON_BORDER_MODE_OGL;
- rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] =
- (RADEON_TXFORMAT_ENDIAN_NO_SWAP |
- RADEON_TXFORMAT_PERSPECTIVE_ENABLE |
- (i << 24) | /* This is one of RADEON_TXFORMAT_ST_ROUTE_STQ[012] */
- (2 << RADEON_TXFORMAT_WIDTH_SHIFT) |
- (2 << RADEON_TXFORMAT_HEIGHT_SHIFT));
-
- /* Initialize the texture offset to the start of the card texture heap */
- rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET] =
- rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
-
- rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0;
- rmesa->hw.tex[i].cmd[TEX_PP_TXCBLEND] =
- (RADEON_COLOR_ARG_A_ZERO |
- RADEON_COLOR_ARG_B_ZERO |
- RADEON_COLOR_ARG_C_CURRENT_COLOR |
- RADEON_BLEND_CTL_ADD |
- RADEON_SCALE_1X |
- RADEON_CLAMP_TX);
- rmesa->hw.tex[i].cmd[TEX_PP_TXABLEND] =
- (RADEON_ALPHA_ARG_A_ZERO |
- RADEON_ALPHA_ARG_B_ZERO |
- RADEON_ALPHA_ARG_C_CURRENT_ALPHA |
- RADEON_BLEND_CTL_ADD |
- RADEON_SCALE_1X |
- RADEON_CLAMP_TX);
- rmesa->hw.tex[i].cmd[TEX_PP_TFACTOR] = 0;
- }
-
- /* Can only add ST1 at the time of doing some multitex but can keep
- * it after that. Errors if DIFFUSE is missing.
- */
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] =
- (RADEON_TCL_VTX_Z0 |
- RADEON_TCL_VTX_W0 |
- RADEON_TCL_VTX_PK_DIFFUSE
- ); /* need to keep this uptodate */
-
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] =
- ( RADEON_TCL_COMPUTE_XYZW |
- (RADEON_TCL_TEX_INPUT_TEX_0 << RADEON_TCL_TEX_0_OUTPUT_SHIFT) |
- (RADEON_TCL_TEX_INPUT_TEX_1 << RADEON_TCL_TEX_1_OUTPUT_SHIFT) |
- (RADEON_TCL_TEX_INPUT_TEX_2 << RADEON_TCL_TEX_2_OUTPUT_SHIFT));
-
-
- /* XXX */
- rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_0] =
- ((MODEL << RADEON_MODELVIEW_0_SHIFT) |
- (MODEL_IT << RADEON_IT_MODELVIEW_0_SHIFT));
-
- rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_1] =
- ((MODEL_PROJ << RADEON_MODELPROJECT_0_SHIFT) |
- (TEXMAT_0 << RADEON_TEXMAT_0_SHIFT) |
- (TEXMAT_1 << RADEON_TEXMAT_1_SHIFT));
-
- rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] =
- (RADEON_UCP_IN_CLIP_SPACE |
- RADEON_CULL_FRONT_IS_CCW);
-
- rmesa->hw.tcl.cmd[TCL_TEXTURE_PROC_CTL] = 0;
-
- rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] =
- (RADEON_SPECULAR_LIGHTS |
- RADEON_DIFFUSE_SPECULAR_COMBINE |
- RADEON_LOCAL_LIGHT_VEC_GL |
- (RADEON_LM_SOURCE_STATE_MULT << RADEON_EMISSIVE_SOURCE_SHIFT) |
- (RADEON_LM_SOURCE_STATE_MULT << RADEON_AMBIENT_SOURCE_SHIFT) |
- (RADEON_LM_SOURCE_STATE_MULT << RADEON_DIFFUSE_SOURCE_SHIFT) |
- (RADEON_LM_SOURCE_STATE_MULT << RADEON_SPECULAR_SOURCE_SHIFT));
-
- for (i = 0 ; i < 8; i++) {
- struct gl_light *l = &ctx->Light.Light[i];
- GLenum p = GL_LIGHT0 + i;
- *(float *)&(rmesa->hw.lit[i].cmd[LIT_RANGE_CUTOFF]) = FLT_MAX;
-
- ctx->Driver.Lightfv( ctx, p, GL_AMBIENT, l->Ambient );
- ctx->Driver.Lightfv( ctx, p, GL_DIFFUSE, l->Diffuse );
- ctx->Driver.Lightfv( ctx, p, GL_SPECULAR, l->Specular );
- ctx->Driver.Lightfv( ctx, p, GL_POSITION, NULL );
- ctx->Driver.Lightfv( ctx, p, GL_SPOT_DIRECTION, NULL );
- ctx->Driver.Lightfv( ctx, p, GL_SPOT_EXPONENT, &l->SpotExponent );
- ctx->Driver.Lightfv( ctx, p, GL_SPOT_CUTOFF, &l->SpotCutoff );
- ctx->Driver.Lightfv( ctx, p, GL_CONSTANT_ATTENUATION,
- &l->ConstantAttenuation );
- ctx->Driver.Lightfv( ctx, p, GL_LINEAR_ATTENUATION,
- &l->LinearAttenuation );
- ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION,
- &l->QuadraticAttenuation );
- *(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0;
- }
-
- ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT,
- ctx->Light.Model.Ambient );
-
- TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange( ctx );
-
- for (i = 0 ; i < 6; i++) {
- ctx->Driver.ClipPlane( ctx, GL_CLIP_PLANE0 + i, NULL );
- }
-
- ctx->Driver.Fogfv( ctx, GL_FOG_MODE, NULL );
- ctx->Driver.Fogfv( ctx, GL_FOG_DENSITY, &ctx->Fog.Density );
- ctx->Driver.Fogfv( ctx, GL_FOG_START, &ctx->Fog.Start );
- ctx->Driver.Fogfv( ctx, GL_FOG_END, &ctx->Fog.End );
- ctx->Driver.Fogfv( ctx, GL_FOG_COLOR, ctx->Fog.Color );
- ctx->Driver.Fogfv( ctx, GL_FOG_COORDINATE_SOURCE_EXT, NULL );
-
- rmesa->hw.grd.cmd[GRD_VERT_GUARD_CLIP_ADJ] = IEEE_ONE;
- rmesa->hw.grd.cmd[GRD_VERT_GUARD_DISCARD_ADJ] = IEEE_ONE;
- rmesa->hw.grd.cmd[GRD_HORZ_GUARD_CLIP_ADJ] = IEEE_ONE;
- rmesa->hw.grd.cmd[GRD_HORZ_GUARD_DISCARD_ADJ] = IEEE_ONE;
-
- rmesa->hw.eye.cmd[EYE_X] = 0;
- rmesa->hw.eye.cmd[EYE_Y] = 0;
- rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE;
- rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE;
-
- rmesa->hw.all_dirty = GL_TRUE;
-}
diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_swtcl.c b/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_swtcl.c
deleted file mode 100644
index 924d4028d..000000000
--- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_swtcl.c
+++ /dev/null
@@ -1,983 +0,0 @@
-/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_swtcl.c,v 1.6 2003/05/06 23:52:08 daenzer Exp $ */
-/**************************************************************************
-
-Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
- VA Linux Systems Inc., Fremont, California.
-
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/*
- * Authors:
- * Keith Whitwell <keith@tungstengraphics.com>
- */
-
-#include "glheader.h"
-#include "mtypes.h"
-#include "colormac.h"
-#include "enums.h"
-#include "imports.h"
-#include "macros.h"
-
-#include "swrast_setup/swrast_setup.h"
-#include "math/m_translate.h"
-#include "tnl/tnl.h"
-#include "tnl/t_context.h"
-#include "tnl/t_pipeline.h"
-#include "tnl/t_vtx_api.h" /* for _tnl_FlushVertices */
-
-#include "radeon_context.h"
-#include "radeon_ioctl.h"
-#include "radeon_state.h"
-#include "radeon_swtcl.h"
-#include "radeon_tcl.h"
-
-
-static void flush_last_swtcl_prim( radeonContextPtr rmesa );
-
-/* R100: xyzw, c0, c1/fog, stq[0..2] = 4+1+1+3*3 = 15 right? */
-/* R200: xyzw, c0, c1/fog, strq[0..5] = 4+1+1+4*6 = 30 */
-#define RADEON_MAX_TNL_VERTEX_SIZE (15 * sizeof(GLfloat)) /* for mesa _tnl stage */
-
-/***********************************************************************
- * Initialization
- ***********************************************************************/
-
-#define EMIT_ATTR( ATTR, STYLE, F0 ) \
-do { \
- rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].attrib = (ATTR); \
- rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].format = (STYLE); \
- rmesa->swtcl.vertex_attr_count++; \
- fmt_0 |= F0; \
-} while (0)
-
-#define EMIT_PAD( N ) \
-do { \
- rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].attrib = 0; \
- rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].format = EMIT_PAD; \
- rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].offset = (N); \
- rmesa->swtcl.vertex_attr_count++; \
-} while (0)
-
-static GLuint radeon_cp_vc_frmts[3][2] =
-{
- { RADEON_CP_VC_FRMT_ST0, RADEON_CP_VC_FRMT_ST0 | RADEON_CP_VC_FRMT_Q0 },
- { RADEON_CP_VC_FRMT_ST1, RADEON_CP_VC_FRMT_ST1 | RADEON_CP_VC_FRMT_Q1 },
- { RADEON_CP_VC_FRMT_ST2, RADEON_CP_VC_FRMT_ST2 | RADEON_CP_VC_FRMT_Q2 },
-};
-
-static void radeonSetVertexFormat( GLcontext *ctx )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
- TNLcontext *tnl = TNL_CONTEXT(ctx);
- struct vertex_buffer *VB = &tnl->vb;
- GLuint index = tnl->render_inputs;
- int fmt_0 = 0;
- int offset = 0;
-
-
- /* Important:
- */
- if ( VB->NdcPtr != NULL ) {
- VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr;
- }
- else {
- VB->AttribPtr[VERT_ATTRIB_POS] = VB->ClipPtr;
- }
-
- assert( VB->AttribPtr[VERT_ATTRIB_POS] != NULL );
- rmesa->swtcl.vertex_attr_count = 0;
-
- /* EMIT_ATTR's must be in order as they tell t_vertex.c how to
- * build up a hardware vertex.
- */
- if ( !rmesa->swtcl.needproj ||
- (index & _TNL_BITS_TEX_ANY)) { /* for projtex */
- EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F,
- RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z | RADEON_CP_VC_FRMT_W0 );
- offset = 4;
- }
- else {
- EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_3F,
- RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z );
- offset = 3;
- }
-
- rmesa->swtcl.coloroffset = offset;
-#if MESA_LITTLE_ENDIAN
- EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_RGBA,
- RADEON_CP_VC_FRMT_PKCOLOR );
-#else
- EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_ABGR,
- RADEON_CP_VC_FRMT_PKCOLOR );
-#endif
- offset += 1;
-
- rmesa->swtcl.specoffset = 0;
- if (index & (_TNL_BIT_COLOR1|_TNL_BIT_FOG)) {
-
-#if MESA_LITTLE_ENDIAN
- if (index & _TNL_BIT_COLOR1) {
- rmesa->swtcl.specoffset = offset;
- EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_RGB,
- RADEON_CP_VC_FRMT_PKSPEC );
- }
- else {
- EMIT_PAD( 3 );
- }
-
- if (index & _TNL_BIT_FOG) {
- EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F,
- RADEON_CP_VC_FRMT_PKSPEC );
- }
- else {
- EMIT_PAD( 1 );
- }
-#else
- if (index & _TNL_BIT_FOG) {
- EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F,
- RADEON_CP_VC_FRMT_PKSPEC );
- }
- else {
- EMIT_PAD( 1 );
- }
-
- if (index & _TNL_BIT_COLOR1) {
- rmesa->swtcl.specoffset = offset;
- EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR,
- RADEON_CP_VC_FRMT_PKSPEC );
- }
- else {
- EMIT_PAD( 3 );
- }
-#endif
- }
-
- if (index & _TNL_BITS_TEX_ANY) {
- int i;
-
- for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
- if (index & _TNL_BIT_TEX(i)) {
- GLuint sz = VB->TexCoordPtr[i]->size;
-
- switch (sz) {
- case 1:
- case 2:
- case 3:
- EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_2F,
- radeon_cp_vc_frmts[i][0] );
- break;
- case 4:
- EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F_XYW,
- radeon_cp_vc_frmts[i][1] );
- break;
- default:
- continue;
- };
- }
- }
- }
-
- if ( rmesa->tnl_index != index ||
- fmt_0 != rmesa->swtcl.vertex_format) {
- RADEON_NEWPRIM(rmesa);
- rmesa->swtcl.vertex_format = fmt_0;
- rmesa->swtcl.vertex_size =
- _tnl_install_attrs( ctx,
- rmesa->swtcl.vertex_attrs,
- rmesa->swtcl.vertex_attr_count,
- NULL, 0 );
- rmesa->swtcl.vertex_size /= 4;
- rmesa->tnl_index = index;
- if (RADEON_DEBUG & DEBUG_VERTS)
- fprintf( stderr, "%s: vertex_size= %d floats\n",
- __FUNCTION__, rmesa->swtcl.vertex_size);
- }
-}
-
-
-static void radeonRenderStart( GLcontext *ctx )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
-
- radeonSetVertexFormat( ctx );
-
- if (rmesa->dma.flush != 0 &&
- rmesa->dma.flush != flush_last_swtcl_prim)
- rmesa->dma.flush( rmesa );
-}
-
-
-/**
- * Set vertex state for SW TCL. The primary purpose of this function is to
- * determine in advance whether or not the hardware can / should do the
- * projection divide or Mesa should do it.
- */
-void radeonChooseVertexState( GLcontext *ctx )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
- TNLcontext *tnl = TNL_CONTEXT(ctx);
-
- GLuint se_coord_fmt;
-
- /* We must ensure that we don't do _tnl_need_projected_coords while in a
- * rasterization fallback. As this function will be called again when we
- * leave a rasterization fallback, we can just skip it for now.
- */
- if (rmesa->Fallback != 0)
- return;
-
- /* HW perspective divide is a win, but tiny vertex formats are a
- * bigger one.
- */
-
- if ( ((tnl->render_inputs & (_TNL_BITS_TEX_ANY|_TNL_BIT_COLOR1) ) == 0)
- || (ctx->_TriangleCaps & (DD_TRI_LIGHT_TWOSIDE|DD_TRI_UNFILLED))) {
- rmesa->swtcl.needproj = GL_TRUE;
- se_coord_fmt = (RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
- RADEON_VTX_Z_PRE_MULT_1_OVER_W0 |
- RADEON_TEX1_W_ROUTING_USE_Q1);
- }
- else {
- rmesa->swtcl.needproj = GL_FALSE;
- se_coord_fmt = (RADEON_VTX_W0_IS_NOT_1_OVER_W0 |
- RADEON_TEX1_W_ROUTING_USE_Q1);
- }
-
- _tnl_need_projected_coords( ctx, rmesa->swtcl.needproj );
-
- if ( se_coord_fmt != rmesa->hw.set.cmd[SET_SE_COORDFMT] ) {
- RADEON_STATECHANGE( rmesa, set );
- rmesa->hw.set.cmd[SET_SE_COORDFMT] = se_coord_fmt;
- }
-}
-
-
-/* Flush vertices in the current dma region.
- */
-static void flush_last_swtcl_prim( radeonContextPtr rmesa )
-{
- if (RADEON_DEBUG & DEBUG_IOCTL)
- fprintf(stderr, "%s\n", __FUNCTION__);
-
- rmesa->dma.flush = NULL;
-
- if (rmesa->dma.current.buf) {
- struct radeon_dma_region *current = &rmesa->dma.current;
- GLuint current_offset = (rmesa->radeonScreen->gart_buffer_offset +
- current->buf->buf->idx * RADEON_BUFFER_SIZE +
- current->start);
-
- assert (!(rmesa->swtcl.hw_primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND));
-
- assert (current->start +
- rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 ==
- current->ptr);
-
- if (rmesa->dma.current.start != rmesa->dma.current.ptr) {
- radeonEnsureCmdBufSpace( rmesa, VERT_AOS_BUFSZ +
- rmesa->hw.max_state_size + VBUF_BUFSZ );
-
- radeonEmitVertexAOS( rmesa,
- rmesa->swtcl.vertex_size,
- current_offset);
-
- radeonEmitVbufPrim( rmesa,
- rmesa->swtcl.vertex_format,
- rmesa->swtcl.hw_primitive,
- rmesa->swtcl.numverts);
- }
-
- rmesa->swtcl.numverts = 0;
- current->start = current->ptr;
- }
-}
-
-
-/* Alloc space in the current dma region.
- */
-static __inline void *radeonAllocDmaLowVerts( radeonContextPtr rmesa,
- int nverts, int vsize )
-{
- GLuint bytes = vsize * nverts;
-
- if ( rmesa->dma.current.ptr + bytes > rmesa->dma.current.end )
- radeonRefillCurrentDmaRegion( rmesa );
-
- if (!rmesa->dma.flush) {
- rmesa->glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES;
- rmesa->dma.flush = flush_last_swtcl_prim;
- }
-
- assert( vsize == rmesa->swtcl.vertex_size * 4 );
- assert( rmesa->dma.flush == flush_last_swtcl_prim );
- assert (rmesa->dma.current.start +
- rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 ==
- rmesa->dma.current.ptr);
-
-
- {
- GLubyte *head = (GLubyte *)(rmesa->dma.current.address + rmesa->dma.current.ptr);
- rmesa->dma.current.ptr += bytes;
- rmesa->swtcl.numverts += nverts;
- return head;
- }
-
-}
-
-
-/*
- * Render unclipped vertex buffers by emitting vertices directly to
- * dma buffers. Use strip/fan hardware primitives where possible.
- * Try to simulate missing primitives with indexed vertices.
- */
-#define HAVE_POINTS 1
-#define HAVE_LINES 1
-#define HAVE_LINE_STRIPS 1
-#define HAVE_TRIANGLES 1
-#define HAVE_TRI_STRIPS 1
-#define HAVE_TRI_STRIP_1 0
-#define HAVE_TRI_FANS 1
-#define HAVE_QUADS 0
-#define HAVE_QUAD_STRIPS 0
-#define HAVE_POLYGONS 0
-/* \todo: is it possible to make "ELTS" work with t_vertex code ? */
-#define HAVE_ELTS 0
-
-static const GLuint hw_prim[GL_POLYGON+1] = {
- RADEON_CP_VC_CNTL_PRIM_TYPE_POINT,
- RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
- 0,
- RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP,
- RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
- RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP,
- RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN,
- 0,
- 0,
- 0
-};
-
-static __inline void radeonDmaPrimitive( radeonContextPtr rmesa, GLenum prim )
-{
- RADEON_NEWPRIM( rmesa );
- rmesa->swtcl.hw_primitive = hw_prim[prim];
- assert(rmesa->dma.current.ptr == rmesa->dma.current.start);
-}
-
-#define LOCAL_VARS radeonContextPtr rmesa = RADEON_CONTEXT(ctx)
-#define INIT( prim ) radeonDmaPrimitive( rmesa, prim )
-#define FLUSH() RADEON_NEWPRIM( rmesa )
-#define GET_CURRENT_VB_MAX_VERTS() \
- (((int)rmesa->dma.current.end - (int)rmesa->dma.current.ptr) / (rmesa->swtcl.vertex_size*4))
-#define GET_SUBSEQUENT_VB_MAX_VERTS() \
- ((RADEON_BUFFER_SIZE) / (rmesa->swtcl.vertex_size*4))
-#define ALLOC_VERTS( nr ) \
- radeonAllocDmaLowVerts( rmesa, nr, rmesa->swtcl.vertex_size * 4 )
-#define EMIT_VERTS( ctx, j, nr, buf ) \
- _tnl_emit_vertices_to_buffer(ctx, j, (j)+(nr), buf)
-
-#define TAG(x) radeon_dma_##x
-#include "tnl_dd/t_dd_dmatmp.h"
-
-
-/**********************************************************************/
-/* Render pipeline stage */
-/**********************************************************************/
-
-
-static GLboolean radeon_run_render( GLcontext *ctx,
- struct tnl_pipeline_stage *stage )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- TNLcontext *tnl = TNL_CONTEXT(ctx);
- struct vertex_buffer *VB = &tnl->vb;
- tnl_render_func *tab = TAG(render_tab_verts);
- GLuint i;
-
- if (rmesa->swtcl.indexed_verts.buf)
- RELEASE_ELT_VERTS();
-
- if (rmesa->swtcl.RenderIndex != 0 ||
- !radeon_dma_validate_render( ctx, VB ))
- return GL_TRUE;
-
- tnl->Driver.Render.Start( ctx );
-
- for (i = 0 ; i < VB->PrimitiveCount ; i++)
- {
- GLuint prim = VB->Primitive[i].mode;
- GLuint start = VB->Primitive[i].start;
- GLuint length = VB->Primitive[i].count;
-
- if (!length)
- continue;
-
- if (RADEON_DEBUG & DEBUG_PRIMS)
- fprintf(stderr, "radeon_render.c: prim %s %d..%d\n",
- _mesa_lookup_enum_by_nr(prim & PRIM_MODE_MASK),
- start, start+length);
-
- if (length)
- tab[prim & PRIM_MODE_MASK]( ctx, start, start + length, prim );
- }
-
- tnl->Driver.Render.Finish( ctx );
-
- return GL_FALSE; /* finished the pipe */
-}
-
-
-
-
-const struct tnl_pipeline_stage _radeon_render_stage =
-{
- "radeon render",
- NULL,
- NULL,
- NULL,
- NULL,
- radeon_run_render /* run */
-};
-
-
-/**************************************************************************/
-
-/* Radeon texture rectangle expects coords in 0..1 range, not 0..dimension
- * as in the extension spec. Need to translate here.
- *
- * Note that swrast expects 0..dimension, so if a fallback is active,
- * don't do anything. (Maybe need to configure swrast to match hw)
- */
-struct texrect_stage_data {
- GLvector4f texcoord[MAX_TEXTURE_UNITS];
-};
-
-#define TEXRECT_STAGE_DATA(stage) ((struct texrect_stage_data *)stage->privatePtr)
-
-
-static GLboolean run_texrect_stage( GLcontext *ctx,
- struct tnl_pipeline_stage *stage )
-{
- struct texrect_stage_data *store = TEXRECT_STAGE_DATA(stage);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- TNLcontext *tnl = TNL_CONTEXT(ctx);
- struct vertex_buffer *VB = &tnl->vb;
- GLuint i;
-
- if (rmesa->Fallback)
- return GL_TRUE;
-
- for (i = 0 ; i < ctx->Const.MaxTextureUnits ; i++) {
- if (ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_RECT_BIT) {
- struct gl_texture_object *texObj = ctx->Texture.Unit[i].CurrentRect;
- struct gl_texture_image *texImage = texObj->Image[0][texObj->BaseLevel];
- const GLfloat iw = 1.0/texImage->Width;
- const GLfloat ih = 1.0/texImage->Height;
- GLfloat *in = (GLfloat *)VB->TexCoordPtr[i]->data;
- GLint instride = VB->TexCoordPtr[i]->stride;
- GLfloat (*out)[4] = store->texcoord[i].data;
- GLint j;
-
- for (j = 0 ; j < VB->Count ; j++) {
- out[j][0] = in[0] * iw;
- out[j][1] = in[1] * ih;
- in = (GLfloat *)((GLubyte *)in + instride);
- }
-
- VB->AttribPtr[VERT_ATTRIB_TEX0+i] = VB->TexCoordPtr[i] = &store->texcoord[i];
- }
- }
-
- return GL_TRUE;
-}
-
-
-/* Called the first time stage->run() is invoked.
- */
-static GLboolean alloc_texrect_data( GLcontext *ctx,
- struct tnl_pipeline_stage *stage )
-{
- struct vertex_buffer *VB = &TNL_CONTEXT(ctx)->vb;
- struct texrect_stage_data *store;
- GLuint i;
-
- stage->privatePtr = CALLOC(sizeof(*store));
- store = TEXRECT_STAGE_DATA(stage);
- if (!store)
- return GL_FALSE;
-
- for (i = 0 ; i < ctx->Const.MaxTextureUnits ; i++)
- _mesa_vector4f_alloc( &store->texcoord[i], 0, VB->Size, 32 );
-
- return GL_TRUE;
-}
-
-static void free_texrect_data( struct tnl_pipeline_stage *stage )
-{
- struct texrect_stage_data *store = TEXRECT_STAGE_DATA(stage);
- GLuint i;
-
- if (store) {
- for (i = 0 ; i < MAX_TEXTURE_UNITS ; i++)
- if (store->texcoord[i].data)
- _mesa_vector4f_free( &store->texcoord[i] );
- FREE( store );
- stage->privatePtr = NULL;
- }
-}
-
-const struct tnl_pipeline_stage _radeon_texrect_stage =
-{
- "radeon texrect stage", /* name */
- NULL,
- alloc_texrect_data,
- free_texrect_data,
- NULL,
- run_texrect_stage
-};
-
-
-/**************************************************************************/
-
-
-static const GLuint reduced_hw_prim[GL_POLYGON+1] = {
- RADEON_CP_VC_CNTL_PRIM_TYPE_POINT,
- RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
- RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
- RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
- RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
- RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
- RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
- RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
- RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
- RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
-};
-
-static void radeonRasterPrimitive( GLcontext *ctx, GLuint hwprim );
-static void radeonRenderPrimitive( GLcontext *ctx, GLenum prim );
-static void radeonResetLineStipple( GLcontext *ctx );
-
-
-/***********************************************************************
- * Emit primitives as inline vertices *
- ***********************************************************************/
-
-#undef LOCAL_VARS
-#undef ALLOC_VERTS
-#define CTX_ARG radeonContextPtr rmesa
-#define GET_VERTEX_DWORDS() rmesa->swtcl.vertex_size
-#define ALLOC_VERTS( n, size ) radeonAllocDmaLowVerts( rmesa, n, (size) * 4 )
-#undef LOCAL_VARS
-#define LOCAL_VARS \
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx); \
- const char *radeonverts = (char *)rmesa->swtcl.verts;
-#define VERT(x) (radeonVertex *)(radeonverts + ((x) * (vertsize) * sizeof(int)))
-#define VERTEX radeonVertex
-#undef TAG
-#define TAG(x) radeon_##x
-#include "tnl_dd/t_dd_triemit.h"
-
-
-/***********************************************************************
- * Macros for t_dd_tritmp.h to draw basic primitives *
- ***********************************************************************/
-
-#define QUAD( a, b, c, d ) radeon_quad( rmesa, a, b, c, d )
-#define TRI( a, b, c ) radeon_triangle( rmesa, a, b, c )
-#define LINE( a, b ) radeon_line( rmesa, a, b )
-#define POINT( a ) radeon_point( rmesa, a )
-
-/***********************************************************************
- * Build render functions from dd templates *
- ***********************************************************************/
-
-#define RADEON_TWOSIDE_BIT 0x01
-#define RADEON_UNFILLED_BIT 0x02
-#define RADEON_MAX_TRIFUNC 0x08
-
-
-static struct {
- tnl_points_func points;
- tnl_line_func line;
- tnl_triangle_func triangle;
- tnl_quad_func quad;
-} rast_tab[RADEON_MAX_TRIFUNC];
-
-
-#define DO_FALLBACK 0
-#define DO_OFFSET 0
-#define DO_UNFILLED (IND & RADEON_UNFILLED_BIT)
-#define DO_TWOSIDE (IND & RADEON_TWOSIDE_BIT)
-#define DO_FLAT 0
-#define DO_TRI 1
-#define DO_QUAD 1
-#define DO_LINE 1
-#define DO_POINTS 1
-#define DO_FULL_QUAD 1
-
-#define HAVE_RGBA 1
-#define HAVE_SPEC 1
-#define HAVE_BACK_COLORS 0
-#define HAVE_HW_FLATSHADE 1
-#define TAB rast_tab
-
-#define DEPTH_SCALE 1.0
-#define UNFILLED_TRI unfilled_tri
-#define UNFILLED_QUAD unfilled_quad
-#define VERT_X(_v) _v->v.x
-#define VERT_Y(_v) _v->v.y
-#define VERT_Z(_v) _v->v.z
-#define AREA_IS_CCW( a ) (a < 0)
-#define GET_VERTEX(e) (rmesa->swtcl.verts + ((e) * rmesa->swtcl.vertex_size * sizeof(int)))
-
-#define VERT_SET_RGBA( v, c ) \
-do { \
- radeon_color_t *color = (radeon_color_t *)&((v)->ui[coloroffset]); \
- UNCLAMPED_FLOAT_TO_UBYTE(color->red, (c)[0]); \
- UNCLAMPED_FLOAT_TO_UBYTE(color->green, (c)[1]); \
- UNCLAMPED_FLOAT_TO_UBYTE(color->blue, (c)[2]); \
- UNCLAMPED_FLOAT_TO_UBYTE(color->alpha, (c)[3]); \
-} while (0)
-
-#define VERT_COPY_RGBA( v0, v1 ) v0->ui[coloroffset] = v1->ui[coloroffset]
-
-#define VERT_SET_SPEC( v, c ) \
-do { \
- if (specoffset) { \
- radeon_color_t *spec = (radeon_color_t *)&((v)->ui[specoffset]); \
- UNCLAMPED_FLOAT_TO_UBYTE(spec->red, (c)[0]); \
- UNCLAMPED_FLOAT_TO_UBYTE(spec->green, (c)[1]); \
- UNCLAMPED_FLOAT_TO_UBYTE(spec->blue, (c)[2]); \
- } \
-} while (0)
-#define VERT_COPY_SPEC( v0, v1 ) \
-do { \
- if (specoffset) { \
- radeon_color_t *spec0 = (radeon_color_t *)&((v0)->ui[specoffset]); \
- radeon_color_t *spec1 = (radeon_color_t *)&((v1)->ui[specoffset]); \
- spec0->red = spec1->red; \
- spec0->green = spec1->green; \
- spec0->blue = spec1->blue; \
- } \
-} while (0)
-
-/* These don't need LE32_TO_CPU() as they used to save and restore
- * colors which are already in the correct format.
- */
-#define VERT_SAVE_RGBA( idx ) color[idx] = v[idx]->ui[coloroffset]
-#define VERT_RESTORE_RGBA( idx ) v[idx]->ui[coloroffset] = color[idx]
-#define VERT_SAVE_SPEC( idx ) if (specoffset) spec[idx] = v[idx]->ui[specoffset]
-#define VERT_RESTORE_SPEC( idx ) if (specoffset) v[idx]->ui[specoffset] = spec[idx]
-
-#undef LOCAL_VARS
-#undef TAG
-#undef INIT
-
-#define LOCAL_VARS(n) \
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx); \
- GLuint color[n], spec[n]; \
- GLuint coloroffset = rmesa->swtcl.coloroffset; \
- GLuint specoffset = rmesa->swtcl.specoffset; \
- (void) color; (void) spec; (void) coloroffset; (void) specoffset;
-
-/***********************************************************************
- * Helpers for rendering unfilled primitives *
- ***********************************************************************/
-
-#define RASTERIZE(x) radeonRasterPrimitive( ctx, reduced_hw_prim[x] )
-#define RENDER_PRIMITIVE rmesa->swtcl.render_primitive
-#undef TAG
-#define TAG(x) x
-#include "tnl_dd/t_dd_unfilled.h"
-#undef IND
-
-
-/***********************************************************************
- * Generate GL render functions *
- ***********************************************************************/
-
-
-#define IND (0)
-#define TAG(x) x
-#include "tnl_dd/t_dd_tritmp.h"
-
-#define IND (RADEON_TWOSIDE_BIT)
-#define TAG(x) x##_twoside
-#include "tnl_dd/t_dd_tritmp.h"
-
-#define IND (RADEON_UNFILLED_BIT)
-#define TAG(x) x##_unfilled
-#include "tnl_dd/t_dd_tritmp.h"
-
-#define IND (RADEON_TWOSIDE_BIT|RADEON_UNFILLED_BIT)
-#define TAG(x) x##_twoside_unfilled
-#include "tnl_dd/t_dd_tritmp.h"
-
-
-static void init_rast_tab( void )
-{
- init();
- init_twoside();
- init_unfilled();
- init_twoside_unfilled();
-}
-
-/**********************************************************************/
-/* Render unclipped begin/end objects */
-/**********************************************************************/
-
-#define RENDER_POINTS( start, count ) \
- for ( ; start < count ; start++) \
- radeon_point( rmesa, VERT(start) )
-#define RENDER_LINE( v0, v1 ) \
- radeon_line( rmesa, VERT(v0), VERT(v1) )
-#define RENDER_TRI( v0, v1, v2 ) \
- radeon_triangle( rmesa, VERT(v0), VERT(v1), VERT(v2) )
-#define RENDER_QUAD( v0, v1, v2, v3 ) \
- radeon_quad( rmesa, VERT(v0), VERT(v1), VERT(v2), VERT(v3) )
-#undef INIT
-#define INIT(x) do { \
- radeonRenderPrimitive( ctx, x ); \
-} while (0)
-#undef LOCAL_VARS
-#define LOCAL_VARS \
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx); \
- const GLuint vertsize = rmesa->swtcl.vertex_size; \
- const char *radeonverts = (char *)rmesa->swtcl.verts; \
- const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts; \
- const GLboolean stipple = ctx->Line.StippleFlag; \
- (void) elt; (void) stipple;
-#define RESET_STIPPLE if ( stipple ) radeonResetLineStipple( ctx );
-#define RESET_OCCLUSION
-#define PRESERVE_VB_DEFS
-#define ELT(x) (x)
-#define TAG(x) radeon_##x##_verts
-#include "tnl/t_vb_rendertmp.h"
-#undef ELT
-#undef TAG
-#define TAG(x) radeon_##x##_elts
-#define ELT(x) elt[x]
-#include "tnl/t_vb_rendertmp.h"
-
-
-
-/**********************************************************************/
-/* Choose render functions */
-/**********************************************************************/
-
-void radeonChooseRenderState( GLcontext *ctx )
-{
- TNLcontext *tnl = TNL_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLuint index = 0;
- GLuint flags = ctx->_TriangleCaps;
-
- if (!rmesa->TclFallback || rmesa->Fallback)
- return;
-
- if (flags & DD_TRI_LIGHT_TWOSIDE) index |= RADEON_TWOSIDE_BIT;
- if (flags & DD_TRI_UNFILLED) index |= RADEON_UNFILLED_BIT;
-
- if (index != rmesa->swtcl.RenderIndex) {
- tnl->Driver.Render.Points = rast_tab[index].points;
- tnl->Driver.Render.Line = rast_tab[index].line;
- tnl->Driver.Render.ClippedLine = rast_tab[index].line;
- tnl->Driver.Render.Triangle = rast_tab[index].triangle;
- tnl->Driver.Render.Quad = rast_tab[index].quad;
-
- if (index == 0) {
- tnl->Driver.Render.PrimTabVerts = radeon_render_tab_verts;
- tnl->Driver.Render.PrimTabElts = radeon_render_tab_elts;
- tnl->Driver.Render.ClippedPolygon = radeon_fast_clipped_poly;
- } else {
- tnl->Driver.Render.PrimTabVerts = _tnl_render_tab_verts;
- tnl->Driver.Render.PrimTabElts = _tnl_render_tab_elts;
- tnl->Driver.Render.ClippedPolygon = _tnl_RenderClippedPolygon;
- }
-
- rmesa->swtcl.RenderIndex = index;
- }
-}
-
-
-/**********************************************************************/
-/* High level hooks for t_vb_render.c */
-/**********************************************************************/
-
-
-static void radeonRasterPrimitive( GLcontext *ctx, GLuint hwprim )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-
- if (rmesa->swtcl.hw_primitive != hwprim) {
- RADEON_NEWPRIM( rmesa );
- rmesa->swtcl.hw_primitive = hwprim;
- }
-}
-
-static void radeonRenderPrimitive( GLcontext *ctx, GLenum prim )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- rmesa->swtcl.render_primitive = prim;
- if (prim < GL_TRIANGLES || !(ctx->_TriangleCaps & DD_TRI_UNFILLED))
- radeonRasterPrimitive( ctx, reduced_hw_prim[prim] );
-}
-
-static void radeonRenderFinish( GLcontext *ctx )
-{
-}
-
-static void radeonResetLineStipple( GLcontext *ctx )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- RADEON_STATECHANGE( rmesa, lin );
-}
-
-
-/**********************************************************************/
-/* Transition to/from hardware rasterization. */
-/**********************************************************************/
-
-static const char * const fallbackStrings[] = {
- "Texture mode",
- "glDrawBuffer(GL_FRONT_AND_BACK)",
- "glEnable(GL_STENCIL) without hw stencil buffer",
- "glRenderMode(selection or feedback)",
- "glBlendEquation",
- "glBlendFunc",
- "RADEON_NO_RAST",
- "Mixing GL_CLAMP_TO_BORDER and GL_CLAMP (or GL_MIRROR_CLAMP_ATI)"
-};
-
-
-static const char *getFallbackString(GLuint bit)
-{
- int i = 0;
- while (bit > 1) {
- i++;
- bit >>= 1;
- }
- return fallbackStrings[i];
-}
-
-
-void radeonFallback( GLcontext *ctx, GLuint bit, GLboolean mode )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- TNLcontext *tnl = TNL_CONTEXT(ctx);
- GLuint oldfallback = rmesa->Fallback;
-
- if (mode) {
- rmesa->Fallback |= bit;
- if (oldfallback == 0) {
- RADEON_FIREVERTICES( rmesa );
- TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_TRUE );
- _swsetup_Wakeup( ctx );
- rmesa->swtcl.RenderIndex = ~0;
- if (RADEON_DEBUG & DEBUG_FALLBACKS) {
- fprintf(stderr, "Radeon begin rasterization fallback: 0x%x %s\n",
- bit, getFallbackString(bit));
- }
- }
- }
- else {
- rmesa->Fallback &= ~bit;
- if (oldfallback == bit) {
- _swrast_flush( ctx );
- tnl->Driver.Render.Start = radeonRenderStart;
- tnl->Driver.Render.PrimitiveNotify = radeonRenderPrimitive;
- tnl->Driver.Render.Finish = radeonRenderFinish;
-
- tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
- tnl->Driver.Render.CopyPV = _tnl_copy_pv;
- tnl->Driver.Render.Interp = _tnl_interp;
-
- tnl->Driver.Render.ResetLineStipple = radeonResetLineStipple;
- TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_FALSE );
- if (rmesa->TclFallback) {
- /* These are already done if rmesa->TclFallback goes to
- * zero above. But not if it doesn't (RADEON_NO_TCL for
- * example?)
- */
- radeonChooseVertexState( ctx );
- radeonChooseRenderState( ctx );
- }
- if (RADEON_DEBUG & DEBUG_FALLBACKS) {
- fprintf(stderr, "Radeon end rasterization fallback: 0x%x %s\n",
- bit, getFallbackString(bit));
- }
- }
- }
-}
-
-
-void radeonFlushVertices( GLcontext *ctx, GLuint flags )
-{
- _tnl_FlushVertices( ctx, flags );
-
- if (flags & FLUSH_STORED_VERTICES)
- RADEON_NEWPRIM( RADEON_CONTEXT( ctx ) );
-}
-
-/**********************************************************************/
-/* Initialization. */
-/**********************************************************************/
-
-void radeonInitSwtcl( GLcontext *ctx )
-{
- TNLcontext *tnl = TNL_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- static int firsttime = 1;
-
- if (firsttime) {
- init_rast_tab();
- firsttime = 0;
- }
-
- tnl->Driver.Render.Start = radeonRenderStart;
- tnl->Driver.Render.Finish = radeonRenderFinish;
- tnl->Driver.Render.PrimitiveNotify = radeonRenderPrimitive;
- tnl->Driver.Render.ResetLineStipple = radeonResetLineStipple;
- tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
- tnl->Driver.Render.CopyPV = _tnl_copy_pv;
- tnl->Driver.Render.Interp = _tnl_interp;
-
- _tnl_init_vertices( ctx, ctx->Const.MaxArrayLockSize + 12,
- RADEON_MAX_TNL_VERTEX_SIZE);
-
- rmesa->swtcl.verts = (GLubyte *)tnl->clipspace.vertex_buf;
- rmesa->swtcl.RenderIndex = ~0;
- rmesa->swtcl.render_primitive = GL_TRIANGLES;
- rmesa->swtcl.hw_primitive = 0;
-}
-
-
-void radeonDestroySwtcl( GLcontext *ctx )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-
- if (rmesa->swtcl.indexed_verts.buf)
- radeonReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts,
- __FUNCTION__ );
-}
diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_swtcl.h b/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_swtcl.h
deleted file mode 100644
index f95a52c0b..000000000
--- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_swtcl.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/* $XFree86$ */
-/**************************************************************************
-
-Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
- VA Linux Systems Inc., Fremont, California.
-
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining a
-copy of this software and associated documentation files (the "Software"),
-to deal in the Software without restriction, including without limitation
-on the rights to use, copy, modify, merge, publish, distribute, sub
-license, and/or sell copies of the Software, and to permit persons to whom
-the Software is furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice (including the next
-paragraph) shall be included in all copies or substantial portions of the
-Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
-ATI, VA LINUX SYSTEMS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
-DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/*
- * Authors:
- * Keith Whitwell <keith@tungstengraphics.com>
- *
- */
-
-#ifndef __RADEON_TRIS_H__
-#define __RADEON_TRIS_H__
-
-#include "mtypes.h"
-#include "swrast/swrast.h"
-#include "radeon_context.h"
-
-extern void radeonInitSwtcl( GLcontext *ctx );
-extern void radeonDestroySwtcl( GLcontext *ctx );
-
-extern void radeonFlushVertices( GLcontext *ctx, GLuint flags );
-extern void radeonChooseRenderState( GLcontext *ctx );
-extern void radeonChooseVertexState( GLcontext *ctx );
-
-extern void radeonCheckTexSizes( GLcontext *ctx );
-
-extern void radeonBuildVertices( GLcontext *ctx, GLuint start, GLuint count,
- GLuint newinputs );
-
-extern void radeonPrintSetupFlags(char *msg, GLuint flags );
-
-
-extern void radeon_emit_indexed_verts( GLcontext *ctx,
- GLuint start,
- GLuint count );
-
-extern void radeon_translate_vertex( GLcontext *ctx,
- const radeonVertex *src,
- SWvertex *dst );
-
-extern void radeon_print_vertex( GLcontext *ctx, const radeonVertex *v );
-
-
-#endif
diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_tcl.c b/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_tcl.c
deleted file mode 100644
index b13042d96..000000000
--- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_tcl.c
+++ /dev/null
@@ -1,489 +0,0 @@
-/* $XFree86$ */
-/**************************************************************************
-
-Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
- Tungsten Graphics Inc., Austin, Texas.
-
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/*
- * Authors:
- * Keith Whitwell <keith@tungstengraphics.com>
- */
-
-#include "glheader.h"
-#include "imports.h"
-#include "light.h"
-#include "mtypes.h"
-#include "enums.h"
-
-#include "array_cache/acache.h"
-#include "tnl/tnl.h"
-#include "tnl/t_pipeline.h"
-
-#include "radeon_context.h"
-#include "radeon_state.h"
-#include "radeon_ioctl.h"
-#include "radeon_tex.h"
-#include "radeon_tcl.h"
-#include "radeon_swtcl.h"
-#include "radeon_maos.h"
-
-
-
-/*
- * Render unclipped vertex buffers by emitting vertices directly to
- * dma buffers. Use strip/fan hardware primitives where possible.
- * Try to simulate missing primitives with indexed vertices.
- */
-#define HAVE_POINTS 1
-#define HAVE_LINES 1
-#define HAVE_LINE_LOOP 0
-#define HAVE_LINE_STRIPS 1
-#define HAVE_TRIANGLES 1
-#define HAVE_TRI_STRIPS 1
-#define HAVE_TRI_STRIP_1 0
-#define HAVE_TRI_FANS 1
-#define HAVE_QUADS 0
-#define HAVE_QUAD_STRIPS 0
-#define HAVE_POLYGONS 1
-#define HAVE_ELTS 1
-
-
-#define HW_POINTS RADEON_CP_VC_CNTL_PRIM_TYPE_POINT
-#define HW_LINES RADEON_CP_VC_CNTL_PRIM_TYPE_LINE
-#define HW_LINE_LOOP 0
-#define HW_LINE_STRIP RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP
-#define HW_TRIANGLES RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
-#define HW_TRIANGLE_STRIP_0 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP
-#define HW_TRIANGLE_STRIP_1 0
-#define HW_TRIANGLE_FAN RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN
-#define HW_QUADS 0
-#define HW_QUAD_STRIP 0
-#define HW_POLYGON RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN
-
-
-static GLboolean discrete_prim[0x10] = {
- 0, /* 0 none */
- 1, /* 1 points */
- 1, /* 2 lines */
- 0, /* 3 line_strip */
- 1, /* 4 tri_list */
- 0, /* 5 tri_fan */
- 0, /* 6 tri_type2 */
- 1, /* 7 rect list (unused) */
- 1, /* 8 3vert point */
- 1, /* 9 3vert line */
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
-};
-
-
-#define LOCAL_VARS radeonContextPtr rmesa = RADEON_CONTEXT(ctx)
-#define ELT_TYPE GLushort
-
-#define ELT_INIT(prim, hw_prim) \
- radeonTclPrimitive( ctx, prim, hw_prim | RADEON_CP_VC_CNTL_PRIM_WALK_IND )
-
-#define GET_MESA_ELTS() rmesa->tcl.Elts
-
-
-/* Don't really know how many elts will fit in what's left of cmdbuf,
- * as there is state to emit, etc:
- */
-
-/* Testing on isosurf shows a maximum around here. Don't know if it's
- * the card or driver or kernel module that is causing the behaviour.
- */
-#define GET_MAX_HW_ELTS() 300
-
-
-#define RESET_STIPPLE() do { \
- RADEON_STATECHANGE( rmesa, lin ); \
- radeonEmitState( rmesa ); \
-} while (0)
-
-#define AUTO_STIPPLE( mode ) do { \
- RADEON_STATECHANGE( rmesa, lin ); \
- if (mode) \
- rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] |= \
- RADEON_LINE_PATTERN_AUTO_RESET; \
- else \
- rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] &= \
- ~RADEON_LINE_PATTERN_AUTO_RESET; \
- radeonEmitState( rmesa ); \
-} while (0)
-
-
-
-#define ALLOC_ELTS(nr) radeonAllocElts( rmesa, nr )
-
-static GLushort *radeonAllocElts( radeonContextPtr rmesa, GLuint nr )
-{
- if (rmesa->dma.flush)
- rmesa->dma.flush( rmesa );
-
- radeonEnsureCmdBufSpace(rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) +
- rmesa->hw.max_state_size + ELTS_BUFSZ(nr));
-
- radeonEmitAOS( rmesa,
- rmesa->tcl.aos_components,
- rmesa->tcl.nr_aos_components, 0 );
-
- return radeonAllocEltsOpenEnded( rmesa,
- rmesa->tcl.vertex_format,
- rmesa->tcl.hw_primitive, nr );
-}
-
-#define CLOSE_ELTS() RADEON_NEWPRIM( rmesa )
-
-
-
-/* TODO: Try to extend existing primitive if both are identical,
- * discrete and there are no intervening state changes. (Somewhat
- * duplicates changes to DrawArrays code)
- */
-static void radeonEmitPrim( GLcontext *ctx,
- GLenum prim,
- GLuint hwprim,
- GLuint start,
- GLuint count)
-{
- radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
- radeonTclPrimitive( ctx, prim, hwprim );
-
- radeonEnsureCmdBufSpace( rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) +
- rmesa->hw.max_state_size + VBUF_BUFSZ );
-
- radeonEmitAOS( rmesa,
- rmesa->tcl.aos_components,
- rmesa->tcl.nr_aos_components,
- start );
-
- /* Why couldn't this packet have taken an offset param?
- */
- radeonEmitVbufPrim( rmesa,
- rmesa->tcl.vertex_format,
- rmesa->tcl.hw_primitive,
- count - start );
-}
-
-#define EMIT_PRIM( ctx, prim, hwprim, start, count ) do { \
- radeonEmitPrim( ctx, prim, hwprim, start, count ); \
- (void) rmesa; } while (0)
-
-/* Try & join small primitives
- */
-#if 0
-#define PREFER_DISCRETE_ELT_PRIM( NR, PRIM ) 0
-#else
-#define PREFER_DISCRETE_ELT_PRIM( NR, PRIM ) \
- ((NR) < 20 || \
- ((NR) < 40 && \
- rmesa->tcl.hw_primitive == (PRIM| \
- RADEON_CP_VC_CNTL_PRIM_WALK_IND| \
- RADEON_CP_VC_CNTL_TCL_ENABLE)))
-#endif
-
-#ifdef MESA_BIG_ENDIAN
-/* We could do without (most of) this ugliness if dest was always 32 bit word aligned... */
-#define EMIT_ELT(dest, offset, x) do { \
- int off = offset + ( ( (GLuint)dest & 0x2 ) >> 1 ); \
- GLushort *des = (GLushort *)( (GLuint)dest & ~0x2 ); \
- (des)[ off + 1 - 2 * ( off & 1 ) ] = (GLushort)(x); \
- (void)rmesa; } while (0)
-#else
-#define EMIT_ELT(dest, offset, x) do { \
- (dest)[offset] = (GLushort) (x); \
- (void)rmesa; } while (0)
-#endif
-
-#define EMIT_TWO_ELTS(dest, offset, x, y) *(GLuint *)(dest+offset) = ((y)<<16)|(x);
-
-
-
-#define TAG(x) tcl_##x
-#include "tnl_dd/t_dd_dmatmp2.h"
-
-/**********************************************************************/
-/* External entrypoints */
-/**********************************************************************/
-
-void radeonEmitPrimitive( GLcontext *ctx,
- GLuint first,
- GLuint last,
- GLuint flags )
-{
- tcl_render_tab_verts[flags&PRIM_MODE_MASK]( ctx, first, last, flags );
-}
-
-void radeonEmitEltPrimitive( GLcontext *ctx,
- GLuint first,
- GLuint last,
- GLuint flags )
-{
- tcl_render_tab_elts[flags&PRIM_MODE_MASK]( ctx, first, last, flags );
-}
-
-void radeonTclPrimitive( GLcontext *ctx,
- GLenum prim,
- int hw_prim )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLuint se_cntl;
- GLuint newprim = hw_prim | RADEON_CP_VC_CNTL_TCL_ENABLE;
-
- if (newprim != rmesa->tcl.hw_primitive ||
- !discrete_prim[hw_prim&0xf]) {
- RADEON_NEWPRIM( rmesa );
- rmesa->tcl.hw_primitive = newprim;
- }
-
- se_cntl = rmesa->hw.set.cmd[SET_SE_CNTL];
- se_cntl &= ~RADEON_FLAT_SHADE_VTX_LAST;
-
- if (prim == GL_POLYGON && (ctx->_TriangleCaps & DD_FLATSHADE))
- se_cntl |= RADEON_FLAT_SHADE_VTX_0;
- else
- se_cntl |= RADEON_FLAT_SHADE_VTX_LAST;
-
- if (se_cntl != rmesa->hw.set.cmd[SET_SE_CNTL]) {
- RADEON_STATECHANGE( rmesa, set );
- rmesa->hw.set.cmd[SET_SE_CNTL] = se_cntl;
- }
-}
-
-
-/**********************************************************************/
-/* Render pipeline stage */
-/**********************************************************************/
-
-
-/* TCL render.
- */
-static GLboolean radeon_run_tcl_render( GLcontext *ctx,
- struct tnl_pipeline_stage *stage )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- TNLcontext *tnl = TNL_CONTEXT(ctx);
- struct vertex_buffer *VB = &tnl->vb;
- GLuint inputs = VERT_BIT_POS | VERT_BIT_COLOR0;
- GLuint i;
-
- /* TODO: separate this from the swtnl pipeline
- */
- if (rmesa->TclFallback)
- return GL_TRUE; /* fallback to software t&l */
-
- if (VB->Count == 0)
- return GL_FALSE;
-
- /* NOTE: inputs != tnl->render_inputs - these are the untransformed
- * inputs.
- */
- if (ctx->Light.Enabled) {
- inputs |= VERT_BIT_NORMAL;
- if (ctx->_TriangleCaps & DD_SEPARATE_SPECULAR) {
- inputs |= VERT_BIT_COLOR1;
- }
- }
-
- if ( ctx->Fog.FogCoordinateSource == GL_FOG_COORD ) {
- inputs |= VERT_BIT_FOG;
- }
-
- for (i = 0 ; i < ctx->Const.MaxTextureUnits; i++) {
- if (ctx->Texture.Unit[i]._ReallyEnabled) {
- if (rmesa->TexGenNeedNormals[i]) {
- inputs |= VERT_BIT_NORMAL;
- }
- inputs |= VERT_BIT_TEX(i);
- }
- }
-
- radeonReleaseArrays( ctx, ~0 );
- radeonEmitArrays( ctx, inputs );
-
- rmesa->tcl.Elts = VB->Elts;
-
- for (i = 0 ; i < VB->PrimitiveCount ; i++)
- {
- GLuint prim = VB->Primitive[i].mode;
- GLuint start = VB->Primitive[i].start;
- GLuint length = VB->Primitive[i].count;
-
- if (!length)
- continue;
-
- if (rmesa->tcl.Elts)
- radeonEmitEltPrimitive( ctx, start, start+length, prim );
- else
- radeonEmitPrimitive( ctx, start, start+length, prim );
- }
-
- return GL_FALSE; /* finished the pipe */
-}
-
-
-
-/* Initial state for tcl stage.
- */
-const struct tnl_pipeline_stage _radeon_tcl_stage =
-{
- "radeon render",
- NULL,
- NULL,
- NULL,
- NULL,
- radeon_run_tcl_render /* run */
-};
-
-
-
-/**********************************************************************/
-/* Validate state at pipeline start */
-/**********************************************************************/
-
-
-/*-----------------------------------------------------------------------
- * Manage TCL fallbacks
- */
-
-
-static void transition_to_swtnl( GLcontext *ctx )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- TNLcontext *tnl = TNL_CONTEXT(ctx);
- GLuint se_cntl;
-
- RADEON_NEWPRIM( rmesa );
- rmesa->swtcl.vertex_format = 0;
-
- radeonChooseVertexState( ctx );
- radeonChooseRenderState( ctx );
-
- _mesa_validate_all_lighting_tables( ctx );
-
- tnl->Driver.NotifyMaterialChange =
- _mesa_validate_all_lighting_tables;
-
- radeonReleaseArrays( ctx, ~0 );
-
- se_cntl = rmesa->hw.set.cmd[SET_SE_CNTL];
- se_cntl |= RADEON_FLAT_SHADE_VTX_LAST;
-
- if (se_cntl != rmesa->hw.set.cmd[SET_SE_CNTL]) {
- RADEON_STATECHANGE( rmesa, set );
- rmesa->hw.set.cmd[SET_SE_CNTL] = se_cntl;
- }
-}
-
-
-static void transition_to_hwtnl( GLcontext *ctx )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- TNLcontext *tnl = TNL_CONTEXT(ctx);
- GLuint se_coord_fmt = (RADEON_VTX_W0_IS_NOT_1_OVER_W0 |
- RADEON_TEX1_W_ROUTING_USE_Q1);
-
- if ( se_coord_fmt != rmesa->hw.set.cmd[SET_SE_COORDFMT] ) {
- RADEON_STATECHANGE( rmesa, set );
- rmesa->hw.set.cmd[SET_SE_COORDFMT] = se_coord_fmt;
- _tnl_need_projected_coords( ctx, GL_FALSE );
- }
-
- radeonUpdateMaterial( ctx );
-
- tnl->Driver.NotifyMaterialChange = radeonUpdateMaterial;
-
- if ( rmesa->dma.flush )
- rmesa->dma.flush( rmesa );
-
- rmesa->dma.flush = NULL;
- rmesa->swtcl.vertex_format = 0;
-
- if (rmesa->swtcl.indexed_verts.buf)
- radeonReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts,
- __FUNCTION__ );
-
- if (RADEON_DEBUG & DEBUG_FALLBACKS)
- fprintf(stderr, "Radeon end tcl fallback\n");
-}
-
-static char *fallbackStrings[] = {
- "Rasterization fallback",
- "Unfilled triangles",
- "Twosided lighting, differing materials",
- "Materials in VB (maybe between begin/end)",
- "Texgen unit 0",
- "Texgen unit 1",
- "Texgen unit 2",
- "User disable",
- "texture rectangle unit 0",
- "texture rectangle unit 1",
- "texture rectangle unit 2"
-};
-
-
-static char *getFallbackString(GLuint bit)
-{
- int i = 0;
- while (bit > 1) {
- i++;
- bit >>= 1;
- }
- return fallbackStrings[i];
-}
-
-
-
-void radeonTclFallback( GLcontext *ctx, GLuint bit, GLboolean mode )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLuint oldfallback = rmesa->TclFallback;
-
- if (mode) {
- rmesa->TclFallback |= bit;
- if (oldfallback == 0) {
- if (RADEON_DEBUG & DEBUG_FALLBACKS)
- fprintf(stderr, "Radeon begin tcl fallback %s\n",
- getFallbackString( bit ));
- transition_to_swtnl( ctx );
- }
- }
- else {
- rmesa->TclFallback &= ~bit;
- if (oldfallback == bit) {
- if (RADEON_DEBUG & DEBUG_FALLBACKS)
- fprintf(stderr, "Radeon end tcl fallback %s\n",
- getFallbackString( bit ));
- transition_to_hwtnl( ctx );
- }
- }
-}
diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_tcl.h b/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_tcl.h
deleted file mode 100644
index e292d2303..000000000
--- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_tcl.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_tcl.h,v 1.2 2003/02/08 21:26:45 dawes Exp $ */
-/**************************************************************************
-
-Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
- Tungsten Grahpics Inc., Austin, Texas.
-
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/*
- * Authors:
- * Keith Whitwell <keith@tungstengraphics.com>
- *
- */
-
-#ifndef __RADEON_TCL_H__
-#define __RADEON_TCL_H__
-
-#include "radeon_context.h"
-
-extern void radeonTclPrimitive( GLcontext *ctx, GLenum prim, int hw_prim );
-extern void radeonEmitEltPrimitive( GLcontext *ctx, GLuint first, GLuint last,
- GLuint flags );
-extern void radeonEmitPrimitive( GLcontext *ctx, GLuint first, GLuint last,
- GLuint flags );
-
-extern void radeonTclFallback( GLcontext *ctx, GLuint bit, GLboolean mode );
-
-#define RADEON_TCL_FALLBACK_RASTER 0x1 /* rasterization */
-#define RADEON_TCL_FALLBACK_UNFILLED 0x2 /* unfilled tris */
-#define RADEON_TCL_FALLBACK_LIGHT_TWOSIDE 0x4 /* twoside tris */
-#define RADEON_TCL_FALLBACK_MATERIAL 0x8 /* material in vb */
-#define RADEON_TCL_FALLBACK_TEXGEN_0 0x10 /* texgen, unit 0 */
-#define RADEON_TCL_FALLBACK_TEXGEN_1 0x20 /* texgen, unit 1 */
-#define RADEON_TCL_FALLBACK_TEXGEN_2 0x40 /* texgen, unit 2 */
-#define RADEON_TCL_FALLBACK_TCL_DISABLE 0x80 /* user disable */
-#define RADEON_TCL_FALLBACK_TEXRECT_0 0x100 /* texture rectangle */
-#define RADEON_TCL_FALLBACK_TEXRECT_1 0x200 /* texture rectangle */
-#define RADEON_TCL_FALLBACK_TEXRECT_2 0x400 /* texture rectangle */
-
-#define RADEON_MAX_TCL_VERTSIZE (15*4)
-
-#define TCL_FALLBACK( ctx, bit, mode ) radeonTclFallback( ctx, bit, mode )
-
-#endif
diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_tex.c b/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_tex.c
deleted file mode 100644
index c466af868..000000000
--- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_tex.c
+++ /dev/null
@@ -1,866 +0,0 @@
-/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_tex.c,v 1.6 2002/09/16 18:05:20 eich Exp $ */
-/*
-Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
- VA Linux Systems Inc., Fremont, California.
-
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-/*
- * Authors:
- * Gareth Hughes <gareth@valinux.com>
- * Brian Paul <brianp@valinux.com>
- */
-
-#include "glheader.h"
-#include "imports.h"
-#include "colormac.h"
-#include "context.h"
-#include "enums.h"
-#include "image.h"
-#include "simple_list.h"
-#include "texformat.h"
-#include "texstore.h"
-#include "teximage.h"
-#include "texobj.h"
-
-
-#include "radeon_context.h"
-#include "radeon_state.h"
-#include "radeon_ioctl.h"
-#include "radeon_swtcl.h"
-#include "radeon_tex.h"
-
-#include "xmlpool.h"
-
-
-
-/**
- * Set the texture wrap modes.
- *
- * \param t Texture object whose wrap modes are to be set
- * \param swrap Wrap mode for the \a s texture coordinate
- * \param twrap Wrap mode for the \a t texture coordinate
- */
-
-static void radeonSetTexWrap( radeonTexObjPtr t, GLenum swrap, GLenum twrap )
-{
- GLboolean is_clamp = GL_FALSE;
- GLboolean is_clamp_to_border = GL_FALSE;
-
- t->pp_txfilter &= ~(RADEON_CLAMP_S_MASK | RADEON_CLAMP_T_MASK | RADEON_BORDER_MODE_D3D);
-
- switch ( swrap ) {
- case GL_REPEAT:
- t->pp_txfilter |= RADEON_CLAMP_S_WRAP;
- break;
- case GL_CLAMP:
- t->pp_txfilter |= RADEON_CLAMP_S_CLAMP_GL;
- is_clamp = GL_TRUE;
- break;
- case GL_CLAMP_TO_EDGE:
- t->pp_txfilter |= RADEON_CLAMP_S_CLAMP_LAST;
- break;
- case GL_CLAMP_TO_BORDER:
- t->pp_txfilter |= RADEON_CLAMP_S_CLAMP_GL;
- is_clamp_to_border = GL_TRUE;
- break;
- case GL_MIRRORED_REPEAT:
- t->pp_txfilter |= RADEON_CLAMP_S_MIRROR;
- break;
- case GL_MIRROR_CLAMP_EXT:
- t->pp_txfilter |= RADEON_CLAMP_S_MIRROR_CLAMP_GL;
- is_clamp = GL_TRUE;
- break;
- case GL_MIRROR_CLAMP_TO_EDGE_EXT:
- t->pp_txfilter |= RADEON_CLAMP_S_MIRROR_CLAMP_LAST;
- break;
- case GL_MIRROR_CLAMP_TO_BORDER_EXT:
- t->pp_txfilter |= RADEON_CLAMP_S_MIRROR_CLAMP_GL;
- is_clamp_to_border = GL_TRUE;
- break;
- default:
- _mesa_problem(NULL, "bad S wrap mode in %s", __FUNCTION__);
- }
-
- switch ( twrap ) {
- case GL_REPEAT:
- t->pp_txfilter |= RADEON_CLAMP_T_WRAP;
- break;
- case GL_CLAMP:
- t->pp_txfilter |= RADEON_CLAMP_T_CLAMP_GL;
- is_clamp = GL_TRUE;
- break;
- case GL_CLAMP_TO_EDGE:
- t->pp_txfilter |= RADEON_CLAMP_T_CLAMP_LAST;
- break;
- case GL_CLAMP_TO_BORDER:
- t->pp_txfilter |= RADEON_CLAMP_T_CLAMP_GL;
- is_clamp_to_border = GL_TRUE;
- break;
- case GL_MIRRORED_REPEAT:
- t->pp_txfilter |= RADEON_CLAMP_T_MIRROR;
- break;
- case GL_MIRROR_CLAMP_EXT:
- t->pp_txfilter |= RADEON_CLAMP_T_MIRROR_CLAMP_GL;
- is_clamp = GL_TRUE;
- break;
- case GL_MIRROR_CLAMP_TO_EDGE_EXT:
- t->pp_txfilter |= RADEON_CLAMP_T_MIRROR_CLAMP_LAST;
- break;
- case GL_MIRROR_CLAMP_TO_BORDER_EXT:
- t->pp_txfilter |= RADEON_CLAMP_T_MIRROR_CLAMP_GL;
- is_clamp_to_border = GL_TRUE;
- break;
- default:
- _mesa_problem(NULL, "bad T wrap mode in %s", __FUNCTION__);
- }
-
- if ( is_clamp_to_border ) {
- t->pp_txfilter |= RADEON_BORDER_MODE_D3D;
- }
-
- t->border_fallback = (is_clamp && is_clamp_to_border);
-}
-
-static void radeonSetTexMaxAnisotropy( radeonTexObjPtr t, GLfloat max )
-{
- t->pp_txfilter &= ~RADEON_MAX_ANISO_MASK;
-
- if ( max == 1.0 ) {
- t->pp_txfilter |= RADEON_MAX_ANISO_1_TO_1;
- } else if ( max <= 2.0 ) {
- t->pp_txfilter |= RADEON_MAX_ANISO_2_TO_1;
- } else if ( max <= 4.0 ) {
- t->pp_txfilter |= RADEON_MAX_ANISO_4_TO_1;
- } else if ( max <= 8.0 ) {
- t->pp_txfilter |= RADEON_MAX_ANISO_8_TO_1;
- } else {
- t->pp_txfilter |= RADEON_MAX_ANISO_16_TO_1;
- }
-}
-
-/**
- * Set the texture magnification and minification modes.
- *
- * \param t Texture whose filter modes are to be set
- * \param minf Texture minification mode
- * \param magf Texture magnification mode
- */
-
-static void radeonSetTexFilter( radeonTexObjPtr t, GLenum minf, GLenum magf )
-{
- GLuint anisotropy = (t->pp_txfilter & RADEON_MAX_ANISO_MASK);
-
- t->pp_txfilter &= ~(RADEON_MIN_FILTER_MASK | RADEON_MAG_FILTER_MASK);
-
- if ( anisotropy == RADEON_MAX_ANISO_1_TO_1 ) {
- switch ( minf ) {
- case GL_NEAREST:
- t->pp_txfilter |= RADEON_MIN_FILTER_NEAREST;
- break;
- case GL_LINEAR:
- t->pp_txfilter |= RADEON_MIN_FILTER_LINEAR;
- break;
- case GL_NEAREST_MIPMAP_NEAREST:
- t->pp_txfilter |= RADEON_MIN_FILTER_NEAREST_MIP_NEAREST;
- break;
- case GL_NEAREST_MIPMAP_LINEAR:
- t->pp_txfilter |= RADEON_MIN_FILTER_LINEAR_MIP_NEAREST;
- break;
- case GL_LINEAR_MIPMAP_NEAREST:
- t->pp_txfilter |= RADEON_MIN_FILTER_NEAREST_MIP_LINEAR;
- break;
- case GL_LINEAR_MIPMAP_LINEAR:
- t->pp_txfilter |= RADEON_MIN_FILTER_LINEAR_MIP_LINEAR;
- break;
- }
- } else {
- switch ( minf ) {
- case GL_NEAREST:
- t->pp_txfilter |= RADEON_MIN_FILTER_ANISO_NEAREST;
- break;
- case GL_LINEAR:
- t->pp_txfilter |= RADEON_MIN_FILTER_ANISO_LINEAR;
- break;
- case GL_NEAREST_MIPMAP_NEAREST:
- case GL_LINEAR_MIPMAP_NEAREST:
- t->pp_txfilter |= RADEON_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST;
- break;
- case GL_NEAREST_MIPMAP_LINEAR:
- case GL_LINEAR_MIPMAP_LINEAR:
- t->pp_txfilter |= RADEON_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR;
- break;
- }
- }
-
- switch ( magf ) {
- case GL_NEAREST:
- t->pp_txfilter |= RADEON_MAG_FILTER_NEAREST;
- break;
- case GL_LINEAR:
- t->pp_txfilter |= RADEON_MAG_FILTER_LINEAR;
- break;
- }
-}
-
-static void radeonSetTexBorderColor( radeonTexObjPtr t, GLubyte c[4] )
-{
- t->pp_border_color = radeonPackColor( 4, c[0], c[1], c[2], c[3] );
-}
-
-
-/**
- * Allocate space for and load the mesa images into the texture memory block.
- * This will happen before drawing with a new texture, or drawing with a
- * texture after it was swapped out or teximaged again.
- */
-
-static radeonTexObjPtr radeonAllocTexObj( struct gl_texture_object *texObj )
-{
- radeonTexObjPtr t;
-
- t = CALLOC_STRUCT( radeon_tex_obj );
- texObj->DriverData = t;
- if ( t != NULL ) {
- if ( RADEON_DEBUG & DEBUG_TEXTURE ) {
- fprintf( stderr, "%s( %p, %p )\n", __FUNCTION__, (void *)texObj, (void *)t );
- }
-
- /* Initialize non-image-dependent parts of the state:
- */
- t->base.tObj = texObj;
- t->border_fallback = GL_FALSE;
-
- t->pp_txfilter = RADEON_BORDER_MODE_OGL;
- t->pp_txformat = (RADEON_TXFORMAT_ENDIAN_NO_SWAP |
- RADEON_TXFORMAT_PERSPECTIVE_ENABLE);
-
- make_empty_list( & t->base );
-
- radeonSetTexWrap( t, texObj->WrapS, texObj->WrapT );
- radeonSetTexMaxAnisotropy( t, texObj->MaxAnisotropy );
- radeonSetTexFilter( t, texObj->MinFilter, texObj->MagFilter );
- radeonSetTexBorderColor( t, texObj->_BorderChan );
- }
-
- return t;
-}
-
-
-static const struct gl_texture_format *
-radeonChooseTextureFormat( GLcontext *ctx, GLint internalFormat,
- GLenum format, GLenum type )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- const GLboolean do32bpt =
- ( rmesa->texture_depth == DRI_CONF_TEXTURE_DEPTH_32 );
- const GLboolean force16bpt =
- ( rmesa->texture_depth == DRI_CONF_TEXTURE_DEPTH_FORCE_16 );
- (void) format;
-
- switch ( internalFormat ) {
- case 4:
- case GL_RGBA:
- case GL_COMPRESSED_RGBA:
- switch ( type ) {
- case GL_UNSIGNED_INT_10_10_10_2:
- case GL_UNSIGNED_INT_2_10_10_10_REV:
- return do32bpt ? _dri_texformat_argb8888 : _dri_texformat_argb1555;
- case GL_UNSIGNED_SHORT_4_4_4_4:
- case GL_UNSIGNED_SHORT_4_4_4_4_REV:
- return _dri_texformat_argb4444;
- case GL_UNSIGNED_SHORT_5_5_5_1:
- case GL_UNSIGNED_SHORT_1_5_5_5_REV:
- return _dri_texformat_argb1555;
- default:
- return do32bpt ? _dri_texformat_rgba8888 : _dri_texformat_argb4444;
- }
-
- case 3:
- case GL_RGB:
- case GL_COMPRESSED_RGB:
- switch ( type ) {
- case GL_UNSIGNED_SHORT_4_4_4_4:
- case GL_UNSIGNED_SHORT_4_4_4_4_REV:
- return _dri_texformat_argb4444;
- case GL_UNSIGNED_SHORT_5_5_5_1:
- case GL_UNSIGNED_SHORT_1_5_5_5_REV:
- return _dri_texformat_argb1555;
- case GL_UNSIGNED_SHORT_5_6_5:
- case GL_UNSIGNED_SHORT_5_6_5_REV:
- return _dri_texformat_rgb565;
- default:
- return do32bpt ? _dri_texformat_rgba8888 : _dri_texformat_rgb565;
- }
-
- case GL_RGBA8:
- case GL_RGB10_A2:
- case GL_RGBA12:
- case GL_RGBA16:
- return !force16bpt ?
- _dri_texformat_rgba8888 : _dri_texformat_argb4444;
-
- case GL_RGBA4:
- case GL_RGBA2:
- return _dri_texformat_argb4444;
-
- case GL_RGB5_A1:
- return _dri_texformat_argb1555;
-
- case GL_RGB8:
- case GL_RGB10:
- case GL_RGB12:
- case GL_RGB16:
- return !force16bpt ? _dri_texformat_rgba8888 : _dri_texformat_rgb565;
-
- case GL_RGB5:
- case GL_RGB4:
- case GL_R3_G3_B2:
- return _dri_texformat_rgb565;
-
- case GL_ALPHA:
- case GL_ALPHA4:
- case GL_ALPHA8:
- case GL_ALPHA12:
- case GL_ALPHA16:
- case GL_COMPRESSED_ALPHA:
- return _dri_texformat_a8;
-
- case 1:
- case GL_LUMINANCE:
- case GL_LUMINANCE4:
- case GL_LUMINANCE8:
- case GL_LUMINANCE12:
- case GL_LUMINANCE16:
- case GL_COMPRESSED_LUMINANCE:
- return _dri_texformat_l8;
-
- case 2:
- case GL_LUMINANCE_ALPHA:
- case GL_LUMINANCE4_ALPHA4:
- case GL_LUMINANCE6_ALPHA2:
- case GL_LUMINANCE8_ALPHA8:
- case GL_LUMINANCE12_ALPHA4:
- case GL_LUMINANCE12_ALPHA12:
- case GL_LUMINANCE16_ALPHA16:
- case GL_COMPRESSED_LUMINANCE_ALPHA:
- return _dri_texformat_al88;
-
- case GL_INTENSITY:
- case GL_INTENSITY4:
- case GL_INTENSITY8:
- case GL_INTENSITY12:
- case GL_INTENSITY16:
- case GL_COMPRESSED_INTENSITY:
- return _dri_texformat_i8;
-
- case GL_YCBCR_MESA:
- if (type == GL_UNSIGNED_SHORT_8_8_APPLE ||
- type == GL_UNSIGNED_BYTE)
- return &_mesa_texformat_ycbcr;
- else
- return &_mesa_texformat_ycbcr_rev;
-
- case GL_RGB_S3TC:
- case GL_RGB4_S3TC:
- case GL_COMPRESSED_RGB_S3TC_DXT1_EXT:
- return &_mesa_texformat_rgb_dxt1;
-
- case GL_COMPRESSED_RGBA_S3TC_DXT1_EXT:
- return &_mesa_texformat_rgba_dxt1;
-
- case GL_RGBA_S3TC:
- case GL_RGBA4_S3TC:
- case GL_COMPRESSED_RGBA_S3TC_DXT3_EXT:
- return &_mesa_texformat_rgba_dxt3;
-
- case GL_COMPRESSED_RGBA_S3TC_DXT5_EXT:
- return &_mesa_texformat_rgba_dxt5;
-
- default:
- _mesa_problem(ctx, "unexpected texture format in %s", __FUNCTION__);
- return NULL;
- }
-
- return NULL; /* never get here */
-}
-
-
-static void radeonTexImage1D( GLcontext *ctx, GLenum target, GLint level,
- GLint internalFormat,
- GLint width, GLint border,
- GLenum format, GLenum type, const GLvoid *pixels,
- const struct gl_pixelstore_attrib *packing,
- struct gl_texture_object *texObj,
- struct gl_texture_image *texImage )
-{
- driTextureObject * t = (driTextureObject *) texObj->DriverData;
-
- if ( t ) {
- driSwapOutTextureObject( t );
- }
- else {
- t = (driTextureObject *) radeonAllocTexObj( texObj );
- if (!t) {
- _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexImage1D");
- return;
- }
- }
-
- /* Note, this will call ChooseTextureFormat */
- _mesa_store_teximage1d(ctx, target, level, internalFormat,
- width, border, format, type, pixels,
- &ctx->Unpack, texObj, texImage);
-
- t->dirty_images[0] |= (1 << level);
-}
-
-
-static void radeonTexSubImage1D( GLcontext *ctx, GLenum target, GLint level,
- GLint xoffset,
- GLsizei width,
- GLenum format, GLenum type,
- const GLvoid *pixels,
- const struct gl_pixelstore_attrib *packing,
- struct gl_texture_object *texObj,
- struct gl_texture_image *texImage )
-{
- driTextureObject * t = (driTextureObject *) texObj->DriverData;
-
- assert( t ); /* this _should_ be true */
- if ( t ) {
- driSwapOutTextureObject( t );
- }
- else {
- t = (driTextureObject *) radeonAllocTexObj( texObj );
- if (!t) {
- _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexSubImage1D");
- return;
- }
- }
-
- _mesa_store_texsubimage1d(ctx, target, level, xoffset, width,
- format, type, pixels, packing, texObj,
- texImage);
-
- t->dirty_images[0] |= (1 << level);
-}
-
-
-static void radeonTexImage2D( GLcontext *ctx, GLenum target, GLint level,
- GLint internalFormat,
- GLint width, GLint height, GLint border,
- GLenum format, GLenum type, const GLvoid *pixels,
- const struct gl_pixelstore_attrib *packing,
- struct gl_texture_object *texObj,
- struct gl_texture_image *texImage )
-{
- driTextureObject * t = (driTextureObject *) texObj->DriverData;
- GLuint face;
-
- /* which cube face or ordinary 2D image */
- switch (target) {
- case GL_TEXTURE_CUBE_MAP_POSITIVE_X:
- case GL_TEXTURE_CUBE_MAP_NEGATIVE_X:
- case GL_TEXTURE_CUBE_MAP_POSITIVE_Y:
- case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y:
- case GL_TEXTURE_CUBE_MAP_POSITIVE_Z:
- case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z:
- face = (GLuint) target - (GLuint) GL_TEXTURE_CUBE_MAP_POSITIVE_X;
- ASSERT(face < 6);
- break;
- default:
- face = 0;
- }
-
- if ( t != NULL ) {
- driSwapOutTextureObject( t );
- }
- else {
- t = (driTextureObject *) radeonAllocTexObj( texObj );
- if (!t) {
- _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexImage2D");
- return;
- }
- }
-
- /* Note, this will call ChooseTextureFormat */
- _mesa_store_teximage2d(ctx, target, level, internalFormat,
- width, height, border, format, type, pixels,
- &ctx->Unpack, texObj, texImage);
-
- t->dirty_images[face] |= (1 << level);
-}
-
-
-static void radeonTexSubImage2D( GLcontext *ctx, GLenum target, GLint level,
- GLint xoffset, GLint yoffset,
- GLsizei width, GLsizei height,
- GLenum format, GLenum type,
- const GLvoid *pixels,
- const struct gl_pixelstore_attrib *packing,
- struct gl_texture_object *texObj,
- struct gl_texture_image *texImage )
-{
- driTextureObject * t = (driTextureObject *) texObj->DriverData;
- GLuint face;
-
- /* which cube face or ordinary 2D image */
- switch (target) {
- case GL_TEXTURE_CUBE_MAP_POSITIVE_X:
- case GL_TEXTURE_CUBE_MAP_NEGATIVE_X:
- case GL_TEXTURE_CUBE_MAP_POSITIVE_Y:
- case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y:
- case GL_TEXTURE_CUBE_MAP_POSITIVE_Z:
- case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z:
- face = (GLuint) target - (GLuint) GL_TEXTURE_CUBE_MAP_POSITIVE_X;
- ASSERT(face < 6);
- break;
- default:
- face = 0;
- }
-
- assert( t ); /* this _should_ be true */
- if ( t ) {
- driSwapOutTextureObject( t );
- }
- else {
- t = (driTextureObject *) radeonAllocTexObj( texObj );
- if (!t) {
- _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexSubImage2D");
- return;
- }
- }
-
- _mesa_store_texsubimage2d(ctx, target, level, xoffset, yoffset, width,
- height, format, type, pixels, packing, texObj,
- texImage);
-
- t->dirty_images[face] |= (1 << level);
-}
-
-static void radeonCompressedTexImage2D( GLcontext *ctx, GLenum target, GLint level,
- GLint internalFormat,
- GLint width, GLint height, GLint border,
- GLsizei imageSize, const GLvoid *data,
- struct gl_texture_object *texObj,
- struct gl_texture_image *texImage )
-{
- driTextureObject * t = (driTextureObject *) texObj->DriverData;
- GLuint face;
-
- /* which cube face or ordinary 2D image */
- switch (target) {
- case GL_TEXTURE_CUBE_MAP_POSITIVE_X:
- case GL_TEXTURE_CUBE_MAP_NEGATIVE_X:
- case GL_TEXTURE_CUBE_MAP_POSITIVE_Y:
- case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y:
- case GL_TEXTURE_CUBE_MAP_POSITIVE_Z:
- case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z:
- face = (GLuint) target - (GLuint) GL_TEXTURE_CUBE_MAP_POSITIVE_X;
- ASSERT(face < 6);
- break;
- default:
- face = 0;
- }
-
- if ( t != NULL ) {
- driSwapOutTextureObject( t );
- }
- else {
- t = (driTextureObject *) radeonAllocTexObj( texObj );
- if (!t) {
- _mesa_error(ctx, GL_OUT_OF_MEMORY, "glCompressedTexImage2D");
- return;
- }
- }
-
- /* Note, this will call ChooseTextureFormat */
- _mesa_store_compressed_teximage2d(ctx, target, level, internalFormat, width,
- height, border, imageSize, data, texObj, texImage);
-
- t->dirty_images[face] |= (1 << level);
-}
-
-
-static void radeonCompressedTexSubImage2D( GLcontext *ctx, GLenum target, GLint level,
- GLint xoffset, GLint yoffset,
- GLsizei width, GLsizei height,
- GLenum format,
- GLsizei imageSize, const GLvoid *data,
- struct gl_texture_object *texObj,
- struct gl_texture_image *texImage )
-{
- driTextureObject * t = (driTextureObject *) texObj->DriverData;
- GLuint face;
-
-
- /* which cube face or ordinary 2D image */
- switch (target) {
- case GL_TEXTURE_CUBE_MAP_POSITIVE_X:
- case GL_TEXTURE_CUBE_MAP_NEGATIVE_X:
- case GL_TEXTURE_CUBE_MAP_POSITIVE_Y:
- case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y:
- case GL_TEXTURE_CUBE_MAP_POSITIVE_Z:
- case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z:
- face = (GLuint) target - (GLuint) GL_TEXTURE_CUBE_MAP_POSITIVE_X;
- ASSERT(face < 6);
- break;
- default:
- face = 0;
- }
-
- assert( t ); /* this _should_ be true */
- if ( t ) {
- driSwapOutTextureObject( t );
- }
- else {
- t = (driTextureObject *) radeonAllocTexObj( texObj );
- if (!t) {
- _mesa_error(ctx, GL_OUT_OF_MEMORY, "glCompressedTexSubImage2D");
- return;
- }
- }
-
- _mesa_store_compressed_texsubimage2d(ctx, target, level, xoffset, yoffset, width,
- height, format, imageSize, data, texObj, texImage);
-
- t->dirty_images[face] |= (1 << level);
-}
-
-#define SCALED_FLOAT_TO_BYTE( x, scale ) \
- (((GLuint)((255.0F / scale) * (x))) / 2)
-
-static void radeonTexEnv( GLcontext *ctx, GLenum target,
- GLenum pname, const GLfloat *param )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLuint unit = ctx->Texture.CurrentUnit;
- struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
-
- if ( RADEON_DEBUG & DEBUG_STATE ) {
- fprintf( stderr, "%s( %s )\n",
- __FUNCTION__, _mesa_lookup_enum_by_nr( pname ) );
- }
-
- switch ( pname ) {
- case GL_TEXTURE_ENV_COLOR: {
- GLubyte c[4];
- GLuint envColor;
- UNCLAMPED_FLOAT_TO_RGBA_CHAN( c, texUnit->EnvColor );
- envColor = radeonPackColor( 4, c[0], c[1], c[2], c[3] );
- if ( rmesa->hw.tex[unit].cmd[TEX_PP_TFACTOR] != envColor ) {
- RADEON_STATECHANGE( rmesa, tex[unit] );
- rmesa->hw.tex[unit].cmd[TEX_PP_TFACTOR] = envColor;
- }
- break;
- }
-
- case GL_TEXTURE_LOD_BIAS_EXT: {
- GLfloat bias, min;
- GLuint b;
-
- /* The Radeon's LOD bias is a signed 2's complement value with a
- * range of -1.0 <= bias < 4.0. We break this into two linear
- * functions, one mapping [-1.0,0.0] to [-128,0] and one mapping
- * [0.0,4.0] to [0,127].
- */
- min = driQueryOptionb (&rmesa->optionCache, "no_neg_lod_bias") ?
- 0.0 : -1.0;
- bias = CLAMP( *param, min, 4.0 );
- if ( bias == 0 ) {
- b = 0;
- } else if ( bias > 0 ) {
- b = ((GLuint)SCALED_FLOAT_TO_BYTE( bias, 4.0 )) << RADEON_LOD_BIAS_SHIFT;
- } else {
- b = ((GLuint)SCALED_FLOAT_TO_BYTE( bias, 1.0 )) << RADEON_LOD_BIAS_SHIFT;
- }
- if ( (rmesa->hw.tex[unit].cmd[TEX_PP_TXFILTER] & RADEON_LOD_BIAS_MASK) != b ) {
- RADEON_STATECHANGE( rmesa, tex[unit] );
- rmesa->hw.tex[unit].cmd[TEX_PP_TXFILTER] &= ~RADEON_LOD_BIAS_MASK;
- rmesa->hw.tex[unit].cmd[TEX_PP_TXFILTER] |= (b & RADEON_LOD_BIAS_MASK);
- }
- break;
- }
-
- default:
- return;
- }
-}
-
-
-/**
- * Changes variables and flags for a state update, which will happen at the
- * next UpdateTextureState
- */
-
-static void radeonTexParameter( GLcontext *ctx, GLenum target,
- struct gl_texture_object *texObj,
- GLenum pname, const GLfloat *params )
-{
- radeonTexObjPtr t = (radeonTexObjPtr) texObj->DriverData;
-
- if ( RADEON_DEBUG & (DEBUG_STATE|DEBUG_TEXTURE) ) {
- fprintf( stderr, "%s( %s )\n", __FUNCTION__,
- _mesa_lookup_enum_by_nr( pname ) );
- }
-
- switch ( pname ) {
- case GL_TEXTURE_MIN_FILTER:
- case GL_TEXTURE_MAG_FILTER:
- case GL_TEXTURE_MAX_ANISOTROPY_EXT:
- radeonSetTexMaxAnisotropy( t, texObj->MaxAnisotropy );
- radeonSetTexFilter( t, texObj->MinFilter, texObj->MagFilter );
- break;
-
- case GL_TEXTURE_WRAP_S:
- case GL_TEXTURE_WRAP_T:
- radeonSetTexWrap( t, texObj->WrapS, texObj->WrapT );
- break;
-
- case GL_TEXTURE_BORDER_COLOR:
- radeonSetTexBorderColor( t, texObj->_BorderChan );
- break;
-
- case GL_TEXTURE_BASE_LEVEL:
- case GL_TEXTURE_MAX_LEVEL:
- case GL_TEXTURE_MIN_LOD:
- case GL_TEXTURE_MAX_LOD:
- /* This isn't the most efficient solution but there doesn't appear to
- * be a nice alternative. Since there's no LOD clamping,
- * we just have to rely on loading the right subset of mipmap levels
- * to simulate a clamped LOD.
- */
- driSwapOutTextureObject( (driTextureObject *) t );
- break;
-
- default:
- return;
- }
-
- /* Mark this texobj as dirty (one bit per tex unit)
- */
- t->dirty_state = TEX_ALL;
-}
-
-
-static void radeonBindTexture( GLcontext *ctx, GLenum target,
- struct gl_texture_object *texObj )
-{
- if ( RADEON_DEBUG & (DEBUG_STATE|DEBUG_TEXTURE) ) {
- fprintf( stderr, "%s( %p ) unit=%d\n", __FUNCTION__, (void *)texObj,
- ctx->Texture.CurrentUnit );
- }
-
- assert( (target != GL_TEXTURE_1D && target != GL_TEXTURE_2D &&
- target != GL_TEXTURE_RECTANGLE_NV) ||
- (texObj->DriverData != NULL) );
-}
-
-
-static void radeonDeleteTexture( GLcontext *ctx,
- struct gl_texture_object *texObj )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- driTextureObject * t = (driTextureObject *) texObj->DriverData;
-
- if ( RADEON_DEBUG & (DEBUG_STATE|DEBUG_TEXTURE) ) {
- fprintf( stderr, "%s( %p (target = %s) )\n", __FUNCTION__, (void *)texObj,
- _mesa_lookup_enum_by_nr( texObj->Target ) );
- }
-
- if ( t != NULL ) {
- if ( rmesa ) {
- RADEON_FIREVERTICES( rmesa );
- }
-
- driDestroyTextureObject( t );
- }
-
- /* Free mipmap images and the texture object itself */
- _mesa_delete_texture_object(ctx, texObj);
-}
-
-/* Need:
- * - Same GEN_MODE for all active bits
- * - Same EyePlane/ObjPlane for all active bits when using Eye/Obj
- * - STRQ presumably all supported (matrix means incoming R values
- * can end up in STQ, this has implications for vertex support,
- * presumably ok if maos is used, though?)
- *
- * Basically impossible to do this on the fly - just collect some
- * basic info & do the checks from ValidateState().
- */
-static void radeonTexGen( GLcontext *ctx,
- GLenum coord,
- GLenum pname,
- const GLfloat *params )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLuint unit = ctx->Texture.CurrentUnit;
- rmesa->recheck_texgen[unit] = GL_TRUE;
-}
-
-/**
- * Allocate a new texture object.
- * Called via ctx->Driver.NewTextureObject.
- * Note: we could use containment here to 'derive' the driver-specific
- * texture object from the core mesa gl_texture_object. Not done at this time.
- */
-static struct gl_texture_object *
-radeonNewTextureObject( GLcontext *ctx, GLuint name, GLenum target )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- struct gl_texture_object *obj;
- obj = _mesa_new_texture_object(ctx, name, target);
- if (!obj)
- return NULL;
- obj->MaxAnisotropy = rmesa->initialMaxAnisotropy;
- radeonAllocTexObj( obj );
- return obj;
-}
-
-
-void radeonInitTextureFuncs( struct dd_function_table *functions )
-{
- functions->ChooseTextureFormat = radeonChooseTextureFormat;
- functions->TexImage1D = radeonTexImage1D;
- functions->TexImage2D = radeonTexImage2D;
- functions->TexSubImage1D = radeonTexSubImage1D;
- functions->TexSubImage2D = radeonTexSubImage2D;
-
- functions->NewTextureObject = radeonNewTextureObject;
- functions->BindTexture = radeonBindTexture;
- functions->DeleteTexture = radeonDeleteTexture;
- functions->IsTextureResident = driIsTextureResident;
-
- functions->TexEnv = radeonTexEnv;
- functions->TexParameter = radeonTexParameter;
- functions->TexGen = radeonTexGen;
-
- functions->CompressedTexImage2D = radeonCompressedTexImage2D;
- functions->CompressedTexSubImage2D = radeonCompressedTexSubImage2D;
-
- driInitTextureFormats();
-}
diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_tex.h b/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_tex.h
deleted file mode 100644
index a806981ae..000000000
--- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_tex.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_tex.h,v 1.3 2002/02/22 21:45:01 dawes Exp $ */
-/**************************************************************************
-
-Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
- VA Linux Systems Inc., Fremont, California.
-
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/*
- * Authors:
- * Kevin E. Martin <martin@valinux.com>
- * Gareth Hughes <gareth@valinux.com>
- *
- */
-
-#ifndef __RADEON_TEX_H__
-#define __RADEON_TEX_H__
-
-extern void radeonUpdateTextureState( GLcontext *ctx );
-
-extern int radeonUploadTexImages( radeonContextPtr rmesa, radeonTexObjPtr t,
- GLuint face );
-
-extern void radeonDestroyTexObj( radeonContextPtr rmesa, radeonTexObjPtr t );
-
-extern void radeonInitTextureFuncs( struct dd_function_table *functions );
-
-#endif /* __RADEON_TEX_H__ */
diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_texmem.c b/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_texmem.c
deleted file mode 100644
index d492e190c..000000000
--- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_texmem.c
+++ /dev/null
@@ -1,404 +0,0 @@
-/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_texmem.c,v 1.7 2002/12/16 16:18:59 dawes Exp $ */
-/**************************************************************************
-
-Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
- VA Linux Systems Inc., Fremont, California.
-
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation on the rights to use, copy, modify, merge, publish,
-distribute, sub license, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR THEIR
-SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR
-IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-SOFTWARE.
-
-**************************************************************************/
-
-/*
- * Authors:
- * Kevin E. Martin <martin@valinux.com>
- * Gareth Hughes <gareth@valinux.com>
- *
- */
-#include <errno.h>
-
-#include "glheader.h"
-#include "imports.h"
-#include "context.h"
-#include "macros.h"
-
-#include "radeon_context.h"
-#include "radeon_ioctl.h"
-#include "radeon_tex.h"
-
-#include <unistd.h> /* for usleep() */
-
-
-/**
- * Destroy any device-dependent state associated with the texture. This may
- * include NULLing out hardware state that points to the texture.
- */
-void
-radeonDestroyTexObj( radeonContextPtr rmesa, radeonTexObjPtr t )
-{
- if ( RADEON_DEBUG & DEBUG_TEXTURE ) {
- fprintf( stderr, "%s( %p, %p )\n", __FUNCTION__, (void *)t, (void *)t->base.tObj );
- }
-
- if ( rmesa != NULL ) {
- unsigned i;
-
-
- for ( i = 0 ; i < rmesa->glCtx->Const.MaxTextureUnits ; i++ ) {
- if ( t == rmesa->state.texture.unit[i].texobj ) {
- rmesa->state.texture.unit[i].texobj = NULL;
- rmesa->hw.tex[i].dirty = GL_FALSE;
- }
- }
- }
-}
-
-
-/* ------------------------------------------------------------
- * Texture image conversions
- */
-
-
-static void radeonUploadRectSubImage( radeonContextPtr rmesa,
- radeonTexObjPtr t,
- struct gl_texture_image *texImage,
- GLint x, GLint y,
- GLint width, GLint height )
-{
- const struct gl_texture_format *texFormat = texImage->TexFormat;
- int blit_format, dstPitch, done;
-
- switch ( texFormat->TexelBytes ) {
- case 1:
- blit_format = RADEON_GMC_DST_8BPP_CI;
- break;
- case 2:
- blit_format = RADEON_GMC_DST_16BPP;
- break;
- case 4:
- blit_format = RADEON_GMC_DST_32BPP;
- break;
- default:
- fprintf( stderr, "radeonUploadRectSubImage: unknown blit_format (texelbytes=%d)\n",
- texFormat->TexelBytes);
- return;
- }
-
- t->image[0][0].data = texImage->Data;
-
- /* Currently don't need to cope with small pitches.
- */
- width = texImage->Width;
- height = texImage->Height;
- dstPitch = t->pp_txpitch + 32;
-
- { /* FIXME: prefer GART-texturing if possible */
- /* Data not in GART memory, or bad pitch.
- */
- for (done = 0; done < height ; ) {
- struct radeon_dma_region region;
- int lines = MIN2( height - done, RADEON_BUFFER_SIZE / dstPitch );
- int src_pitch;
- char *tex;
-
- src_pitch = texImage->RowStride * texFormat->TexelBytes;
-
- tex = (char *)texImage->Data + done * src_pitch;
-
- memset(&region, 0, sizeof(region));
- radeonAllocDmaRegion( rmesa, &region, lines * dstPitch, 1024 );
-
- /* Copy texdata to dma:
- */
- if (0)
- fprintf(stderr, "%s: src_pitch %d dst_pitch %d\n",
- __FUNCTION__, src_pitch, dstPitch);
-
- if (src_pitch == dstPitch) {
- memcpy( region.address + region.start, tex, lines * src_pitch );
- }
- else {
- char *buf = region.address + region.start;
- int i;
- for (i = 0 ; i < lines ; i++) {
- memcpy( buf, tex, src_pitch );
- buf += dstPitch;
- tex += src_pitch;
- }
- }
-
- radeonEmitWait( rmesa, RADEON_WAIT_3D );
-
-
-
- /* Blit to framebuffer
- */
- radeonEmitBlit( rmesa,
- blit_format,
- dstPitch, GET_START( &region ),
- dstPitch, t->bufAddr,
- 0, 0,
- 0, done,
- width, lines );
-
- radeonEmitWait( rmesa, RADEON_WAIT_2D );
-
- radeonReleaseDmaRegion( rmesa, &region, __FUNCTION__ );
- done += lines;
- }
- }
-}
-
-
-/**
- * Upload the texture image associated with texture \a t at the specified
- * level at the address relative to \a start.
- */
-static void uploadSubImage( radeonContextPtr rmesa, radeonTexObjPtr t,
- GLint hwlevel,
- GLint x, GLint y, GLint width, GLint height,
- GLuint face )
-{
- struct gl_texture_image *texImage = NULL;
- GLuint offset;
- GLint imageWidth, imageHeight;
- GLint ret;
- drm_radeon_texture_t tex;
- drm_radeon_tex_image_t tmp;
- const int level = hwlevel + t->base.firstLevel;
-
- if ( RADEON_DEBUG & DEBUG_TEXTURE ) {
- fprintf( stderr, "%s( %p, %p ) level/width/height/face = %d/%d/%d/%u\n",
- __FUNCTION__, (void *)t, (void *)t->base.tObj, level, width, height, face );
- }
-
- ASSERT(face < 6);
-
- /* Ensure we have a valid texture to upload */
- if ( ( hwlevel < 0 ) || ( hwlevel >= RADEON_MAX_TEXTURE_LEVELS ) ) {
- _mesa_problem(NULL, "bad texture level in %s", __FUNCTION__);
- return;
- }
-
- texImage = t->base.tObj->Image[face][level];
-
- if ( !texImage ) {
- if ( RADEON_DEBUG & DEBUG_TEXTURE )
- fprintf( stderr, "%s: texImage %d is NULL!\n", __FUNCTION__, level );
- return;
- }
- if ( !texImage->Data ) {
- if ( RADEON_DEBUG & DEBUG_TEXTURE )
- fprintf( stderr, "%s: image data is NULL!\n", __FUNCTION__ );
- return;
- }
-
-
- if (t->base.tObj->Target == GL_TEXTURE_RECTANGLE_NV) {
- assert(level == 0);
- assert(hwlevel == 0);
- if ( RADEON_DEBUG & DEBUG_TEXTURE )
- fprintf( stderr, "%s: image data is rectangular\n", __FUNCTION__);
- radeonUploadRectSubImage( rmesa, t, texImage, x, y, width, height );
- return;
- }
-
- imageWidth = texImage->Width;
- imageHeight = texImage->Height;
-
- offset = t->bufAddr;
-
- if ( RADEON_DEBUG & (DEBUG_TEXTURE|DEBUG_IOCTL) ) {
- GLint imageX = 0;
- GLint imageY = 0;
- GLint blitX = t->image[face][hwlevel].x;
- GLint blitY = t->image[face][hwlevel].y;
- GLint blitWidth = t->image[face][hwlevel].width;
- GLint blitHeight = t->image[face][hwlevel].height;
- fprintf( stderr, " upload image: %d,%d at %d,%d\n",
- imageWidth, imageHeight, imageX, imageY );
- fprintf( stderr, " upload blit: %d,%d at %d,%d\n",
- blitWidth, blitHeight, blitX, blitY );
- fprintf( stderr, " blit ofs: 0x%07x level: %d/%d\n",
- (GLuint)offset, hwlevel, level );
- }
-
- t->image[face][hwlevel].data = texImage->Data;
-
- /* Init the DRM_RADEON_TEXTURE command / drm_radeon_texture_t struct.
- * NOTE: we're always use a 1KB-wide blit and I8 texture format.
- * We used to use 1, 2 and 4-byte texels and used to use the texture
- * width to dictate the blit width - but that won't work for compressed
- * textures. (Brian)
- * NOTE: can't do that with texture tiling. (sroland)
- */
- tex.offset = offset;
- tex.image = &tmp;
- /* copy (x,y,width,height,data) */
- memcpy( &tmp, &t->image[face][hwlevel], sizeof(drm_radeon_tex_image_t) );
-
- if (texImage->TexFormat->TexelBytes) {
- /* use multi-byte upload scheme */
- tex.height = imageHeight;
- tex.width = imageWidth;
- tex.format = t->pp_txformat & RADEON_TXFORMAT_FORMAT_MASK;
- tex.pitch = MAX2((texImage->Width * texImage->TexFormat->TexelBytes) / 64, 1);
- tex.offset += tmp.x & ~1023;
- tmp.x = tmp.x % 1024;
- if (t->tile_bits & RADEON_TXO_MICRO_TILE_X2) {
- /* need something like "tiled coordinates" ? */
- tmp.y = tmp.x / (tex.pitch * 128) * 2;
- tmp.x = tmp.x % (tex.pitch * 128) / 2 / texImage->TexFormat->TexelBytes;
- tex.pitch |= RADEON_DST_TILE_MICRO >> 22;
- }
- else {
- tmp.x = tmp.x >> (texImage->TexFormat->TexelBytes >> 1);
- }
- if ((t->tile_bits & RADEON_TXO_MACRO_TILE) &&
- (texImage->Width * texImage->TexFormat->TexelBytes >= 256)) {
- /* radeon switches off macro tiling for small textures/mipmaps it seems */
- tex.pitch |= RADEON_DST_TILE_MACRO >> 22;
- }
- }
- else {
- /* In case of for instance 8x8 texture (2x2 dxt blocks), padding after the first two blocks is
- needed (only with dxt1 since 2 dxt3/dxt5 blocks already use 32 Byte). */
- /* set tex.height to 1/4 since 1 "macropixel" (dxt-block) has 4 real pixels. Needed
- so the kernel module reads the right amount of data. */
- tex.format = RADEON_TXFORMAT_I8; /* any 1-byte texel format */
- tex.pitch = (BLIT_WIDTH_BYTES / 64);
- tex.height = (imageHeight + 3) / 4;
- tex.width = (imageWidth + 3) / 4;
- switch (t->pp_txformat & RADEON_TXFORMAT_FORMAT_MASK) {
- case RADEON_TXFORMAT_DXT1:
- tex.width *= 8;
- break;
- case RADEON_TXFORMAT_DXT23:
- case RADEON_TXFORMAT_DXT45:
- tex.width *= 16;
- break;
- }
- }
-
- LOCK_HARDWARE( rmesa );
- do {
- ret = drmCommandWriteRead( rmesa->dri.fd, DRM_RADEON_TEXTURE,
- &tex, sizeof(drm_radeon_texture_t) );
- } while ( ret && errno == EAGAIN );
-
- UNLOCK_HARDWARE( rmesa );
-
- if ( ret ) {
- fprintf( stderr, "DRM_RADEON_TEXTURE: return = %d\n", ret );
- fprintf( stderr, " offset=0x%08x\n",
- offset );
- fprintf( stderr, " image width=%d height=%d\n",
- imageWidth, imageHeight );
- fprintf( stderr, " blit width=%d height=%d data=%p\n",
- t->image[face][hwlevel].width, t->image[face][hwlevel].height,
- t->image[face][hwlevel].data );
- exit( 1 );
- }
-}
-
-
-/**
- * Upload the texture images associated with texture \a t. This might
- * require the allocation of texture memory.
- *
- * \param rmesa Context pointer
- * \param t Texture to be uploaded
- * \param face Cube map face to be uploaded. Zero for non-cube maps.
- */
-
-int radeonUploadTexImages( radeonContextPtr rmesa, radeonTexObjPtr t, GLuint face )
-{
- const int numLevels = t->base.lastLevel - t->base.firstLevel + 1;
-
- if ( RADEON_DEBUG & (DEBUG_TEXTURE|DEBUG_IOCTL) ) {
- fprintf( stderr, "%s( %p, %p ) sz=%d lvls=%d-%d\n", __FUNCTION__,
- (void *)rmesa->glCtx, (void *)t->base.tObj, t->base.totalSize,
- t->base.firstLevel, t->base.lastLevel );
- }
-
- if ( !t || t->base.totalSize == 0 )
- return 0;
-
- if (RADEON_DEBUG & DEBUG_SYNC) {
- fprintf(stderr, "%s: Syncing\n", __FUNCTION__ );
- radeonFinish( rmesa->glCtx );
- }
-
- LOCK_HARDWARE( rmesa );
-
- if ( t->base.memBlock == NULL ) {
- int heap;
-
- heap = driAllocateTexture( rmesa->texture_heaps, rmesa->nr_heaps,
- (driTextureObject *) t );
- if ( heap == -1 ) {
- UNLOCK_HARDWARE( rmesa );
- return -1;
- }
-
- /* Set the base offset of the texture image */
- t->bufAddr = rmesa->radeonScreen->texOffset[heap]
- + t->base.memBlock->ofs;
- t->pp_txoffset = t->bufAddr;
-
- if (!(t->base.tObj->Image[0][0]->IsClientData)) {
- /* hope it's safe to add that here... */
- t->pp_txoffset |= t->tile_bits;
- }
-
- /* Mark this texobj as dirty on all units:
- */
- t->dirty_state = TEX_ALL;
- }
-
-
- /* Let the world know we've used this memory recently.
- */
- driUpdateTextureLRU( (driTextureObject *) t );
- UNLOCK_HARDWARE( rmesa );
-
-
- /* Upload any images that are new */
- if (t->base.dirty_images[face]) {
- int i;
- for ( i = 0 ; i < numLevels ; i++ ) {
- if ( (t->base.dirty_images[face] & (1 << (i+t->base.firstLevel))) != 0 ) {
- uploadSubImage( rmesa, t, i, 0, 0, t->image[face][i].width,
- t->image[face][i].height, face );
- }
- }
- t->base.dirty_images[face] = 0;
- }
-
- if (RADEON_DEBUG & DEBUG_SYNC) {
- fprintf(stderr, "%s: Syncing\n", __FUNCTION__ );
- radeonFinish( rmesa->glCtx );
- }
-
- return 0;
-}
diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_texstate.c b/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_texstate.c
deleted file mode 100644
index 43fe509fb..000000000
--- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_texstate.c
+++ /dev/null
@@ -1,1171 +0,0 @@
-/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_texstate.c,v 1.6 2002/12/16 16:18:59 dawes Exp $ */
-/**************************************************************************
-
-Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
- VA Linux Systems Inc., Fremont, California.
-
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/*
- * Authors:
- * Kevin E. Martin <martin@valinux.com>
- * Gareth Hughes <gareth@valinux.com>
- */
-
-#include "glheader.h"
-#include "imports.h"
-#include "colormac.h"
-#include "context.h"
-#include "macros.h"
-#include "texformat.h"
-#include "enums.h"
-
-#include "radeon_context.h"
-#include "radeon_state.h"
-#include "radeon_ioctl.h"
-#include "radeon_swtcl.h"
-#include "radeon_tex.h"
-#include "radeon_tcl.h"
-
-
-#define RADEON_TXFORMAT_A8 RADEON_TXFORMAT_I8
-#define RADEON_TXFORMAT_L8 RADEON_TXFORMAT_I8
-#define RADEON_TXFORMAT_AL88 RADEON_TXFORMAT_AI88
-#define RADEON_TXFORMAT_YCBCR RADEON_TXFORMAT_YVYU422
-#define RADEON_TXFORMAT_YCBCR_REV RADEON_TXFORMAT_VYUY422
-#define RADEON_TXFORMAT_RGB_DXT1 RADEON_TXFORMAT_DXT1
-#define RADEON_TXFORMAT_RGBA_DXT1 RADEON_TXFORMAT_DXT1
-#define RADEON_TXFORMAT_RGBA_DXT3 RADEON_TXFORMAT_DXT23
-#define RADEON_TXFORMAT_RGBA_DXT5 RADEON_TXFORMAT_DXT45
-
-#define _COLOR(f) \
- [ MESA_FORMAT_ ## f ] = { RADEON_TXFORMAT_ ## f, 0 }
-#define _COLOR_REV(f) \
- [ MESA_FORMAT_ ## f ## _REV ] = { RADEON_TXFORMAT_ ## f, 0 }
-#define _ALPHA(f) \
- [ MESA_FORMAT_ ## f ] = { RADEON_TXFORMAT_ ## f | RADEON_TXFORMAT_ALPHA_IN_MAP, 0 }
-#define _ALPHA_REV(f) \
- [ MESA_FORMAT_ ## f ## _REV ] = { RADEON_TXFORMAT_ ## f | RADEON_TXFORMAT_ALPHA_IN_MAP, 0 }
-#define _YUV(f) \
- [ MESA_FORMAT_ ## f ] = { RADEON_TXFORMAT_ ## f, RADEON_YUV_TO_RGB }
-#define _INVALID(f) \
- [ MESA_FORMAT_ ## f ] = { 0xffffffff, 0 }
-#define VALID_FORMAT(f) ( ((f) <= MESA_FORMAT_RGBA_DXT5) \
- && (tx_table[f].format != 0xffffffff) )
-
-static const struct {
- GLuint format, filter;
-}
-tx_table[] =
-{
- _ALPHA(RGBA8888),
- _ALPHA_REV(RGBA8888),
- _ALPHA(ARGB8888),
- _ALPHA_REV(ARGB8888),
- _INVALID(RGB888),
- _COLOR(RGB565),
- _COLOR_REV(RGB565),
- _ALPHA(ARGB4444),
- _ALPHA_REV(ARGB4444),
- _ALPHA(ARGB1555),
- _ALPHA_REV(ARGB1555),
- _ALPHA(AL88),
- _ALPHA_REV(AL88),
- _ALPHA(A8),
- _COLOR(L8),
- _ALPHA(I8),
- _INVALID(CI8),
- _YUV(YCBCR),
- _YUV(YCBCR_REV),
- _INVALID(RGB_FXT1),
- _INVALID(RGBA_FXT1),
- _COLOR(RGB_DXT1),
- _ALPHA(RGBA_DXT1),
- _ALPHA(RGBA_DXT3),
- _ALPHA(RGBA_DXT5),
-};
-
-#undef _COLOR
-#undef _ALPHA
-#undef _INVALID
-
-/**
- * This function computes the number of bytes of storage needed for
- * the given texture object (all mipmap levels, all cube faces).
- * The \c image[face][level].x/y/width/height parameters for upload/blitting
- * are computed here. \c pp_txfilter, \c pp_txformat, etc. will be set here
- * too.
- *
- * \param rmesa Context pointer
- * \param tObj GL texture object whose images are to be posted to
- * hardware state.
- */
-static void radeonSetTexImages( radeonContextPtr rmesa,
- struct gl_texture_object *tObj )
-{
- radeonTexObjPtr t = (radeonTexObjPtr)tObj->DriverData;
- const struct gl_texture_image *baseImage = tObj->Image[0][tObj->BaseLevel];
- GLint curOffset, blitWidth;
- GLint i, texelBytes;
- GLint numLevels;
- GLint log2Width, log2Height, log2Depth;
-
- /* Set the hardware texture format
- */
-
- t->pp_txformat &= ~(RADEON_TXFORMAT_FORMAT_MASK |
- RADEON_TXFORMAT_ALPHA_IN_MAP);
- t->pp_txfilter &= ~RADEON_YUV_TO_RGB;
-
- if ( VALID_FORMAT( baseImage->TexFormat->MesaFormat ) ) {
- t->pp_txformat |= tx_table[ baseImage->TexFormat->MesaFormat ].format;
- t->pp_txfilter |= tx_table[ baseImage->TexFormat->MesaFormat ].filter;
- }
- else {
- _mesa_problem(NULL, "unexpected texture format in %s", __FUNCTION__);
- return;
- }
-
- texelBytes = baseImage->TexFormat->TexelBytes;
-
- /* Compute which mipmap levels we really want to send to the hardware.
- */
-
- driCalculateTextureFirstLastLevel( (driTextureObject *) t );
- log2Width = tObj->Image[0][t->base.firstLevel]->WidthLog2;
- log2Height = tObj->Image[0][t->base.firstLevel]->HeightLog2;
- log2Depth = tObj->Image[0][t->base.firstLevel]->DepthLog2;
-
- numLevels = t->base.lastLevel - t->base.firstLevel + 1;
-
- assert(numLevels <= RADEON_MAX_TEXTURE_LEVELS);
-
- /* Calculate mipmap offsets and dimensions for blitting (uploading)
- * The idea is that we lay out the mipmap levels within a block of
- * memory organized as a rectangle of width BLIT_WIDTH_BYTES.
- */
- curOffset = 0;
- blitWidth = BLIT_WIDTH_BYTES;
- t->tile_bits = 0;
-
- /* figure out if this texture is suitable for tiling. */
- if (texelBytes && (tObj->Target != GL_TEXTURE_RECTANGLE_NV)) {
- if (rmesa->texmicrotile && (baseImage->Height > 1)) {
- /* allow 32 (bytes) x 1 mip (which will use two times the space
- the non-tiled version would use) max if base texture is large enough */
- if ((numLevels == 1) ||
- (((baseImage->Width * texelBytes / baseImage->Height) <= 32) &&
- (baseImage->Width * texelBytes > 64)) ||
- ((baseImage->Width * texelBytes / baseImage->Height) <= 16)) {
- /* R100 has two microtile bits (only the txoffset reg, not the blitter)
- weird: X2 + OPT: 32bit correct, 16bit completely hosed
- X2: 32bit correct, 16bit correct
- OPT: 32bit large mips correct, small mips hosed, 16bit completely hosed */
- t->tile_bits |= RADEON_TXO_MICRO_TILE_X2 /*| RADEON_TXO_MICRO_TILE_OPT*/;
- }
- }
- if ((baseImage->Width * texelBytes >= 256) && (baseImage->Height >= 16)) {
- /* R100 disables macro tiling only if mip width is smaller than 256 bytes, and not
- in the case if height is smaller than 16 (not 100% sure), as does the r200,
- so need to disable macro tiling in that case */
- if ((numLevels == 1) || ((baseImage->Width * texelBytes / baseImage->Height) <= 4)) {
- t->tile_bits |= RADEON_TXO_MACRO_TILE;
- }
- }
- }
-
- for (i = 0; i < numLevels; i++) {
- const struct gl_texture_image *texImage;
- GLuint size;
-
- texImage = tObj->Image[0][i + t->base.firstLevel];
- if ( !texImage )
- break;
-
- /* find image size in bytes */
- if (texImage->IsCompressed) {
- /* need to calculate the size AFTER padding even though the texture is
- submitted without padding.
- Only handle pot textures currently - don't know if npot is even possible,
- size calculation would certainly need (trivial) adjustments.
- Align (and later pad) to 32byte, not sure what that 64byte blit width is
- good for? */
- if ((t->pp_txformat & RADEON_TXFORMAT_FORMAT_MASK) == RADEON_TXFORMAT_DXT1) {
- /* RGB_DXT1/RGBA_DXT1, 8 bytes per block */
- if ((texImage->Width + 3) < 8) /* width one block */
- size = texImage->CompressedSize * 4;
- else if ((texImage->Width + 3) < 16)
- size = texImage->CompressedSize * 2;
- else size = texImage->CompressedSize;
- }
- else /* DXT3/5, 16 bytes per block */
- if ((texImage->Width + 3) < 8)
- size = texImage->CompressedSize * 2;
- else size = texImage->CompressedSize;
- }
- else if (tObj->Target == GL_TEXTURE_RECTANGLE_NV) {
- size = ((texImage->Width * texelBytes + 63) & ~63) * texImage->Height;
- }
- else if (t->tile_bits & RADEON_TXO_MICRO_TILE_X2) {
- /* tile pattern is 16 bytes x2. mipmaps stay 32 byte aligned,
- though the actual offset may be different (if texture is less than
- 32 bytes width) to the untiled case */
- int w = (texImage->Width * texelBytes * 2 + 31) & ~31;
- size = (w * ((texImage->Height + 1) / 2)) * texImage->Depth;
- blitWidth = MAX2(texImage->Width, 64 / texelBytes);
- }
- else {
- int w = (texImage->Width * texelBytes + 31) & ~31;
- size = w * texImage->Height * texImage->Depth;
- blitWidth = MAX2(texImage->Width, 64 / texelBytes);
- }
- assert(size > 0);
-
- /* Align to 32-byte offset. It is faster to do this unconditionally
- * (no branch penalty).
- */
-
- curOffset = (curOffset + 0x1f) & ~0x1f;
-
- if (texelBytes) {
- t->image[0][i].x = curOffset; /* fix x and y coords up later together with offset */
- t->image[0][i].y = 0;
- t->image[0][i].width = MIN2(size / texelBytes, blitWidth);
- t->image[0][i].height = (size / texelBytes) / t->image[0][i].width;
- }
- else {
- t->image[0][i].x = curOffset % BLIT_WIDTH_BYTES;
- t->image[0][i].y = curOffset / BLIT_WIDTH_BYTES;
- t->image[0][i].width = MIN2(size, BLIT_WIDTH_BYTES);
- t->image[0][i].height = size / t->image[0][i].width;
- }
-
-#if 0
- /* for debugging only and only applicable to non-rectangle targets */
- assert(size % t->image[0][i].width == 0);
- assert(t->image[0][i].x == 0
- || (size < BLIT_WIDTH_BYTES && t->image[0][i].height == 1));
-#endif
-
- if (0)
- fprintf(stderr,
- "level %d: %dx%d x=%d y=%d w=%d h=%d size=%d at %d\n",
- i, texImage->Width, texImage->Height,
- t->image[0][i].x, t->image[0][i].y,
- t->image[0][i].width, t->image[0][i].height, size, curOffset);
-
- curOffset += size;
-
- }
-
- /* Align the total size of texture memory block.
- */
- t->base.totalSize = (curOffset + RADEON_OFFSET_MASK) & ~RADEON_OFFSET_MASK;
-
- /* Hardware state:
- */
- t->pp_txfilter &= ~RADEON_MAX_MIP_LEVEL_MASK;
- t->pp_txfilter |= (numLevels - 1) << RADEON_MAX_MIP_LEVEL_SHIFT;
-
- t->pp_txformat &= ~(RADEON_TXFORMAT_WIDTH_MASK |
- RADEON_TXFORMAT_HEIGHT_MASK |
- RADEON_TXFORMAT_CUBIC_MAP_ENABLE);
- t->pp_txformat |= ((log2Width << RADEON_TXFORMAT_WIDTH_SHIFT) |
- (log2Height << RADEON_TXFORMAT_HEIGHT_SHIFT));
-
- t->pp_txsize = (((tObj->Image[0][t->base.firstLevel]->Width - 1) << 0) |
- ((tObj->Image[0][t->base.firstLevel]->Height - 1) << 16));
-
- /* Only need to round to nearest 32 for textures, but the blitter
- * requires 64-byte aligned pitches, and we may/may not need the
- * blitter. NPOT only!
- */
- if (baseImage->IsCompressed)
- t->pp_txpitch = (tObj->Image[0][t->base.firstLevel]->Width + 63) & ~(63);
- else
- t->pp_txpitch = ((tObj->Image[0][t->base.firstLevel]->Width * texelBytes) + 63) & ~(63);
- t->pp_txpitch -= 32;
-
- t->dirty_state = TEX_ALL;
-
- /* FYI: radeonUploadTexImages( rmesa, t ); used to be called here */
-}
-
-
-
-/* ================================================================
- * Texture combine functions
- */
-
-/* GL_ARB_texture_env_combine support
- */
-
-/* The color tables have combine functions for GL_SRC_COLOR,
- * GL_ONE_MINUS_SRC_COLOR, GL_SRC_ALPHA and GL_ONE_MINUS_SRC_ALPHA.
- */
-static GLuint radeon_texture_color[][RADEON_MAX_TEXTURE_UNITS] =
-{
- {
- RADEON_COLOR_ARG_A_T0_COLOR,
- RADEON_COLOR_ARG_A_T1_COLOR,
- RADEON_COLOR_ARG_A_T2_COLOR
- },
- {
- RADEON_COLOR_ARG_A_T0_COLOR | RADEON_COMP_ARG_A,
- RADEON_COLOR_ARG_A_T1_COLOR | RADEON_COMP_ARG_A,
- RADEON_COLOR_ARG_A_T2_COLOR | RADEON_COMP_ARG_A
- },
- {
- RADEON_COLOR_ARG_A_T0_ALPHA,
- RADEON_COLOR_ARG_A_T1_ALPHA,
- RADEON_COLOR_ARG_A_T2_ALPHA
- },
- {
- RADEON_COLOR_ARG_A_T0_ALPHA | RADEON_COMP_ARG_A,
- RADEON_COLOR_ARG_A_T1_ALPHA | RADEON_COMP_ARG_A,
- RADEON_COLOR_ARG_A_T2_ALPHA | RADEON_COMP_ARG_A
- },
-};
-
-static GLuint radeon_tfactor_color[] =
-{
- RADEON_COLOR_ARG_A_TFACTOR_COLOR,
- RADEON_COLOR_ARG_A_TFACTOR_COLOR | RADEON_COMP_ARG_A,
- RADEON_COLOR_ARG_A_TFACTOR_ALPHA,
- RADEON_COLOR_ARG_A_TFACTOR_ALPHA | RADEON_COMP_ARG_A
-};
-
-static GLuint radeon_primary_color[] =
-{
- RADEON_COLOR_ARG_A_DIFFUSE_COLOR,
- RADEON_COLOR_ARG_A_DIFFUSE_COLOR | RADEON_COMP_ARG_A,
- RADEON_COLOR_ARG_A_DIFFUSE_ALPHA,
- RADEON_COLOR_ARG_A_DIFFUSE_ALPHA | RADEON_COMP_ARG_A
-};
-
-static GLuint radeon_previous_color[] =
-{
- RADEON_COLOR_ARG_A_CURRENT_COLOR,
- RADEON_COLOR_ARG_A_CURRENT_COLOR | RADEON_COMP_ARG_A,
- RADEON_COLOR_ARG_A_CURRENT_ALPHA,
- RADEON_COLOR_ARG_A_CURRENT_ALPHA | RADEON_COMP_ARG_A
-};
-
-/* GL_ZERO table - indices 0-3
- * GL_ONE table - indices 1-4
- */
-static GLuint radeon_zero_color[] =
-{
- RADEON_COLOR_ARG_A_ZERO,
- RADEON_COLOR_ARG_A_ZERO | RADEON_COMP_ARG_A,
- RADEON_COLOR_ARG_A_ZERO,
- RADEON_COLOR_ARG_A_ZERO | RADEON_COMP_ARG_A,
- RADEON_COLOR_ARG_A_ZERO
-};
-
-
-/* The alpha tables only have GL_SRC_ALPHA and GL_ONE_MINUS_SRC_ALPHA.
- */
-static GLuint radeon_texture_alpha[][RADEON_MAX_TEXTURE_UNITS] =
-{
- {
- RADEON_ALPHA_ARG_A_T0_ALPHA,
- RADEON_ALPHA_ARG_A_T1_ALPHA,
- RADEON_ALPHA_ARG_A_T2_ALPHA
- },
- {
- RADEON_ALPHA_ARG_A_T0_ALPHA | RADEON_COMP_ARG_A,
- RADEON_ALPHA_ARG_A_T1_ALPHA | RADEON_COMP_ARG_A,
- RADEON_ALPHA_ARG_A_T2_ALPHA | RADEON_COMP_ARG_A
- },
-};
-
-static GLuint radeon_tfactor_alpha[] =
-{
- RADEON_ALPHA_ARG_A_TFACTOR_ALPHA,
- RADEON_ALPHA_ARG_A_TFACTOR_ALPHA | RADEON_COMP_ARG_A
-};
-
-static GLuint radeon_primary_alpha[] =
-{
- RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA,
- RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA | RADEON_COMP_ARG_A
-};
-
-static GLuint radeon_previous_alpha[] =
-{
- RADEON_ALPHA_ARG_A_CURRENT_ALPHA,
- RADEON_ALPHA_ARG_A_CURRENT_ALPHA | RADEON_COMP_ARG_A
-};
-
-/* GL_ZERO table - indices 0-1
- * GL_ONE table - indices 1-2
- */
-static GLuint radeon_zero_alpha[] =
-{
- RADEON_ALPHA_ARG_A_ZERO,
- RADEON_ALPHA_ARG_A_ZERO | RADEON_COMP_ARG_A,
- RADEON_ALPHA_ARG_A_ZERO
-};
-
-
-/* Extract the arg from slot A, shift it into the correct argument slot
- * and set the corresponding complement bit.
- */
-#define RADEON_COLOR_ARG( n, arg ) \
-do { \
- color_combine |= \
- ((color_arg[n] & RADEON_COLOR_ARG_MASK) \
- << RADEON_COLOR_ARG_##arg##_SHIFT); \
- color_combine |= \
- ((color_arg[n] >> RADEON_COMP_ARG_SHIFT) \
- << RADEON_COMP_ARG_##arg##_SHIFT); \
-} while (0)
-
-#define RADEON_ALPHA_ARG( n, arg ) \
-do { \
- alpha_combine |= \
- ((alpha_arg[n] & RADEON_ALPHA_ARG_MASK) \
- << RADEON_ALPHA_ARG_##arg##_SHIFT); \
- alpha_combine |= \
- ((alpha_arg[n] >> RADEON_COMP_ARG_SHIFT) \
- << RADEON_COMP_ARG_##arg##_SHIFT); \
-} while (0)
-
-
-/* ================================================================
- * Texture unit state management
- */
-
-static GLboolean radeonUpdateTextureEnv( GLcontext *ctx, int unit )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
- GLuint color_combine, alpha_combine;
- const GLuint color_combine0 = RADEON_COLOR_ARG_A_ZERO | RADEON_COLOR_ARG_B_ZERO
- | RADEON_COLOR_ARG_C_CURRENT_COLOR | RADEON_BLEND_CTL_ADD
- | RADEON_SCALE_1X | RADEON_CLAMP_TX;
- const GLuint alpha_combine0 = RADEON_ALPHA_ARG_A_ZERO | RADEON_ALPHA_ARG_B_ZERO
- | RADEON_ALPHA_ARG_C_CURRENT_ALPHA | RADEON_BLEND_CTL_ADD
- | RADEON_SCALE_1X | RADEON_CLAMP_TX;
-
-
- /* texUnit->_Current can be NULL if and only if the texture unit is
- * not actually enabled.
- */
- assert( (texUnit->_ReallyEnabled == 0)
- || (texUnit->_Current != NULL) );
-
- if ( RADEON_DEBUG & DEBUG_TEXTURE ) {
- fprintf( stderr, "%s( %p, %d )\n", __FUNCTION__, (void *)ctx, unit );
- }
-
- /* Set the texture environment state. Isn't this nice and clean?
- * The chip will automagically set the texture alpha to 0xff when
- * the texture format does not include an alpha component. This
- * reduces the amount of special-casing we have to do, alpha-only
- * textures being a notable exception.
- */
- /* Don't cache these results.
- */
- rmesa->state.texture.unit[unit].format = 0;
- rmesa->state.texture.unit[unit].envMode = 0;
-
- if ( !texUnit->_ReallyEnabled ) {
- color_combine = color_combine0;
- alpha_combine = alpha_combine0;
- }
- else {
- GLuint color_arg[3], alpha_arg[3];
- GLuint i;
- const GLuint numColorArgs = texUnit->_CurrentCombine->_NumArgsRGB;
- const GLuint numAlphaArgs = texUnit->_CurrentCombine->_NumArgsA;
- GLuint RGBshift = texUnit->_CurrentCombine->ScaleShiftRGB;
- GLuint Ashift = texUnit->_CurrentCombine->ScaleShiftA;
-
-
- /* Step 1:
- * Extract the color and alpha combine function arguments.
- */
- for ( i = 0 ; i < numColorArgs ; i++ ) {
- const GLint op = texUnit->_CurrentCombine->OperandRGB[i] - GL_SRC_COLOR;
- const GLuint srcRGBi = texUnit->_CurrentCombine->SourceRGB[i];
- assert(op >= 0);
- assert(op <= 3);
- switch ( srcRGBi ) {
- case GL_TEXTURE:
- color_arg[i] = radeon_texture_color[op][unit];
- break;
- case GL_CONSTANT:
- color_arg[i] = radeon_tfactor_color[op];
- break;
- case GL_PRIMARY_COLOR:
- color_arg[i] = radeon_primary_color[op];
- break;
- case GL_PREVIOUS:
- color_arg[i] = radeon_previous_color[op];
- break;
- case GL_ZERO:
- color_arg[i] = radeon_zero_color[op];
- break;
- case GL_ONE:
- color_arg[i] = radeon_zero_color[op+1];
- break;
- case GL_TEXTURE0:
- case GL_TEXTURE1:
- case GL_TEXTURE2:
- /* implement ogl 1.4/1.5 core spec here, not specification of
- * GL_ARB_texture_env_crossbar (which would require disabling blending
- * instead of undefined results when referencing not enabled texunit) */
- color_arg[i] = radeon_texture_color[op][srcRGBi - GL_TEXTURE0];
- break;
- default:
- return GL_FALSE;
- }
- }
-
- for ( i = 0 ; i < numAlphaArgs ; i++ ) {
- const GLint op = texUnit->_CurrentCombine->OperandA[i] - GL_SRC_ALPHA;
- const GLuint srcAi = texUnit->_CurrentCombine->SourceA[i];
- assert(op >= 0);
- assert(op <= 1);
- switch ( srcAi ) {
- case GL_TEXTURE:
- alpha_arg[i] = radeon_texture_alpha[op][unit];
- break;
- case GL_CONSTANT:
- alpha_arg[i] = radeon_tfactor_alpha[op];
- break;
- case GL_PRIMARY_COLOR:
- alpha_arg[i] = radeon_primary_alpha[op];
- break;
- case GL_PREVIOUS:
- alpha_arg[i] = radeon_previous_alpha[op];
- break;
- case GL_ZERO:
- alpha_arg[i] = radeon_zero_alpha[op];
- break;
- case GL_ONE:
- alpha_arg[i] = radeon_zero_alpha[op+1];
- break;
- case GL_TEXTURE0:
- case GL_TEXTURE1:
- case GL_TEXTURE2:
- alpha_arg[i] = radeon_texture_alpha[op][srcAi - GL_TEXTURE0];
- break;
- default:
- return GL_FALSE;
- }
- }
-
- /* Step 2:
- * Build up the color and alpha combine functions.
- */
- switch ( texUnit->_CurrentCombine->ModeRGB ) {
- case GL_REPLACE:
- color_combine = (RADEON_COLOR_ARG_A_ZERO |
- RADEON_COLOR_ARG_B_ZERO |
- RADEON_BLEND_CTL_ADD |
- RADEON_CLAMP_TX);
- RADEON_COLOR_ARG( 0, C );
- break;
- case GL_MODULATE:
- color_combine = (RADEON_COLOR_ARG_C_ZERO |
- RADEON_BLEND_CTL_ADD |
- RADEON_CLAMP_TX);
- RADEON_COLOR_ARG( 0, A );
- RADEON_COLOR_ARG( 1, B );
- break;
- case GL_ADD:
- color_combine = (RADEON_COLOR_ARG_B_ZERO |
- RADEON_COMP_ARG_B |
- RADEON_BLEND_CTL_ADD |
- RADEON_CLAMP_TX);
- RADEON_COLOR_ARG( 0, A );
- RADEON_COLOR_ARG( 1, C );
- break;
- case GL_ADD_SIGNED:
- color_combine = (RADEON_COLOR_ARG_B_ZERO |
- RADEON_COMP_ARG_B |
- RADEON_BLEND_CTL_ADDSIGNED |
- RADEON_CLAMP_TX);
- RADEON_COLOR_ARG( 0, A );
- RADEON_COLOR_ARG( 1, C );
- break;
- case GL_SUBTRACT:
- color_combine = (RADEON_COLOR_ARG_B_ZERO |
- RADEON_COMP_ARG_B |
- RADEON_BLEND_CTL_SUBTRACT |
- RADEON_CLAMP_TX);
- RADEON_COLOR_ARG( 0, A );
- RADEON_COLOR_ARG( 1, C );
- break;
- case GL_INTERPOLATE:
- color_combine = (RADEON_BLEND_CTL_BLEND |
- RADEON_CLAMP_TX);
- RADEON_COLOR_ARG( 0, B );
- RADEON_COLOR_ARG( 1, A );
- RADEON_COLOR_ARG( 2, C );
- break;
-
- case GL_DOT3_RGB_EXT:
- case GL_DOT3_RGBA_EXT:
- /* The EXT version of the DOT3 extension does not support the
- * scale factor, but the ARB version (and the version in OpenGL
- * 1.3) does.
- */
- RGBshift = 0;
- /* FALLTHROUGH */
-
- case GL_DOT3_RGB:
- case GL_DOT3_RGBA:
- /* The R100 / RV200 only support a 1X multiplier in hardware
- * w/the ARB version.
- */
- if ( RGBshift != (RADEON_SCALE_1X >> RADEON_SCALE_SHIFT) ) {
- return GL_FALSE;
- }
-
- RGBshift += 2;
- if ( (texUnit->_CurrentCombine->ModeRGB == GL_DOT3_RGBA_EXT)
- || (texUnit->_CurrentCombine->ModeRGB == GL_DOT3_RGBA) ) {
- /* is it necessary to set this or will it be ignored anyway? */
- Ashift = RGBshift;
- }
-
- color_combine = (RADEON_COLOR_ARG_C_ZERO |
- RADEON_BLEND_CTL_DOT3 |
- RADEON_CLAMP_TX);
- RADEON_COLOR_ARG( 0, A );
- RADEON_COLOR_ARG( 1, B );
- break;
-
- case GL_MODULATE_ADD_ATI:
- color_combine = (RADEON_BLEND_CTL_ADD |
- RADEON_CLAMP_TX);
- RADEON_COLOR_ARG( 0, A );
- RADEON_COLOR_ARG( 1, C );
- RADEON_COLOR_ARG( 2, B );
- break;
- case GL_MODULATE_SIGNED_ADD_ATI:
- color_combine = (RADEON_BLEND_CTL_ADDSIGNED |
- RADEON_CLAMP_TX);
- RADEON_COLOR_ARG( 0, A );
- RADEON_COLOR_ARG( 1, C );
- RADEON_COLOR_ARG( 2, B );
- break;
- case GL_MODULATE_SUBTRACT_ATI:
- color_combine = (RADEON_BLEND_CTL_SUBTRACT |
- RADEON_CLAMP_TX);
- RADEON_COLOR_ARG( 0, A );
- RADEON_COLOR_ARG( 1, C );
- RADEON_COLOR_ARG( 2, B );
- break;
- default:
- return GL_FALSE;
- }
-
- switch ( texUnit->_CurrentCombine->ModeA ) {
- case GL_REPLACE:
- alpha_combine = (RADEON_ALPHA_ARG_A_ZERO |
- RADEON_ALPHA_ARG_B_ZERO |
- RADEON_BLEND_CTL_ADD |
- RADEON_CLAMP_TX);
- RADEON_ALPHA_ARG( 0, C );
- break;
- case GL_MODULATE:
- alpha_combine = (RADEON_ALPHA_ARG_C_ZERO |
- RADEON_BLEND_CTL_ADD |
- RADEON_CLAMP_TX);
- RADEON_ALPHA_ARG( 0, A );
- RADEON_ALPHA_ARG( 1, B );
- break;
- case GL_ADD:
- alpha_combine = (RADEON_ALPHA_ARG_B_ZERO |
- RADEON_COMP_ARG_B |
- RADEON_BLEND_CTL_ADD |
- RADEON_CLAMP_TX);
- RADEON_ALPHA_ARG( 0, A );
- RADEON_ALPHA_ARG( 1, C );
- break;
- case GL_ADD_SIGNED:
- alpha_combine = (RADEON_ALPHA_ARG_B_ZERO |
- RADEON_COMP_ARG_B |
- RADEON_BLEND_CTL_ADDSIGNED |
- RADEON_CLAMP_TX);
- RADEON_ALPHA_ARG( 0, A );
- RADEON_ALPHA_ARG( 1, C );
- break;
- case GL_SUBTRACT:
- alpha_combine = (RADEON_COLOR_ARG_B_ZERO |
- RADEON_COMP_ARG_B |
- RADEON_BLEND_CTL_SUBTRACT |
- RADEON_CLAMP_TX);
- RADEON_ALPHA_ARG( 0, A );
- RADEON_ALPHA_ARG( 1, C );
- break;
- case GL_INTERPOLATE:
- alpha_combine = (RADEON_BLEND_CTL_BLEND |
- RADEON_CLAMP_TX);
- RADEON_ALPHA_ARG( 0, B );
- RADEON_ALPHA_ARG( 1, A );
- RADEON_ALPHA_ARG( 2, C );
- break;
-
- case GL_MODULATE_ADD_ATI:
- alpha_combine = (RADEON_BLEND_CTL_ADD |
- RADEON_CLAMP_TX);
- RADEON_ALPHA_ARG( 0, A );
- RADEON_ALPHA_ARG( 1, C );
- RADEON_ALPHA_ARG( 2, B );
- break;
- case GL_MODULATE_SIGNED_ADD_ATI:
- alpha_combine = (RADEON_BLEND_CTL_ADDSIGNED |
- RADEON_CLAMP_TX);
- RADEON_ALPHA_ARG( 0, A );
- RADEON_ALPHA_ARG( 1, C );
- RADEON_ALPHA_ARG( 2, B );
- break;
- case GL_MODULATE_SUBTRACT_ATI:
- alpha_combine = (RADEON_BLEND_CTL_SUBTRACT |
- RADEON_CLAMP_TX);
- RADEON_ALPHA_ARG( 0, A );
- RADEON_ALPHA_ARG( 1, C );
- RADEON_ALPHA_ARG( 2, B );
- break;
- default:
- return GL_FALSE;
- }
-
- if ( (texUnit->_CurrentCombine->ModeRGB == GL_DOT3_RGB_EXT)
- || (texUnit->_CurrentCombine->ModeRGB == GL_DOT3_RGB) ) {
- alpha_combine |= RADEON_DOT_ALPHA_DONT_REPLICATE;
- }
-
- /* Step 3:
- * Apply the scale factor.
- */
- color_combine |= (RGBshift << RADEON_SCALE_SHIFT);
- alpha_combine |= (Ashift << RADEON_SCALE_SHIFT);
-
- /* All done!
- */
- }
-
- if ( rmesa->hw.tex[unit].cmd[TEX_PP_TXCBLEND] != color_combine ||
- rmesa->hw.tex[unit].cmd[TEX_PP_TXABLEND] != alpha_combine ) {
- RADEON_STATECHANGE( rmesa, tex[unit] );
- rmesa->hw.tex[unit].cmd[TEX_PP_TXCBLEND] = color_combine;
- rmesa->hw.tex[unit].cmd[TEX_PP_TXABLEND] = alpha_combine;
- }
-
- return GL_TRUE;
-}
-
-#define TEXOBJ_TXFILTER_MASK (RADEON_MAX_MIP_LEVEL_MASK | \
- RADEON_MIN_FILTER_MASK | \
- RADEON_MAG_FILTER_MASK | \
- RADEON_MAX_ANISO_MASK | \
- RADEON_YUV_TO_RGB | \
- RADEON_YUV_TEMPERATURE_MASK | \
- RADEON_CLAMP_S_MASK | \
- RADEON_CLAMP_T_MASK | \
- RADEON_BORDER_MODE_D3D )
-
-#define TEXOBJ_TXFORMAT_MASK (RADEON_TXFORMAT_WIDTH_MASK | \
- RADEON_TXFORMAT_HEIGHT_MASK | \
- RADEON_TXFORMAT_FORMAT_MASK | \
- RADEON_TXFORMAT_F5_WIDTH_MASK | \
- RADEON_TXFORMAT_F5_HEIGHT_MASK | \
- RADEON_TXFORMAT_ALPHA_IN_MAP | \
- RADEON_TXFORMAT_CUBIC_MAP_ENABLE | \
- RADEON_TXFORMAT_NON_POWER2)
-
-
-static void import_tex_obj_state( radeonContextPtr rmesa,
- int unit,
- radeonTexObjPtr texobj )
-{
- GLuint *cmd = RADEON_DB_STATE( tex[unit] );
-
- cmd[TEX_PP_TXFILTER] &= ~TEXOBJ_TXFILTER_MASK;
- cmd[TEX_PP_TXFILTER] |= texobj->pp_txfilter & TEXOBJ_TXFILTER_MASK;
- cmd[TEX_PP_TXFORMAT] &= ~TEXOBJ_TXFORMAT_MASK;
- cmd[TEX_PP_TXFORMAT] |= texobj->pp_txformat & TEXOBJ_TXFORMAT_MASK;
- cmd[TEX_PP_TXOFFSET] = texobj->pp_txoffset;
- cmd[TEX_PP_BORDER_COLOR] = texobj->pp_border_color;
- RADEON_DB_STATECHANGE( rmesa, &rmesa->hw.tex[unit] );
-
- if (texobj->base.tObj->Target == GL_TEXTURE_RECTANGLE_NV) {
- GLuint *txr_cmd = RADEON_DB_STATE( txr[unit] );
- txr_cmd[TXR_PP_TEX_SIZE] = texobj->pp_txsize; /* NPOT only! */
- txr_cmd[TXR_PP_TEX_PITCH] = texobj->pp_txpitch; /* NPOT only! */
- RADEON_DB_STATECHANGE( rmesa, &rmesa->hw.txr[unit] );
- }
-
- texobj->dirty_state &= ~(1<<unit);
-}
-
-
-
-
-static void set_texgen_matrix( radeonContextPtr rmesa,
- GLuint unit,
- const GLfloat *s_plane,
- const GLfloat *t_plane )
-{
- static const GLfloat scale_identity[4] = { 1,1,1,1 };
-
- if (!TEST_EQ_4V( s_plane, scale_identity) ||
- !TEST_EQ_4V( t_plane, scale_identity)) {
- rmesa->TexGenEnabled |= RADEON_TEXMAT_0_ENABLE<<unit;
- rmesa->TexGenMatrix[unit].m[0] = s_plane[0];
- rmesa->TexGenMatrix[unit].m[4] = s_plane[1];
- rmesa->TexGenMatrix[unit].m[8] = s_plane[2];
- rmesa->TexGenMatrix[unit].m[12] = s_plane[3];
-
- rmesa->TexGenMatrix[unit].m[1] = t_plane[0];
- rmesa->TexGenMatrix[unit].m[5] = t_plane[1];
- rmesa->TexGenMatrix[unit].m[9] = t_plane[2];
- rmesa->TexGenMatrix[unit].m[13] = t_plane[3];
- rmesa->NewGLState |= _NEW_TEXTURE_MATRIX;
- }
-}
-
-/* Ignoring the Q texcoord for now.
- *
- * Returns GL_FALSE if fallback required.
- */
-static GLboolean radeon_validate_texgen( GLcontext *ctx, GLuint unit )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
- GLuint inputshift = RADEON_TEXGEN_0_INPUT_SHIFT + unit*4;
- GLuint tmp = rmesa->TexGenEnabled;
-
- rmesa->TexGenEnabled &= ~(RADEON_TEXGEN_TEXMAT_0_ENABLE<<unit);
- rmesa->TexGenEnabled &= ~(RADEON_TEXMAT_0_ENABLE<<unit);
- rmesa->TexGenEnabled &= ~(RADEON_TEXGEN_INPUT_MASK<<inputshift);
- rmesa->TexGenNeedNormals[unit] = 0;
-
- if ((texUnit->TexGenEnabled & (S_BIT|T_BIT)) == 0) {
- /* Disabled, no fallback:
- */
- rmesa->TexGenEnabled |=
- (RADEON_TEXGEN_INPUT_TEXCOORD_0+unit) << inputshift;
- return GL_TRUE;
- }
- else if (texUnit->TexGenEnabled & Q_BIT) {
- /* Very easy to do this, in fact would remove a fallback case
- * elsewhere, but I haven't done it yet... Fallback:
- */
- if (RADEON_DEBUG & DEBUG_FALLBACKS)
- fprintf(stderr, "fallback Q_BIT\n");
- return GL_FALSE;
- }
- else if ((texUnit->TexGenEnabled & (S_BIT|T_BIT)) != (S_BIT|T_BIT) ||
- texUnit->GenModeS != texUnit->GenModeT) {
- /* Mixed modes, fallback:
- */
- if (RADEON_DEBUG & DEBUG_FALLBACKS)
- fprintf(stderr, "fallback mixed texgen\n");
- return GL_FALSE;
- }
- else
- rmesa->TexGenEnabled |= RADEON_TEXGEN_TEXMAT_0_ENABLE << unit;
-
- switch (texUnit->GenModeS) {
- case GL_OBJECT_LINEAR:
- rmesa->TexGenEnabled |= RADEON_TEXGEN_INPUT_OBJ << inputshift;
- set_texgen_matrix( rmesa, unit,
- texUnit->ObjectPlaneS,
- texUnit->ObjectPlaneT);
- break;
-
- case GL_EYE_LINEAR:
- rmesa->TexGenEnabled |= RADEON_TEXGEN_INPUT_EYE << inputshift;
- set_texgen_matrix( rmesa, unit,
- texUnit->EyePlaneS,
- texUnit->EyePlaneT);
- break;
-
- case GL_REFLECTION_MAP_NV:
- rmesa->TexGenNeedNormals[unit] = GL_TRUE;
- rmesa->TexGenEnabled |= RADEON_TEXGEN_INPUT_EYE_REFLECT<<inputshift;
- break;
-
- case GL_NORMAL_MAP_NV:
- rmesa->TexGenNeedNormals[unit] = GL_TRUE;
- rmesa->TexGenEnabled |= RADEON_TEXGEN_INPUT_EYE_NORMAL<<inputshift;
- break;
-
- case GL_SPHERE_MAP:
- default:
- /* Unsupported mode, fallback:
- */
- if (RADEON_DEBUG & DEBUG_FALLBACKS)
- fprintf(stderr, "fallback GL_SPHERE_MAP\n");
- return GL_FALSE;
- }
-
- if (tmp != rmesa->TexGenEnabled) {
- rmesa->NewGLState |= _NEW_TEXTURE_MATRIX;
- }
-
- return GL_TRUE;
-}
-
-
-static void disable_tex( GLcontext *ctx, int unit )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-
- if (rmesa->hw.ctx.cmd[CTX_PP_CNTL] & (RADEON_TEX_0_ENABLE<<unit)) {
- /* Texture unit disabled */
- if ( rmesa->state.texture.unit[unit].texobj != NULL ) {
- /* The old texture is no longer bound to this texture unit.
- * Mark it as such.
- */
-
- rmesa->state.texture.unit[unit].texobj->base.bound &= ~(1UL << unit);
- rmesa->state.texture.unit[unit].texobj = NULL;
- }
-
- RADEON_STATECHANGE( rmesa, ctx );
- rmesa->hw.ctx.cmd[CTX_PP_CNTL] &=
- ~((RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE) << unit);
-
- RADEON_STATECHANGE( rmesa, tcl );
- switch (unit) {
- case 0:
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] &= ~(RADEON_TCL_VTX_ST0 |
- RADEON_TCL_VTX_Q0);
- break;
- case 1:
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] &= ~(RADEON_TCL_VTX_ST1 |
- RADEON_TCL_VTX_Q1);
- break;
- default:
- break;
- }
-
-
- if (rmesa->TclFallback & (RADEON_TCL_FALLBACK_TEXGEN_0<<unit)) {
- TCL_FALLBACK( ctx, (RADEON_TCL_FALLBACK_TEXGEN_0<<unit), GL_FALSE);
- rmesa->recheck_texgen[unit] = GL_TRUE;
- }
-
-
-
- {
- GLuint inputshift = RADEON_TEXGEN_0_INPUT_SHIFT + unit*4;
- GLuint tmp = rmesa->TexGenEnabled;
-
- rmesa->TexGenEnabled &= ~(RADEON_TEXGEN_TEXMAT_0_ENABLE<<unit);
- rmesa->TexGenEnabled &= ~(RADEON_TEXMAT_0_ENABLE<<unit);
- rmesa->TexGenEnabled &= ~(RADEON_TEXGEN_INPUT_MASK<<inputshift);
- rmesa->TexGenNeedNormals[unit] = 0;
- rmesa->TexGenEnabled |=
- (RADEON_TEXGEN_INPUT_TEXCOORD_0+unit) << inputshift;
-
- if (tmp != rmesa->TexGenEnabled) {
- rmesa->recheck_texgen[unit] = GL_TRUE;
- rmesa->NewGLState |= _NEW_TEXTURE_MATRIX;
- }
- }
- }
-}
-
-static GLboolean enable_tex_2d( GLcontext *ctx, int unit )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
- struct gl_texture_object *tObj = texUnit->_Current;
- radeonTexObjPtr t = (radeonTexObjPtr) tObj->DriverData;
-
- /* Need to load the 2d images associated with this unit.
- */
- if (t->pp_txformat & RADEON_TXFORMAT_NON_POWER2) {
- t->pp_txformat &= ~RADEON_TXFORMAT_NON_POWER2;
- t->base.dirty_images[0] = ~0;
- }
-
- ASSERT(tObj->Target == GL_TEXTURE_2D || tObj->Target == GL_TEXTURE_1D);
-
- if ( t->base.dirty_images[0] ) {
- RADEON_FIREVERTICES( rmesa );
- radeonSetTexImages( rmesa, tObj );
- radeonUploadTexImages( rmesa, (radeonTexObjPtr) tObj->DriverData, 0 );
- if ( !t->base.memBlock )
- return GL_FALSE;
- }
-
- return GL_TRUE;
-}
-
-static GLboolean enable_tex_rect( GLcontext *ctx, int unit )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
- struct gl_texture_object *tObj = texUnit->_Current;
- radeonTexObjPtr t = (radeonTexObjPtr) tObj->DriverData;
-
- if (!(t->pp_txformat & RADEON_TXFORMAT_NON_POWER2)) {
- t->pp_txformat |= RADEON_TXFORMAT_NON_POWER2;
- t->base.dirty_images[0] = ~0;
- }
-
- ASSERT(tObj->Target == GL_TEXTURE_RECTANGLE_NV);
-
- if ( t->base.dirty_images[0] ) {
- RADEON_FIREVERTICES( rmesa );
- radeonSetTexImages( rmesa, tObj );
- radeonUploadTexImages( rmesa, (radeonTexObjPtr) tObj->DriverData, 0 );
- if ( !t->base.memBlock /* && !rmesa->prefer_gart_client_texturing FIXME */ ) {
- fprintf(stderr, "%s: upload failed\n", __FUNCTION__);
- return GL_FALSE;
- }
- }
-
- return GL_TRUE;
-}
-
-
-static GLboolean update_tex_common( GLcontext *ctx, int unit )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
- struct gl_texture_object *tObj = texUnit->_Current;
- radeonTexObjPtr t = (radeonTexObjPtr) tObj->DriverData;
- GLenum format;
-
- /* Fallback if there's a texture border */
- if ( tObj->Image[0][tObj->BaseLevel]->Border > 0 ) {
- fprintf(stderr, "%s: border\n", __FUNCTION__);
- return GL_FALSE;
- }
-
- /* Update state if this is a different texture object to last
- * time.
- */
- if ( rmesa->state.texture.unit[unit].texobj != t ) {
- if ( rmesa->state.texture.unit[unit].texobj != NULL ) {
- /* The old texture is no longer bound to this texture unit.
- * Mark it as such.
- */
-
- rmesa->state.texture.unit[unit].texobj->base.bound &=
- ~(1UL << unit);
- }
-
- rmesa->state.texture.unit[unit].texobj = t;
- t->base.bound |= (1UL << unit);
- t->dirty_state |= 1<<unit;
- driUpdateTextureLRU( (driTextureObject *) t ); /* XXX: should be locked! */
- }
-
-
- /* Newly enabled?
- */
- if ( !(rmesa->hw.ctx.cmd[CTX_PP_CNTL] & (RADEON_TEX_0_ENABLE<<unit))) {
- RADEON_STATECHANGE( rmesa, ctx );
- rmesa->hw.ctx.cmd[CTX_PP_CNTL] |=
- (RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE) << unit;
-
- RADEON_STATECHANGE( rmesa, tcl );
-
- if (unit == 0)
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_TCL_VTX_ST0;
- else
- rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_TCL_VTX_ST1;
-
- rmesa->recheck_texgen[unit] = GL_TRUE;
- }
-
- if (t->dirty_state & (1<<unit)) {
- import_tex_obj_state( rmesa, unit, t );
- }
-
- if (rmesa->recheck_texgen[unit]) {
- GLboolean fallback = !radeon_validate_texgen( ctx, unit );
- TCL_FALLBACK( ctx, (RADEON_TCL_FALLBACK_TEXGEN_0<<unit), fallback);
- rmesa->recheck_texgen[unit] = 0;
- rmesa->NewGLState |= _NEW_TEXTURE_MATRIX;
- }
-
- format = tObj->Image[0][tObj->BaseLevel]->Format;
- if ( rmesa->state.texture.unit[unit].format != format ||
- rmesa->state.texture.unit[unit].envMode != texUnit->EnvMode ) {
- rmesa->state.texture.unit[unit].format = format;
- rmesa->state.texture.unit[unit].envMode = texUnit->EnvMode;
- if ( ! radeonUpdateTextureEnv( ctx, unit ) ) {
- return GL_FALSE;
- }
- }
-
- FALLBACK( rmesa, RADEON_FALLBACK_BORDER_MODE, t->border_fallback );
- return !t->border_fallback;
-}
-
-
-
-static GLboolean radeonUpdateTextureUnit( GLcontext *ctx, int unit )
-{
- struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
-
- TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_TEXRECT_0 << unit, 0 );
-
- if ( texUnit->_ReallyEnabled & (TEXTURE_RECT_BIT) ) {
- TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_TEXRECT_0 << unit, 1 );
-
- return (enable_tex_rect( ctx, unit ) &&
- update_tex_common( ctx, unit ));
- }
- else if ( texUnit->_ReallyEnabled & (TEXTURE_1D_BIT | TEXTURE_2D_BIT) ) {
- return (enable_tex_2d( ctx, unit ) &&
- update_tex_common( ctx, unit ));
- }
- else if ( texUnit->_ReallyEnabled ) {
- return GL_FALSE;
- }
- else {
- disable_tex( ctx, unit );
- return GL_TRUE;
- }
-}
-
-void radeonUpdateTextureState( GLcontext *ctx )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLboolean ok;
-
- ok = (radeonUpdateTextureUnit( ctx, 0 ) &&
- radeonUpdateTextureUnit( ctx, 1 ));
-
- FALLBACK( rmesa, RADEON_FALLBACK_TEXTURE, !ok );
-
- if (rmesa->TclFallback)
- radeonChooseVertexState( ctx );
-}
diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_vtxfmt.c b/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_vtxfmt.c
deleted file mode 100644
index 5a4cad8ba..000000000
--- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_vtxfmt.c
+++ /dev/null
@@ -1,1093 +0,0 @@
-/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_vtxfmt.c,v 1.6 2003/05/06 23:52:08 daenzer Exp $ */
-/**************************************************************************
-
-Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
- Tungsten Graphics Inc., Cedar Park, Texas.
-
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/*
- * Authors:
- * Keith Whitwell <keith@tungstengraphics.com>
- */
-#include "glheader.h"
-#include "imports.h"
-#include "api_noop.h"
-#include "api_arrayelt.h"
-#include "context.h"
-#include "mtypes.h"
-#include "enums.h"
-#include "glapi.h"
-#include "colormac.h"
-#include "light.h"
-#include "state.h"
-#include "vtxfmt.h"
-
-#include "tnl/tnl.h"
-#include "tnl/t_context.h"
-#include "tnl/t_array_api.h"
-
-#include "radeon_context.h"
-#include "radeon_state.h"
-#include "radeon_ioctl.h"
-#include "radeon_tex.h"
-#include "radeon_tcl.h"
-#include "radeon_swtcl.h"
-#include "radeon_vtxfmt.h"
-
-#include "dispatch.h"
-
-static void radeonVtxfmtFlushVertices( GLcontext *, GLuint );
-
-static void count_func( const char *name, struct dynfn *l )
-{
- int i = 0;
- struct dynfn *f;
- foreach (f, l) i++;
- if (i) fprintf(stderr, "%s: %d\n", name, i );
-}
-
-static void count_funcs( radeonContextPtr rmesa )
-{
- count_func( "Vertex2f", &rmesa->vb.dfn_cache.Vertex2f );
- count_func( "Vertex2fv", &rmesa->vb.dfn_cache.Vertex2fv );
- count_func( "Vertex3f", &rmesa->vb.dfn_cache.Vertex3f );
- count_func( "Vertex3fv", &rmesa->vb.dfn_cache.Vertex3fv );
- count_func( "Color4ub", &rmesa->vb.dfn_cache.Color4ub );
- count_func( "Color4ubv", &rmesa->vb.dfn_cache.Color4ubv );
- count_func( "Color3ub", &rmesa->vb.dfn_cache.Color3ub );
- count_func( "Color3ubv", &rmesa->vb.dfn_cache.Color3ubv );
- count_func( "Color4f", &rmesa->vb.dfn_cache.Color4f );
- count_func( "Color4fv", &rmesa->vb.dfn_cache.Color4fv );
- count_func( "Color3f", &rmesa->vb.dfn_cache.Color3f );
- count_func( "Color3fv", &rmesa->vb.dfn_cache.Color3fv );
- count_func( "SecondaryColor3f", &rmesa->vb.dfn_cache.SecondaryColor3fEXT );
- count_func( "SecondaryColor3fv", &rmesa->vb.dfn_cache.SecondaryColor3fvEXT );
- count_func( "SecondaryColor3ub", &rmesa->vb.dfn_cache.SecondaryColor3ubEXT );
- count_func( "SecondaryColor3ubv", &rmesa->vb.dfn_cache.SecondaryColor3ubvEXT );
- count_func( "Normal3f", &rmesa->vb.dfn_cache.Normal3f );
- count_func( "Normal3fv", &rmesa->vb.dfn_cache.Normal3fv );
- count_func( "TexCoord2f", &rmesa->vb.dfn_cache.TexCoord2f );
- count_func( "TexCoord2fv", &rmesa->vb.dfn_cache.TexCoord2fv );
- count_func( "TexCoord1f", &rmesa->vb.dfn_cache.TexCoord1f );
- count_func( "TexCoord1fv", &rmesa->vb.dfn_cache.TexCoord1fv );
- count_func( "MultiTexCoord2fARB", &rmesa->vb.dfn_cache.MultiTexCoord2fARB );
- count_func( "MultiTexCoord2fvARB", &rmesa->vb.dfn_cache.MultiTexCoord2fvARB );
- count_func( "MultiTexCoord1fARB", &rmesa->vb.dfn_cache.MultiTexCoord1fARB );
- count_func( "MultiTexCoord1fvARB", &rmesa->vb.dfn_cache.MultiTexCoord1fvARB );
-}
-
-
-void radeon_copy_to_current( GLcontext *ctx )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-
- assert(ctx->Driver.NeedFlush & FLUSH_UPDATE_CURRENT);
-
- if (rmesa->vb.vertex_format & RADEON_CP_VC_FRMT_N0) {
- ctx->Current.Attrib[VERT_ATTRIB_NORMAL][0] = rmesa->vb.normalptr[0];
- ctx->Current.Attrib[VERT_ATTRIB_NORMAL][1] = rmesa->vb.normalptr[1];
- ctx->Current.Attrib[VERT_ATTRIB_NORMAL][2] = rmesa->vb.normalptr[2];
- }
-
- if (rmesa->vb.vertex_format & RADEON_CP_VC_FRMT_PKCOLOR) {
- ctx->Current.Attrib[VERT_ATTRIB_COLOR0][0] = UBYTE_TO_FLOAT( rmesa->vb.colorptr->red );
- ctx->Current.Attrib[VERT_ATTRIB_COLOR0][1] = UBYTE_TO_FLOAT( rmesa->vb.colorptr->green );
- ctx->Current.Attrib[VERT_ATTRIB_COLOR0][2] = UBYTE_TO_FLOAT( rmesa->vb.colorptr->blue );
- ctx->Current.Attrib[VERT_ATTRIB_COLOR0][3] = UBYTE_TO_FLOAT( rmesa->vb.colorptr->alpha );
- }
-
- if (rmesa->vb.vertex_format & RADEON_CP_VC_FRMT_FPCOLOR) {
- ctx->Current.Attrib[VERT_ATTRIB_COLOR0][0] = rmesa->vb.floatcolorptr[0];
- ctx->Current.Attrib[VERT_ATTRIB_COLOR0][1] = rmesa->vb.floatcolorptr[1];
- ctx->Current.Attrib[VERT_ATTRIB_COLOR0][2] = rmesa->vb.floatcolorptr[2];
- }
-
- if (rmesa->vb.vertex_format & RADEON_CP_VC_FRMT_FPALPHA)
- ctx->Current.Attrib[VERT_ATTRIB_COLOR0][3] = rmesa->vb.floatcolorptr[3];
-
- if (rmesa->vb.vertex_format & RADEON_CP_VC_FRMT_PKSPEC) {
- ctx->Current.Attrib[VERT_ATTRIB_COLOR1][0] = UBYTE_TO_FLOAT( rmesa->vb.specptr->red );
- ctx->Current.Attrib[VERT_ATTRIB_COLOR1][1] = UBYTE_TO_FLOAT( rmesa->vb.specptr->green );
- ctx->Current.Attrib[VERT_ATTRIB_COLOR1][2] = UBYTE_TO_FLOAT( rmesa->vb.specptr->blue );
- }
-
- if (rmesa->vb.vertex_format & RADEON_CP_VC_FRMT_ST0) {
- ctx->Current.Attrib[VERT_ATTRIB_TEX0][0] = rmesa->vb.texcoordptr[0][0];
- ctx->Current.Attrib[VERT_ATTRIB_TEX0][1] = rmesa->vb.texcoordptr[0][1];
- ctx->Current.Attrib[VERT_ATTRIB_TEX0][2] = 0.0F;
- ctx->Current.Attrib[VERT_ATTRIB_TEX0][3] = 1.0F;
- }
-
- if (rmesa->vb.vertex_format & RADEON_CP_VC_FRMT_ST1) {
- ctx->Current.Attrib[VERT_ATTRIB_TEX1][0] = rmesa->vb.texcoordptr[1][0];
- ctx->Current.Attrib[VERT_ATTRIB_TEX1][1] = rmesa->vb.texcoordptr[1][1];
- ctx->Current.Attrib[VERT_ATTRIB_TEX1][2] = 0.0F;
- ctx->Current.Attrib[VERT_ATTRIB_TEX1][3] = 1.0F;
- }
-
- ctx->Driver.NeedFlush &= ~FLUSH_UPDATE_CURRENT;
-}
-
-static GLboolean discreet_gl_prim[GL_POLYGON+1] = {
- 1, /* 0 points */
- 1, /* 1 lines */
- 0, /* 2 line_strip */
- 0, /* 3 line_loop */
- 1, /* 4 tris */
- 0, /* 5 tri_fan */
- 0, /* 6 tri_strip */
- 1, /* 7 quads */
- 0, /* 8 quadstrip */
- 0, /* 9 poly */
-};
-
-static void flush_prims( radeonContextPtr rmesa )
-{
- int i,j;
- struct radeon_dma_region tmp = rmesa->dma.current;
-
- tmp.buf->refcount++;
- tmp.aos_size = rmesa->vb.vertex_size;
- tmp.aos_stride = rmesa->vb.vertex_size;
- tmp.aos_start = GET_START(&tmp);
-
- rmesa->dma.current.ptr = rmesa->dma.current.start +=
- (rmesa->vb.initial_counter - rmesa->vb.counter) * rmesa->vb.vertex_size * 4;
-
- rmesa->tcl.vertex_format = rmesa->vb.vertex_format;
- rmesa->tcl.aos_components[0] = &tmp;
- rmesa->tcl.nr_aos_components = 1;
- rmesa->dma.flush = NULL;
-
- /* Optimize the primitive list:
- */
- if (rmesa->vb.nrprims > 1) {
- for (j = 0, i = 1 ; i < rmesa->vb.nrprims; i++) {
- int pj = rmesa->vb.primlist[j].prim & 0xf;
- int pi = rmesa->vb.primlist[i].prim & 0xf;
-
- if (pj == pi && discreet_gl_prim[pj] &&
- rmesa->vb.primlist[i].start == rmesa->vb.primlist[j].end) {
- rmesa->vb.primlist[j].end = rmesa->vb.primlist[i].end;
- }
- else {
- j++;
- if (j != i) rmesa->vb.primlist[j] = rmesa->vb.primlist[i];
- }
- }
- rmesa->vb.nrprims = j+1;
- }
-
- for (i = 0 ; i < rmesa->vb.nrprims; i++) {
- if (RADEON_DEBUG & DEBUG_PRIMS)
- fprintf(stderr, "vtxfmt prim %d: %s %d..%d\n", i,
- _mesa_lookup_enum_by_nr( rmesa->vb.primlist[i].prim &
- PRIM_MODE_MASK ),
- rmesa->vb.primlist[i].start,
- rmesa->vb.primlist[i].end);
-
- radeonEmitPrimitive( rmesa->glCtx,
- rmesa->vb.primlist[i].start,
- rmesa->vb.primlist[i].end,
- rmesa->vb.primlist[i].prim );
- }
-
- rmesa->vb.nrprims = 0;
- radeonReleaseDmaRegion( rmesa, &tmp, __FUNCTION__ );
-}
-
-
-static void start_prim( radeonContextPtr rmesa, GLuint mode )
-{
- if (RADEON_DEBUG & DEBUG_VFMT)
- fprintf(stderr, "%s %d\n", __FUNCTION__, rmesa->vb.initial_counter - rmesa->vb.counter);
-
- rmesa->vb.primlist[rmesa->vb.nrprims].start = rmesa->vb.initial_counter - rmesa->vb.counter;
- rmesa->vb.primlist[rmesa->vb.nrprims].prim = mode;
-}
-
-static void note_last_prim( radeonContextPtr rmesa, GLuint flags )
-{
- if (RADEON_DEBUG & DEBUG_VFMT)
- fprintf(stderr, "%s %d\n", __FUNCTION__, rmesa->vb.initial_counter - rmesa->vb.counter);
-
- if (rmesa->vb.prim[0] != GL_POLYGON+1) {
- rmesa->vb.primlist[rmesa->vb.nrprims].prim |= flags;
- rmesa->vb.primlist[rmesa->vb.nrprims].end = rmesa->vb.initial_counter - rmesa->vb.counter;
-
- if (++(rmesa->vb.nrprims) == RADEON_MAX_PRIMS)
- flush_prims( rmesa );
- }
-}
-
-
-static void copy_vertex( radeonContextPtr rmesa, GLuint n, GLfloat *dst )
-{
- GLuint i;
- GLfloat *src = (GLfloat *)(rmesa->dma.current.address +
- rmesa->dma.current.ptr +
- (rmesa->vb.primlist[rmesa->vb.nrprims].start + n) *
- rmesa->vb.vertex_size * 4);
-
- if (RADEON_DEBUG & DEBUG_VFMT)
- fprintf(stderr, "copy_vertex %d\n", rmesa->vb.primlist[rmesa->vb.nrprims].start + n);
-
- for (i = 0 ; i < rmesa->vb.vertex_size; i++) {
- dst[i] = src[i];
- }
-}
-
-/* NOTE: This actually reads the copied vertices back from uncached
- * memory. Could also use the counter/notify mechanism to populate
- * tmp on the fly as vertices are generated.
- */
-static GLuint copy_dma_verts( radeonContextPtr rmesa, GLfloat (*tmp)[15] )
-{
- GLuint ovf, i;
- GLuint nr = (rmesa->vb.initial_counter - rmesa->vb.counter) - rmesa->vb.primlist[rmesa->vb.nrprims].start;
-
- if (RADEON_DEBUG & DEBUG_VFMT)
- fprintf(stderr, "%s %d verts\n", __FUNCTION__, nr);
-
- switch( rmesa->vb.prim[0] )
- {
- case GL_POINTS:
- return 0;
- case GL_LINES:
- ovf = nr&1;
- for (i = 0 ; i < ovf ; i++)
- copy_vertex( rmesa, nr-ovf+i, tmp[i] );
- return i;
- case GL_TRIANGLES:
- ovf = nr%3;
- for (i = 0 ; i < ovf ; i++)
- copy_vertex( rmesa, nr-ovf+i, tmp[i] );
- return i;
- case GL_QUADS:
- ovf = nr&3;
- for (i = 0 ; i < ovf ; i++)
- copy_vertex( rmesa, nr-ovf+i, tmp[i] );
- return i;
- case GL_LINE_STRIP:
- if (nr == 0)
- return 0;
- copy_vertex( rmesa, nr-1, tmp[0] );
- return 1;
- case GL_LINE_LOOP:
- case GL_TRIANGLE_FAN:
- case GL_POLYGON:
- if (nr == 0)
- return 0;
- else if (nr == 1) {
- copy_vertex( rmesa, 0, tmp[0] );
- return 1;
- } else {
- copy_vertex( rmesa, 0, tmp[0] );
- copy_vertex( rmesa, nr-1, tmp[1] );
- return 2;
- }
- case GL_TRIANGLE_STRIP:
- ovf = MIN2(nr, 2);
- for (i = 0 ; i < ovf ; i++)
- copy_vertex( rmesa, nr-ovf+i, tmp[i] );
- return i;
- case GL_QUAD_STRIP:
- switch (nr) {
- case 0: ovf = 0; break;
- case 1: ovf = 1; break;
- default: ovf = 2 + (nr&1); break;
- }
- for (i = 0 ; i < ovf ; i++)
- copy_vertex( rmesa, nr-ovf+i, tmp[i] );
- return i;
- default:
- assert(0);
- return 0;
- }
-}
-
-static void VFMT_FALLBACK_OUTSIDE_BEGIN_END( const char *caller )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-
- if (RADEON_DEBUG & (DEBUG_VFMT|DEBUG_FALLBACKS))
- fprintf(stderr, "%s from %s\n", __FUNCTION__, caller);
-
- if (ctx->Driver.NeedFlush)
- radeonVtxfmtFlushVertices( ctx, ctx->Driver.NeedFlush );
-
- if (ctx->NewState)
- _mesa_update_state( ctx ); /* clear state so fell_back sticks */
-
- _tnl_wakeup_exec( ctx );
- ctx->Driver.FlushVertices = radeonFlushVertices;
-
- assert( rmesa->dma.flush == 0 );
- rmesa->vb.fell_back = GL_TRUE;
- rmesa->vb.installed = GL_FALSE;
-}
-
-
-static void VFMT_FALLBACK( const char *caller )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLfloat tmp[3][15];
- GLuint i, prim;
- GLuint ind = rmesa->vb.vertex_format;
- GLuint nrverts;
- GLfloat alpha = 1.0;
-
- if (RADEON_DEBUG & (DEBUG_FALLBACKS|DEBUG_VFMT))
- fprintf(stderr, "%s from %s\n", __FUNCTION__, caller);
-
- if (rmesa->vb.prim[0] == GL_POLYGON+1) {
- VFMT_FALLBACK_OUTSIDE_BEGIN_END( __FUNCTION__ );
- return;
- }
-
- /* Copy vertices out of dma:
- */
- nrverts = copy_dma_verts( rmesa, tmp );
-
- /* Finish the prim at this point:
- */
- note_last_prim( rmesa, 0 );
- flush_prims( rmesa );
-
- /* Update ctx->Driver.CurrentExecPrimitive and swap in swtnl.
- */
- prim = rmesa->vb.prim[0];
- ctx->Driver.CurrentExecPrimitive = GL_POLYGON+1;
- _tnl_wakeup_exec( ctx );
- ctx->Driver.FlushVertices = radeonFlushVertices;
-
- assert(rmesa->dma.flush == 0);
- rmesa->vb.fell_back = GL_TRUE;
- rmesa->vb.installed = GL_FALSE;
- CALL_Begin(GET_DISPATCH(), (prim));
-
- if (rmesa->vb.installed_color_3f_sz == 4)
- alpha = ctx->Current.Attrib[VERT_ATTRIB_COLOR0][3];
-
- /* Replay saved vertices
- */
- for (i = 0 ; i < nrverts; i++) {
- GLuint offset = 3;
- if (ind & RADEON_CP_VC_FRMT_N0) {
- CALL_Normal3fv(GET_DISPATCH(), (&tmp[i][offset]));
- offset += 3;
- }
-
- if (ind & RADEON_CP_VC_FRMT_PKCOLOR) {
- radeon_color_t *col = (radeon_color_t *)&tmp[i][offset];
- CALL_Color4ub(GET_DISPATCH(), (col->red, col->green, col->blue, col->alpha));
- offset++;
- }
- else if (ind & RADEON_CP_VC_FRMT_FPALPHA) {
- CALL_Color4fv(GET_DISPATCH(), (&tmp[i][offset]));
- offset+=4;
- }
- else if (ind & RADEON_CP_VC_FRMT_FPCOLOR) {
- CALL_Color3fv(GET_DISPATCH(), (&tmp[i][offset]));
- offset+=3;
- }
-
- if (ind & RADEON_CP_VC_FRMT_PKSPEC) {
- radeon_color_t *spec = (radeon_color_t *)&tmp[i][offset];
- CALL_SecondaryColor3ubEXT(GET_DISPATCH(), (spec->red, spec->green, spec->blue));
- offset++;
- }
-
- if (ind & RADEON_CP_VC_FRMT_ST0) {
- CALL_TexCoord2fv(GET_DISPATCH(), (&tmp[i][offset]));
- offset += 2;
- }
-
- if (ind & RADEON_CP_VC_FRMT_ST1) {
- CALL_MultiTexCoord2fvARB(GET_DISPATCH(), (GL_TEXTURE1_ARB, &tmp[i][offset]));
- offset += 2;
- }
- CALL_Vertex3fv(GET_DISPATCH(), (&tmp[i][0]));
- }
-
- /* Replay current vertex
- */
- if (ind & RADEON_CP_VC_FRMT_N0)
- CALL_Normal3fv(GET_DISPATCH(), (rmesa->vb.normalptr));
-
- if (ind & RADEON_CP_VC_FRMT_PKCOLOR)
- CALL_Color4ub(GET_DISPATCH(), (rmesa->vb.colorptr->red, rmesa->vb.colorptr->green, rmesa->vb.colorptr->blue, rmesa->vb.colorptr->alpha));
- else if (ind & RADEON_CP_VC_FRMT_FPALPHA)
- CALL_Color4fv(GET_DISPATCH(), (rmesa->vb.floatcolorptr));
- else if (ind & RADEON_CP_VC_FRMT_FPCOLOR) {
- if (rmesa->vb.installed_color_3f_sz == 4 && alpha != 1.0)
- CALL_Color4f(GET_DISPATCH(), (rmesa->vb.floatcolorptr[0],
- rmesa->vb.floatcolorptr[1],
- rmesa->vb.floatcolorptr[2],
- alpha));
- else
- CALL_Color3fv(GET_DISPATCH(), (rmesa->vb.floatcolorptr));
- }
-
- if (ind & RADEON_CP_VC_FRMT_PKSPEC)
- CALL_SecondaryColor3ubEXT(GET_DISPATCH(), (rmesa->vb.specptr->red, rmesa->vb.specptr->green, rmesa->vb.specptr->blue));
-
- if (ind & RADEON_CP_VC_FRMT_ST0)
- CALL_TexCoord2fv(GET_DISPATCH(), (rmesa->vb.texcoordptr[0]));
-
- if (ind & RADEON_CP_VC_FRMT_ST1)
- CALL_MultiTexCoord2fvARB(GET_DISPATCH(), (GL_TEXTURE1_ARB, rmesa->vb.texcoordptr[1]));
-}
-
-
-
-static void wrap_buffer( void )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLfloat tmp[3][15];
- GLuint i, nrverts;
-
- if (RADEON_DEBUG & (DEBUG_VFMT|DEBUG_PRIMS))
- fprintf(stderr, "%s %d\n", __FUNCTION__, rmesa->vb.initial_counter - rmesa->vb.counter);
-
- /* Don't deal with parity.
- */
- if ((((rmesa->vb.initial_counter - rmesa->vb.counter) -
- rmesa->vb.primlist[rmesa->vb.nrprims].start) & 1)) {
- rmesa->vb.counter++;
- rmesa->vb.initial_counter++;
- return;
- }
-
- /* Copy vertices out of dma:
- */
- if (rmesa->vb.prim[0] == GL_POLYGON+1)
- nrverts = 0;
- else {
- nrverts = copy_dma_verts( rmesa, tmp );
-
- if (RADEON_DEBUG & DEBUG_VFMT)
- fprintf(stderr, "%d vertices to copy\n", nrverts);
-
- /* Finish the prim at this point:
- */
- note_last_prim( rmesa, 0 );
- }
-
- /* Fire any buffered primitives
- */
- flush_prims( rmesa );
-
- /* Get new buffer
- */
- radeonRefillCurrentDmaRegion( rmesa );
-
- /* Reset counter, dmaptr
- */
- rmesa->vb.dmaptr = (int *)(rmesa->dma.current.ptr + rmesa->dma.current.address);
- rmesa->vb.counter = (rmesa->dma.current.end - rmesa->dma.current.ptr) /
- (rmesa->vb.vertex_size * 4);
- rmesa->vb.counter--;
- rmesa->vb.initial_counter = rmesa->vb.counter;
- rmesa->vb.notify = wrap_buffer;
-
- rmesa->dma.flush = flush_prims;
-
- /* Restart wrapped primitive:
- */
- if (rmesa->vb.prim[0] != GL_POLYGON+1)
- start_prim( rmesa, rmesa->vb.prim[0] );
-
- /* Reemit saved vertices
- */
- for (i = 0 ; i < nrverts; i++) {
- if (RADEON_DEBUG & DEBUG_VERTS) {
- int j;
- fprintf(stderr, "re-emit vertex %d to %p\n", i, (void *)rmesa->vb.dmaptr);
- if (RADEON_DEBUG & DEBUG_VERBOSE)
- for (j = 0 ; j < rmesa->vb.vertex_size; j++)
- fprintf(stderr, "\t%08x/%f\n", *(int*)&tmp[i][j], tmp[i][j]);
- }
-
- memcpy( rmesa->vb.dmaptr, tmp[i], rmesa->vb.vertex_size * 4 );
- rmesa->vb.dmaptr += rmesa->vb.vertex_size;
- rmesa->vb.counter--;
- }
-}
-
-
-
-static GLboolean check_vtx_fmt( GLcontext *ctx )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLuint ind = RADEON_CP_VC_FRMT_Z;
-
- if (rmesa->TclFallback || rmesa->vb.fell_back || ctx->CompileFlag)
- return GL_FALSE;
-
- if (ctx->Driver.NeedFlush & FLUSH_UPDATE_CURRENT)
- ctx->Driver.FlushVertices( ctx, FLUSH_UPDATE_CURRENT );
-
- /* Make all this event-driven:
- */
- if (ctx->Light.Enabled) {
- ind |= RADEON_CP_VC_FRMT_N0;
-
- /* TODO: make this data driven: If we receive only ubytes, send
- * color as ubytes. Also check if converting (with free
- * checking for overflow) is cheaper than sending floats
- * directly.
- */
- if (ctx->Light.ColorMaterialEnabled) {
- ind |= (RADEON_CP_VC_FRMT_FPCOLOR |
- RADEON_CP_VC_FRMT_FPALPHA);
- }
- else
- ind |= RADEON_CP_VC_FRMT_PKCOLOR; /* for alpha? */
- }
- else {
- /* TODO: make this data driven?
- */
- ind |= RADEON_CP_VC_FRMT_PKCOLOR;
-
- if (ctx->_TriangleCaps & DD_SEPARATE_SPECULAR) {
- ind |= RADEON_CP_VC_FRMT_PKSPEC;
- }
- }
-
- if (ctx->Texture.Unit[0]._ReallyEnabled) {
- if (ctx->Texture.Unit[0].TexGenEnabled) {
- if (rmesa->TexGenNeedNormals[0]) {
- ind |= RADEON_CP_VC_FRMT_N0;
- }
- } else {
- if (ctx->Current.Attrib[VERT_ATTRIB_TEX0][2] != 0.0F ||
- ctx->Current.Attrib[VERT_ATTRIB_TEX0][3] != 1.0) {
- if (RADEON_DEBUG & (DEBUG_VFMT|DEBUG_FALLBACKS))
- fprintf(stderr, "%s: rq0\n", __FUNCTION__);
- return GL_FALSE;
- }
- ind |= RADEON_CP_VC_FRMT_ST0;
- }
- }
-
- if (ctx->Texture.Unit[1]._ReallyEnabled) {
- if (ctx->Texture.Unit[1].TexGenEnabled) {
- if (rmesa->TexGenNeedNormals[1]) {
- ind |= RADEON_CP_VC_FRMT_N0;
- }
- } else {
- if (ctx->Current.Attrib[VERT_ATTRIB_TEX1][2] != 0.0F ||
- ctx->Current.Attrib[VERT_ATTRIB_TEX1][3] != 1.0) {
- if (RADEON_DEBUG & (DEBUG_VFMT|DEBUG_FALLBACKS))
- fprintf(stderr, "%s: rq1\n", __FUNCTION__);
- return GL_FALSE;
- }
- ind |= RADEON_CP_VC_FRMT_ST1;
- }
- }
-
- if (RADEON_DEBUG & (DEBUG_VFMT|DEBUG_STATE))
- fprintf(stderr, "%s: format: 0x%x\n", __FUNCTION__, ind );
-
- RADEON_NEWPRIM(rmesa);
- rmesa->vb.vertex_format = ind;
- rmesa->vb.vertex_size = 3;
- rmesa->vb.prim = &ctx->Driver.CurrentExecPrimitive;
-
- rmesa->vb.normalptr = ctx->Current.Attrib[VERT_ATTRIB_NORMAL];
- rmesa->vb.colorptr = NULL;
- rmesa->vb.floatcolorptr = ctx->Current.Attrib[VERT_ATTRIB_COLOR0];
- rmesa->vb.specptr = NULL;
- rmesa->vb.floatspecptr = ctx->Current.Attrib[VERT_ATTRIB_COLOR1];
- rmesa->vb.texcoordptr[0] = ctx->Current.Attrib[VERT_ATTRIB_TEX0];
- rmesa->vb.texcoordptr[1] = ctx->Current.Attrib[VERT_ATTRIB_TEX1];
-
- /* Run through and initialize the vertex components in the order
- * the hardware understands:
- */
- if (ind & RADEON_CP_VC_FRMT_N0) {
- rmesa->vb.normalptr = &rmesa->vb.vertex[rmesa->vb.vertex_size].f;
- rmesa->vb.vertex_size += 3;
- rmesa->vb.normalptr[0] = ctx->Current.Attrib[VERT_ATTRIB_NORMAL][0];
- rmesa->vb.normalptr[1] = ctx->Current.Attrib[VERT_ATTRIB_NORMAL][1];
- rmesa->vb.normalptr[2] = ctx->Current.Attrib[VERT_ATTRIB_NORMAL][2];
- }
-
- if (ind & RADEON_CP_VC_FRMT_PKCOLOR) {
- rmesa->vb.colorptr = &rmesa->vb.vertex[rmesa->vb.vertex_size].color;
- rmesa->vb.vertex_size += 1;
- UNCLAMPED_FLOAT_TO_CHAN( rmesa->vb.colorptr->red, ctx->Current.Attrib[VERT_ATTRIB_COLOR0][0] );
- UNCLAMPED_FLOAT_TO_CHAN( rmesa->vb.colorptr->green, ctx->Current.Attrib[VERT_ATTRIB_COLOR0][1] );
- UNCLAMPED_FLOAT_TO_CHAN( rmesa->vb.colorptr->blue, ctx->Current.Attrib[VERT_ATTRIB_COLOR0][2] );
- UNCLAMPED_FLOAT_TO_CHAN( rmesa->vb.colorptr->alpha, ctx->Current.Attrib[VERT_ATTRIB_COLOR0][3] );
- }
-
- if (ind & RADEON_CP_VC_FRMT_FPCOLOR) {
- assert(!(ind & RADEON_CP_VC_FRMT_PKCOLOR));
- rmesa->vb.floatcolorptr = &rmesa->vb.vertex[rmesa->vb.vertex_size].f;
- rmesa->vb.vertex_size += 3;
- rmesa->vb.floatcolorptr[0] = ctx->Current.Attrib[VERT_ATTRIB_COLOR0][0];
- rmesa->vb.floatcolorptr[1] = ctx->Current.Attrib[VERT_ATTRIB_COLOR0][1];
- rmesa->vb.floatcolorptr[2] = ctx->Current.Attrib[VERT_ATTRIB_COLOR0][2];
-
- if (ind & RADEON_CP_VC_FRMT_FPALPHA) {
- rmesa->vb.vertex_size += 1;
- rmesa->vb.floatcolorptr[3] = ctx->Current.Attrib[VERT_ATTRIB_COLOR0][3];
- }
- }
-
- if (ind & RADEON_CP_VC_FRMT_PKSPEC) {
- rmesa->vb.specptr = &rmesa->vb.vertex[rmesa->vb.vertex_size].color;
- rmesa->vb.vertex_size += 1;
- UNCLAMPED_FLOAT_TO_CHAN( rmesa->vb.specptr->red, ctx->Current.Attrib[VERT_ATTRIB_COLOR1][0] );
- UNCLAMPED_FLOAT_TO_CHAN( rmesa->vb.specptr->green, ctx->Current.Attrib[VERT_ATTRIB_COLOR1][1] );
- UNCLAMPED_FLOAT_TO_CHAN( rmesa->vb.specptr->blue, ctx->Current.Attrib[VERT_ATTRIB_COLOR1][2] );
- }
-
- if (ind & RADEON_CP_VC_FRMT_ST0) {
- rmesa->vb.texcoordptr[0] = &rmesa->vb.vertex[rmesa->vb.vertex_size].f;
- rmesa->vb.vertex_size += 2;
- rmesa->vb.texcoordptr[0][0] = ctx->Current.Attrib[VERT_ATTRIB_TEX0][0];
- rmesa->vb.texcoordptr[0][1] = ctx->Current.Attrib[VERT_ATTRIB_TEX0][1];
- }
-
- if (ind & RADEON_CP_VC_FRMT_ST1) {
- rmesa->vb.texcoordptr[1] = &rmesa->vb.vertex[rmesa->vb.vertex_size].f;
- rmesa->vb.vertex_size += 2;
- rmesa->vb.texcoordptr[1][0] = ctx->Current.Attrib[VERT_ATTRIB_TEX1][0];
- rmesa->vb.texcoordptr[1][1] = ctx->Current.Attrib[VERT_ATTRIB_TEX1][1];
- }
-
- if (rmesa->vb.installed_vertex_format != rmesa->vb.vertex_format) {
- if (RADEON_DEBUG & DEBUG_VFMT)
- fprintf(stderr, "reinstall on vertex_format change\n");
- _mesa_install_exec_vtxfmt( ctx, &rmesa->vb.vtxfmt );
- rmesa->vb.installed_vertex_format = rmesa->vb.vertex_format;
- }
-
- if (RADEON_DEBUG & DEBUG_VFMT)
- fprintf(stderr, "%s -- success\n", __FUNCTION__);
-
- return GL_TRUE;
-}
-
-void radeonVtxfmtInvalidate( GLcontext *ctx )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
-
- rmesa->vb.recheck = GL_TRUE;
- rmesa->vb.fell_back = GL_FALSE;
-}
-
-
-static void radeonVtxfmtValidate( GLcontext *ctx )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
-
- if (RADEON_DEBUG & DEBUG_VFMT)
- fprintf(stderr, "%s\n", __FUNCTION__);
-
- if (ctx->Driver.NeedFlush)
- ctx->Driver.FlushVertices( ctx, ctx->Driver.NeedFlush );
-
- rmesa->vb.recheck = GL_FALSE;
-
- if (check_vtx_fmt( ctx )) {
- if (!rmesa->vb.installed) {
- if (RADEON_DEBUG & DEBUG_VFMT)
- fprintf(stderr, "reinstall (new install)\n");
-
- _mesa_install_exec_vtxfmt( ctx, &rmesa->vb.vtxfmt );
- ctx->Driver.FlushVertices = radeonVtxfmtFlushVertices;
- rmesa->vb.installed = GL_TRUE;
- }
- else if (RADEON_DEBUG & DEBUG_VFMT)
- fprintf(stderr, "%s: already installed", __FUNCTION__);
- }
- else {
- if (RADEON_DEBUG & DEBUG_VFMT)
- fprintf(stderr, "%s: failed\n", __FUNCTION__);
-
- if (rmesa->vb.installed) {
- if (rmesa->dma.flush)
- rmesa->dma.flush( rmesa );
- _tnl_wakeup_exec( ctx );
- ctx->Driver.FlushVertices = radeonFlushVertices;
- rmesa->vb.installed = GL_FALSE;
- }
- }
-}
-
-
-
-/* Materials:
- */
-static void radeon_Materialfv( GLenum face, GLenum pname,
- const GLfloat *params )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
-
- if (RADEON_DEBUG & DEBUG_VFMT)
- fprintf(stderr, "%s\n", __FUNCTION__);
-
- if (rmesa->vb.prim[0] != GL_POLYGON+1) {
- VFMT_FALLBACK( __FUNCTION__ );
- CALL_Materialfv(GET_DISPATCH(), (face, pname, params));
- return;
- }
- _mesa_noop_Materialfv( face, pname, params );
- radeonUpdateMaterial( ctx );
-}
-
-
-/* Begin/End
- */
-static void radeon_Begin( GLenum mode )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-
- if (RADEON_DEBUG & DEBUG_VFMT)
- fprintf(stderr, "%s( %s )\n", __FUNCTION__,
- _mesa_lookup_enum_by_nr( mode ));
-
- if (mode > GL_POLYGON) {
- _mesa_error( ctx, GL_INVALID_ENUM, "glBegin" );
- return;
- }
-
- if (rmesa->vb.prim[0] != GL_POLYGON+1) {
- _mesa_error( ctx, GL_INVALID_OPERATION, "glBegin" );
- return;
- }
-
- if (ctx->NewState)
- _mesa_update_state( ctx );
-
- if (rmesa->NewGLState)
- radeonValidateState( ctx );
-
- if (rmesa->vb.recheck)
- radeonVtxfmtValidate( ctx );
-
- if (!rmesa->vb.installed) {
- CALL_Begin(GET_DISPATCH(), (mode));
- return;
- }
-
-
- if (rmesa->dma.flush && rmesa->vb.counter < 12) {
- if (RADEON_DEBUG & DEBUG_VFMT)
- fprintf(stderr, "%s: flush almost-empty buffers\n", __FUNCTION__);
- flush_prims( rmesa );
- }
-
- /* Need to arrange to save vertices here? Or always copy from dma (yuk)?
- */
- if (!rmesa->dma.flush) {
- if (rmesa->dma.current.ptr + 12*rmesa->vb.vertex_size*4 >
- rmesa->dma.current.end) {
- RADEON_NEWPRIM( rmesa );
- radeonRefillCurrentDmaRegion( rmesa );
- }
-
- rmesa->vb.dmaptr = (int *)(rmesa->dma.current.address + rmesa->dma.current.ptr);
- rmesa->vb.counter = (rmesa->dma.current.end - rmesa->dma.current.ptr) /
- (rmesa->vb.vertex_size * 4);
- rmesa->vb.counter--;
- rmesa->vb.initial_counter = rmesa->vb.counter;
- rmesa->vb.notify = wrap_buffer;
- rmesa->dma.flush = flush_prims;
- ctx->Driver.NeedFlush |= FLUSH_STORED_VERTICES;
- }
-
-
- rmesa->vb.prim[0] = mode;
- start_prim( rmesa, mode | PRIM_BEGIN );
-}
-
-
-
-static void radeon_End( void )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-
- if (RADEON_DEBUG & DEBUG_VFMT)
- fprintf(stderr, "%s\n", __FUNCTION__);
-
- if (rmesa->vb.prim[0] == GL_POLYGON+1) {
- _mesa_error( ctx, GL_INVALID_OPERATION, "glEnd" );
- return;
- }
-
- note_last_prim( rmesa, PRIM_END );
- rmesa->vb.prim[0] = GL_POLYGON+1;
-}
-
-
-/* Fallback on difficult entrypoints:
- */
-#define PRE_LOOPBACK( FUNC ) \
-do { \
- if (RADEON_DEBUG & DEBUG_VFMT) \
- fprintf(stderr, "%s\n", __FUNCTION__); \
- VFMT_FALLBACK( __FUNCTION__ ); \
-} while (0)
-#define TAG(x) radeon_fallback_##x
-#include "vtxfmt_tmp.h"
-
-
-
-static GLboolean radeonNotifyBegin( GLcontext *ctx, GLenum p )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
-
- if (RADEON_DEBUG & DEBUG_VFMT)
- fprintf(stderr, "%s\n", __FUNCTION__);
-
- assert(!rmesa->vb.installed);
-
- if (ctx->NewState)
- _mesa_update_state( ctx );
-
- if (rmesa->NewGLState)
- radeonValidateState( ctx );
-
- if (ctx->Driver.NeedFlush)
- ctx->Driver.FlushVertices( ctx, ctx->Driver.NeedFlush );
-
- if (rmesa->vb.recheck)
- radeonVtxfmtValidate( ctx );
-
- if (!rmesa->vb.installed) {
- if (RADEON_DEBUG & DEBUG_VFMT)
- fprintf(stderr, "%s -- failed\n", __FUNCTION__);
- return GL_FALSE;
- }
-
- radeon_Begin( p );
- return GL_TRUE;
-}
-
-static void radeonVtxfmtFlushVertices( GLcontext *ctx, GLuint flags )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
-
- if (RADEON_DEBUG & DEBUG_VFMT)
- fprintf(stderr, "%s\n", __FUNCTION__);
-
- assert(rmesa->vb.installed);
-
- if (flags & FLUSH_UPDATE_CURRENT) {
- radeon_copy_to_current( ctx );
- if (RADEON_DEBUG & DEBUG_VFMT)
- fprintf(stderr, "reinstall on update_current\n");
- _mesa_install_exec_vtxfmt( ctx, &rmesa->vb.vtxfmt );
- ctx->Driver.NeedFlush &= ~FLUSH_UPDATE_CURRENT;
- }
-
- if (flags & FLUSH_STORED_VERTICES) {
- radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
- assert (rmesa->dma.flush == 0 ||
- rmesa->dma.flush == flush_prims);
- if (rmesa->dma.flush == flush_prims)
- flush_prims( RADEON_CONTEXT( ctx ) );
- ctx->Driver.NeedFlush &= ~FLUSH_STORED_VERTICES;
- }
-}
-
-
-
-/* At this point, don't expect very many versions of each function to
- * be generated, so not concerned about freeing them?
- */
-
-
-void radeonVtxfmtInit( GLcontext *ctx, GLboolean useCodegen )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
- GLvertexformat *vfmt = &(rmesa->vb.vtxfmt);
-
- MEMSET( vfmt, 0, sizeof(GLvertexformat) );
-
- /* Hook in chooser functions for codegen, etc:
- */
- radeonVtxfmtInitChoosers( vfmt );
-
- /* Handled fully in supported states, but no codegen:
- */
- vfmt->Materialfv = radeon_Materialfv;
- vfmt->ArrayElement = _ae_loopback_array_elt; /* generic helper */
- vfmt->Rectf = _mesa_noop_Rectf; /* generic helper */
- vfmt->Begin = radeon_Begin;
- vfmt->End = radeon_End;
-
- /* Fallback for performance reasons: (Fix with cva/elt path here and
- * dmatmp2.h style primitive-merging)
- *
- * These should call NotifyBegin(), as should _tnl_EvalMesh, to allow
- * a driver-hook.
- */
- vfmt->DrawArrays = radeon_fallback_DrawArrays;
- vfmt->DrawElements = radeon_fallback_DrawElements;
- vfmt->DrawRangeElements = radeon_fallback_DrawRangeElements;
-
-
- /* Not active in supported states; just keep ctx->Current uptodate:
- */
- vfmt->FogCoordfvEXT = _mesa_noop_FogCoordfvEXT;
- vfmt->FogCoordfEXT = _mesa_noop_FogCoordfEXT;
- vfmt->EdgeFlag = _mesa_noop_EdgeFlag;
- vfmt->EdgeFlagv = _mesa_noop_EdgeFlagv;
- vfmt->Indexf = _mesa_noop_Indexf;
- vfmt->Indexfv = _mesa_noop_Indexfv;
-
-
- /* Active but unsupported -- fallback if we receive these:
- */
- vfmt->CallList = radeon_fallback_CallList;
- vfmt->CallLists = radeon_fallback_CallLists;
- vfmt->EvalCoord1f = radeon_fallback_EvalCoord1f;
- vfmt->EvalCoord1fv = radeon_fallback_EvalCoord1fv;
- vfmt->EvalCoord2f = radeon_fallback_EvalCoord2f;
- vfmt->EvalCoord2fv = radeon_fallback_EvalCoord2fv;
- vfmt->EvalMesh1 = radeon_fallback_EvalMesh1;
- vfmt->EvalMesh2 = radeon_fallback_EvalMesh2;
- vfmt->EvalPoint1 = radeon_fallback_EvalPoint1;
- vfmt->EvalPoint2 = radeon_fallback_EvalPoint2;
- vfmt->TexCoord3f = radeon_fallback_TexCoord3f;
- vfmt->TexCoord3fv = radeon_fallback_TexCoord3fv;
- vfmt->TexCoord4f = radeon_fallback_TexCoord4f;
- vfmt->TexCoord4fv = radeon_fallback_TexCoord4fv;
- vfmt->MultiTexCoord3fARB = radeon_fallback_MultiTexCoord3fARB;
- vfmt->MultiTexCoord3fvARB = radeon_fallback_MultiTexCoord3fvARB;
- vfmt->MultiTexCoord4fARB = radeon_fallback_MultiTexCoord4fARB;
- vfmt->MultiTexCoord4fvARB = radeon_fallback_MultiTexCoord4fvARB;
- vfmt->Vertex4f = radeon_fallback_Vertex4f;
- vfmt->Vertex4fv = radeon_fallback_Vertex4fv;
- vfmt->VertexAttrib1fNV = radeon_fallback_VertexAttrib1fNV;
- vfmt->VertexAttrib1fvNV = radeon_fallback_VertexAttrib1fvNV;
- vfmt->VertexAttrib2fNV = radeon_fallback_VertexAttrib2fNV;
- vfmt->VertexAttrib2fvNV = radeon_fallback_VertexAttrib2fvNV;
- vfmt->VertexAttrib3fNV = radeon_fallback_VertexAttrib3fNV;
- vfmt->VertexAttrib3fvNV = radeon_fallback_VertexAttrib3fvNV;
- vfmt->VertexAttrib4fNV = radeon_fallback_VertexAttrib4fNV;
- vfmt->VertexAttrib4fvNV = radeon_fallback_VertexAttrib4fvNV;
-
- (void)radeon_fallback_vtxfmt;
-
- TNL_CONTEXT(ctx)->Driver.NotifyBegin = radeonNotifyBegin;
-
- rmesa->vb.enabled = 1;
- rmesa->vb.prim = &ctx->Driver.CurrentExecPrimitive;
- rmesa->vb.primflags = 0;
-
- make_empty_list( &rmesa->vb.dfn_cache.Vertex2f );
- make_empty_list( &rmesa->vb.dfn_cache.Vertex2fv );
- make_empty_list( &rmesa->vb.dfn_cache.Vertex3f );
- make_empty_list( &rmesa->vb.dfn_cache.Vertex3fv );
- make_empty_list( &rmesa->vb.dfn_cache.Color4ub );
- make_empty_list( &rmesa->vb.dfn_cache.Color4ubv );
- make_empty_list( &rmesa->vb.dfn_cache.Color3ub );
- make_empty_list( &rmesa->vb.dfn_cache.Color3ubv );
- make_empty_list( &rmesa->vb.dfn_cache.Color4f );
- make_empty_list( &rmesa->vb.dfn_cache.Color4fv );
- make_empty_list( &rmesa->vb.dfn_cache.Color3f );
- make_empty_list( &rmesa->vb.dfn_cache.Color3fv );
- make_empty_list( &rmesa->vb.dfn_cache.SecondaryColor3fEXT );
- make_empty_list( &rmesa->vb.dfn_cache.SecondaryColor3fvEXT );
- make_empty_list( &rmesa->vb.dfn_cache.SecondaryColor3ubEXT );
- make_empty_list( &rmesa->vb.dfn_cache.SecondaryColor3ubvEXT );
- make_empty_list( &rmesa->vb.dfn_cache.Normal3f );
- make_empty_list( &rmesa->vb.dfn_cache.Normal3fv );
- make_empty_list( &rmesa->vb.dfn_cache.TexCoord2f );
- make_empty_list( &rmesa->vb.dfn_cache.TexCoord2fv );
- make_empty_list( &rmesa->vb.dfn_cache.TexCoord1f );
- make_empty_list( &rmesa->vb.dfn_cache.TexCoord1fv );
- make_empty_list( &rmesa->vb.dfn_cache.MultiTexCoord2fARB );
- make_empty_list( &rmesa->vb.dfn_cache.MultiTexCoord2fvARB );
- make_empty_list( &rmesa->vb.dfn_cache.MultiTexCoord1fARB );
- make_empty_list( &rmesa->vb.dfn_cache.MultiTexCoord1fvARB );
-
- radeonInitCodegen( &rmesa->vb.codegen, useCodegen );
-}
-
-static void free_funcs( struct dynfn *l )
-{
- struct dynfn *f, *tmp;
- foreach_s (f, tmp, l) {
- remove_from_list( f );
- _mesa_exec_free( f->code );
- _mesa_free( f );
- }
-}
-
-
-
-void radeonVtxfmtMakeCurrent( GLcontext *ctx )
-{
-}
-
-
-void radeonVtxfmtDestroy( GLcontext *ctx )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
-
- count_funcs( rmesa );
- free_funcs( &rmesa->vb.dfn_cache.Vertex2f );
- free_funcs( &rmesa->vb.dfn_cache.Vertex2fv );
- free_funcs( &rmesa->vb.dfn_cache.Vertex3f );
- free_funcs( &rmesa->vb.dfn_cache.Vertex3fv );
- free_funcs( &rmesa->vb.dfn_cache.Color4ub );
- free_funcs( &rmesa->vb.dfn_cache.Color4ubv );
- free_funcs( &rmesa->vb.dfn_cache.Color3ub );
- free_funcs( &rmesa->vb.dfn_cache.Color3ubv );
- free_funcs( &rmesa->vb.dfn_cache.Color4f );
- free_funcs( &rmesa->vb.dfn_cache.Color4fv );
- free_funcs( &rmesa->vb.dfn_cache.Color3f );
- free_funcs( &rmesa->vb.dfn_cache.Color3fv );
- free_funcs( &rmesa->vb.dfn_cache.SecondaryColor3ubEXT );
- free_funcs( &rmesa->vb.dfn_cache.SecondaryColor3ubvEXT );
- free_funcs( &rmesa->vb.dfn_cache.SecondaryColor3fEXT );
- free_funcs( &rmesa->vb.dfn_cache.SecondaryColor3fvEXT );
- free_funcs( &rmesa->vb.dfn_cache.Normal3f );
- free_funcs( &rmesa->vb.dfn_cache.Normal3fv );
- free_funcs( &rmesa->vb.dfn_cache.TexCoord2f );
- free_funcs( &rmesa->vb.dfn_cache.TexCoord2fv );
- free_funcs( &rmesa->vb.dfn_cache.TexCoord1f );
- free_funcs( &rmesa->vb.dfn_cache.TexCoord1fv );
- free_funcs( &rmesa->vb.dfn_cache.MultiTexCoord2fARB );
- free_funcs( &rmesa->vb.dfn_cache.MultiTexCoord2fvARB );
- free_funcs( &rmesa->vb.dfn_cache.MultiTexCoord1fARB );
- free_funcs( &rmesa->vb.dfn_cache.MultiTexCoord1fvARB );
-}
-
diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_vtxfmt.h b/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_vtxfmt.h
deleted file mode 100644
index a656e49e4..000000000
--- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_vtxfmt.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_vtxfmt.h,v 1.3 2002/12/21 17:02:16 dawes Exp $ */
-/**************************************************************************
-
-Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
- Tungsten Graphics Inc., Cedar Park, Texas.
-
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/*
- * Authors:
- * Keith Whitwell <keith@tungstengraphics.com>
- */
-
-#ifndef __RADEON_VTXFMT_H__
-#define __RADEON_VTXFMT_H__
-
-#include "radeon_context.h"
-
-
-extern void radeonVtxfmtUpdate( GLcontext *ctx );
-extern void radeonVtxfmtInit( GLcontext *ctx, GLboolean useCodegen );
-extern void radeonVtxfmtInvalidate( GLcontext *ctx );
-extern void radeonVtxfmtDestroy( GLcontext *ctx );
-extern void radeonVtxfmtInitChoosers( GLvertexformat *vfmt );
-
-extern void radeonVtxfmtMakeCurrent( GLcontext *ctx );
-extern void radeonVtxfmtUnbindContext( GLcontext *ctx );
-
-extern void radeon_copy_to_current( GLcontext *ctx );
-
-#define DFN( FUNC, CACHE) \
-do { \
- char *start = (char *)&FUNC; \
- char *end = (char *)&FUNC##_end; \
- insert_at_head( &CACHE, dfn ); \
- dfn->key = key; \
- dfn->code = _mesa_exec_malloc( end - start ); \
- _mesa_memcpy(dfn->code, start, end - start); \
-} \
-while ( 0 )
-
-#define FIXUP( CODE, OFFSET, CHECKVAL, NEWVAL ) \
-do { \
- int *icode = (int *)(CODE+OFFSET); \
- assert (*icode == CHECKVAL); \
- *icode = (int)NEWVAL; \
-} while (0)
-
-
-/* Useful for figuring out the offsets:
- */
-#define FIXUP2( CODE, OFFSET, CHECKVAL, NEWVAL ) \
-do { \
- while (*(int *)(CODE+OFFSET) != CHECKVAL) OFFSET++; \
- fprintf(stderr, "%s/%d CVAL %x OFFSET %d VAL %x\n", __FUNCTION__, \
- __LINE__, CHECKVAL, OFFSET, (int)(NEWVAL)); \
- *(int *)(CODE+OFFSET) = (int)(NEWVAL); \
- OFFSET += 4; \
-} while (0)
-
-/*
- */
-void radeonInitCodegen( struct dfn_generators *gen, GLboolean useCodegen );
-void radeonInitX86Codegen( struct dfn_generators *gen );
-void radeonInitSSECodegen( struct dfn_generators *gen );
-
-
-
-/* Defined in radeon_vtxfmt_x86.c
- */
-struct dynfn *radeon_makeX86Vertex2f( GLcontext *, int );
-struct dynfn *radeon_makeX86Vertex2fv( GLcontext *, int );
-struct dynfn *radeon_makeX86Vertex3f( GLcontext *, int );
-struct dynfn *radeon_makeX86Vertex3fv( GLcontext *, int );
-struct dynfn *radeon_makeX86Color4ub( GLcontext *, int );
-struct dynfn *radeon_makeX86Color4ubv( GLcontext *, int );
-struct dynfn *radeon_makeX86Color3ub( GLcontext *, int );
-struct dynfn *radeon_makeX86Color3ubv( GLcontext *, int );
-struct dynfn *radeon_makeX86Color4f( GLcontext *, int );
-struct dynfn *radeon_makeX86Color4fv( GLcontext *, int );
-struct dynfn *radeon_makeX86Color3f( GLcontext *, int );
-struct dynfn *radeon_makeX86Color3fv( GLcontext *, int );
-struct dynfn *radeon_makeX86SecondaryColor3ubEXT( GLcontext *, int );
-struct dynfn *radeon_makeX86SecondaryColor3ubvEXT( GLcontext *, int );
-struct dynfn *radeon_makeX86SecondaryColor3fEXT( GLcontext *, int );
-struct dynfn *radeon_makeX86SecondaryColor3fvEXT( GLcontext *, int );
-struct dynfn *radeon_makeX86Normal3f( GLcontext *, int );
-struct dynfn *radeon_makeX86Normal3fv( GLcontext *, int );
-struct dynfn *radeon_makeX86TexCoord2f( GLcontext *, int );
-struct dynfn *radeon_makeX86TexCoord2fv( GLcontext *, int );
-struct dynfn *radeon_makeX86TexCoord1f( GLcontext *, int );
-struct dynfn *radeon_makeX86TexCoord1fv( GLcontext *, int );
-struct dynfn *radeon_makeX86MultiTexCoord2fARB( GLcontext *, int );
-struct dynfn *radeon_makeX86MultiTexCoord2fvARB( GLcontext *, int );
-struct dynfn *radeon_makeX86MultiTexCoord1fARB( GLcontext *, int );
-struct dynfn *radeon_makeX86MultiTexCoord1fvARB( GLcontext *, int );
-
-#endif
diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_vtxfmt_c.c b/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_vtxfmt_c.c
deleted file mode 100644
index 342b0b39c..000000000
--- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_vtxfmt_c.c
+++ /dev/null
@@ -1,922 +0,0 @@
-/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_vtxfmt_c.c,v 1.2 2002/12/16 16:18:59 dawes Exp $ */
-/**************************************************************************
-
-Copyright 2002 ATI Technologies Inc., Ontario, Canada, and
- Tungsten Graphics Inc., Cedar Park, Texas.
-
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/*
- * Authors:
- * Keith Whitwell <keith@tungstengraphics.com>
- */
-#include "glheader.h"
-#include "mtypes.h"
-#include "colormac.h"
-#include "simple_list.h"
-#include "api_noop.h"
-#include "vtxfmt.h"
-
-#include "radeon_vtxfmt.h"
-
-#include "dispatch.h"
-
-/* Fallback versions of all the entrypoints for situations where
- * codegen isn't available. This is still a lot faster than the
- * vb/pipeline implementation in Mesa.
- */
-static void radeon_Vertex3f( GLfloat x, GLfloat y, GLfloat z )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- int i;
-
- *rmesa->vb.dmaptr++ = *(int *)&x;
- *rmesa->vb.dmaptr++ = *(int *)&y;
- *rmesa->vb.dmaptr++ = *(int *)&z;
-
- for (i = 3; i < rmesa->vb.vertex_size; i++)
- *rmesa->vb.dmaptr++ = rmesa->vb.vertex[i].i;
-
- if (--rmesa->vb.counter == 0)
- rmesa->vb.notify();
-}
-
-
-static void radeon_Vertex3fv( const GLfloat *v )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- int i;
-
- *rmesa->vb.dmaptr++ = *(int *)&v[0];
- *rmesa->vb.dmaptr++ = *(int *)&v[1];
- *rmesa->vb.dmaptr++ = *(int *)&v[2];
-
- for (i = 3; i < rmesa->vb.vertex_size; i++)
- *rmesa->vb.dmaptr++ = rmesa->vb.vertex[i].i;
-
- if (--rmesa->vb.counter == 0)
- rmesa->vb.notify();
-}
-
-
-static void radeon_Vertex2f( GLfloat x, GLfloat y )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- int i;
-
- *rmesa->vb.dmaptr++ = *(int *)&x;
- *rmesa->vb.dmaptr++ = *(int *)&y;
- *rmesa->vb.dmaptr++ = 0;
-
- for (i = 3; i < rmesa->vb.vertex_size; i++)
- *rmesa->vb.dmaptr++ = *(int *)&rmesa->vb.vertex[i];
-
- if (--rmesa->vb.counter == 0)
- rmesa->vb.notify();
-}
-
-
-static void radeon_Vertex2fv( const GLfloat *v )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- int i;
-
- *rmesa->vb.dmaptr++ = *(int *)&v[0];
- *rmesa->vb.dmaptr++ = *(int *)&v[1];
- *rmesa->vb.dmaptr++ = 0;
-
- for (i = 3; i < rmesa->vb.vertex_size; i++)
- *rmesa->vb.dmaptr++ = rmesa->vb.vertex[i].i;
-
- if (--rmesa->vb.counter == 0)
- rmesa->vb.notify();
-}
-
-
-#if 0
-/* Color for ubyte (packed) color formats:
- */
-static void radeon_Color3ub_ub( GLubyte r, GLubyte g, GLubyte b )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- radeon_color_t *dest = rmesa->vb.colorptr;
- dest->red = r;
- dest->green = g;
- dest->blue = b;
- dest->alpha = 0xff;
-}
-
-static void radeon_Color3ubv_ub( const GLubyte *v )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- radeon_color_t *dest = rmesa->vb.colorptr;
- dest->red = v[0];
- dest->green = v[1];
- dest->blue = v[2];
- dest->alpha = 0xff;
-}
-
-static void radeon_Color4ub_ub( GLubyte r, GLubyte g, GLubyte b, GLubyte a )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- radeon_color_t *dest = rmesa->vb.colorptr;
- dest->red = r;
- dest->green = g;
- dest->blue = b;
- dest->alpha = a;
-}
-
-static void radeon_Color4ubv_ub( const GLubyte *v )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- *(GLuint *)rmesa->vb.colorptr = LE32_TO_CPU(*(GLuint *)v);
-}
-#endif /* 0 */
-
-static void radeon_Color3f_ub( GLfloat r, GLfloat g, GLfloat b )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- radeon_color_t *dest = rmesa->vb.colorptr;
- UNCLAMPED_FLOAT_TO_UBYTE( dest->red, r );
- UNCLAMPED_FLOAT_TO_UBYTE( dest->green, g );
- UNCLAMPED_FLOAT_TO_UBYTE( dest->blue, b );
- dest->alpha = 255;
-}
-
-static void radeon_Color3fv_ub( const GLfloat *v )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- radeon_color_t *dest = rmesa->vb.colorptr;
- UNCLAMPED_FLOAT_TO_UBYTE( dest->red, v[0] );
- UNCLAMPED_FLOAT_TO_UBYTE( dest->green, v[1] );
- UNCLAMPED_FLOAT_TO_UBYTE( dest->blue, v[2] );
- dest->alpha = 255;
-}
-
-static void radeon_Color4f_ub( GLfloat r, GLfloat g, GLfloat b, GLfloat a )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- radeon_color_t *dest = rmesa->vb.colorptr;
- UNCLAMPED_FLOAT_TO_UBYTE( dest->red, r );
- UNCLAMPED_FLOAT_TO_UBYTE( dest->green, g );
- UNCLAMPED_FLOAT_TO_UBYTE( dest->blue, b );
- UNCLAMPED_FLOAT_TO_UBYTE( dest->alpha, a );
-}
-
-static void radeon_Color4fv_ub( const GLfloat *v )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- radeon_color_t *dest = rmesa->vb.colorptr;
- UNCLAMPED_FLOAT_TO_UBYTE( dest->red, v[0] );
- UNCLAMPED_FLOAT_TO_UBYTE( dest->green, v[1] );
- UNCLAMPED_FLOAT_TO_UBYTE( dest->blue, v[2] );
- UNCLAMPED_FLOAT_TO_UBYTE( dest->alpha, v[3] );
-}
-
-
-/* Color for float color+alpha formats:
- */
-#if 0
-static void radeon_Color3ub_4f( GLubyte r, GLubyte g, GLubyte b )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLfloat *dest = rmesa->vb.floatcolorptr;
- dest[0] = UBYTE_TO_FLOAT(r);
- dest[1] = UBYTE_TO_FLOAT(g);
- dest[2] = UBYTE_TO_FLOAT(b);
- dest[3] = 1.0;
-}
-
-static void radeon_Color3ubv_4f( const GLubyte *v )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLfloat *dest = rmesa->vb.floatcolorptr;
- dest[0] = UBYTE_TO_FLOAT(v[0]);
- dest[1] = UBYTE_TO_FLOAT(v[1]);
- dest[2] = UBYTE_TO_FLOAT(v[2]);
- dest[3] = 1.0;
-}
-
-static void radeon_Color4ub_4f( GLubyte r, GLubyte g, GLubyte b, GLubyte a )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLfloat *dest = rmesa->vb.floatcolorptr;
- dest[0] = UBYTE_TO_FLOAT(r);
- dest[1] = UBYTE_TO_FLOAT(g);
- dest[2] = UBYTE_TO_FLOAT(b);
- dest[3] = UBYTE_TO_FLOAT(a);
-}
-
-static void radeon_Color4ubv_4f( const GLubyte *v )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLfloat *dest = rmesa->vb.floatcolorptr;
- dest[0] = UBYTE_TO_FLOAT(v[0]);
- dest[1] = UBYTE_TO_FLOAT(v[1]);
- dest[2] = UBYTE_TO_FLOAT(v[2]);
- dest[3] = UBYTE_TO_FLOAT(v[3]);
-}
-#endif /* 0 */
-
-
-static void radeon_Color3f_4f( GLfloat r, GLfloat g, GLfloat b )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLfloat *dest = rmesa->vb.floatcolorptr;
- dest[0] = r;
- dest[1] = g;
- dest[2] = b;
- dest[3] = 1.0;
-}
-
-static void radeon_Color3fv_4f( const GLfloat *v )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLfloat *dest = rmesa->vb.floatcolorptr;
- dest[0] = v[0];
- dest[1] = v[1];
- dest[2] = v[2];
- dest[3] = 1.0;
-}
-
-static void radeon_Color4f_4f( GLfloat r, GLfloat g, GLfloat b, GLfloat a )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLfloat *dest = rmesa->vb.floatcolorptr;
- dest[0] = r;
- dest[1] = g;
- dest[2] = b;
- dest[3] = a;
-}
-
-static void radeon_Color4fv_4f( const GLfloat *v )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLfloat *dest = rmesa->vb.floatcolorptr;
- dest[0] = v[0];
- dest[1] = v[1];
- dest[2] = v[2];
- dest[3] = v[3];
-}
-
-
-/* Color for float color formats:
- */
-#if 0
-static void radeon_Color3ub_3f( GLubyte r, GLubyte g, GLubyte b )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLfloat *dest = rmesa->vb.floatcolorptr;
- dest[0] = UBYTE_TO_FLOAT(r);
- dest[1] = UBYTE_TO_FLOAT(g);
- dest[2] = UBYTE_TO_FLOAT(b);
-}
-
-static void radeon_Color3ubv_3f( const GLubyte *v )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLfloat *dest = rmesa->vb.floatcolorptr;
- dest[0] = UBYTE_TO_FLOAT(v[0]);
- dest[1] = UBYTE_TO_FLOAT(v[1]);
- dest[2] = UBYTE_TO_FLOAT(v[2]);
-}
-
-static void radeon_Color4ub_3f( GLubyte r, GLubyte g, GLubyte b, GLubyte a )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLfloat *dest = rmesa->vb.floatcolorptr;
- dest[0] = UBYTE_TO_FLOAT(r);
- dest[1] = UBYTE_TO_FLOAT(g);
- dest[2] = UBYTE_TO_FLOAT(b);
- ctx->Current.Attrib[VERT_ATTRIB_COLOR0][3] = UBYTE_TO_FLOAT(a);
-}
-
-static void radeon_Color4ubv_3f( const GLubyte *v )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLfloat *dest = rmesa->vb.floatcolorptr;
- dest[0] = UBYTE_TO_FLOAT(v[0]);
- dest[1] = UBYTE_TO_FLOAT(v[1]);
- dest[2] = UBYTE_TO_FLOAT(v[2]);
- ctx->Current.Attrib[VERT_ATTRIB_COLOR0][3] = UBYTE_TO_FLOAT(v[3]);
-}
-#endif /* 0 */
-
-
-static void radeon_Color3f_3f( GLfloat r, GLfloat g, GLfloat b )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLfloat *dest = rmesa->vb.floatcolorptr;
- dest[0] = r;
- dest[1] = g;
- dest[2] = b;
-}
-
-static void radeon_Color3fv_3f( const GLfloat *v )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLfloat *dest = rmesa->vb.floatcolorptr;
- dest[0] = v[0];
- dest[1] = v[1];
- dest[2] = v[2];
-}
-
-static void radeon_Color4f_3f( GLfloat r, GLfloat g, GLfloat b, GLfloat a )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLfloat *dest = rmesa->vb.floatcolorptr;
- dest[0] = r;
- dest[1] = g;
- dest[2] = b;
- ctx->Current.Attrib[VERT_ATTRIB_COLOR0][3] = a;
-}
-
-static void radeon_Color4fv_3f( const GLfloat *v )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLfloat *dest = rmesa->vb.floatcolorptr;
- dest[0] = v[0];
- dest[1] = v[1];
- dest[2] = v[2];
- ctx->Current.Attrib[VERT_ATTRIB_COLOR0][3] = v[3];
-}
-
-
-/* Secondary Color:
- */
-#if 0
-static void radeon_SecondaryColor3ubEXT_ub( GLubyte r, GLubyte g, GLubyte b )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- radeon_color_t *dest = rmesa->vb.specptr;
- dest->red = r;
- dest->green = g;
- dest->blue = b;
- dest->alpha = 0xff;
-}
-
-static void radeon_SecondaryColor3ubvEXT_ub( const GLubyte *v )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- radeon_color_t *dest = rmesa->vb.specptr;
- dest->red = v[0];
- dest->green = v[1];
- dest->blue = v[2];
- dest->alpha = 0xff;
-}
-#endif /* 0 */
-
-static void radeon_SecondaryColor3fEXT_ub( GLfloat r, GLfloat g, GLfloat b )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- radeon_color_t *dest = rmesa->vb.specptr;
- UNCLAMPED_FLOAT_TO_UBYTE( dest->red, r );
- UNCLAMPED_FLOAT_TO_UBYTE( dest->green, g );
- UNCLAMPED_FLOAT_TO_UBYTE( dest->blue, b );
- dest->alpha = 255;
-}
-
-static void radeon_SecondaryColor3fvEXT_ub( const GLfloat *v )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- radeon_color_t *dest = rmesa->vb.specptr;
- UNCLAMPED_FLOAT_TO_UBYTE( dest->red, v[0] );
- UNCLAMPED_FLOAT_TO_UBYTE( dest->green, v[1] );
- UNCLAMPED_FLOAT_TO_UBYTE( dest->blue, v[2] );
- dest->alpha = 255;
-}
-
-#if 0
-static void radeon_SecondaryColor3ubEXT_3f( GLubyte r, GLubyte g, GLubyte b )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLfloat *dest = rmesa->vb.floatspecptr;
- dest[0] = UBYTE_TO_FLOAT(r);
- dest[1] = UBYTE_TO_FLOAT(g);
- dest[2] = UBYTE_TO_FLOAT(b);
- dest[3] = 1.0;
-}
-
-static void radeon_SecondaryColor3ubvEXT_3f( const GLubyte *v )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLfloat *dest = rmesa->vb.floatspecptr;
- dest[0] = UBYTE_TO_FLOAT(v[0]);
- dest[1] = UBYTE_TO_FLOAT(v[1]);
- dest[2] = UBYTE_TO_FLOAT(v[2]);
- dest[3] = 1.0;
-}
-#endif /* 0 */
-
-static void radeon_SecondaryColor3fEXT_3f( GLfloat r, GLfloat g, GLfloat b )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLfloat *dest = rmesa->vb.floatspecptr;
- dest[0] = r;
- dest[1] = g;
- dest[2] = b;
- dest[3] = 1.0;
-}
-
-static void radeon_SecondaryColor3fvEXT_3f( const GLfloat *v )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLfloat *dest = rmesa->vb.floatspecptr;
- dest[0] = v[0];
- dest[1] = v[1];
- dest[2] = v[2];
- dest[3] = 1.0;
-}
-
-
-/* Normal
- */
-static void radeon_Normal3f( GLfloat n0, GLfloat n1, GLfloat n2 )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLfloat *dest = rmesa->vb.normalptr;
- dest[0] = n0;
- dest[1] = n1;
- dest[2] = n2;
-}
-
-static void radeon_Normal3fv( const GLfloat *v )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLfloat *dest = rmesa->vb.normalptr;
- dest[0] = v[0];
- dest[1] = v[1];
- dest[2] = v[2];
-}
-
-
-/* TexCoord
- */
-static void radeon_TexCoord1f( GLfloat s )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLfloat *dest = rmesa->vb.texcoordptr[0];
- dest[0] = s;
- dest[1] = 0;
-}
-
-static void radeon_TexCoord1fv( const GLfloat *v )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLfloat *dest = rmesa->vb.texcoordptr[0];
- dest[0] = v[0];
- dest[1] = 0;
-}
-
-static void radeon_TexCoord2f( GLfloat s, GLfloat t )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLfloat *dest = rmesa->vb.texcoordptr[0];
- dest[0] = s;
- dest[1] = t;
-}
-
-static void radeon_TexCoord2fv( const GLfloat *v )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLfloat *dest = rmesa->vb.texcoordptr[0];
- dest[0] = v[0];
- dest[1] = v[1];
-}
-
-
-/* MultiTexcoord
- *
- * Technically speaking, these functions should subtract GL_TEXTURE0 from
- * \c target before masking and using it. The value of GL_TEXTURE0 is 0x84C0,
- * which has the low-order 5 bits 0. For all possible valid values of
- * \c target. Subtracting GL_TEXTURE0 has the net effect of masking \c target
- * with 0x1F. Masking with 0x1F and then masking with 0x01 is redundant, so
- * the subtraction has been omitted.
- */
-
-static void radeon_MultiTexCoord1fARB( GLenum target, GLfloat s )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLfloat *dest = rmesa->vb.texcoordptr[target & 1];
- dest[0] = s;
- dest[1] = 0;
-}
-
-static void radeon_MultiTexCoord1fvARB( GLenum target, const GLfloat *v )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLfloat *dest = rmesa->vb.texcoordptr[target & 1];
- dest[0] = v[0];
- dest[1] = 0;
-}
-
-static void radeon_MultiTexCoord2fARB( GLenum target, GLfloat s, GLfloat t )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLfloat *dest = rmesa->vb.texcoordptr[target & 1];
- dest[0] = s;
- dest[1] = t;
-}
-
-static void radeon_MultiTexCoord2fvARB( GLenum target, const GLfloat *v )
-{
- GET_CURRENT_CONTEXT(ctx);
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- GLfloat *dest = rmesa->vb.texcoordptr[target & 1];
- dest[0] = v[0];
- dest[1] = v[1];
-}
-
-static struct dynfn *lookup( struct dynfn *l, int key )
-{
- struct dynfn *f;
-
- foreach( f, l ) {
- if (f->key == key)
- return f;
- }
-
- return NULL;
-}
-
-/* Can't use the loopback template for this:
- */
-
-#define CHOOSE(FN, FNTYPE, MASK, ACTIVE, ARGS1, ARGS2 ) \
-static void choose_##FN ARGS1 \
-{ \
- GET_CURRENT_CONTEXT(ctx); \
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx); \
- int key = rmesa->vb.vertex_format & (MASK|ACTIVE); \
- struct dynfn *dfn; \
- \
- dfn = lookup( &rmesa->vb.dfn_cache.FN, key ); \
- if (dfn == 0) \
- dfn = rmesa->vb.codegen.FN( ctx, key ); \
- else if (RADEON_DEBUG & DEBUG_CODEGEN) \
- fprintf(stderr, "%s -- cached codegen\n", __FUNCTION__ ); \
- \
- if (dfn) \
- SET_ ## FN (ctx->Exec, (FNTYPE)(dfn->code)); \
- else { \
- if (RADEON_DEBUG & DEBUG_CODEGEN) \
- fprintf(stderr, "%s -- generic version\n", __FUNCTION__ ); \
- SET_ ## FN (ctx->Exec, radeon_##FN); \
- } \
- \
- ctx->Driver.NeedFlush |= FLUSH_UPDATE_CURRENT; \
- CALL_ ## FN (ctx->Exec, ARGS2); \
-}
-
-
-
-/* For the _3f case, only allow one color function to be hooked in at
- * a time. Eventually, use a similar mechanism to allow selecting the
- * color component of the vertex format based on client behaviour.
- *
- * Note: Perform these actions even if there is a codegen or cached
- * codegen version of the chosen function.
- */
-#define CHOOSE_COLOR(FN, FNTYPE, NR, MASK, ACTIVE, ARGS1, ARGS2 ) \
-static void choose_##FN ARGS1 \
-{ \
- GET_CURRENT_CONTEXT(ctx); \
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx); \
- int key = rmesa->vb.vertex_format & (MASK|ACTIVE); \
- struct dynfn *dfn; \
- \
- if (rmesa->vb.vertex_format & ACTIVE_PKCOLOR) { \
- SET_ ## FN (ctx->Exec, radeon_##FN##_ub); \
- } \
- else if ((rmesa->vb.vertex_format & \
- (ACTIVE_FPCOLOR|ACTIVE_FPALPHA)) == ACTIVE_FPCOLOR) { \
- \
- if (rmesa->vb.installed_color_3f_sz != NR) { \
- rmesa->vb.installed_color_3f_sz = NR; \
- if (NR == 3) ctx->Current.Attrib[VERT_ATTRIB_COLOR0][3] = 1.0; \
- if (ctx->Driver.NeedFlush & FLUSH_UPDATE_CURRENT) { \
- radeon_copy_to_current( ctx ); \
- _mesa_install_exec_vtxfmt( ctx, &rmesa->vb.vtxfmt ); \
- CALL_ ## FN (ctx->Exec, ARGS2); \
- return; \
- } \
- } \
- \
- SET_ ## FN (ctx->Exec, radeon_##FN##_3f); \
- } \
- else { \
- SET_ ## FN (ctx->Exec, radeon_##FN##_4f); \
- } \
- \
- \
- dfn = lookup( &rmesa->vb.dfn_cache.FN, key ); \
- if (!dfn) dfn = rmesa->vb.codegen.FN( ctx, key ); \
- \
- if (dfn) { \
- if (RADEON_DEBUG & DEBUG_CODEGEN) \
- fprintf(stderr, "%s -- codegen version\n", __FUNCTION__ ); \
- SET_ ## FN (ctx->Exec, (FNTYPE)dfn->code); \
- } \
- else if (RADEON_DEBUG & DEBUG_CODEGEN) \
- fprintf(stderr, "%s -- 'c' version\n", __FUNCTION__ ); \
- \
- ctx->Driver.NeedFlush |= FLUSH_UPDATE_CURRENT; \
- CALL_ ## FN (ctx->Exec, ARGS2); \
-}
-
-
-
-/* Right now there are both _ub and _3f versions of the secondary color
- * functions. Currently, we only set-up the hardware to use the _ub versions.
- * The _3f versions are needed for the cases where secondary color isn't used
- * in the vertex format, but it still needs to be stored in the context
- * state vector.
- */
-#define CHOOSE_SECONDARY_COLOR(FN, FNTYPE, MASK, ACTIVE, ARGS1, ARGS2 ) \
-static void choose_##FN ARGS1 \
-{ \
- GET_CURRENT_CONTEXT(ctx); \
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx); \
- int key = rmesa->vb.vertex_format & (MASK|ACTIVE); \
- struct dynfn *dfn = lookup( &rmesa->vb.dfn_cache.FN, key ); \
- \
- if (dfn == 0) \
- dfn = rmesa->vb.codegen.FN( ctx, key ); \
- else if (RADEON_DEBUG & DEBUG_CODEGEN) \
- fprintf(stderr, "%s -- cached version\n", __FUNCTION__ ); \
- \
- if (dfn) \
- SET_ ## FN (ctx->Exec, (FNTYPE)(dfn->code)); \
- else { \
- if (RADEON_DEBUG & DEBUG_CODEGEN) \
- fprintf(stderr, "%s -- generic version\n", __FUNCTION__ ); \
- SET_ ## FN (ctx->Exec, ((rmesa->vb.vertex_format & ACTIVE_PKSPEC) != 0) \
- ? radeon_##FN##_ub : radeon_##FN##_3f); \
- } \
- \
- ctx->Driver.NeedFlush |= FLUSH_UPDATE_CURRENT; \
- CALL_ ## FN (ctx->Exec, ARGS2); \
-}
-
-
-
-
-
-/* Shorthands
- */
-#define ACTIVE_XYZW (RADEON_CP_VC_FRMT_W0|RADEON_CP_VC_FRMT_Z)
-#define ACTIVE_NORM RADEON_CP_VC_FRMT_N0
-
-#define ACTIVE_PKCOLOR RADEON_CP_VC_FRMT_PKCOLOR
-#define ACTIVE_FPCOLOR RADEON_CP_VC_FRMT_FPCOLOR
-#define ACTIVE_FPALPHA RADEON_CP_VC_FRMT_FPALPHA
-#define ACTIVE_COLOR (ACTIVE_FPCOLOR|ACTIVE_PKCOLOR)
-
-#define ACTIVE_PKSPEC RADEON_CP_VC_FRMT_PKSPEC
-#define ACTIVE_FPSPEC RADEON_CP_VC_FRMT_FPSPEC
-#define ACTIVE_SPEC (ACTIVE_FPSPEC|ACTIVE_PKSPEC)
-
-#define ACTIVE_ST0 RADEON_CP_VC_FRMT_ST0
-#define ACTIVE_ST1 RADEON_CP_VC_FRMT_ST1
-#define ACTIVE_ST_ALL (RADEON_CP_VC_FRMT_ST1|RADEON_CP_VC_FRMT_ST0)
-
-/* Each codegen function should be able to be fully specified by a
- * subsetted version of rmesa->vb.vertex_format.
- */
-#define MASK_NORM (ACTIVE_XYZW)
-#define MASK_COLOR (MASK_NORM|ACTIVE_NORM)
-#define MASK_SPEC (MASK_COLOR|ACTIVE_COLOR)
-#define MASK_ST0 (MASK_SPEC|ACTIVE_SPEC)
-#define MASK_ST1 (MASK_ST0|ACTIVE_ST0)
-#define MASK_ST_ALL (MASK_ST1|ACTIVE_ST1)
-#define MASK_VERTEX (MASK_ST_ALL|ACTIVE_FPALPHA)
-
-
-typedef void (*p4f)( GLfloat, GLfloat, GLfloat, GLfloat );
-typedef void (*p3f)( GLfloat, GLfloat, GLfloat );
-typedef void (*p2f)( GLfloat, GLfloat );
-typedef void (*p1f)( GLfloat );
-typedef void (*pe2f)( GLenum, GLfloat, GLfloat );
-typedef void (*pe1f)( GLenum, GLfloat );
-typedef void (*p4ub)( GLubyte, GLubyte, GLubyte, GLubyte );
-typedef void (*p3ub)( GLubyte, GLubyte, GLubyte );
-typedef void (*pfv)( const GLfloat * );
-typedef void (*pefv)( GLenum, const GLfloat * );
-typedef void (*pubv)( const GLubyte * );
-
-
-CHOOSE(Normal3f, p3f, MASK_NORM, ACTIVE_NORM,
- (GLfloat a,GLfloat b,GLfloat c), (a,b,c))
-CHOOSE(Normal3fv, pfv, MASK_NORM, ACTIVE_NORM,
- (const GLfloat *v), (v))
-
-#if 0
-CHOOSE_COLOR(Color4ub, p4ub, 4, MASK_COLOR, ACTIVE_COLOR,
- (GLubyte a,GLubyte b, GLubyte c, GLubyte d), (a,b,c,d))
-CHOOSE_COLOR(Color4ubv, pubv, 4, MASK_COLOR, ACTIVE_COLOR,
- (const GLubyte *v), (v))
-CHOOSE_COLOR(Color3ub, p3ub, 3, MASK_COLOR, ACTIVE_COLOR,
- (GLubyte a,GLubyte b, GLubyte c), (a,b,c))
-CHOOSE_COLOR(Color3ubv, pubv, 3, MASK_COLOR, ACTIVE_COLOR,
- (const GLubyte *v), (v))
-#endif
-
-CHOOSE_COLOR(Color4f, p4f, 4, MASK_COLOR, ACTIVE_COLOR,
- (GLfloat a,GLfloat b, GLfloat c, GLfloat d), (a,b,c,d))
-CHOOSE_COLOR(Color4fv, pfv, 4, MASK_COLOR, ACTIVE_COLOR,
- (const GLfloat *v), (v))
-CHOOSE_COLOR(Color3f, p3f, 3, MASK_COLOR, ACTIVE_COLOR,
- (GLfloat a,GLfloat b, GLfloat c), (a,b,c))
-CHOOSE_COLOR(Color3fv, pfv, 3, MASK_COLOR, ACTIVE_COLOR,
- (const GLfloat *v), (v))
-
-
-#if 0
-CHOOSE_SECONDARY_COLOR(SecondaryColor3ubEXT, p3ub, MASK_SPEC, ACTIVE_SPEC,
- (GLubyte a,GLubyte b, GLubyte c), (a,b,c))
-CHOOSE_SECONDARY_COLOR(SecondaryColor3ubvEXT, pubv, MASK_SPEC, ACTIVE_SPEC,
- (const GLubyte *v), (v))
-#endif
-CHOOSE_SECONDARY_COLOR(SecondaryColor3fEXT, p3f, MASK_SPEC, ACTIVE_SPEC,
- (GLfloat a,GLfloat b, GLfloat c), (a,b,c))
-CHOOSE_SECONDARY_COLOR(SecondaryColor3fvEXT, pfv, MASK_SPEC, ACTIVE_SPEC,
- (const GLfloat *v), (v))
-
-CHOOSE(TexCoord2f, p2f, MASK_ST0, ACTIVE_ST0,
- (GLfloat a,GLfloat b), (a,b))
-CHOOSE(TexCoord2fv, pfv, MASK_ST0, ACTIVE_ST0,
- (const GLfloat *v), (v))
-CHOOSE(TexCoord1f, p1f, MASK_ST0, ACTIVE_ST0,
- (GLfloat a), (a))
-CHOOSE(TexCoord1fv, pfv, MASK_ST0, ACTIVE_ST0,
- (const GLfloat *v), (v))
-
-CHOOSE(MultiTexCoord2fARB, pe2f, MASK_ST_ALL, ACTIVE_ST_ALL,
- (GLenum u,GLfloat a,GLfloat b), (u,a,b))
-CHOOSE(MultiTexCoord2fvARB, pefv, MASK_ST_ALL, ACTIVE_ST_ALL,
- (GLenum u,const GLfloat *v), (u,v))
-CHOOSE(MultiTexCoord1fARB, pe1f, MASK_ST_ALL, ACTIVE_ST_ALL,
- (GLenum u,GLfloat a), (u,a))
-CHOOSE(MultiTexCoord1fvARB, pefv, MASK_ST_ALL, ACTIVE_ST_ALL,
- (GLenum u,const GLfloat *v), (u,v))
-
-CHOOSE(Vertex3f, p3f, MASK_VERTEX, MASK_VERTEX,
- (GLfloat a,GLfloat b,GLfloat c), (a,b,c))
-CHOOSE(Vertex3fv, pfv, MASK_VERTEX, MASK_VERTEX,
- (const GLfloat *v), (v))
-CHOOSE(Vertex2f, p2f, MASK_VERTEX, MASK_VERTEX,
- (GLfloat a,GLfloat b), (a,b))
-CHOOSE(Vertex2fv, pfv, MASK_VERTEX, MASK_VERTEX,
- (const GLfloat *v), (v))
-
-
-
-
-
-void radeonVtxfmtInitChoosers( GLvertexformat *vfmt )
-{
- vfmt->Color3f = choose_Color3f;
- vfmt->Color3fv = choose_Color3fv;
- vfmt->Color4f = choose_Color4f;
- vfmt->Color4fv = choose_Color4fv;
- vfmt->SecondaryColor3fEXT = choose_SecondaryColor3fEXT;
- vfmt->SecondaryColor3fvEXT = choose_SecondaryColor3fvEXT;
- vfmt->MultiTexCoord1fARB = choose_MultiTexCoord1fARB;
- vfmt->MultiTexCoord1fvARB = choose_MultiTexCoord1fvARB;
- vfmt->MultiTexCoord2fARB = choose_MultiTexCoord2fARB;
- vfmt->MultiTexCoord2fvARB = choose_MultiTexCoord2fvARB;
- vfmt->Normal3f = choose_Normal3f;
- vfmt->Normal3fv = choose_Normal3fv;
- vfmt->TexCoord1f = choose_TexCoord1f;
- vfmt->TexCoord1fv = choose_TexCoord1fv;
- vfmt->TexCoord2f = choose_TexCoord2f;
- vfmt->TexCoord2fv = choose_TexCoord2fv;
- vfmt->Vertex2f = choose_Vertex2f;
- vfmt->Vertex2fv = choose_Vertex2fv;
- vfmt->Vertex3f = choose_Vertex3f;
- vfmt->Vertex3fv = choose_Vertex3fv;
-
-#if 0
- vfmt->Color3ub = choose_Color3ub;
- vfmt->Color3ubv = choose_Color3ubv;
- vfmt->Color4ub = choose_Color4ub;
- vfmt->Color4ubv = choose_Color4ubv;
- vfmt->SecondaryColor3ubEXT = choose_SecondaryColor3ubEXT;
- vfmt->SecondaryColor3ubvEXT = choose_SecondaryColor3ubvEXT;
-#endif
-}
-
-
-static struct dynfn *codegen_noop( GLcontext *ctx, int key )
-{
- (void) ctx; (void) key;
- return NULL;
-}
-
-void radeonInitCodegen( struct dfn_generators *gen, GLboolean useCodegen )
-{
- gen->Vertex3f = codegen_noop;
- gen->Vertex3fv = codegen_noop;
- gen->Color4ub = codegen_noop;
- gen->Color4ubv = codegen_noop;
- gen->Normal3f = codegen_noop;
- gen->Normal3fv = codegen_noop;
- gen->TexCoord2f = codegen_noop;
- gen->TexCoord2fv = codegen_noop;
- gen->MultiTexCoord2fARB = codegen_noop;
- gen->MultiTexCoord2fvARB = codegen_noop;
- gen->Vertex2f = codegen_noop;
- gen->Vertex2fv = codegen_noop;
- gen->Color3ub = codegen_noop;
- gen->Color3ubv = codegen_noop;
- gen->Color4f = codegen_noop;
- gen->Color4fv = codegen_noop;
- gen->Color3f = codegen_noop;
- gen->Color3fv = codegen_noop;
- gen->SecondaryColor3fEXT = codegen_noop;
- gen->SecondaryColor3fvEXT = codegen_noop;
- gen->SecondaryColor3ubEXT = codegen_noop;
- gen->SecondaryColor3ubvEXT = codegen_noop;
- gen->TexCoord1f = codegen_noop;
- gen->TexCoord1fv = codegen_noop;
- gen->MultiTexCoord1fARB = codegen_noop;
- gen->MultiTexCoord1fvARB = codegen_noop;
-
- if (useCodegen) {
-#if defined(USE_X86_ASM)
- radeonInitX86Codegen( gen );
-#endif
-
-#if defined(USE_SSE_ASM)
- radeonInitSSECodegen( gen );
-#endif
- }
-}
diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_vtxfmt_sse.c b/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_vtxfmt_sse.c
deleted file mode 100644
index cb5d84011..000000000
--- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_vtxfmt_sse.c
+++ /dev/null
@@ -1,232 +0,0 @@
-/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_vtxfmt_sse.c,v 1.1 2002/10/30 12:51:58 alanh Exp $ */
-/**************************************************************************
-
-Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
- Tungsten Graphics Inc., Cedar Park, Texas.
-
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/*
- * Authors:
- * Keith Whitwell <keith@tungstengraphics.com>
- */
-
-#include "glheader.h"
-#include "imports.h"
-#include "simple_list.h"
-#include "radeon_vtxfmt.h"
-
-#if defined(USE_SSE_ASM)
-#include "x86/common_x86_asm.h"
-
-#define EXTERN( FUNC ) \
-extern const char *FUNC; \
-extern const char *FUNC##_end
-
-EXTERN( _sse_Attribute2fv );
-EXTERN( _sse_Attribute2f );
-EXTERN( _sse_Attribute3fv );
-EXTERN( _sse_Attribute3f );
-EXTERN( _sse_MultiTexCoord2fv );
-EXTERN( _sse_MultiTexCoord2f );
-EXTERN( _sse_MultiTexCoord2fv_2 );
-EXTERN( _sse_MultiTexCoord2f_2 );
-
-/* Build specialized versions of the immediate calls on the fly for
- * the current state.
- */
-
-static struct dynfn *radeon_makeSSEAttribute2fv( struct dynfn * cache, int key,
- const char * name, void * dest)
-{
- struct dynfn *dfn = MALLOC_STRUCT( dynfn );
-
- if (RADEON_DEBUG & DEBUG_CODEGEN)
- fprintf(stderr, "%s 0x%08x\n", name, key );
-
- DFN ( _sse_Attribute2fv, (*cache) );
- FIXUP(dfn->code, 10, 0x0, (int)dest);
- return dfn;
-}
-
-static struct dynfn *radeon_makeSSEAttribute2f( struct dynfn * cache, int key,
- const char * name, void * dest )
-{
- struct dynfn *dfn = MALLOC_STRUCT( dynfn );
-
- if (RADEON_DEBUG & DEBUG_CODEGEN)
- fprintf(stderr, "%s 0x%08x\n", name, key );
-
- DFN ( _sse_Attribute2f, (*cache) );
- FIXUP(dfn->code, 8, 0x0, (int)dest);
- return dfn;
-}
-
-static struct dynfn *radeon_makeSSEAttribute3fv( struct dynfn * cache, int key,
- const char * name, void * dest)
-{
- struct dynfn *dfn = MALLOC_STRUCT( dynfn );
-
- if (RADEON_DEBUG & DEBUG_CODEGEN)
- fprintf(stderr, "%s 0x%08x\n", name, key );
-
- DFN ( _sse_Attribute3fv, (*cache) );
- FIXUP(dfn->code, 13, 0x0, (int)dest);
- FIXUP(dfn->code, 18, 0x8, 8+(int)dest);
- return dfn;
-}
-
-static struct dynfn *radeon_makeSSEAttribute3f( struct dynfn * cache, int key,
- const char * name, void * dest )
-{
- struct dynfn *dfn = MALLOC_STRUCT( dynfn );
-
- if (RADEON_DEBUG & DEBUG_CODEGEN)
- fprintf(stderr, "%s 0x%08x\n", name, key );
-
- DFN ( _sse_Attribute3f, (*cache) );
- FIXUP(dfn->code, 12, 0x0, (int)dest);
- FIXUP(dfn->code, 17, 0x8, 8+(int)dest);
- return dfn;
-}
-
-static struct dynfn * radeon_makeSSENormal3fv( GLcontext *ctx, int key )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-
- return radeon_makeSSEAttribute3fv( & rmesa->vb.dfn_cache.Normal3fv, key,
- __FUNCTION__, rmesa->vb.normalptr );
-}
-
-static struct dynfn *radeon_makeSSENormal3f( GLcontext *ctx, int key )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-
- return radeon_makeSSEAttribute3f( & rmesa->vb.dfn_cache.Normal3f, key,
- __FUNCTION__, rmesa->vb.normalptr );
-}
-
-static struct dynfn *radeon_makeSSEColor3fv( GLcontext *ctx, int key )
-{
- if (key & (RADEON_CP_VC_FRMT_PKCOLOR|RADEON_CP_VC_FRMT_FPALPHA))
- return NULL;
- else
- {
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-
- return radeon_makeSSEAttribute3fv( & rmesa->vb.dfn_cache.Color3fv, key,
- __FUNCTION__, rmesa->vb.floatcolorptr );
- }
-}
-
-static struct dynfn *radeon_makeSSEColor3f( GLcontext *ctx, int key )
-{
- if (key & (RADEON_CP_VC_FRMT_PKCOLOR|RADEON_CP_VC_FRMT_FPALPHA))
- return NULL;
- else
- {
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-
- return radeon_makeSSEAttribute3f( & rmesa->vb.dfn_cache.Color3f, key,
- __FUNCTION__, rmesa->vb.floatcolorptr );
- }
-}
-
-static struct dynfn *radeon_makeSSETexCoord2fv( GLcontext *ctx, int key )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-
- return radeon_makeSSEAttribute2fv( & rmesa->vb.dfn_cache.TexCoord2fv, key,
- __FUNCTION__, rmesa->vb.texcoordptr[0] );
-}
-
-static struct dynfn *radeon_makeSSETexCoord2f( GLcontext *ctx, int key )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-
- return radeon_makeSSEAttribute2f( & rmesa->vb.dfn_cache.TexCoord2f, key,
- __FUNCTION__, rmesa->vb.texcoordptr[0] );
-}
-
-static struct dynfn *radeon_makeSSEMultiTexCoord2fv( GLcontext *ctx, int key )
-{
- struct dynfn *dfn = MALLOC_STRUCT( dynfn );
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-
- if (RADEON_DEBUG & DEBUG_CODEGEN)
- fprintf(stderr, "%s 0x%08x\n", __FUNCTION__, key );
-
- if ((key & (RADEON_CP_VC_FRMT_ST0|RADEON_CP_VC_FRMT_ST1)) ==
- (RADEON_CP_VC_FRMT_ST0|RADEON_CP_VC_FRMT_ST1)) {
- DFN ( _sse_MultiTexCoord2fv, rmesa->vb.dfn_cache.MultiTexCoord2fvARB );
- FIXUP(dfn->code, 18, 0xdeadbeef, (int)rmesa->vb.texcoordptr[0]);
- } else {
- DFN ( _sse_MultiTexCoord2fv_2, rmesa->vb.dfn_cache.MultiTexCoord2fvARB );
- FIXUP(dfn->code, 14, 0x0, (int)rmesa->vb.texcoordptr);
- }
- return dfn;
-}
-
-static struct dynfn *radeon_makeSSEMultiTexCoord2f( GLcontext *ctx, int key )
-{
- struct dynfn *dfn = MALLOC_STRUCT( dynfn );
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-
- if (RADEON_DEBUG & DEBUG_CODEGEN)
- fprintf(stderr, "%s 0x%08x\n", __FUNCTION__, key );
-
- if ((key & (RADEON_CP_VC_FRMT_ST0|RADEON_CP_VC_FRMT_ST1)) ==
- (RADEON_CP_VC_FRMT_ST0|RADEON_CP_VC_FRMT_ST1)) {
- DFN ( _sse_MultiTexCoord2f, rmesa->vb.dfn_cache.MultiTexCoord2fARB );
- FIXUP(dfn->code, 16, 0xdeadbeef, (int)rmesa->vb.texcoordptr[0]);
- } else {
- DFN ( _sse_MultiTexCoord2f_2, rmesa->vb.dfn_cache.MultiTexCoord2fARB );
- FIXUP(dfn->code, 15, 0x0, (int)rmesa->vb.texcoordptr);
- }
- return dfn;
-}
-
-void radeonInitSSECodegen( struct dfn_generators *gen )
-{
- if ( cpu_has_xmm ) {
- gen->Normal3fv = (void *) radeon_makeSSENormal3fv;
- gen->Normal3f = (void *) radeon_makeSSENormal3f;
- gen->Color3fv = (void *) radeon_makeSSEColor3fv;
- gen->Color3f = (void *) radeon_makeSSEColor3f;
- gen->TexCoord2fv = (void *) radeon_makeSSETexCoord2fv;
- gen->TexCoord2f = (void *) radeon_makeSSETexCoord2f;
- gen->MultiTexCoord2fvARB = (void *) radeon_makeSSEMultiTexCoord2fv;
- gen->MultiTexCoord2fARB = (void *) radeon_makeSSEMultiTexCoord2f;
- }
-}
-
-#else
-
-void radeonInitSSECodegen( struct dfn_generators *gen )
-{
- (void) gen;
-}
-
-#endif
diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_vtxfmt_x86.c b/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_vtxfmt_x86.c
deleted file mode 100644
index d1cf1979f..000000000
--- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_vtxfmt_x86.c
+++ /dev/null
@@ -1,437 +0,0 @@
-/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_vtxfmt_x86.c,v 1.2 2002/12/21 17:02:16 dawes Exp $ */
-/**************************************************************************
-
-Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
- Tungsten Graphics Inc., Cedar Park, Texas.
-
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/*
- * Authors:
- * Keith Whitwell <keith@tungstengraphics.com>
- */
-
-#include "glheader.h"
-#include "imports.h"
-#include "simple_list.h"
-#include "radeon_vtxfmt.h"
-
-#if defined(USE_X86_ASM)
-
-#define EXTERN( FUNC ) \
-extern const char *FUNC; \
-extern const char *FUNC##_end
-
-EXTERN ( _x86_Attribute2fv );
-EXTERN ( _x86_Attribute2f );
-EXTERN ( _x86_Attribute3fv );
-EXTERN ( _x86_Attribute3f );
-EXTERN ( _x86_Vertex3fv_6 );
-EXTERN ( _x86_Vertex3fv_8 );
-EXTERN ( _x86_Vertex3fv );
-EXTERN ( _x86_Vertex3f_4 );
-EXTERN ( _x86_Vertex3f_6 );
-EXTERN ( _x86_Vertex3f );
-EXTERN ( _x86_Color4ubv_ub );
-EXTERN ( _x86_Color4ubv_4f );
-EXTERN ( _x86_Color4ub_ub );
-EXTERN ( _x86_MultiTexCoord2fv );
-EXTERN ( _x86_MultiTexCoord2fv_2 );
-EXTERN ( _x86_MultiTexCoord2f );
-EXTERN ( _x86_MultiTexCoord2f_2 );
-
-
-/* Build specialized versions of the immediate calls on the fly for
- * the current state. Generic x86 versions.
- */
-
-struct dynfn *radeon_makeX86Vertex3f( GLcontext *ctx, int key )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- struct dynfn *dfn = MALLOC_STRUCT( dynfn );
-
- if (RADEON_DEBUG & DEBUG_CODEGEN)
- fprintf(stderr, "%s 0x%08x %d\n", __FUNCTION__, key, rmesa->vb.vertex_size );
-
- switch (rmesa->vb.vertex_size) {
- case 4: {
-
- DFN ( _x86_Vertex3f_4, rmesa->vb.dfn_cache.Vertex3f );
- FIXUP(dfn->code, 2, 0x0, (int)&rmesa->vb.dmaptr);
- FIXUP(dfn->code, 25, 0x0, (int)&rmesa->vb.vertex[3]);
- FIXUP(dfn->code, 36, 0x0, (int)&rmesa->vb.counter);
- FIXUP(dfn->code, 46, 0x0, (int)&rmesa->vb.dmaptr);
- FIXUP(dfn->code, 51, 0x0, (int)&rmesa->vb.counter);
- FIXUP(dfn->code, 60, 0x0, (int)&rmesa->vb.notify);
- break;
- }
- case 6: {
-
- DFN ( _x86_Vertex3f_6, rmesa->vb.dfn_cache.Vertex3f );
- FIXUP(dfn->code, 3, 0x0, (int)&rmesa->vb.dmaptr);
- FIXUP(dfn->code, 28, 0x0, (int)&rmesa->vb.vertex[3]);
- FIXUP(dfn->code, 34, 0x0, (int)&rmesa->vb.vertex[4]);
- FIXUP(dfn->code, 40, 0x0, (int)&rmesa->vb.vertex[5]);
- FIXUP(dfn->code, 57, 0x0, (int)&rmesa->vb.counter);
- FIXUP(dfn->code, 63, 0x0, (int)&rmesa->vb.dmaptr);
- FIXUP(dfn->code, 70, 0x0, (int)&rmesa->vb.counter);
- FIXUP(dfn->code, 79, 0x0, (int)&rmesa->vb.notify);
- break;
- }
- default: {
-
- DFN ( _x86_Vertex3f, rmesa->vb.dfn_cache.Vertex3f );
- FIXUP(dfn->code, 3, 0x0, (int)&rmesa->vb.vertex[3]);
- FIXUP(dfn->code, 9, 0x0, (int)&rmesa->vb.dmaptr);
- FIXUP(dfn->code, 37, 0x0, rmesa->vb.vertex_size-3);
- FIXUP(dfn->code, 44, 0x0, (int)&rmesa->vb.counter);
- FIXUP(dfn->code, 50, 0x0, (int)&rmesa->vb.dmaptr);
- FIXUP(dfn->code, 56, 0x0, (int)&rmesa->vb.counter);
- FIXUP(dfn->code, 67, 0x0, (int)&rmesa->vb.notify);
- break;
- }
- }
-
- return dfn;
-}
-
-
-
-struct dynfn *radeon_makeX86Vertex3fv( GLcontext *ctx, int key )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- struct dynfn *dfn = MALLOC_STRUCT( dynfn );
-
- if (RADEON_DEBUG & DEBUG_CODEGEN)
- fprintf(stderr, "%s 0x%08x %d\n", __FUNCTION__, key, rmesa->vb.vertex_size );
-
- switch (rmesa->vb.vertex_size) {
- case 6: {
-
- DFN ( _x86_Vertex3fv_6, rmesa->vb.dfn_cache.Vertex3fv );
- FIXUP(dfn->code, 1, 0x00000000, (int)&rmesa->vb.dmaptr);
- FIXUP(dfn->code, 27, 0x0000001c, (int)&rmesa->vb.vertex[3]);
- FIXUP(dfn->code, 33, 0x00000020, (int)&rmesa->vb.vertex[4]);
- FIXUP(dfn->code, 45, 0x00000024, (int)&rmesa->vb.vertex[5]);
- FIXUP(dfn->code, 56, 0x00000000, (int)&rmesa->vb.dmaptr);
- FIXUP(dfn->code, 61, 0x00000004, (int)&rmesa->vb.counter);
- FIXUP(dfn->code, 67, 0x00000004, (int)&rmesa->vb.counter);
- FIXUP(dfn->code, 76, 0x00000008, (int)&rmesa->vb.notify);
- break;
- }
-
-
- case 8: {
-
- DFN ( _x86_Vertex3fv_8, rmesa->vb.dfn_cache.Vertex3fv );
- FIXUP(dfn->code, 1, 0x00000000, (int)&rmesa->vb.dmaptr);
- FIXUP(dfn->code, 27, 0x0000001c, (int)&rmesa->vb.vertex[3]);
- FIXUP(dfn->code, 33, 0x00000020, (int)&rmesa->vb.vertex[4]);
- FIXUP(dfn->code, 45, 0x0000001c, (int)&rmesa->vb.vertex[5]);
- FIXUP(dfn->code, 51, 0x00000020, (int)&rmesa->vb.vertex[6]);
- FIXUP(dfn->code, 63, 0x00000024, (int)&rmesa->vb.vertex[7]);
- FIXUP(dfn->code, 74, 0x00000000, (int)&rmesa->vb.dmaptr);
- FIXUP(dfn->code, 79, 0x00000004, (int)&rmesa->vb.counter);
- FIXUP(dfn->code, 85, 0x00000004, (int)&rmesa->vb.counter);
- FIXUP(dfn->code, 94, 0x00000008, (int)&rmesa->vb.notify);
- break;
- }
-
-
-
- default: {
-
- DFN ( _x86_Vertex3fv, rmesa->vb.dfn_cache.Vertex3fv );
- FIXUP(dfn->code, 8, 0x01010101, (int)&rmesa->vb.dmaptr);
- FIXUP(dfn->code, 32, 0x00000006, rmesa->vb.vertex_size-3);
- FIXUP(dfn->code, 37, 0x00000058, (int)&rmesa->vb.vertex[3]);
- FIXUP(dfn->code, 45, 0x01010101, (int)&rmesa->vb.dmaptr);
- FIXUP(dfn->code, 50, 0x02020202, (int)&rmesa->vb.counter);
- FIXUP(dfn->code, 58, 0x02020202, (int)&rmesa->vb.counter);
- FIXUP(dfn->code, 67, 0x0, (int)&rmesa->vb.notify);
- break;
- }
- }
-
- return dfn;
-}
-
-static struct dynfn *
-radeon_makeX86Attribute2fv( struct dynfn * cache, int key,
- const char * name, void * dest )
-{
- struct dynfn *dfn = MALLOC_STRUCT( dynfn );
-
- if (RADEON_DEBUG & DEBUG_CODEGEN)
- fprintf(stderr, "%s 0x%08x\n", name, key );
-
- DFN ( _x86_Attribute2fv, (*cache) );
- FIXUP(dfn->code, 11, 0x0, (int)dest);
- FIXUP(dfn->code, 16, 0x4, 4+(int)dest);
-
- return dfn;
-}
-
-static struct dynfn *
-radeon_makeX86Attribute2f( struct dynfn * cache, int key,
- const char * name, void * dest )
-{
- struct dynfn *dfn = MALLOC_STRUCT( dynfn );
-
- if (RADEON_DEBUG & DEBUG_CODEGEN)
- fprintf(stderr, "%s 0x%08x\n", name, key );
-
- DFN ( _x86_Attribute2f, (*cache) );
- FIXUP(dfn->code, 1, 0x0, (int)dest);
-
- return dfn;
-}
-
-
-static struct dynfn *
-radeon_makeX86Attribute3fv( struct dynfn * cache, int key,
- const char * name, void * dest )
-{
- struct dynfn *dfn = MALLOC_STRUCT( dynfn );
-
- if (RADEON_DEBUG & DEBUG_CODEGEN)
- fprintf(stderr, "%s 0x%08x\n", name, key );
-
- DFN ( _x86_Attribute3fv, (*cache) );
- FIXUP(dfn->code, 14, 0x0, (int)dest);
- FIXUP(dfn->code, 20, 0x4, 4+(int)dest);
- FIXUP(dfn->code, 25, 0x8, 8+(int)dest);
-
- return dfn;
-}
-
-static struct dynfn *
-radeon_makeX86Attribute3f( struct dynfn * cache, int key,
- const char * name, void * dest )
-{
- struct dynfn *dfn = MALLOC_STRUCT( dynfn );
-
- if (RADEON_DEBUG & DEBUG_CODEGEN)
- fprintf(stderr, "%s 0x%08x\n", name, key );
-
- DFN ( _x86_Attribute3f, (*cache) );
- FIXUP(dfn->code, 14, 0x0, (int)dest);
- FIXUP(dfn->code, 20, 0x4, 4+(int)dest);
- FIXUP(dfn->code, 25, 0x8, 8+(int)dest);
-
- return dfn;
-}
-
-struct dynfn *radeon_makeX86Normal3fv( GLcontext *ctx, int key )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-
- return radeon_makeX86Attribute3fv( & rmesa->vb.dfn_cache.Normal3fv, key,
- __FUNCTION__, rmesa->vb.normalptr );
-}
-
-struct dynfn *radeon_makeX86Normal3f( GLcontext *ctx, int key )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-
- return radeon_makeX86Attribute3f( & rmesa->vb.dfn_cache.Normal3f, key,
- __FUNCTION__, rmesa->vb.normalptr );
-}
-
-struct dynfn *radeon_makeX86Color4ubv( GLcontext *ctx, int key )
-{
- struct dynfn *dfn = MALLOC_STRUCT( dynfn );
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-
-
- if (RADEON_DEBUG & DEBUG_CODEGEN)
- fprintf(stderr, "%s 0x%08x\n", __FUNCTION__, key );
-
- if (key & RADEON_CP_VC_FRMT_PKCOLOR) {
- DFN ( _x86_Color4ubv_ub, rmesa->vb.dfn_cache.Color4ubv);
- FIXUP(dfn->code, 5, 0x12345678, (int)rmesa->vb.colorptr);
- return dfn;
- }
- else {
-
- DFN ( _x86_Color4ubv_4f, rmesa->vb.dfn_cache.Color4ubv);
- FIXUP(dfn->code, 2, 0x00000000, (int)_mesa_ubyte_to_float_color_tab);
- FIXUP(dfn->code, 27, 0xdeadbeaf, (int)rmesa->vb.floatcolorptr);
- FIXUP(dfn->code, 33, 0xdeadbeaf, (int)rmesa->vb.floatcolorptr+4);
- FIXUP(dfn->code, 55, 0xdeadbeaf, (int)rmesa->vb.floatcolorptr+8);
- FIXUP(dfn->code, 61, 0xdeadbeaf, (int)rmesa->vb.floatcolorptr+12);
- return dfn;
- }
-}
-
-struct dynfn *radeon_makeX86Color4ub( GLcontext *ctx, int key )
-{
- if (RADEON_DEBUG & DEBUG_CODEGEN)
- fprintf(stderr, "%s 0x%08x\n", __FUNCTION__, key );
-
- if (key & RADEON_CP_VC_FRMT_PKCOLOR) {
- struct dynfn *dfn = MALLOC_STRUCT( dynfn );
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-
- DFN ( _x86_Color4ub_ub, rmesa->vb.dfn_cache.Color4ub );
- FIXUP(dfn->code, 18, 0x0, (int)rmesa->vb.colorptr);
- FIXUP(dfn->code, 24, 0x0, (int)rmesa->vb.colorptr+1);
- FIXUP(dfn->code, 30, 0x0, (int)rmesa->vb.colorptr+2);
- FIXUP(dfn->code, 36, 0x0, (int)rmesa->vb.colorptr+3);
- return dfn;
- }
- else
- return NULL;
-}
-
-
-struct dynfn *radeon_makeX86Color3fv( GLcontext *ctx, int key )
-{
- if (key & (RADEON_CP_VC_FRMT_PKCOLOR|RADEON_CP_VC_FRMT_FPALPHA))
- return NULL;
- else
- {
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-
- return radeon_makeX86Attribute3fv( & rmesa->vb.dfn_cache.Color3fv, key,
- __FUNCTION__, rmesa->vb.floatcolorptr );
- }
-}
-
-struct dynfn *radeon_makeX86Color3f( GLcontext *ctx, int key )
-{
- if (key & (RADEON_CP_VC_FRMT_PKCOLOR|RADEON_CP_VC_FRMT_FPALPHA))
- return NULL;
- else
- {
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-
- return radeon_makeX86Attribute3f( & rmesa->vb.dfn_cache.Color3f, key,
- __FUNCTION__, rmesa->vb.floatcolorptr );
- }
-}
-
-
-
-struct dynfn *radeon_makeX86TexCoord2fv( GLcontext *ctx, int key )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-
- return radeon_makeX86Attribute2fv( & rmesa->vb.dfn_cache.TexCoord2fv, key,
- __FUNCTION__, rmesa->vb.texcoordptr[0] );
-}
-
-struct dynfn *radeon_makeX86TexCoord2f( GLcontext *ctx, int key )
-{
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-
- return radeon_makeX86Attribute2f( & rmesa->vb.dfn_cache.TexCoord2f, key,
- __FUNCTION__, rmesa->vb.texcoordptr[0] );
-}
-
-struct dynfn *radeon_makeX86MultiTexCoord2fvARB( GLcontext *ctx, int key )
-{
- struct dynfn *dfn = MALLOC_STRUCT( dynfn );
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-
- if (RADEON_DEBUG & DEBUG_CODEGEN)
- fprintf(stderr, "%s 0x%08x\n", __FUNCTION__, key );
-
- if ((key & (RADEON_CP_VC_FRMT_ST0|RADEON_CP_VC_FRMT_ST1)) ==
- (RADEON_CP_VC_FRMT_ST0|RADEON_CP_VC_FRMT_ST1)) {
- DFN ( _x86_MultiTexCoord2fv, rmesa->vb.dfn_cache.MultiTexCoord2fvARB );
- FIXUP(dfn->code, 21, 0xdeadbeef, (int)rmesa->vb.texcoordptr[0]);
- FIXUP(dfn->code, 27, 0xdeadbeef, (int)rmesa->vb.texcoordptr[0]+4);
- } else {
- DFN ( _x86_MultiTexCoord2fv_2, rmesa->vb.dfn_cache.MultiTexCoord2fvARB );
- FIXUP(dfn->code, 14, 0x0, (int)rmesa->vb.texcoordptr);
- }
- return dfn;
-}
-
-struct dynfn *radeon_makeX86MultiTexCoord2fARB( GLcontext *ctx,
- int key )
-{
- struct dynfn *dfn = MALLOC_STRUCT( dynfn );
- radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-
- if (RADEON_DEBUG & DEBUG_CODEGEN)
- fprintf(stderr, "%s 0x%08x\n", __FUNCTION__, key );
-
- if ((key & (RADEON_CP_VC_FRMT_ST0|RADEON_CP_VC_FRMT_ST1)) ==
- (RADEON_CP_VC_FRMT_ST0|RADEON_CP_VC_FRMT_ST1)) {
- DFN ( _x86_MultiTexCoord2f, rmesa->vb.dfn_cache.MultiTexCoord2fARB );
- FIXUP(dfn->code, 20, 0xdeadbeef, (int)rmesa->vb.texcoordptr[0]);
- FIXUP(dfn->code, 26, 0xdeadbeef, (int)rmesa->vb.texcoordptr[0]+4);
- }
- else {
- /* Note: this might get generated multiple times, even though the
- * actual emitted code is the same.
- */
- DFN ( _x86_MultiTexCoord2f_2, rmesa->vb.dfn_cache.MultiTexCoord2fARB );
- FIXUP(dfn->code, 18, 0x0, (int)rmesa->vb.texcoordptr);
- }
- return dfn;
-}
-
-
-void radeonInitX86Codegen( struct dfn_generators *gen )
-{
- gen->Vertex3f = radeon_makeX86Vertex3f;
- gen->Vertex3fv = radeon_makeX86Vertex3fv;
- gen->Color4ub = radeon_makeX86Color4ub; /* PKCOLOR only */
- gen->Color4ubv = radeon_makeX86Color4ubv; /* PKCOLOR only */
- gen->Normal3f = radeon_makeX86Normal3f;
- gen->Normal3fv = radeon_makeX86Normal3fv;
- gen->TexCoord2f = radeon_makeX86TexCoord2f;
- gen->TexCoord2fv = radeon_makeX86TexCoord2fv;
- gen->MultiTexCoord2fARB = radeon_makeX86MultiTexCoord2fARB;
- gen->MultiTexCoord2fvARB = radeon_makeX86MultiTexCoord2fvARB;
- gen->Color3f = radeon_makeX86Color3f;
- gen->Color3fv = radeon_makeX86Color3fv;
-
- /* Not done:
- */
-/* gen->Vertex2f = radeon_makeX86Vertex2f; */
-/* gen->Vertex2fv = radeon_makeX86Vertex2fv; */
-/* gen->Color3ub = radeon_makeX86Color3ub; */
-/* gen->Color3ubv = radeon_makeX86Color3ubv; */
-/* gen->Color4f = radeon_makeX86Color4f; */
-/* gen->Color4fv = radeon_makeX86Color4fv; */
-/* gen->TexCoord1f = radeon_makeX86TexCoord1f; */
-/* gen->TexCoord1fv = radeon_makeX86TexCoord1fv; */
-/* gen->MultiTexCoord1fARB = radeon_makeX86MultiTexCoord1fARB; */
-/* gen->MultiTexCoord1fvARB = radeon_makeX86MultiTexCoord1fvARB; */
-}
-
-
-#else
-
-void radeonInitX86Codegen( struct dfn_generators *gen )
-{
- (void) gen;
-}
-
-#endif
diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_vtxtmp_x86.S b/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_vtxtmp_x86.S
deleted file mode 100644
index 569d3b9b4..000000000
--- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/radeon_vtxtmp_x86.S
+++ /dev/null
@@ -1,494 +0,0 @@
-/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_vtxtmp_x86.S,v 1.1 2002/10/30 12:51:58 alanh Exp $ */
-/**************************************************************************
-
-Copyright 2002 Tungsten Graphics Inc., Cedar Park, Texas.
-
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining a
-copy of this software and associated documentation files (the "Software"),
-to deal in the Software without restriction, including without limitation
-on the rights to use, copy, modify, merge, publish, distribute, sub
-license, and/or sell copies of the Software, and to permit persons to whom
-the Software is furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice (including the next
-paragraph) shall be included in all copies or substantial portions of the
-Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
-ATI, TUNGSTEN GRAPHICS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
-DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-#define GLOBL( x ) \
-.globl x; \
-x:
-
-.data
-.align 4
-
-/*
- vertex 3f vertex size 4
-*/
-
-GLOBL ( _x86_Vertex3f_4 )
- movl (0), %ecx
- movl 4(%esp), %eax
- movl 8(%esp), %edx
- movl %eax, (%ecx)
- movl %edx, 4(%ecx)
- movl 12(%esp), %eax
- movl (0), %edx
- movl %eax, 8(%ecx)
- movl %edx, 12(%ecx)
- movl (0), %eax
- addl $16, %ecx
- dec %eax
- movl %ecx, (0)
- movl %eax, (0)
- je .1
- ret
-.1: jmp *0
-
-GLOBL ( _x86_Vertex3f_4_end )
-
-/*
- vertex 3f vertex size 6
-*/
-GLOBL ( _x86_Vertex3f_6 )
- push %edi
- movl (0), %edi
- movl 8(%esp), %eax
- movl 12(%esp), %edx
- movl 16(%esp), %ecx
- movl %eax, (%edi)
- movl %edx, 4(%edi)
- movl %ecx, 8(%edi)
- movl (0), %eax
- movl (0), %edx
- movl (0), %ecx
- movl %eax, 12(%edi)
- movl %edx, 16(%edi)
- movl %ecx, 20(%edi)
- addl $24, %edi
- movl (0), %eax
- movl %edi, (0)
- dec %eax
- pop %edi
- movl %eax, (0)
- je .2
- ret
-.2: jmp *0
-GLOBL ( _x86_Vertex3f_6_end )
-/*
- vertex 3f generic size
-*/
-GLOBL ( _x86_Vertex3f )
- push %edi
- push %esi
- movl $0, %esi
- movl (0), %edi
- movl 12(%esp), %eax
- movl 16(%esp), %edx
- movl 20(%esp), %ecx
- movl %eax, (%edi)
- movl %edx, 4(%edi)
- movl %ecx, 8(%edi)
- addl $12, %edi
- movl $0, %ecx
- repz
- movsl %ds:(%esi), %es:(%edi)
- movl (0), %eax
- movl %edi, (0)
- dec %eax
- movl %eax, (0)
- pop %esi
- pop %edi
- je .3
- ret
-.3: jmp *0
-
-GLOBL ( _x86_Vertex3f_end )
-
-/*
- Vertex 3fv vertex size 6
-*/
-GLOBL ( _x86_Vertex3fv_6 )
- movl (0), %eax
- movl 4(%esp), %ecx
- movl (%ecx), %edx
- movl %edx, (%eax)
- movl 4(%ecx), %edx
- movl 8(%ecx), %ecx
- movl %edx, 4(%eax)
- movl %ecx, 8(%eax)
- movl (28), %edx
- movl (32), %ecx
- movl %edx, 12(%eax)
- movl %ecx, 16(%eax)
- movl (36), %edx
- movl %edx, 20(%eax)
- addl $24, %eax
- movl %eax, 0
- movl 4, %eax
- dec %eax
- movl %eax, 4
- je .4
- ret
-.4: jmp *8
-
-GLOBL ( _x86_Vertex3fv_6_end )
-
-/*
- Vertex 3fv vertex size 8
-*/
-GLOBL ( _x86_Vertex3fv_8 )
- movl (0), %eax
- movl 4(%esp), %ecx
- movl (%ecx), %edx
- movl %edx ,(%eax)
- movl 4(%ecx) ,%edx
- movl 8(%ecx) ,%ecx
- movl %edx, 4(%eax)
- movl %ecx, 8(%eax)
- movl (28), %edx
- movl (32), %ecx
- movl %edx, 12(%eax)
- movl %ecx, 16(%eax)
- movl (28), %edx
- movl (32), %ecx
- movl %edx, 20(%eax)
- movl %ecx, 24(%eax)
- movl (36), %edx
- movl %edx, 28(%eax)
- addl $32, %eax
- movl %eax, (0)
- movl 4, %eax
- dec %eax
- movl %eax, (4)
- je .5
- ret
-.5: jmp *8
-
-GLOBL ( _x86_Vertex3fv_8_end )
-
-/*
- Vertex 3fv generic vertex size
-*/
-GLOBL ( _x86_Vertex3fv )
- movl 4(%esp), %edx
- push %edi
- push %esi
- movl (0x1010101), %edi
- movl (%edx), %eax
- movl 4(%edx), %ecx
- movl 8(%edx), %esi
- movl %eax, (%edi)
- movl %ecx, 4(%edi)
- movl %esi, 8(%edi)
- addl $12, %edi
- movl $6, %ecx
- movl $0x58, %esi
- repz
- movsl %ds:(%esi), %es:(%edi)
- movl %edi, (0x1010101)
- movl (0x2020202), %eax
- pop %esi
- pop %edi
- dec %eax
- movl %eax, (0x2020202)
- je .6
- ret
-.6: jmp *0
-GLOBL ( _x86_Vertex3fv_end )
-
-
-/**
- * Generic handler for 2 float format data. This can be used for
- * TexCoord2f and possibly other functions.
- */
-
-GLOBL ( _x86_Attribute2f )
- movl $0x0, %edx
- movl 4(%esp), %eax
- movl 8(%esp), %ecx
- movl %eax, (%edx)
- movl %ecx, 4(%edx)
- ret
-GLOBL ( _x86_Attribute2f_end )
-
-
-/**
- * Generic handler for 2 float vector format data. This can be used for
- * TexCoord2fv and possibly other functions.
- */
-
-GLOBL( _x86_Attribute2fv)
- movl 4(%esp), %eax /* load 'v' off stack */
- movl (%eax), %ecx /* load v[0] */
- movl 4(%eax), %eax /* load v[1] */
- movl %ecx, 0 /* store v[0] to current vertex */
- movl %eax, 4 /* store v[1] to current vertex */
- ret
-GLOBL ( _x86_Attribute2fv_end )
-
-
-/**
- * Generic handler for 3 float format data. This can be used for
- * Normal3f, Color3f (when the color target is also float), or
- * TexCoord3f.
- */
-
-GLOBL ( _x86_Attribute3f )
- movl 4(%esp), %ecx
- movl 8(%esp), %edx
- movl 12(%esp), %eax
- movl %ecx, 0
- movl %edx, 4
- movl %eax, 8
- ret
-GLOBL ( _x86_Attribute3f_end )
-
-/**
- * Generic handler for 3 float vector format data. This can be used for
- * Normal3f, Color3f (when the color target is also float), or
- * TexCoord3f.
- */
-
-GLOBL( _x86_Attribute3fv)
- movl 4(%esp), %eax /* load 'v' off stack */
- movl (%eax), %ecx /* load v[0] */
- movl 4(%eax), %edx /* load v[1] */
- movl 8(%eax), %eax /* load v[2] */
- movl %ecx, 0 /* store v[0] to current vertex */
- movl %edx, 4 /* store v[1] to current vertex */
- movl %eax, 8 /* store v[2] to current vertex */
- ret
-GLOBL ( _x86_Attribute3fv_end )
-
-
-/*
- Color 4ubv_ub
-*/
-GLOBL ( _x86_Color4ubv_ub )
- movl 4(%esp), %eax
- movl $0x12345678, %edx
- movl (%eax), %eax
- movl %eax, (%edx)
- ret
-GLOBL ( _x86_Color4ubv_ub_end )
-
-/*
- Color 4ubv 4f
-*/
-GLOBL ( _x86_Color4ubv_4f )
- push %ebx
- movl $0, %edx
- xor %eax, %eax
- xor %ecx, %ecx
- movl 8(%esp), %ebx
- movl (%ebx), %ebx
- mov %bl, %al
- mov %bh, %cl
- movl (%edx,%eax,4),%eax
- movl (%edx,%ecx,4),%ecx
- movl %eax, (0xdeadbeaf)
- movl %ecx, (0xdeadbeaf)
- xor %eax, %eax
- xor %ecx, %ecx
- shr $16, %ebx
- mov %bl, %al
- mov %bh, %cl
- movl (%edx,%eax,4), %eax
- movl (%edx,%ecx,4), %ecx
- movl %eax, (0xdeadbeaf)
- movl %ecx, (0xdeadbeaf)
- pop %ebx
- ret
-GLOBL ( _x86_Color4ubv_4f_end )
-
-/*
-
- Color4ub_ub
-*/
-GLOBL( _x86_Color4ub_ub )
- push %ebx
- movl 8(%esp), %eax
- movl 12(%esp), %edx
- movl 16(%esp), %ecx
- movl 20(%esp), %ebx
- mov %al, (0)
- mov %dl, (0)
- mov %cl, (0)
- mov %bl, (0)
- pop %ebx
- ret
-GLOBL( _x86_Color4ub_ub_end )
-
-
-/*
- MultiTexCoord2fv st0/st1
-*/
-GLOBL( _x86_MultiTexCoord2fv )
- movl 4(%esp), %eax
- movl 8(%esp), %ecx
- and $1, %eax
- movl (%ecx), %edx
- shl $3, %eax
- movl 4(%ecx), %ecx
- movl %edx, 0xdeadbeef(%eax)
- movl %ecx, 0xdeadbeef(%eax)
- ret
-GLOBL( _x86_MultiTexCoord2fv_end )
-
-/*
- MultiTexCoord2fv
-*/
-
-GLOBL( _x86_MultiTexCoord2fv_2 )
- movl 4(%esp,1), %eax
- movl 8(%esp,1), %ecx
- and $0x1, %eax
- movl 0(,%eax,4), %edx
- movl (%ecx), %eax
- movl %eax, (%edx)
- movl 4(%ecx), %eax
- movl %eax, 4(%edx)
- ret
-GLOBL( _x86_MultiTexCoord2fv_2_end )
-
-/*
- MultiTexCoord2f st0/st1
-*/
-GLOBL( _x86_MultiTexCoord2f )
- movl 4(%esp), %eax
- movl 8(%esp), %edx
- movl 12(%esp), %ecx
- and $1, %eax
- shl $3, %eax
- movl %edx, 0xdeadbeef(%eax)
- movl %ecx, 0xdeadbeef(%eax)
- ret
-GLOBL( _x86_MultiTexCoord2f_end )
-
-/*
- MultiTexCoord2f
-*/
-GLOBL( _x86_MultiTexCoord2f_2 )
- movl 4(%esp), %eax
- movl 8(%esp), %edx
- movl 12(%esp,1), %ecx
- and $1,%eax
- movl 0(,%eax,4), %eax
- movl %edx, (%eax)
- movl %ecx, 4(%eax)
- ret
-GLOBL( _x86_MultiTexCoord2f_2_end )
-
-#if defined(USE_SSE_ASM)
-/**
- * This can be used as a template for either Color3fv (when the color
- * target is also a 3f) or Normal3fv.
- */
-
-GLOBL( _sse_Attribute3fv )
- movl 4(%esp), %eax
- movlps (%eax), %xmm0
- movl 8(%eax), %eax
- movlps %xmm0, 0
- movl %eax, 8
- ret
-GLOBL( _sse_Attribute3fv_end )
-
-/**
- * This can be used as a template for either Color3f (when the color
- * target is also a 3f) or Normal3f.
- */
-
-GLOBL( _sse_Attribute3f )
- movlps 4(%esp), %xmm0
- movl 12(%esp), %eax
- movlps %xmm0, 0
- movl %eax, 8
- ret
-GLOBL( _sse_Attribute3f_end )
-
-
-/**
- * Generic handler for 2 float vector format data. This can be used for
- * TexCoord2fv and possibly other functions.
- */
-
-GLOBL( _sse_Attribute2fv )
- movl 4(%esp), %eax
- movlps (%eax), %xmm0
- movlps %xmm0, 0
- ret
-GLOBL( _sse_Attribute2fv_end )
-
-
-/**
- * Generic handler for 2 float format data. This can be used for
- * TexCoord2f and possibly other functions.
- */
-
-GLOBL( _sse_Attribute2f )
- movlps 4(%esp), %xmm0
- movlps %xmm0, 0
- ret
-GLOBL( _sse_Attribute2f_end )
-
-/*
- MultiTexCoord2fv st0/st1
-*/
-GLOBL( _sse_MultiTexCoord2fv )
- movl 4(%esp), %eax
- movl 8(%esp), %ecx
- and $1, %eax
- movlps (%ecx), %xmm0
- movlps %xmm0, 0xdeadbeef(,%eax,8)
- ret
-GLOBL( _sse_MultiTexCoord2fv_end )
-
-/*
- MultiTexCoord2fv
-*/
-GLOBL( _sse_MultiTexCoord2fv_2 )
- movl 4(%esp), %eax
- movl 8(%esp), %ecx
- and $0x1, %eax
- movl 0(,%eax,4), %edx
- movlps (%ecx), %xmm0
- movlps %xmm0, (%edx)
- ret
-GLOBL( _sse_MultiTexCoord2fv_2_end )
-
-/*
- MultiTexCoord2f st0/st1
-*/
-GLOBL( _sse_MultiTexCoord2f )
- movl 4(%esp), %eax
- and $1, %eax
- movlps 8(%esp), %xmm0
- movlps %xmm0, 0xdeadbeef(,%eax,8)
- ret
-GLOBL( _sse_MultiTexCoord2f_end )
-
-/*
- MultiTexCoord2f
-*/
-GLOBL( _sse_MultiTexCoord2f_2 )
- movl 4(%esp), %eax
- movlps 8(%esp), %xmm0
- and $1,%eax
- movl 0(,%eax,4), %eax
- movlps %xmm0, (%eax)
- ret
-GLOBL( _sse_MultiTexCoord2f_2_end )
-#endif
diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/server/radeon.h b/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/server/radeon.h
deleted file mode 100644
index 21db825c9..000000000
--- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/server/radeon.h
+++ /dev/null
@@ -1,202 +0,0 @@
-/**
- * \file server/radeon.h
- * \brief Radeon 2D driver data structures.
- */
-
-/*
- * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
- * VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
- * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.h,v 1.29 2002/10/12 01:38:07 martin Exp $ */
-
-#ifndef _RADEON_H_
-#define _RADEON_H_
-
-#include "xf86drm.h" /* drm_handle_t, etc */
-
-# define RADEON_AGP_1X_MODE 0x01
-# define RADEON_AGP_2X_MODE 0x02
-# define RADEON_AGP_4X_MODE 0x04
-# define RADEON_AGP_FW_MODE 0x10
-# define RADEON_AGP_MODE_MASK 0x17
-#define RADEON_CP_CSQ_CNTL 0x0740
-# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
-# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
-# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
-# define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
-# define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
-# define RADEON_CSQ_PRIBM_INDBM (4 << 28)
-# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
-
-
-#define PCI_CHIP_R200_BB 0x4242
-#define PCI_CHIP_RV250_Id 0x4964
-#define PCI_CHIP_RV250_Ie 0x4965
-#define PCI_CHIP_RV250_If 0x4966
-#define PCI_CHIP_RV250_Ig 0x4967
-#define PCI_CHIP_RADEON_LW 0x4C57
-#define PCI_CHIP_RADEON_LX 0x4C58
-#define PCI_CHIP_RADEON_LY 0x4C59
-#define PCI_CHIP_RADEON_LZ 0x4C5A
-#define PCI_CHIP_RV250_Ld 0x4C64
-#define PCI_CHIP_RV250_Le 0x4C65
-#define PCI_CHIP_RV250_Lf 0x4C66
-#define PCI_CHIP_RV250_Lg 0x4C67
-#define PCI_CHIP_R300_ND 0x4E44
-#define PCI_CHIP_R300_NE 0x4E45
-#define PCI_CHIP_R300_NF 0x4E46
-#define PCI_CHIP_R300_NG 0x4E47
-#define PCI_CHIP_RADEON_QD 0x5144
-#define PCI_CHIP_RADEON_QE 0x5145
-#define PCI_CHIP_RADEON_QF 0x5146
-#define PCI_CHIP_RADEON_QG 0x5147
-#define PCI_CHIP_R200_QL 0x514C
-#define PCI_CHIP_R200_QN 0x514E
-#define PCI_CHIP_R200_QO 0x514F
-#define PCI_CHIP_RV200_QW 0x5157
-#define PCI_CHIP_RV200_QX 0x5158
-#define PCI_CHIP_RADEON_QY 0x5159
-#define PCI_CHIP_RADEON_QZ 0x515A
-#define PCI_CHIP_R200_Ql 0x516C
-#define PCI_CHIP_RV280_Y_ 0x5960
-#define PCI_CHIP_RV280_Ya 0x5961
-#define PCI_CHIP_RV280_Yb 0x5962
-#define PCI_CHIP_RV280_Yc 0x5963
-
-/**
- * \brief Chip families.
- */
-typedef enum {
- CHIP_FAMILY_UNKNOW,
- CHIP_FAMILY_LEGACY,
- CHIP_FAMILY_R128,
- CHIP_FAMILY_M3,
- CHIP_FAMILY_RADEON,
- CHIP_FAMILY_VE,
- CHIP_FAMILY_M6,
- CHIP_FAMILY_RV200,
- CHIP_FAMILY_M7,
- CHIP_FAMILY_R200,
- CHIP_FAMILY_RV250,
- CHIP_FAMILY_M9,
- CHIP_FAMILY_RV280,
- CHIP_FAMILY_R300
-} RADEONChipFamily;
-
-
-typedef unsigned long memType;
-
-
-/**
- * \brief Radeon DDX driver private data.
- */
-typedef struct {
- int Chipset; /**< \brief Chipset number */
- RADEONChipFamily ChipFamily; /**< \brief Chip family */
-
- unsigned long LinearAddr; /**< \brief Frame buffer physical address */
-
-
- drmSize registerSize; /**< \brief MMIO register map size */
- drm_handle_t registerHandle; /**< \brief MMIO register map handle */
-
- int IsPCI; /* Current card is a PCI card */
-
- /**
- * \name AGP
- */
- /*@{*/
- drmSize gartSize; /**< \brief AGP map size */
- drm_handle_t gartMemHandle; /**< \brief AGP map handle */
- unsigned long gartOffset; /**< \brief AGP offset */
- int gartMode; /**< \brief AGP mode */
- int gartFastWrite;
- /*@}*/
-
- /**
- * \name CP ring buffer data
- */
- /*@{*/
- unsigned long ringStart; /**< \brief Offset into AGP space */
- drm_handle_t ringHandle; /**< \brief Handle from drmAddMap() */
- drmSize ringMapSize; /**< \brief Size of map */
- int ringSize; /**< \brief Size of ring (in MB) */
-
- unsigned long ringReadOffset; /**< \brief Read offset into AGP space */
- drm_handle_t ringReadPtrHandle;/**< \brief Handle from drmAddMap() */
- drmSize ringReadMapSize; /**< \brief Size of map */
- /*@}*/
-
- /**
- * \name CP vertex/indirect buffer data
- */
- /*@{*/
- unsigned long bufStart; /**< \brief Offset into AGP space */
- drm_handle_t bufHandle; /**< \brief Handle from drmAddMap() */
- drmSize bufMapSize; /**< \brief Size of map */
- int bufSize; /**< \brief Size of buffers (in MB) */
- int bufNumBufs; /**< \brief Number of buffers */
- /*@}*/
-
- /**
- * \name CP AGP Texture data
- */
- /*@{*/
- unsigned long gartTexStart; /**< \brief Offset into AGP space */
- drm_handle_t gartTexHandle; /**< \brief Handle from drmAddMap() */
- drmSize gartTexMapSize; /**< \brief Size of map */
- int gartTexSize; /**< \brief Size of AGP tex space (in MB) */
- int log2GARTTexGran;
- /*@}*/
-
- int drmMinor; /**< \brief DRM device minor number */
-
- int frontOffset; /**< \brief Front color buffer offset */
- int frontPitch; /**< \brief Front color buffer pitch */
- int backOffset; /**< \brief Back color buffer offset */
- int backPitch; /**< \brief Back color buffer pitch */
- int depthOffset; /**< \brief Depth buffer offset */
- int depthPitch; /**< \brief Depth buffer pitch */
- int textureOffset; /**< \brief Texture area offset */
- int textureSize; /**< \brief Texture area size */
- int log2TexGran; /**< \brief Texture granularity in base 2 log */
-
- unsigned int frontPitchOffset;
- unsigned int backPitchOffset;
- unsigned int depthPitchOffset;
-
- int colorTiling; /**< \brief Enable color tiling */
-
- int irq; /**< \brief IRQ number */
- int page_flip_enable; /**< \brief Page Flip enable */
- unsigned int gen_int_cntl;
- unsigned int crtc_offset_cntl;
-
-} RADEONInfoRec, *RADEONInfoPtr;
-
-
-#endif /* _RADEON_H_ */
diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/server/radeon_dri.c b/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/server/radeon_dri.c
deleted file mode 100644
index 7f83d868c..000000000
--- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/server/radeon_dri.c
+++ /dev/null
@@ -1,1336 +0,0 @@
-/**
- * \file server/radeon_dri.c
- * \brief File to perform the device-specific initialization tasks typically
- * done in the X server.
- *
- * Here they are converted to run in the client (or perhaps a standalone
- * process), and to work with the frame buffer device rather than the X
- * server infrastructure.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <errno.h>
-#include <unistd.h>
-
-#include "driver.h"
-#include "drm.h"
-#include "memops.h"
-
-#include "radeon.h"
-#include "radeon_dri.h"
-#include "radeon_macros.h"
-#include "radeon_reg.h"
-#include "drm_sarea.h"
-
-static size_t radeon_drm_page_size;
-
-static int RadeonSetParam(const DRIDriverContext *ctx, int param, int value)
-{
- drm_radeon_setparam_t sp;
-
- memset(&sp, 0, sizeof(sp));
- sp.param = param;
- sp.value = value;
-
- if (drmCommandWrite(ctx->drmFD, DRM_RADEON_SETPARAM, &sp, sizeof(sp))) {
- return -1;
- }
-
- return 0;
-}
-
-/**
- * \brief Wait for free FIFO entries.
- *
- * \param ctx display handle.
- * \param entries number of free entries to wait.
- *
- * It polls the free entries from the chip until it reaches the requested value
- * or a timeout (3000 tries) occurs. Aborts the program if the FIFO times out.
- */
-static void RADEONWaitForFifo( const DRIDriverContext *ctx,
- int entries )
-{
- unsigned char *RADEONMMIO = ctx->MMIOAddress;
- int i;
-
- for (i = 0; i < 3000; i++) {
- int fifo_slots =
- INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
- if (fifo_slots >= entries) return;
- }
-
- /* There are recoveries possible, but I haven't seen them work
- * in practice:
- */
- fprintf(stderr, "FIFO timed out: %d entries, stat=0x%08x\n",
- INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK,
- INREG(RADEON_RBBM_STATUS));
- exit(1);
-}
-
-/**
- * \brief Read a PLL register.
- *
- * \param ctx display handle.
- * \param addr PLL register index.
- *
- * \return value of the PLL register.
- */
-static unsigned int RADEONINPLL( const DRIDriverContext *ctx, int addr)
-{
- unsigned char *RADEONMMIO = ctx->MMIOAddress;
- unsigned int data;
-
- OUTREG8(RADEON_CLOCK_CNTL_INDEX, addr & 0x3f);
- data = INREG(RADEON_CLOCK_CNTL_DATA);
-
- return data;
-}
-
-/**
- * \brief Reset graphics card to known state.
- *
- * \param ctx display handle.
- *
- * Resets the values of several Radeon registers.
- */
-static void RADEONEngineReset( const DRIDriverContext *ctx )
-{
- unsigned char *RADEONMMIO = ctx->MMIOAddress;
- unsigned int clock_cntl_index;
- unsigned int mclk_cntl;
- unsigned int rbbm_soft_reset;
- unsigned int host_path_cntl;
- int i;
-
- OUTREGP(RADEON_RB2D_DSTCACHE_CTLSTAT,
- RADEON_RB2D_DC_FLUSH_ALL,
- ~RADEON_RB2D_DC_FLUSH_ALL);
- for (i = 0; i < 512; i++) {
- if (!(INREG(RADEON_RB2D_DSTCACHE_CTLSTAT) & RADEON_RB2D_DC_BUSY))
- break;
- }
-
- clock_cntl_index = INREG(RADEON_CLOCK_CNTL_INDEX);
-
- mclk_cntl = INPLL(ctx, RADEON_MCLK_CNTL);
- OUTPLL(RADEON_MCLK_CNTL, (mclk_cntl |
- RADEON_FORCEON_MCLKA |
- RADEON_FORCEON_MCLKB |
- RADEON_FORCEON_YCLKA |
- RADEON_FORCEON_YCLKB |
- RADEON_FORCEON_MC |
- RADEON_FORCEON_AIC));
-
- /* Soft resetting HDP thru RBBM_SOFT_RESET register can cause some
- * unexpected behaviour on some machines. Here we use
- * RADEON_HOST_PATH_CNTL to reset it.
- */
- host_path_cntl = INREG(RADEON_HOST_PATH_CNTL);
- rbbm_soft_reset = INREG(RADEON_RBBM_SOFT_RESET);
-
- OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
- RADEON_SOFT_RESET_CP |
- RADEON_SOFT_RESET_HI |
- RADEON_SOFT_RESET_SE |
- RADEON_SOFT_RESET_RE |
- RADEON_SOFT_RESET_PP |
- RADEON_SOFT_RESET_E2 |
- RADEON_SOFT_RESET_RB));
- INREG(RADEON_RBBM_SOFT_RESET);
- OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
- (unsigned int) ~(RADEON_SOFT_RESET_CP |
- RADEON_SOFT_RESET_HI |
- RADEON_SOFT_RESET_SE |
- RADEON_SOFT_RESET_RE |
- RADEON_SOFT_RESET_PP |
- RADEON_SOFT_RESET_E2 |
- RADEON_SOFT_RESET_RB)));
- INREG(RADEON_RBBM_SOFT_RESET);
-
- OUTREG(RADEON_HOST_PATH_CNTL, host_path_cntl | RADEON_HDP_SOFT_RESET);
- INREG(RADEON_HOST_PATH_CNTL);
- OUTREG(RADEON_HOST_PATH_CNTL, host_path_cntl);
-
- OUTREG(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
-
- OUTREG(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
- OUTPLL(RADEON_MCLK_CNTL, mclk_cntl);
-}
-
-/**
- * \brief Restore the drawing engine.
- *
- * \param ctx display handle
- *
- * Resets the graphics card and sets initial values for several registers of
- * the card's drawing engine.
- *
- * Turns on the radeon command processor engine (i.e., the ringbuffer).
- */
-static int RADEONEngineRestore( const DRIDriverContext *ctx )
-{
- RADEONInfoPtr info = ctx->driverPrivate;
- unsigned char *RADEONMMIO = ctx->MMIOAddress;
- int pitch64, datatype, dp_gui_master_cntl, err;
-
- fprintf(stderr, "%s\n", __FUNCTION__);
-
- OUTREG(RADEON_RB3D_CNTL, 0);
- RADEONEngineReset( ctx );
-
- switch (ctx->bpp) {
- case 16: datatype = 4; break;
- case 32: datatype = 6; break;
- default: return 0;
- }
-
- dp_gui_master_cntl =
- ((datatype << RADEON_GMC_DST_DATATYPE_SHIFT)
- | RADEON_GMC_CLR_CMP_CNTL_DIS);
-
- pitch64 = ((ctx->shared.virtualWidth * (ctx->bpp / 8) + 0x3f)) >> 6;
-
- RADEONWaitForFifo(ctx, 1);
- OUTREG(RADEON_DEFAULT_OFFSET, ((INREG(RADEON_DEFAULT_OFFSET) & 0xC0000000)
- | (pitch64 << 22)));
-
- RADEONWaitForFifo(ctx, 1);
- OUTREG(RADEON_SURFACE_CNTL, RADEON_SURF_TRANSLATION_DIS);
-
- RADEONWaitForFifo(ctx, 1);
- OUTREG(RADEON_DEFAULT_SC_BOTTOM_RIGHT, (RADEON_DEFAULT_SC_RIGHT_MAX
- | RADEON_DEFAULT_SC_BOTTOM_MAX));
-
- RADEONWaitForFifo(ctx, 1);
- OUTREG(RADEON_DP_GUI_MASTER_CNTL, (dp_gui_master_cntl
- | RADEON_GMC_BRUSH_SOLID_COLOR
- | RADEON_GMC_SRC_DATATYPE_COLOR));
-
- RADEONWaitForFifo(ctx, 7);
- OUTREG(RADEON_DST_LINE_START, 0);
- OUTREG(RADEON_DST_LINE_END, 0);
- OUTREG(RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff);
- OUTREG(RADEON_DP_BRUSH_BKGD_CLR, 0);
- OUTREG(RADEON_DP_SRC_FRGD_CLR, 0xffffffff);
- OUTREG(RADEON_DP_SRC_BKGD_CLR, 0);
- OUTREG(RADEON_DP_WRITE_MASK, 0xffffffff);
- OUTREG(RADEON_AUX_SC_CNTL, 0);
-
-/* RADEONWaitForIdleMMIO(ctx); */
- usleep(100);
-
-
- OUTREG(RADEON_GEN_INT_CNTL, info->gen_int_cntl);
- if (info->colorTiling)
- info->crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
- OUTREG(RADEON_CRTC_OFFSET_CNTL, info->crtc_offset_cntl);
-
- /* Initialize and start the CP if required */
- if ((err = drmCommandNone(ctx->drmFD, DRM_RADEON_CP_START)) != 0) {
- fprintf(stderr, "%s: CP start %d\n", __FUNCTION__, err);
- return 0;
- }
-
- return 1;
-}
-
-
-/**
- * \brief Shutdown the drawing engine.
- *
- * \param ctx display handle
- *
- * Turns off the command processor engine & restores the graphics card
- * to a state that fbdev understands.
- */
-static int RADEONEngineShutdown( const DRIDriverContext *ctx )
-{
- drm_radeon_cp_stop_t stop;
- int ret, i;
-
- stop.flush = 1;
- stop.idle = 1;
-
- ret = drmCommandWrite(ctx->drmFD, DRM_RADEON_CP_STOP, &stop,
- sizeof(drm_radeon_cp_stop_t));
-
- if (ret == 0) {
- return 0;
- } else if (errno != EBUSY) {
- return -errno;
- }
-
- stop.flush = 0;
-
- i = 0;
- do {
- ret = drmCommandWrite(ctx->drmFD, DRM_RADEON_CP_STOP, &stop,
- sizeof(drm_radeon_cp_stop_t));
- } while (ret && errno == EBUSY && i++ < 10);
-
- if (ret == 0) {
- return 0;
- } else if (errno != EBUSY) {
- return -errno;
- }
-
- stop.idle = 0;
-
- if (drmCommandWrite(ctx->drmFD, DRM_RADEON_CP_STOP,
- &stop, sizeof(drm_radeon_cp_stop_t))) {
- return -errno;
- } else {
- return 0;
- }
-}
-
-/**
- * \brief Compute base 2 logarithm.
- *
- * \param val value.
- *
- * \return base 2 logarithm of \p val.
- */
-static int RADEONMinBits(int val)
-{
- int bits;
-
- if (!val) return 1;
- for (bits = 0; val; val >>= 1, ++bits);
- return bits;
-}
-
-/**
- * \brief Initialize the AGP state
- *
- * \param ctx display handle.
- * \param info driver private data.
- *
- * \return one on success, or zero on failure.
- *
- * Acquires and enables the AGP device. Reserves memory in the AGP space for
- * the ring buffer, vertex buffers and textures. Initialize the Radeon
- * registers to point to that memory and add client mappings.
- */
-static int RADEONDRIAgpInit( const DRIDriverContext *ctx, RADEONInfoPtr info)
-{
- unsigned char *RADEONMMIO = ctx->MMIOAddress;
- unsigned long mode;
- int ret;
- int s, l;
-
- if (drmAgpAcquire(ctx->drmFD) < 0) {
- fprintf(stderr, "[gart] AGP not available\n");
- return 0;
- }
-
- /* Modify the mode if the default mode is not appropriate for this
- * particular combination of graphics card and AGP chipset.
- */
- mode = drmAgpGetMode(ctx->drmFD); /* Default mode */
-
- /* Disable fast write entirely - too many lockups.
- */
- mode &= ~RADEON_AGP_MODE_MASK;
- switch (ctx->agpmode) {
- case 4: mode |= RADEON_AGP_4X_MODE;
- case 2: mode |= RADEON_AGP_2X_MODE;
- case 1: default: mode |= RADEON_AGP_1X_MODE;
- }
-
- if (drmAgpEnable(ctx->drmFD, mode) < 0) {
- fprintf(stderr, "[gart] AGP not enabled\n");
- drmAgpRelease(ctx->drmFD);
- return 0;
- }
- else
- fprintf(stderr, "[gart] AGP enabled at %dx\n", ctx->agpmode);
-
- /* Workaround for some hardware bugs */
- if (info->ChipFamily < CHIP_FAMILY_R200)
- OUTREG(RADEON_AGP_CNTL, INREG(RADEON_AGP_CNTL) | 0x000e0000);
-
- info->gartOffset = 0;
-
- if ((ret = drmAgpAlloc(ctx->drmFD, info->gartSize*1024*1024, 0, NULL,
- &info->gartMemHandle)) < 0) {
- fprintf(stderr, "[gart] Out of memory (%d)\n", ret);
- drmAgpRelease(ctx->drmFD);
- return 0;
- }
- fprintf(stderr,
- "[gart] %d kB allocated with handle 0x%08x\n",
- info->gartSize*1024, (unsigned)info->gartMemHandle);
-
- if (drmAgpBind(ctx->drmFD,
- info->gartMemHandle, info->gartOffset) < 0) {
- fprintf(stderr, "[gart] Could not bind\n");
- drmAgpFree(ctx->drmFD, info->gartMemHandle);
- drmAgpRelease(ctx->drmFD);
- return 0;
- }
-
- /* Initialize the CP ring buffer data */
- info->ringStart = info->gartOffset;
- info->ringMapSize = info->ringSize*1024*1024 + radeon_drm_page_size;
-
- info->ringReadOffset = info->ringStart + info->ringMapSize;
- info->ringReadMapSize = radeon_drm_page_size;
-
- /* Reserve space for vertex/indirect buffers */
- info->bufStart = info->ringReadOffset + info->ringReadMapSize;
- info->bufMapSize = info->bufSize*1024*1024;
-
- /* Reserve the rest for AGP textures */
- info->gartTexStart = info->bufStart + info->bufMapSize;
- s = (info->gartSize*1024*1024 - info->gartTexStart);
- l = RADEONMinBits((s-1) / RADEON_NR_TEX_REGIONS);
- if (l < RADEON_LOG_TEX_GRANULARITY) l = RADEON_LOG_TEX_GRANULARITY;
- info->gartTexMapSize = (s >> l) << l;
- info->log2GARTTexGran = l;
-
- if (drmAddMap(ctx->drmFD, info->ringStart, info->ringMapSize,
- DRM_AGP, DRM_READ_ONLY, &info->ringHandle) < 0) {
- fprintf(stderr, "[gart] Could not add ring mapping\n");
- return 0;
- }
- fprintf(stderr, "[gart] ring handle = 0x%08x\n", info->ringHandle);
-
-
- if (drmAddMap(ctx->drmFD, info->ringReadOffset, info->ringReadMapSize,
- DRM_AGP, DRM_READ_ONLY, &info->ringReadPtrHandle) < 0) {
- fprintf(stderr,
- "[gart] Could not add ring read ptr mapping\n");
- return 0;
- }
-
- fprintf(stderr,
- "[gart] ring read ptr handle = 0x%08lx\n",
- info->ringReadPtrHandle);
-
- if (drmAddMap(ctx->drmFD, info->bufStart, info->bufMapSize,
- DRM_AGP, 0, &info->bufHandle) < 0) {
- fprintf(stderr,
- "[gart] Could not add vertex/indirect buffers mapping\n");
- return 0;
- }
- fprintf(stderr,
- "[gart] vertex/indirect buffers handle = 0x%08x\n",
- info->bufHandle);
-
- if (drmAddMap(ctx->drmFD, info->gartTexStart, info->gartTexMapSize,
- DRM_AGP, 0, &info->gartTexHandle) < 0) {
- fprintf(stderr,
- "[gart] Could not add AGP texture map mapping\n");
- return 0;
- }
- fprintf(stderr,
- "[gart] AGP texture map handle = 0x%08lx\n",
- info->gartTexHandle);
-
- /* Initialize Radeon's AGP registers */
- /* Ring buffer is at AGP offset 0 */
- OUTREG(RADEON_AGP_BASE, info->ringHandle);
-
- return 1;
-}
-
-/* Initialize the PCI GART state. Request memory for use in PCI space,
- * and initialize the Radeon registers to point to that memory.
- */
-static int RADEONDRIPciInit(const DRIDriverContext *ctx, RADEONInfoPtr info)
-{
- int ret;
- int flags = DRM_READ_ONLY | DRM_LOCKED | DRM_KERNEL;
- int s, l;
-
- ret = drmScatterGatherAlloc(ctx->drmFD, info->gartSize*1024*1024,
- &info->gartMemHandle);
- if (ret < 0) {
- fprintf(stderr, "[pci] Out of memory (%d)\n", ret);
- return 0;
- }
- fprintf(stderr,
- "[pci] %d kB allocated with handle 0x%08lx\n",
- info->gartSize*1024, info->gartMemHandle);
-
- info->gartOffset = 0;
-
- /* Initialize the CP ring buffer data */
- info->ringStart = info->gartOffset;
- info->ringMapSize = info->ringSize*1024*1024 + radeon_drm_page_size;
-
- info->ringReadOffset = info->ringStart + info->ringMapSize;
- info->ringReadMapSize = radeon_drm_page_size;
-
- /* Reserve space for vertex/indirect buffers */
- info->bufStart = info->ringReadOffset + info->ringReadMapSize;
- info->bufMapSize = info->bufSize*1024*1024;
-
- /* Reserve the rest for AGP textures */
- info->gartTexStart = info->bufStart + info->bufMapSize;
- s = (info->gartSize*1024*1024 - info->gartTexStart);
- l = RADEONMinBits((s-1) / RADEON_NR_TEX_REGIONS);
- if (l < RADEON_LOG_TEX_GRANULARITY) l = RADEON_LOG_TEX_GRANULARITY;
- info->gartTexMapSize = (s >> l) << l;
- info->log2GARTTexGran = l;
-
- if (drmAddMap(ctx->drmFD, info->ringStart, info->ringMapSize,
- DRM_SCATTER_GATHER, flags, &info->ringHandle) < 0) {
- fprintf(stderr,
- "[pci] Could not add ring mapping\n");
- return 0;
- }
- fprintf(stderr,
- "[pci] ring handle = 0x%08x\n", info->ringHandle);
-
- if (drmAddMap(ctx->drmFD, info->ringReadOffset, info->ringReadMapSize,
- DRM_SCATTER_GATHER, flags, &info->ringReadPtrHandle) < 0) {
- fprintf(stderr,
- "[pci] Could not add ring read ptr mapping\n");
- return 0;
- }
- fprintf(stderr,
- "[pci] ring read ptr handle = 0x%08lx\n",
- info->ringReadPtrHandle);
-
- if (drmAddMap(ctx->drmFD, info->bufStart, info->bufMapSize,
- DRM_SCATTER_GATHER, 0, &info->bufHandle) < 0) {
- fprintf(stderr,
- "[pci] Could not add vertex/indirect buffers mapping\n");
- return 0;
- }
- fprintf(stderr,
- "[pci] vertex/indirect buffers handle = 0x%08lx\n",
- info->bufHandle);
-
- if (drmAddMap(ctx->drmFD, info->gartTexStart, info->gartTexMapSize,
- DRM_SCATTER_GATHER, 0, &info->gartTexHandle) < 0) {
- fprintf(stderr,
- "[pci] Could not add GART texture map mapping\n");
- return 0;
- }
- fprintf(stderr,
- "[pci] GART texture map handle = 0x%08x\n",
- info->gartTexHandle);
-
- return 1;
-}
-
-
-/**
- * \brief Initialize the kernel data structures and enable the CP engine.
- *
- * \param ctx display handle.
- * \param info driver private data.
- *
- * \return non-zero on success, or zero on failure.
- *
- * This function is a wrapper around the DRM_RADEON_CP_INIT command, passing
- * all the parameters in a drm_radeon_init_t structure.
- */
-static int RADEONDRIKernelInit( const DRIDriverContext *ctx,
- RADEONInfoPtr info)
-{
- int cpp = ctx->bpp / 8;
- drm_radeon_init_t drmInfo;
- int ret;
-
- memset(&drmInfo, 0, sizeof(drm_radeon_init_t));
-
- if ( (info->ChipFamily == CHIP_FAMILY_R200) ||
- (info->ChipFamily == CHIP_FAMILY_RV250) ||
- (info->ChipFamily == CHIP_FAMILY_M9) ||
- (info->ChipFamily == CHIP_FAMILY_RV280) )
- drmInfo.func = RADEON_INIT_R200_CP;
- else
- drmInfo.func = RADEON_INIT_CP;
-
- /* This is the struct passed to the kernel module for its initialization */
- drmInfo.sarea_priv_offset = sizeof(drm_sarea_t);
- drmInfo.is_pci = ctx->isPCI;
- drmInfo.cp_mode = RADEON_DEFAULT_CP_BM_MODE;
- drmInfo.gart_size = info->gartSize*1024*1024;
- drmInfo.ring_size = info->ringSize*1024*1024;
- drmInfo.usec_timeout = 1000;
- drmInfo.fb_bpp = ctx->bpp;
- drmInfo.depth_bpp = ctx->bpp;
- drmInfo.front_offset = info->frontOffset;
- drmInfo.front_pitch = info->frontPitch * cpp;
- drmInfo.back_offset = info->backOffset;
- drmInfo.back_pitch = info->backPitch * cpp;
- drmInfo.depth_offset = info->depthOffset;
- drmInfo.depth_pitch = info->depthPitch * cpp;
- drmInfo.fb_offset = info->LinearAddr;
- drmInfo.mmio_offset = info->registerHandle;
- drmInfo.ring_offset = info->ringHandle;
- drmInfo.ring_rptr_offset = info->ringReadPtrHandle;
- drmInfo.buffers_offset = info->bufHandle;
- drmInfo.gart_textures_offset = info->gartTexHandle;
-
- ret = drmCommandWrite(ctx->drmFD, DRM_RADEON_CP_INIT, &drmInfo,
- sizeof(drm_radeon_init_t));
-
- return ret >= 0;
-}
-
-
-/**
- * \brief Initialize the AGP heap.
- *
- * \param ctx display handle.
- * \param info driver private data.
- *
- * This function is a wrapper around the DRM_RADEON_INIT_HEAP command, passing
- * all the parameters in a drm_radeon_mem_init_heap structure.
- */
-static void RADEONDRIAgpHeapInit(const DRIDriverContext *ctx,
- RADEONInfoPtr info)
-{
- drm_radeon_mem_init_heap_t drmHeap;
-
- /* Start up the simple memory manager for gart space */
- drmHeap.region = RADEON_MEM_REGION_GART;
- drmHeap.start = 0;
- drmHeap.size = info->gartTexMapSize;
-
- if (drmCommandWrite(ctx->drmFD, DRM_RADEON_INIT_HEAP,
- &drmHeap, sizeof(drmHeap))) {
- fprintf(stderr,
- "[drm] Failed to initialized gart heap manager\n");
- } else {
- fprintf(stderr,
- "[drm] Initialized kernel gart heap manager, %d\n",
- info->gartTexMapSize);
- }
-}
-
-/**
- * \brief Add a map for the vertex buffers that will be accessed by any
- * DRI-based clients.
- *
- * \param ctx display handle.
- * \param info driver private data.
- *
- * \return one on success, or zero on failure.
- *
- * Calls drmAddBufs() with the previously allocated vertex buffers.
- */
-static int RADEONDRIBufInit( const DRIDriverContext *ctx, RADEONInfoPtr info )
-{
- /* Initialize vertex buffers */
- info->bufNumBufs = drmAddBufs(ctx->drmFD,
- info->bufMapSize / RADEON_BUFFER_SIZE,
- RADEON_BUFFER_SIZE,
- ctx->isPCI ? DRM_SG_BUFFER : DRM_AGP_BUFFER,
- info->bufStart);
-
- if (info->bufNumBufs <= 0) {
- fprintf(stderr,
- "[drm] Could not create vertex/indirect buffers list\n");
- return 0;
- }
- fprintf(stderr,
- "[drm] Added %d %d byte vertex/indirect buffers\n",
- info->bufNumBufs, RADEON_BUFFER_SIZE);
-
- return 1;
-}
-
-/**
- * \brief Install an IRQ handler.
- *
- * \param ctx display handle.
- * \param info driver private data.
- *
- * Attempts to install an IRQ handler via drmCtlInstHandler(), falling back to
- * IRQ-free operation on failure.
- */
-static void RADEONDRIIrqInit(const DRIDriverContext *ctx,
- RADEONInfoPtr info)
-{
- if (!info->irq) {
- info->irq = drmGetInterruptFromBusID(ctx->drmFD,
- ctx->pciBus,
- ctx->pciDevice,
- ctx->pciFunc);
-
- if ((drmCtlInstHandler(ctx->drmFD, info->irq)) != 0) {
- fprintf(stderr,
- "[drm] failure adding irq handler, "
- "there is a device already using that irq\n"
- "[drm] falling back to irq-free operation\n");
- info->irq = 0;
- }
- }
-
- if (info->irq)
- fprintf(stderr,
- "[drm] dma control initialized, using IRQ %d\n",
- info->irq);
-}
-
-static int RADEONCheckDRMVersion( const DRIDriverContext *ctx,
- RADEONInfoPtr info )
-{
- drmVersionPtr version;
-
- version = drmGetVersion(ctx->drmFD);
- if (version) {
- int req_minor, req_patch;
-
- /* Need 1.8.x for proper cleanup-on-client-exit behaviour.
- */
- req_minor = 8;
- req_patch = 0;
-
- if (version->version_major != 1 ||
- version->version_minor < req_minor ||
- (version->version_minor == req_minor &&
- version->version_patchlevel < req_patch)) {
- /* Incompatible drm version */
- fprintf(stderr,
- "[dri] RADEONDRIScreenInit failed because of a version "
- "mismatch.\n"
- "[dri] radeon.o kernel module version is %d.%d.%d "
- "but version 1.%d.%d or newer is needed.\n"
- "[dri] Disabling DRI.\n",
- version->version_major,
- version->version_minor,
- version->version_patchlevel,
- req_minor,
- req_patch);
- drmFreeVersion(version);
- return 0;
- }
-
- info->drmMinor = version->version_minor;
- drmFreeVersion(version);
- }
-
- return 1;
-}
-
-static int RADEONMemoryInit( const DRIDriverContext *ctx, RADEONInfoPtr info )
-{
- int width_bytes = ctx->shared.virtualWidth * ctx->cpp;
- int cpp = ctx->cpp;
- int bufferSize = ((((ctx->shared.virtualHeight+15) & ~15) * width_bytes + RADEON_BUFFER_ALIGN) & ~RADEON_BUFFER_ALIGN);
- int depthSize = ((((ctx->shared.virtualHeight+15) & ~15) * width_bytes
- + RADEON_BUFFER_ALIGN) & ~RADEON_BUFFER_ALIGN);
- int l;
-
- info->frontOffset = 0;
- info->frontPitch = ctx->shared.virtualWidth;
-
- fprintf(stderr,
- "Using %d MB AGP aperture\n", info->gartSize);
- fprintf(stderr,
- "Using %d MB for the ring buffer\n", info->ringSize);
- fprintf(stderr,
- "Using %d MB for vertex/indirect buffers\n", info->bufSize);
- fprintf(stderr,
- "Using %d MB for AGP textures\n", info->gartTexSize);
-
- /* Front, back and depth buffers - everything else texture??
- */
- info->textureSize = ctx->shared.fbSize - 2 * bufferSize - depthSize;
-
- if (ctx->colorTiling==1)
- {
- info->textureSize = ctx->shared.fbSize - ((ctx->shared.fbSize - info->textureSize + width_bytes * 16 - 1) / (width_bytes * 16)) * (width_bytes*16);
- }
-
- if (info->textureSize < 0)
- return 0;
-
- l = RADEONMinBits((info->textureSize-1) / RADEON_NR_TEX_REGIONS);
- if (l < RADEON_LOG_TEX_GRANULARITY) l = RADEON_LOG_TEX_GRANULARITY;
-
- /* Round the texture size up to the nearest whole number of
- * texture regions. Again, be greedy about this, don't
- * round down.
- */
- info->log2TexGran = l;
- info->textureSize = (info->textureSize >> l) << l;
-
- /* Set a minimum usable local texture heap size. This will fit
- * two 256x256x32bpp textures.
- */
- if (info->textureSize < 512 * 1024) {
- info->textureOffset = 0;
- info->textureSize = 0;
- }
-
- /* Reserve space for textures */
- if (ctx->colorTiling==1)
- {
- info->textureOffset = ((ctx->shared.fbSize - info->textureSize) /
- (width_bytes * 16)) * (width_bytes*16);
- }
- else
- {
- info->textureOffset = ((ctx->shared.fbSize - info->textureSize +
- RADEON_BUFFER_ALIGN) &
- ~RADEON_BUFFER_ALIGN);
- }
- /* Reserve space for the shared depth
- * buffer.
- */
- info->depthOffset = ((info->textureOffset - depthSize +
- RADEON_BUFFER_ALIGN) &
- ~RADEON_BUFFER_ALIGN);
- info->depthPitch = ctx->shared.virtualWidth;
-
- info->backOffset = ((info->depthOffset - bufferSize +
- RADEON_BUFFER_ALIGN) &
- ~RADEON_BUFFER_ALIGN);
- info->backPitch = ctx->shared.virtualWidth;
-
-
- fprintf(stderr,
- "Will use back buffer at offset 0x%x\n",
- info->backOffset);
- fprintf(stderr,
- "Will use depth buffer at offset 0x%x\n",
- info->depthOffset);
- fprintf(stderr,
- "Will use %d kb for textures at offset 0x%x\n",
- info->textureSize/1024, info->textureOffset);
-
- info->frontPitchOffset = (((info->frontPitch * cpp / 64) << 22) |
- (info->frontOffset >> 10));
-
- info->backPitchOffset = (((info->backPitch * cpp / 64) << 22) |
- (info->backOffset >> 10));
-
- info->depthPitchOffset = (((info->depthPitch * cpp / 64) << 22) |
- (info->depthOffset >> 10));
-
- return 1;
-}
-
-static int RADEONColorTilingInit( const DRIDriverContext *ctx, RADEONInfoPtr info )
-{
- int width_bytes = ctx->shared.virtualWidth * ctx->cpp;
- int bufferSize = ((((ctx->shared.virtualHeight+15) & ~15) * width_bytes + RADEON_BUFFER_ALIGN)
- & ~RADEON_BUFFER_ALIGN);
- /* Setup color tiling */
- if (info->drmMinor<14)
- info->colorTiling=0;
-
- if (info->colorTiling)
- {
-
- int colorTilingFlag;
- drm_radeon_surface_alloc_t front,back;
-
- RadeonSetParam(ctx, RADEON_SETPARAM_SWITCH_TILING, info->colorTiling ? 1 : 0);
-
- /* Setup the surfaces */
- if (info->ChipFamily < CHIP_FAMILY_R200)
- colorTilingFlag=RADEON_SURF_TILE_COLOR_MACRO;
- else
- colorTilingFlag=R200_SURF_TILE_COLOR_MACRO;
-
- front.address = info->frontOffset;
- front.size = bufferSize;
- front.flags = (width_bytes) | colorTilingFlag;
- drmCommandWrite(ctx->drmFD, DRM_RADEON_SURF_ALLOC, &front,sizeof(front));
-
- back.address = info->backOffset;
- back.size = bufferSize;
- back.flags = (width_bytes) | colorTilingFlag;
- drmCommandWrite(ctx->drmFD, DRM_RADEON_SURF_ALLOC, &back,sizeof(back));
-
- }
- return 1;
-}
-
-
-
-/**
- * Called at the start of each server generation.
- *
- * \param ctx display handle.
- * \param info driver private data.
- *
- * \return non-zero on success, or zero on failure.
- *
- * Performs static frame buffer allocation. Opens the DRM device and add maps
- * to the SAREA, framebuffer and MMIO regions. Fills in \p info with more
- * information. Creates a \e server context to grab the lock for the
- * initialization ioctls and calls the other initilization functions in this
- * file. Starts the CP engine via the DRM_RADEON_CP_START command.
- *
- * Setups a RADEONDRIRec structure to be passed to radeon_dri.so for its
- * initialization.
- */
-static int RADEONScreenInit( DRIDriverContext *ctx, RADEONInfoPtr info )
-{
- RADEONDRIPtr pRADEONDRI;
- int err;
-
- usleep(100);
- /*assert(!ctx->IsClient);*/
-
- {
- int width_bytes = (ctx->shared.virtualWidth * ctx->cpp);
- int maxy = ctx->shared.fbSize / width_bytes;
-
-
- if (maxy <= ctx->shared.virtualHeight * 3) {
- fprintf(stderr,
- "Static buffer allocation failed -- "
- "need at least %d kB video memory (have %d kB)\n",
- (ctx->shared.virtualWidth * ctx->shared.virtualHeight *
- ctx->cpp * 3 + 1023) / 1024,
- ctx->shared.fbSize / 1024);
- return 0;
- }
- }
-
-
- if (info->ChipFamily >= CHIP_FAMILY_R300) {
- fprintf(stderr,
- "Direct rendering not yet supported on "
- "Radeon 9700 and newer cards\n");
- return 0;
- }
-
- radeon_drm_page_size = getpagesize();
-
- info->registerSize = ctx->MMIOSize;
- ctx->shared.SAREASize = SAREA_MAX;
-
- /* Note that drmOpen will try to load the kernel module, if needed. */
- ctx->drmFD = drmOpen("radeon", NULL );
- if (ctx->drmFD < 0) {
- fprintf(stderr, "[drm] drmOpen failed\n");
- return 0;
- }
-
- if ((err = drmSetBusid(ctx->drmFD, ctx->pciBusID)) < 0) {
- fprintf(stderr, "[drm] drmSetBusid failed (%d, %s), %s\n",
- ctx->drmFD, ctx->pciBusID, strerror(-err));
- return 0;
- }
-
- if (drmAddMap( ctx->drmFD,
- 0,
- ctx->shared.SAREASize,
- DRM_SHM,
- DRM_CONTAINS_LOCK,
- &ctx->shared.hSAREA) < 0)
- {
- fprintf(stderr, "[drm] drmAddMap failed\n");
- return 0;
- }
- fprintf(stderr, "[drm] added %d byte SAREA at 0x%08lx\n",
- ctx->shared.SAREASize, ctx->shared.hSAREA);
-
- if (drmMap( ctx->drmFD,
- ctx->shared.hSAREA,
- ctx->shared.SAREASize,
- (drmAddressPtr)(&ctx->pSAREA)) < 0)
- {
- fprintf(stderr, "[drm] drmMap failed\n");
- return 0;
- }
- memset(ctx->pSAREA, 0, ctx->shared.SAREASize);
- fprintf(stderr, "[drm] mapped SAREA 0x%08lx to %p, size %d\n",
- ctx->shared.hSAREA, ctx->pSAREA, ctx->shared.SAREASize);
-
- /* Need to AddMap the framebuffer and mmio regions here:
- */
- if (drmAddMap( ctx->drmFD,
- (drm_handle_t)ctx->FBStart,
- ctx->FBSize,
- DRM_FRAME_BUFFER,
-#ifndef _EMBEDDED
- 0,
-#else
- DRM_READ_ONLY,
-#endif
- &ctx->shared.hFrameBuffer) < 0)
- {
- fprintf(stderr, "[drm] drmAddMap framebuffer failed\n");
- return 0;
- }
-
- fprintf(stderr, "[drm] framebuffer handle = 0x%08lx\n",
- ctx->shared.hFrameBuffer);
-
-
-
- if (drmAddMap(ctx->drmFD,
- ctx->MMIOStart,
- ctx->MMIOSize,
- DRM_REGISTERS,
- DRM_READ_ONLY,
- &info->registerHandle) < 0) {
- fprintf(stderr, "[drm] drmAddMap mmio failed\n");
- return 0;
- }
- fprintf(stderr,
- "[drm] register handle = 0x%08lx\n", info->registerHandle);
-
- /* Check the radeon DRM version */
- if (!RADEONCheckDRMVersion(ctx, info)) {
- return 0;
- }
-
- if (ctx->isPCI) {
- /* Initialize PCI */
- if (!RADEONDRIPciInit(ctx, info))
- return 0;
- }
- else {
- /* Initialize AGP */
- if (!RADEONDRIAgpInit(ctx, info))
- return 0;
- }
-
- /* Memory manager setup */
- if (!RADEONMemoryInit(ctx, info)) {
- return 0;
- }
-
- /* Create a 'server' context so we can grab the lock for
- * initialization ioctls.
- */
- if ((err = drmCreateContext(ctx->drmFD, &ctx->serverContext)) != 0) {
- fprintf(stderr, "%s: drmCreateContext failed %d\n", __FUNCTION__, err);
- return 0;
- }
-
- DRM_LOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext, 0);
-
- /* Initialize the kernel data structures */
- if (!RADEONDRIKernelInit(ctx, info)) {
- fprintf(stderr, "RADEONDRIKernelInit failed\n");
- DRM_UNLOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext);
- return 0;
- }
-
- /* Initialize the vertex buffers list */
- if (!RADEONDRIBufInit(ctx, info)) {
- fprintf(stderr, "RADEONDRIBufInit failed\n");
- DRM_UNLOCK(ctx->drmFD, ctx->pSAREA, ctx->serverContext);
- return 0;
- }
-
- RADEONColorTilingInit(ctx, info);
-
- /* Initialize IRQ */
- RADEONDRIIrqInit(ctx, info);
-
- /* Initialize kernel gart memory manager */
- RADEONDRIAgpHeapInit(ctx, info);
-
- fprintf(stderr,"color tiling %sabled\n", info->colorTiling?"en":"dis");
- fprintf(stderr,"page flipping %sabled\n", info->page_flip_enable?"en":"dis");
- /* Initialize the SAREA private data structure */
- {
- drm_radeon_sarea_t *pSAREAPriv;
- pSAREAPriv = (drm_radeon_sarea_t *)(((char*)ctx->pSAREA) +
- sizeof(drm_sarea_t));
- memset(pSAREAPriv, 0, sizeof(*pSAREAPriv));
- pSAREAPriv->pfState = info->page_flip_enable;
- }
-
-
- /* Quick hack to clear the front & back buffers. Could also use
- * the clear ioctl to do this, but would need to setup hw state
- * first.
- */
- drimemsetio((char *)ctx->FBAddress + info->frontOffset,
- 0,
- info->frontPitch * ctx->cpp * ctx->shared.virtualHeight );
-
- drimemsetio((char *)ctx->FBAddress + info->backOffset,
- 0,
- info->backPitch * ctx->cpp * ctx->shared.virtualHeight );
-
- /* This is the struct passed to radeon_dri.so for its initialization */
- ctx->driverClientMsg = malloc(sizeof(RADEONDRIRec));
- ctx->driverClientMsgSize = sizeof(RADEONDRIRec);
- pRADEONDRI = (RADEONDRIPtr)ctx->driverClientMsg;
- pRADEONDRI->deviceID = info->Chipset;
- pRADEONDRI->width = ctx->shared.virtualWidth;
- pRADEONDRI->height = ctx->shared.virtualHeight;
- pRADEONDRI->depth = ctx->bpp; /* XXX: depth */
- pRADEONDRI->bpp = ctx->bpp;
- pRADEONDRI->IsPCI = ctx->isPCI;
- pRADEONDRI->AGPMode = ctx->agpmode;
- pRADEONDRI->frontOffset = info->frontOffset;
- pRADEONDRI->frontPitch = info->frontPitch;
- pRADEONDRI->backOffset = info->backOffset;
- pRADEONDRI->backPitch = info->backPitch;
- pRADEONDRI->depthOffset = info->depthOffset;
- pRADEONDRI->depthPitch = info->depthPitch;
- pRADEONDRI->textureOffset = info->textureOffset;
- pRADEONDRI->textureSize = info->textureSize;
- pRADEONDRI->log2TexGran = info->log2TexGran;
- pRADEONDRI->registerHandle = info->registerHandle;
- pRADEONDRI->registerSize = info->registerSize;
- pRADEONDRI->statusHandle = info->ringReadPtrHandle;
- pRADEONDRI->statusSize = info->ringReadMapSize;
- pRADEONDRI->gartTexHandle = info->gartTexHandle;
- pRADEONDRI->gartTexMapSize = info->gartTexMapSize;
- pRADEONDRI->log2GARTTexGran = info->log2GARTTexGran;
- pRADEONDRI->gartTexOffset = info->gartTexStart;
- pRADEONDRI->sarea_priv_offset = sizeof(drm_sarea_t);
-
- /* Don't release the lock now - let the VT switch handler do it. */
-
- return 1;
-}
-
-
-/**
- * \brief Get Radeon chip family from chipset number.
- *
- * \param info driver private data.
- *
- * \return non-zero on success, or zero on failure.
- *
- * Called by radeonInitFBDev() to set RADEONInfoRec::ChipFamily
- * according to the value of RADEONInfoRec::Chipset. Fails if the
- * chipset is unrecognized or not appropriate for this driver (i.e., not
- * an r100 style radeon)
- */
-static int get_chipfamily_from_chipset( RADEONInfoPtr info )
-{
- switch (info->Chipset) {
- case PCI_CHIP_RADEON_LY:
- case PCI_CHIP_RADEON_LZ:
- info->ChipFamily = CHIP_FAMILY_M6;
- break;
-
- case PCI_CHIP_RADEON_QY:
- case PCI_CHIP_RADEON_QZ:
- info->ChipFamily = CHIP_FAMILY_VE;
- break;
-
- case PCI_CHIP_R200_QL:
- case PCI_CHIP_R200_QN:
- case PCI_CHIP_R200_QO:
- case PCI_CHIP_R200_Ql:
- case PCI_CHIP_R200_BB:
- info->ChipFamily = CHIP_FAMILY_R200;
- break;
-
- case PCI_CHIP_RV200_QW: /* RV200 desktop */
- case PCI_CHIP_RV200_QX:
- info->ChipFamily = CHIP_FAMILY_RV200;
- break;
-
- case PCI_CHIP_RADEON_LW:
- case PCI_CHIP_RADEON_LX:
- info->ChipFamily = CHIP_FAMILY_M7;
- break;
-
- case PCI_CHIP_RV250_Id:
- case PCI_CHIP_RV250_Ie:
- case PCI_CHIP_RV250_If:
- case PCI_CHIP_RV250_Ig:
- info->ChipFamily = CHIP_FAMILY_RV250;
- break;
-
- case PCI_CHIP_RV250_Ld:
- case PCI_CHIP_RV250_Le:
- case PCI_CHIP_RV250_Lf:
- case PCI_CHIP_RV250_Lg:
- info->ChipFamily = CHIP_FAMILY_M9;
- break;
-
- case PCI_CHIP_RV280_Y_:
- case PCI_CHIP_RV280_Ya:
- case PCI_CHIP_RV280_Yb:
- case PCI_CHIP_RV280_Yc:
- info->ChipFamily = CHIP_FAMILY_RV280;
- break;
-
- case PCI_CHIP_R300_ND:
- case PCI_CHIP_R300_NE:
- case PCI_CHIP_R300_NF:
- case PCI_CHIP_R300_NG:
- info->ChipFamily = CHIP_FAMILY_R300;
- break;
-
- default:
- /* Original Radeon/7200 */
- info->ChipFamily = CHIP_FAMILY_RADEON;
- }
-
- return 1;
-}
-
-
-/**
- * \brief Validate the fbdev mode.
- *
- * \param ctx display handle.
- *
- * \return one on success, or zero on failure.
- *
- * Saves some registers and returns 1.
- *
- * \sa radeonValidateMode().
- */
-static int radeonValidateMode( const DRIDriverContext *ctx )
-{
- unsigned char *RADEONMMIO = ctx->MMIOAddress;
- RADEONInfoPtr info = ctx->driverPrivate;
-
- info->gen_int_cntl = INREG(RADEON_GEN_INT_CNTL);
- info->crtc_offset_cntl = INREG(RADEON_CRTC_OFFSET_CNTL);
-
- if (info->colorTiling)
- info->crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
- return 1;
-}
-
-
-/**
- * \brief Examine mode returned by fbdev.
- *
- * \param ctx display handle.
- *
- * \return one on success, or zero on failure.
- *
- * Restores registers that fbdev has clobbered and returns 1.
- *
- * \sa radeonValidateMode().
- */
-static int radeonPostValidateMode( const DRIDriverContext *ctx )
-{
- unsigned char *RADEONMMIO = ctx->MMIOAddress;
- RADEONInfoPtr info = ctx->driverPrivate;
-
- RADEONColorTilingInit( ctx, info);
- OUTREG(RADEON_GEN_INT_CNTL, info->gen_int_cntl);
- if (info->colorTiling)
- info->crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
- OUTREG(RADEON_CRTC_OFFSET_CNTL, info->crtc_offset_cntl);
-
- return 1;
-}
-
-
-/**
- * \brief Initialize the framebuffer device mode
- *
- * \param ctx display handle.
- *
- * \return one on success, or zero on failure.
- *
- * Fills in \p info with some default values and some information from \p ctx
- * and then calls RADEONScreenInit() for the screen initialization.
- *
- * Before exiting clears the framebuffer memory accessing it directly.
- */
-static int radeonInitFBDev( DRIDriverContext *ctx )
-{
- RADEONInfoPtr info = calloc(1, sizeof(*info));
-
- {
- int dummy = ctx->shared.virtualWidth;
-
- if (ctx->colorTiling==1)
- {
- switch (ctx->bpp / 8) {
- case 1: dummy = (ctx->shared.virtualWidth + 255) & ~255; break;
- case 2: dummy = (ctx->shared.virtualWidth + 127) & ~127; break;
- case 3:
- case 4: dummy = (ctx->shared.virtualWidth + 63) & ~63; break;
- }
- } else {
- switch (ctx->bpp / 8) {
- case 1: dummy = (ctx->shared.virtualWidth + 127) & ~127; break;
- case 2: dummy = (ctx->shared.virtualWidth + 31) & ~31; break;
- case 3:
- case 4: dummy = (ctx->shared.virtualWidth + 15) & ~15; break;
- }
- }
-
- ctx->shared.virtualWidth = dummy;
- }
-
- fprintf(stderr,"shared virtual width is %d\n", ctx->shared.virtualWidth);
- ctx->driverPrivate = (void *)info;
-
- info->gartFastWrite = RADEON_DEFAULT_AGP_FAST_WRITE;
- info->gartSize = RADEON_DEFAULT_AGP_SIZE;
- info->gartTexSize = RADEON_DEFAULT_AGP_TEX_SIZE;
- info->bufSize = RADEON_DEFAULT_BUFFER_SIZE;
- info->ringSize = RADEON_DEFAULT_RING_SIZE;
- info->page_flip_enable = RADEON_DEFAULT_PAGE_FLIP;
- info->colorTiling = ctx->colorTiling;
-
- info->Chipset = ctx->chipset;
-
- if (!get_chipfamily_from_chipset( info )) {
- fprintf(stderr, "Unknown or non-radeon chipset -- cannot continue\n");
- fprintf(stderr, "==> Verify PCI BusID is correct in miniglx.conf\n");
- return 0;
- }
-
- info->frontPitch = ctx->shared.virtualWidth;
- info->LinearAddr = ctx->FBStart & 0xfc000000;
-
-
- if (!RADEONScreenInit( ctx, info ))
- return 0;
-
-
- return 1;
-}
-
-
-/**
- * \brief The screen is being closed, so clean up any state and free any
- * resources used by the DRI.
- *
- * \param ctx display handle.
- *
- * Unmaps the SAREA, closes the DRM device file descriptor and frees the driver
- * private data.
- */
-static void radeonHaltFBDev( DRIDriverContext *ctx )
-{
- drmUnmap( ctx->pSAREA, ctx->shared.SAREASize );
- drmClose(ctx->drmFD);
-
- if (ctx->driverPrivate) {
- free(ctx->driverPrivate);
- ctx->driverPrivate = 0;
- }
-}
-
-
-extern void radeonNotifyFocus( int );
-
-/**
- * \brief Exported driver interface for Mini GLX.
- *
- * \sa DRIDriverRec.
- */
-const struct DRIDriverRec __driDriver = {
- radeonValidateMode,
- radeonPostValidateMode,
- radeonInitFBDev,
- radeonHaltFBDev,
- RADEONEngineShutdown,
- RADEONEngineRestore,
-#ifndef _EMBEDDED
- 0,
-#else
- radeonNotifyFocus,
-#endif
-};
diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/server/radeon_dri.h b/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/server/radeon_dri.h
deleted file mode 100644
index ecd532333..000000000
--- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/server/radeon_dri.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/**
- * \file server/radeon_dri.h
- * \brief Radeon server-side structures.
- *
- * \author Kevin E. Martin <martin@xfree86.org>
- * \author Rickard E. Faith <faith@valinux.com>
- */
-
-/*
- * Copyright 2000 ATI Technologies Inc., Markham, Ontario,
- * VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
- * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.h,v 1.3 2002/04/24 16:20:40 martin Exp $ */
-
-#ifndef _RADEON_DRI_
-#define _RADEON_DRI_
-
-#include "xf86drm.h"
-#include "drm.h"
-#include "radeon_drm.h"
-
-/* DRI Driver defaults */
-#define RADEON_DEFAULT_CP_PIO_MODE RADEON_CSQ_PRIPIO_INDPIO
-#define RADEON_DEFAULT_CP_BM_MODE RADEON_CSQ_PRIBM_INDBM
-#define RADEON_DEFAULT_AGP_MODE 1
-#define RADEON_DEFAULT_AGP_FAST_WRITE 0
-#define RADEON_DEFAULT_AGP_SIZE 8 /* MB (must be 2^n and > 4MB) */
-#define RADEON_DEFAULT_RING_SIZE 1 /* MB (must be page aligned) */
-#define RADEON_DEFAULT_BUFFER_SIZE 2 /* MB (must be page aligned) */
-#define RADEON_DEFAULT_AGP_TEX_SIZE 1 /* MB (must be page aligned) */
-#define RADEON_DEFAULT_CP_TIMEOUT 10000 /* usecs */
-#define RADEON_DEFAULT_PAGE_FLIP 0 /* page flipping diabled */
-#define RADEON_BUFFER_ALIGN 0x00000fff
-
-/**
- * \brief Radeon DRI driver private data.
- */
-typedef struct {
- /**
- * \name DRI screen private data
- */
- /*@{*/
- int deviceID; /**< \brief PCI device ID */
- int width; /**< \brief width in pixels of display */
- int height; /**< \brief height in scanlines of display */
- int depth; /**< \brief depth of display (8, 15, 16, 24) */
- int bpp; /**< \brief bit depth of display (8, 16, 24, 32) */
-
- int IsPCI; /**< \brief is current card a PCI card? */
- int AGPMode; /**< \brief AGP mode */
-
- int frontOffset; /**< \brief front buffer offset */
- int frontPitch; /**< \brief front buffer pitch */
- int backOffset; /**< \brief shared back buffer offset */
- int backPitch; /**< \brief shared back buffer pitch */
- int depthOffset; /**< \brief shared depth buffer offset */
- int depthPitch; /**< \brief shared depth buffer pitch */
- int textureOffset; /**< \brief start of texture data in frame buffer */
- int textureSize; /**< \brief size of texture date */
- int log2TexGran; /**< \brief log2 texture granularity */
- /*@}*/
-
- /**
- * \name MMIO register data
- */
- /*@{*/
- drm_handle_t registerHandle; /**< \brief MMIO register map size */
- drmSize registerSize; /**< \brief MMIO register map handle */
- /*@}*/
-
- /**
- * \name CP in-memory status information
- */
- /*@{*/
- drm_handle_t statusHandle; /**< \brief status map handle */
- drmSize statusSize; /**< \brief status map size */
- /*@}*/
-
- /**
- * \name CP AGP Texture data
- */
- /*@{*/
- drm_handle_t gartTexHandle; /**< \brief AGP texture area map handle */
- drmSize gartTexMapSize; /**< \brief AGP texture area map size */
- int log2GARTTexGran; /**< \brief AGP texture granularity in log base 2 */
- int gartTexOffset; /**< \brief AGP texture area offset in AGP space */
- /*@}*/
-
- unsigned int sarea_priv_offset; /**< \brief offset of the private SAREA data*/
-} RADEONDRIRec, *RADEONDRIPtr;
-
-#endif
diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/server/radeon_egl.c b/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/server/radeon_egl.c
deleted file mode 100644
index 736fed5b5..000000000
--- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/server/radeon_egl.c
+++ /dev/null
@@ -1,978 +0,0 @@
-/*
- * EGL driver for radeon_dri.so
- */
-#include <assert.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <dirent.h>
-#include <errno.h>
-#include <fcntl.h>
-#include <unistd.h>
-#include <sys/ioctl.h>
-#include <sys/mman.h>
-
-#include "eglconfig.h"
-#include "eglcontext.h"
-#include "egldisplay.h"
-#include "egldriver.h"
-#include "eglglobals.h"
-#include "eglmode.h"
-#include "eglscreen.h"
-#include "eglsurface.h"
-#include "egldri.h"
-
-#include "mtypes.h"
-#include "memops.h"
-#include "drm.h"
-#include "drm_sarea.h"
-#include "radeon_drm.h"
-#include "radeon_dri.h"
-#include "radeon.h"
-
-static size_t radeon_drm_page_size;
-
-/**
- * radeon driver-specific driver class derived from _EGLDriver
- */
-typedef struct radeon_driver
-{
- _EGLDriver Base; /* base class/object */
- GLuint radeonStuff;
-} radeonDriver;
-
-static int RADEONCheckDRMVersion( driDisplay *disp,
- RADEONInfoPtr info )
-{
- drmVersionPtr version;
-
- version = drmGetVersion(disp->drmFD);
- if (version) {
- int req_minor, req_patch;
-
- /* Need 1.8.x for proper cleanup-on-client-exit behaviour.
- */
- req_minor = 8;
- req_patch = 0;
-
- if (version->version_major != 1 ||
- version->version_minor < req_minor ||
- (version->version_minor == req_minor &&
- version->version_patchlevel < req_patch)) {
- /* Incompatible drm version */
- fprintf(stderr,
- "[dri] RADEONDRIScreenInit failed because of a version "
- "mismatch.\n"
- "[dri] radeon.o kernel module version is %d.%d.%d "
- "but version 1.%d.%d or newer is needed.\n"
- "[dri] Disabling DRI.\n",
- version->version_major,
- version->version_minor,
- version->version_patchlevel,
- req_minor,
- req_patch);
- drmFreeVersion(version);
- return 0;
- }
-
- info->drmMinor = version->version_minor;
- drmFreeVersion(version);
- }
-
- return 1;
-}
-
-
-/**
- * \brief Compute base 2 logarithm.
- *
- * \param val value.
- *
- * \return base 2 logarithm of \p val.
- */
-static int RADEONMinBits(int val)
-{
- int bits;
-
- if (!val) return 1;
- for (bits = 0; val; val >>= 1, ++bits);
- return bits;
-}
-
-
-/* Initialize the PCI GART state. Request memory for use in PCI space,
- * and initialize the Radeon registers to point to that memory.
- */
-static int RADEONDRIPciInit(driDisplay *disp, RADEONInfoPtr info)
-{
- int ret;
- int flags = DRM_READ_ONLY | DRM_LOCKED | DRM_KERNEL;
- int s, l;
-
- ret = drmScatterGatherAlloc(disp->drmFD, info->gartSize*1024*1024,
- &info->gartMemHandle);
- if (ret < 0) {
- fprintf(stderr, "[pci] Out of memory (%d)\n", ret);
- return 0;
- }
- fprintf(stderr,
- "[pci] %d kB allocated with handle 0x%04lx\n",
- info->gartSize*1024, info->gartMemHandle);
-
- info->gartOffset = 0;
-
- /* Initialize the CP ring buffer data */
- info->ringStart = info->gartOffset;
- info->ringMapSize = info->ringSize*1024*1024 + radeon_drm_page_size;
-
- info->ringReadOffset = info->ringStart + info->ringMapSize;
- info->ringReadMapSize = radeon_drm_page_size;
-
- /* Reserve space for vertex/indirect buffers */
- info->bufStart = info->ringReadOffset + info->ringReadMapSize;
- info->bufMapSize = info->bufSize*1024*1024;
-
- /* Reserve the rest for AGP textures */
- info->gartTexStart = info->bufStart + info->bufMapSize;
- s = (info->gartSize*1024*1024 - info->gartTexStart);
- l = RADEONMinBits((s-1) / RADEON_NR_TEX_REGIONS);
- if (l < RADEON_LOG_TEX_GRANULARITY) l = RADEON_LOG_TEX_GRANULARITY;
- info->gartTexMapSize = (s >> l) << l;
- info->log2GARTTexGran = l;
-
- if (drmAddMap(disp->drmFD, info->ringStart, info->ringMapSize,
- DRM_SCATTER_GATHER, flags, &info->ringHandle) < 0) {
- fprintf(stderr,
- "[pci] Could not add ring mapping\n");
- return 0;
- }
- fprintf(stderr,
- "[pci] ring handle = 0x%08lx\n", info->ringHandle);
-
- if (drmAddMap(disp->drmFD, info->ringReadOffset, info->ringReadMapSize,
- DRM_SCATTER_GATHER, flags, &info->ringReadPtrHandle) < 0) {
- fprintf(stderr,
- "[pci] Could not add ring read ptr mapping\n");
- return 0;
- }
- fprintf(stderr,
- "[pci] ring read ptr handle = 0x%08lx\n",
- info->ringReadPtrHandle);
-
- if (drmAddMap(disp->drmFD, info->bufStart, info->bufMapSize,
- DRM_SCATTER_GATHER, 0, &info->bufHandle) < 0) {
- fprintf(stderr,
- "[pci] Could not add vertex/indirect buffers mapping\n");
- return 0;
- }
- fprintf(stderr,
- "[pci] vertex/indirect buffers handle = 0x%08lx\n",
- info->bufHandle);
-
- if (drmAddMap(disp->drmFD, info->gartTexStart, info->gartTexMapSize,
- DRM_SCATTER_GATHER, 0, &info->gartTexHandle) < 0) {
- fprintf(stderr,
- "[pci] Could not add GART texture map mapping\n");
- return 0;
- }
- fprintf(stderr,
- "[pci] GART texture map handle = 0x%08lx\n",
- info->gartTexHandle);
-
- return 1;
-}
-
-
-/**
- * \brief Initialize the AGP state
- *
- * \param ctx display handle.
- * \param info driver private data.
- *
- * \return one on success, or zero on failure.
- *
- * Acquires and enables the AGP device. Reserves memory in the AGP space for
- * the ring buffer, vertex buffers and textures. Initialize the Radeon
- * registers to point to that memory and add client mappings.
- */
-static int RADEONDRIAgpInit( driDisplay *disp, RADEONInfoPtr info)
-{
- int mode, ret;
- int s, l;
- int agpmode = 1;
-
- if (drmAgpAcquire(disp->drmFD) < 0) {
- fprintf(stderr, "[gart] AGP not available\n");
- return 0;
- }
-
- mode = drmAgpGetMode(disp->drmFD); /* Default mode */
- /* Disable fast write entirely - too many lockups.
- */
- mode &= ~RADEON_AGP_MODE_MASK;
- switch (agpmode) {
- case 4: mode |= RADEON_AGP_4X_MODE;
- case 2: mode |= RADEON_AGP_2X_MODE;
- case 1: default: mode |= RADEON_AGP_1X_MODE;
- }
-
- if (drmAgpEnable(disp->drmFD, mode) < 0) {
- fprintf(stderr, "[gart] AGP not enabled\n");
- drmAgpRelease(disp->drmFD);
- return 0;
- }
-
-#if 0
- /* Workaround for some hardware bugs */
- if (info->ChipFamily < CHIP_FAMILY_R200)
- OUTREG(RADEON_AGP_CNTL, INREG(RADEON_AGP_CNTL) | 0x000e0000);
-#endif
- info->gartOffset = 0;
-
- if ((ret = drmAgpAlloc(disp->drmFD, info->gartSize*1024*1024, 0, NULL,
- &info->gartMemHandle)) < 0) {
- fprintf(stderr, "[gart] Out of memory (%d)\n", ret);
- drmAgpRelease(disp->drmFD);
- return 0;
- }
- fprintf(stderr,
- "[gart] %d kB allocated with handle 0x%08x\n",
- info->gartSize*1024, (unsigned)info->gartMemHandle);
-
- if (drmAgpBind(disp->drmFD,
- info->gartMemHandle, info->gartOffset) < 0) {
- fprintf(stderr, "[gart] Could not bind\n");
- drmAgpFree(disp->drmFD, info->gartMemHandle);
- drmAgpRelease(disp->drmFD);
- return 0;
- }
-
- /* Initialize the CP ring buffer data */
- info->ringStart = info->gartOffset;
- info->ringMapSize = info->ringSize*1024*1024 + radeon_drm_page_size;
-
- info->ringReadOffset = info->ringStart + info->ringMapSize;
- info->ringReadMapSize = radeon_drm_page_size;
-
- /* Reserve space for vertex/indirect buffers */
- info->bufStart = info->ringReadOffset + info->ringReadMapSize;
- info->bufMapSize = info->bufSize*1024*1024;
-
- /* Reserve the rest for AGP textures */
- info->gartTexStart = info->bufStart + info->bufMapSize;
- s = (info->gartSize*1024*1024 - info->gartTexStart);
- l = RADEONMinBits((s-1) / RADEON_NR_TEX_REGIONS);
- if (l < RADEON_LOG_TEX_GRANULARITY) l = RADEON_LOG_TEX_GRANULARITY;
- info->gartTexMapSize = (s >> l) << l;
- info->log2GARTTexGran = l;
-
- if (drmAddMap(disp->drmFD, info->ringStart, info->ringMapSize,
- DRM_AGP, DRM_READ_ONLY, &info->ringHandle) < 0) {
- fprintf(stderr, "[gart] Could not add ring mapping\n");
- return 0;
- }
- fprintf(stderr, "[gart] ring handle = 0x%08lx\n", info->ringHandle);
-
-
- if (drmAddMap(disp->drmFD, info->ringReadOffset, info->ringReadMapSize,
- DRM_AGP, DRM_READ_ONLY, &info->ringReadPtrHandle) < 0) {
- fprintf(stderr,
- "[gart] Could not add ring read ptr mapping\n");
- return 0;
- }
-
- fprintf(stderr,
- "[gart] ring read ptr handle = 0x%08lx\n",
- info->ringReadPtrHandle);
-
- if (drmAddMap(disp->drmFD, info->bufStart, info->bufMapSize,
- DRM_AGP, 0, &info->bufHandle) < 0) {
- fprintf(stderr,
- "[gart] Could not add vertex/indirect buffers mapping\n");
- return 0;
- }
- fprintf(stderr,
- "[gart] vertex/indirect buffers handle = 0x%08lx\n",
- info->bufHandle);
-
- if (drmAddMap(disp->drmFD, info->gartTexStart, info->gartTexMapSize,
- DRM_AGP, 0, &info->gartTexHandle) < 0) {
- fprintf(stderr,
- "[gart] Could not add AGP texture map mapping\n");
- return 0;
- }
- fprintf(stderr,
- "[gart] AGP texture map handle = 0x%08lx\n",
- info->gartTexHandle);
-
- return 1;
-}
-
-
-static int RADEONMemoryInit( driDisplay *disp, RADEONInfoPtr info )
-{
- int width_bytes = disp->virtualWidth * disp->cpp;
- int cpp = disp->cpp;
- int bufferSize = ((disp->virtualHeight * width_bytes
- + RADEON_BUFFER_ALIGN)
- & ~RADEON_BUFFER_ALIGN);
- int depthSize = ((((disp->virtualHeight+15) & ~15) * width_bytes
- + RADEON_BUFFER_ALIGN)
- & ~RADEON_BUFFER_ALIGN);
- int l;
-
- info->frontOffset = 0;
- info->frontPitch = disp->virtualWidth;
-
- fprintf(stderr,
- "Using %d MB AGP aperture\n", info->gartSize);
- fprintf(stderr,
- "Using %d MB for the ring buffer\n", info->ringSize);
- fprintf(stderr,
- "Using %d MB for vertex/indirect buffers\n", info->bufSize);
- fprintf(stderr,
- "Using %d MB for AGP textures\n", info->gartTexSize);
-
- /* Front, back and depth buffers - everything else texture??
- */
- info->textureSize = disp->fbSize - 2 * bufferSize - depthSize;
-
- if (info->textureSize < 0)
- return 0;
-
- l = RADEONMinBits((info->textureSize-1) / RADEON_NR_TEX_REGIONS);
- if (l < RADEON_LOG_TEX_GRANULARITY) l = RADEON_LOG_TEX_GRANULARITY;
-
- /* Round the texture size up to the nearest whole number of
- * texture regions. Again, be greedy about this, don't
- * round down.
- */
- info->log2TexGran = l;
- info->textureSize = (info->textureSize >> l) << l;
-
- /* Set a minimum usable local texture heap size. This will fit
- * two 256x256x32bpp textures.
- */
- if (info->textureSize < 512 * 1024) {
- info->textureOffset = 0;
- info->textureSize = 0;
- }
-
- /* Reserve space for textures */
- info->textureOffset = ((disp->fbSize - info->textureSize +
- RADEON_BUFFER_ALIGN) &
- ~RADEON_BUFFER_ALIGN);
-
- /* Reserve space for the shared depth
- * buffer.
- */
- info->depthOffset = ((info->textureOffset - depthSize +
- RADEON_BUFFER_ALIGN) &
- ~RADEON_BUFFER_ALIGN);
- info->depthPitch = disp->virtualWidth;
-
- info->backOffset = ((info->depthOffset - bufferSize +
- RADEON_BUFFER_ALIGN) &
- ~RADEON_BUFFER_ALIGN);
- info->backPitch = disp->virtualWidth;
-
-
- fprintf(stderr,
- "Will use back buffer at offset 0x%x\n",
- info->backOffset);
- fprintf(stderr,
- "Will use depth buffer at offset 0x%x\n",
- info->depthOffset);
- fprintf(stderr,
- "Will use %d kb for textures at offset 0x%x\n",
- info->textureSize/1024, info->textureOffset);
-
- info->frontPitchOffset = (((info->frontPitch * cpp / 64) << 22) |
- (info->frontOffset >> 10));
-
- info->backPitchOffset = (((info->backPitch * cpp / 64) << 22) |
- (info->backOffset >> 10));
-
- info->depthPitchOffset = (((info->depthPitch * cpp / 64) << 22) |
- (info->depthOffset >> 10));
-
- return 1;
-}
-
-
-/**
- * \brief Initialize the kernel data structures and enable the CP engine.
- *
- * \param ctx display handle.
- * \param info driver private data.
- *
- * \return non-zero on success, or zero on failure.
- *
- * This function is a wrapper around the DRM_RADEON_CP_INIT command, passing
- * all the parameters in a drm_radeon_init_t structure.
- */
-static int RADEONDRIKernelInit( driDisplay *disp,
- RADEONInfoPtr info)
-{
- int cpp = disp->bpp / 8;
- drm_radeon_init_t drmInfo;
- int ret;
-
- memset(&drmInfo, 0, sizeof(drmInfo));
-
- if ( (info->ChipFamily == CHIP_FAMILY_R200) ||
- (info->ChipFamily == CHIP_FAMILY_RV250) ||
- (info->ChipFamily == CHIP_FAMILY_M9) ||
- (info->ChipFamily == CHIP_FAMILY_RV280) )
- drmInfo.func = RADEON_INIT_R200_CP;
- else
- drmInfo.func = RADEON_INIT_CP;
-
- /* This is the struct passed to the kernel module for its initialization */
- drmInfo.sarea_priv_offset = sizeof(drm_sarea_t);
- drmInfo.cp_mode = RADEON_DEFAULT_CP_BM_MODE;
- drmInfo.gart_size = info->gartSize*1024*1024;
- drmInfo.ring_size = info->ringSize*1024*1024;
- drmInfo.usec_timeout = 1000;
- drmInfo.fb_bpp = disp->bpp;
- drmInfo.depth_bpp = disp->bpp;
- drmInfo.front_offset = info->frontOffset;
- drmInfo.front_pitch = info->frontPitch * cpp;
- drmInfo.back_offset = info->backOffset;
- drmInfo.back_pitch = info->backPitch * cpp;
- drmInfo.depth_offset = info->depthOffset;
- drmInfo.depth_pitch = info->depthPitch * cpp;
- drmInfo.ring_offset = info->ringHandle;
- drmInfo.ring_rptr_offset = info->ringReadPtrHandle;
- drmInfo.buffers_offset = info->bufHandle;
- drmInfo.gart_textures_offset = info->gartTexHandle;
-
- ret = drmCommandWrite(disp->drmFD, DRM_RADEON_CP_INIT, &drmInfo,
- sizeof(drm_radeon_init_t));
-
- return ret >= 0;
-}
-
-
-/**
- * \brief Add a map for the vertex buffers that will be accessed by any
- * DRI-based clients.
- *
- * \param ctx display handle.
- * \param info driver private data.
- *
- * \return one on success, or zero on failure.
- *
- * Calls drmAddBufs() with the previously allocated vertex buffers.
- */
-static int RADEONDRIBufInit( driDisplay *disp, RADEONInfoPtr info )
-{
- /* Initialize vertex buffers */
- info->bufNumBufs = drmAddBufs(disp->drmFD,
- info->bufMapSize / RADEON_BUFFER_SIZE,
- RADEON_BUFFER_SIZE,
- disp->isPCI ? DRM_SG_BUFFER : DRM_AGP_BUFFER,
- info->bufStart);
-
- if (info->bufNumBufs <= 0) {
- fprintf(stderr,
- "[drm] Could not create vertex/indirect buffers list\n");
- return 0;
- }
- fprintf(stderr,
- "[drm] Added %d %d byte vertex/indirect buffers\n",
- info->bufNumBufs, RADEON_BUFFER_SIZE);
-
- return 1;
-}
-
-
-/**
- * \brief Install an IRQ handler.
- *
- * \param disp display handle.
- * \param info driver private data.
- *
- * Attempts to install an IRQ handler via drmCtlInstHandler(), falling back to
- * IRQ-free operation on failure.
- */
-static void RADEONDRIIrqInit(driDisplay *disp, RADEONInfoPtr info)
-{
- if ((drmCtlInstHandler(disp->drmFD, 0)) != 0)
- fprintf(stderr, "[drm] failure adding irq handler, "
- "there is a device already using that irq\n"
- "[drm] falling back to irq-free operation\n");
-}
-
-
-/**
- * \brief Initialize the AGP heap.
- *
- * \param disp display handle.
- * \param info driver private data.
- *
- * This function is a wrapper around the DRM_RADEON_INIT_HEAP command, passing
- * all the parameters in a drm_radeon_mem_init_heap structure.
- */
-static void RADEONDRIAgpHeapInit(driDisplay *disp,
- RADEONInfoPtr info)
-{
- drm_radeon_mem_init_heap_t drmHeap;
-
- /* Start up the simple memory manager for gart space */
- drmHeap.region = RADEON_MEM_REGION_GART;
- drmHeap.start = 0;
- drmHeap.size = info->gartTexMapSize;
-
- if (drmCommandWrite(disp->drmFD, DRM_RADEON_INIT_HEAP,
- &drmHeap, sizeof(drmHeap))) {
- fprintf(stderr,
- "[drm] Failed to initialized gart heap manager\n");
- } else {
- fprintf(stderr,
- "[drm] Initialized kernel gart heap manager, %d\n",
- info->gartTexMapSize);
- }
-}
-
-
-/**
- * Called at the start of each server generation.
- *
- * \param disp display handle.
- * \param info driver private data.
- *
- * \return non-zero on success, or zero on failure.
- *
- * Performs static frame buffer allocation. Opens the DRM device and add maps
- * to the SAREA, framebuffer and MMIO regions. Fills in \p info with more
- * information. Creates a \e server context to grab the lock for the
- * initialization ioctls and calls the other initilization functions in this
- * file. Starts the CP engine via the DRM_RADEON_CP_START command.
- *
- * Setups a RADEONDRIRec structure to be passed to radeon_dri.so for its
- * initialization.
- */
-static int RADEONScreenInit( driDisplay *disp, RADEONInfoPtr info, RADEONDRIPtr pRADEONDRI)
-{
- int i, err;
-
- {
- int width_bytes = (disp->virtualWidth * disp->cpp);
- int maxy = disp->fbSize / width_bytes;
-
-
- if (maxy <= disp->virtualHeight * 3) {
- fprintf(stderr,
- "Static buffer allocation failed -- "
- "need at least %d kB video memory (have %d kB)\n",
- (disp->virtualWidth * disp->virtualHeight *
- disp->cpp * 3 + 1023) / 1024,
- disp->fbSize / 1024);
- return 0;
- }
- }
- if (info->ChipFamily >= CHIP_FAMILY_R300) {
- fprintf(stderr,
- "Direct rendering not yet supported on "
- "Radeon 9700 and newer cards\n");
- return 0;
- }
-
- radeon_drm_page_size = getpagesize();
-
- /* Check the radeon DRM version */
- if (!RADEONCheckDRMVersion(disp, info)) {
- return 0;
- }
-
- if (disp->isPCI) {
- /* Initialize PCI */
- if (!RADEONDRIPciInit(disp, info))
- return 0;
- }
- else {
- /* Initialize AGP */
- if (!RADEONDRIAgpInit(disp, info))
- return 0;
- }
-
- /* Memory manager setup */
- if (!RADEONMemoryInit(disp, info)) {
- return 0;
- }
-
- /* Create a 'server' context so we can grab the lock for
- * initialization ioctls.
- */
- if ((err = drmCreateContext(disp->drmFD, &disp->serverContext)) != 0) {
- fprintf(stderr, "%s: drmCreateContext failed %d\n", __FUNCTION__, err);
- return 0;
- }
-
- DRM_LOCK(disp->drmFD, disp->pSAREA, disp->serverContext, 0);
-
- /* Initialize the kernel data structures */
- if (!RADEONDRIKernelInit(disp, info)) {
- fprintf(stderr, "RADEONDRIKernelInit failed\n");
- DRM_UNLOCK(disp->drmFD, disp->pSAREA, disp->serverContext);
- return 0;
- }
-
- /* Initialize the vertex buffers list */
- if (!RADEONDRIBufInit(disp, info)) {
- fprintf(stderr, "RADEONDRIBufInit failed\n");
- DRM_UNLOCK(disp->drmFD, disp->pSAREA, disp->serverContext);
- return 0;
- }
-
- /* Initialize IRQ */
- RADEONDRIIrqInit(disp, info);
-
- /* Initialize kernel gart memory manager */
- RADEONDRIAgpHeapInit(disp, info);
-
- fprintf(stderr,"page flipping %sabled\n", info->page_flip_enable?"en":"dis");
- /* Initialize the SAREA private data structure */
- {
- drm_radeon_sarea_t *pSAREAPriv;
- pSAREAPriv = (drm_radeon_sarea_t *)(((char*)disp->pSAREA) +
- sizeof(drm_sarea_t));
- memset(pSAREAPriv, 0, sizeof(*pSAREAPriv));
- pSAREAPriv->pfState = info->page_flip_enable;
- }
-
- for ( i = 0;; i++ ) {
- drmMapType type;
- drmMapFlags flags;
- drm_handle_t handle, offset;
- drmSize size;
- int rc, mtrr;
-
- if ( ( rc = drmGetMap( disp->drmFD, i, &offset, &size, &type, &flags, &handle, &mtrr ) ) != 0 )
- break;
- if ( type == DRM_REGISTERS ) {
- pRADEONDRI->registerHandle = offset;
- pRADEONDRI->registerSize = size;
- break;
- }
- }
- /* Quick hack to clear the front & back buffers. Could also use
- * the clear ioctl to do this, but would need to setup hw state
- * first.
- */
- drimemsetio((char *)disp->pFB + info->frontOffset,
- 0xEE,
- info->frontPitch * disp->cpp * disp->virtualHeight );
-
- drimemsetio((char *)disp->pFB + info->backOffset,
- 0x30,
- info->backPitch * disp->cpp * disp->virtualHeight );
-
-
- /* This is the struct passed to radeon_dri.so for its initialization */
- pRADEONDRI->deviceID = info->Chipset;
- pRADEONDRI->width = disp->virtualWidth;
- pRADEONDRI->height = disp->virtualHeight;
- pRADEONDRI->depth = disp->bpp; /* XXX: depth */
- pRADEONDRI->bpp = disp->bpp;
- pRADEONDRI->IsPCI = disp->isPCI;
- pRADEONDRI->frontOffset = info->frontOffset;
- pRADEONDRI->frontPitch = info->frontPitch;
- pRADEONDRI->backOffset = info->backOffset;
- pRADEONDRI->backPitch = info->backPitch;
- pRADEONDRI->depthOffset = info->depthOffset;
- pRADEONDRI->depthPitch = info->depthPitch;
- pRADEONDRI->textureOffset = info->textureOffset;
- pRADEONDRI->textureSize = info->textureSize;
- pRADEONDRI->log2TexGran = info->log2TexGran;
- pRADEONDRI->statusHandle = info->ringReadPtrHandle;
- pRADEONDRI->statusSize = info->ringReadMapSize;
- pRADEONDRI->gartTexHandle = info->gartTexHandle;
- pRADEONDRI->gartTexMapSize = info->gartTexMapSize;
- pRADEONDRI->log2GARTTexGran = info->log2GARTTexGran;
- pRADEONDRI->gartTexOffset = info->gartTexStart;
- pRADEONDRI->sarea_priv_offset = sizeof(drm_sarea_t);
-
- /* Don't release the lock now - let the VT switch handler do it. */
-
- return 1;
-}
-
-
-/**
- * \brief Get Radeon chip family from chipset number.
- *
- * \param info driver private data.
- *
- * \return non-zero on success, or zero on failure.
- *
- * Called by radeonInitFBDev() to set RADEONInfoRec::ChipFamily
- * according to the value of RADEONInfoRec::Chipset. Fails if the
- * chipset is unrecognized or not appropriate for this driver (i.e., not
- * an r100 style radeon)
- */
-static int get_chipfamily_from_chipset( RADEONInfoPtr info )
-{
- switch (info->Chipset) {
- case PCI_CHIP_RADEON_LY:
- case PCI_CHIP_RADEON_LZ:
- info->ChipFamily = CHIP_FAMILY_M6;
- break;
-
- case PCI_CHIP_RADEON_QY:
- case PCI_CHIP_RADEON_QZ:
- info->ChipFamily = CHIP_FAMILY_VE;
- break;
-
- case PCI_CHIP_R200_QL:
- case PCI_CHIP_R200_QN:
- case PCI_CHIP_R200_QO:
- case PCI_CHIP_R200_Ql:
- case PCI_CHIP_R200_BB:
- info->ChipFamily = CHIP_FAMILY_R200;
- break;
-
- case PCI_CHIP_RV200_QW: /* RV200 desktop */
- case PCI_CHIP_RV200_QX:
- info->ChipFamily = CHIP_FAMILY_RV200;
- break;
-
- case PCI_CHIP_RADEON_LW:
- case PCI_CHIP_RADEON_LX:
- info->ChipFamily = CHIP_FAMILY_M7;
- break;
-
- case PCI_CHIP_RV250_Id:
- case PCI_CHIP_RV250_Ie:
- case PCI_CHIP_RV250_If:
- case PCI_CHIP_RV250_Ig:
- info->ChipFamily = CHIP_FAMILY_RV250;
- break;
-
- case PCI_CHIP_RV250_Ld:
- case PCI_CHIP_RV250_Le:
- case PCI_CHIP_RV250_Lf:
- case PCI_CHIP_RV250_Lg:
- info->ChipFamily = CHIP_FAMILY_M9;
- break;
-
- case PCI_CHIP_RV280_Y_:
- case PCI_CHIP_RV280_Ya:
- case PCI_CHIP_RV280_Yb:
- case PCI_CHIP_RV280_Yc:
- info->ChipFamily = CHIP_FAMILY_RV280;
- break;
-
- case PCI_CHIP_R300_ND:
- case PCI_CHIP_R300_NE:
- case PCI_CHIP_R300_NF:
- case PCI_CHIP_R300_NG:
- info->ChipFamily = CHIP_FAMILY_R300;
- break;
-
- default:
- /* Original Radeon/7200 */
- info->ChipFamily = CHIP_FAMILY_RADEON;
- }
-
- return 1;
-}
-
-
-/**
- * \brief Initialize the framebuffer device mode
- *
- * \param disp display handle.
- *
- * \return one on success, or zero on failure.
- *
- * Fills in \p info with some default values and some information from \p disp
- * and then calls RADEONScreenInit() for the screen initialization.
- *
- * Before exiting clears the framebuffer memory accessing it directly.
- */
-static int radeonInitFBDev( driDisplay *disp, RADEONDRIPtr pRADEONDRI )
-{
- int err;
- RADEONInfoPtr info = calloc(1, sizeof(*info));
-
- disp->driverPrivate = (void *)info;
-
- info->gartFastWrite = RADEON_DEFAULT_AGP_FAST_WRITE;
- info->gartSize = RADEON_DEFAULT_AGP_SIZE;
- info->gartTexSize = RADEON_DEFAULT_AGP_TEX_SIZE;
- info->bufSize = RADEON_DEFAULT_BUFFER_SIZE;
- info->ringSize = RADEON_DEFAULT_RING_SIZE;
- info->page_flip_enable = RADEON_DEFAULT_PAGE_FLIP;
-
- info->Chipset = disp->chipset;
-
- if (!get_chipfamily_from_chipset( info )) {
- fprintf(stderr, "Unknown or non-radeon chipset -- cannot continue\n");
- fprintf(stderr, "==> Verify PCI BusID is correct in miniglx.conf\n");
- return 0;
- }
-
- info->frontPitch = disp->virtualWidth;
-
- if (!RADEONScreenInit( disp, info, pRADEONDRI))
- return 0;
-
- /* Initialize and start the CP if required */
- if ((err = drmCommandNone(disp->drmFD, DRM_RADEON_CP_START)) != 0) {
- fprintf(stderr, "%s: CP start %d\n", __FUNCTION__, err);
- return 0;
- }
-
- return 1;
-}
-
-static EGLBoolean
-radeonFillInConfigs(_EGLDisplay *disp, unsigned pixel_bits, unsigned depth_bits,
- unsigned stencil_bits, GLboolean have_back_buffer) {
- _EGLConfig *configs;
- _EGLConfig *c;
- unsigned int i, num_configs;
- unsigned int depth_buffer_factor;
- unsigned int back_buffer_factor;
- GLenum fb_format;
- GLenum fb_type;
-
- /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
- * enough to add support. Basically, if a context is created with an
- * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
- * will never be used.
- */
- static const GLenum back_buffer_modes[] = {
- GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
- };
-
- u_int8_t depth_bits_array[2];
- u_int8_t stencil_bits_array[2];
-
- depth_bits_array[0] = depth_bits;
- depth_bits_array[1] = depth_bits;
-
- /* Just like with the accumulation buffer, always provide some modes
- * with a stencil buffer. It will be a sw fallback, but some apps won't
- * care about that.
- */
- stencil_bits_array[0] = 0;
- stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits;
-
- depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1;
- back_buffer_factor = (have_back_buffer) ? 2 : 1;
-
- num_configs = depth_buffer_factor * back_buffer_factor * 2;
-
- if (pixel_bits == 16) {
- fb_format = GL_RGB;
- fb_type = GL_UNSIGNED_SHORT_5_6_5;
- } else {
- fb_format = GL_RGBA;
- fb_type = GL_UNSIGNED_INT_8_8_8_8_REV;
- }
-
- configs = calloc(sizeof(*configs), num_configs);
- c = configs;
- if (!_eglFillInConfigs(c, fb_format, fb_type,
- depth_bits_array, stencil_bits_array, depth_buffer_factor,
- back_buffer_modes, back_buffer_factor,
- GLX_TRUE_COLOR)) {
- fprintf(stderr, "[%s:%u] Error creating FBConfig!\n",
- __func__, __LINE__);
- return EGL_FALSE;
- }
-
- /* Mark the visual as slow if there are "fake" stencil bits.
- */
- for (i = 0, c = configs; i < num_configs; i++, c++) {
- int stencil = GET_CONFIG_ATTRIB(c, EGL_STENCIL_SIZE);
- if ((stencil != 0) && (stencil != stencil_bits)) {
- SET_CONFIG_ATTRIB(c, EGL_CONFIG_CAVEAT, EGL_SLOW_CONFIG);
- }
- }
-
- for (i = 0, c = configs; i < num_configs; i++, c++)
- _eglAddConfig(disp, c);
-
- free(configs);
-
- return EGL_TRUE;
-}
-
-/**
- * Show the given surface on the named screen.
- * If surface is EGL_NO_SURFACE, disable the screen's output.
- */
-static EGLBoolean
-radeonShowSurfaceMESA(_EGLDriver *drv, EGLDisplay dpy, EGLScreenMESA screen,
- EGLSurface surface, EGLModeMESA m)
-{
- _eglDRIShowSurfaceMESA(drv, dpy, screen, surface, m);
- return EGL_FALSE;
-}
-
-static EGLBoolean
-radeonInitialize(_EGLDriver *drv, EGLDisplay dpy, EGLint *major, EGLint *minor)
-{
- __DRIframebuffer framebuffer;
- driDisplay *display;
-
- if (!_eglDRIInitialize(drv, dpy, major, minor))
- return EGL_FALSE;
-
- display = Lookup_driDisplay(dpy);
-
- framebuffer.dev_priv_size = sizeof(RADEONDRIRec);
- framebuffer.dev_priv = malloc(sizeof(RADEONDRIRec));
-
- display->virtualWidth = 1024;
- display->virtualHeight = 768;
- display->bpp = 32;
- display->cpp = 4;
-
- if (!_eglDRIGetDisplayInfo(display))
- return EGL_FALSE;
-
- framebuffer.base = display->pFB;
- radeonInitFBDev( display, framebuffer.dev_priv );
-
- if (!_eglDRICreateDisplay(display, &framebuffer))
- return EGL_FALSE;
-
- if (!_eglDRICreateScreen(display))
- return EGL_FALSE;
-
- radeonFillInConfigs(&display->Base, 32, 24, 8, 1);
- radeonFillInConfigs(&display->Base, 16, 16, 0, 1);
-
- drv->Initialized = EGL_TRUE;
- return EGL_TRUE;
-}
-
-
-/**
- * The bootstrap function. Return a new radeonDriver object and
- * plug in API functions.
- */
-_EGLDriver *
-_eglMain(_EGLDisplay *dpy)
-{
- radeonDriver *radeon;
-
- radeon = (radeonDriver *) calloc(1, sizeof(*radeon));
- if (!radeon) {
- return NULL;
- }
-
- /* First fill in the dispatch table with defaults */
- _eglDRIInitDriverFallbacks(&radeon->Base);
-
- /* then plug in our radeon-specific functions */
- radeon->Base.Initialize = radeonInitialize;
- radeon->Base.ShowSurfaceMESA = radeonShowSurfaceMESA;
-
- return &radeon->Base;
-}
diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/server/radeon_macros.h b/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/server/radeon_macros.h
deleted file mode 100644
index 60f0fa2d3..000000000
--- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/server/radeon_macros.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/**
- * \file server/radeon_macros.h
- * \brief Macros for Radeon MMIO operation.
- *
- * \authors Kevin E. Martin <martin@xfree86.org>
- * \authors Rickard E. Faith <faith@valinux.com>
- * \authors Alan Hourihane <alanh@fairlite.demon.co.uk>
- */
-
-/*
- * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
- * VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
- * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h,v 1.20 2002/10/12 01:38:07 martin Exp $ */
-
-#ifndef _RADEON_MACROS_H_
-#define _RADEON_MACROS_H_
-
-#include <mmio.h>
-
-# define MMIO_IN8(base, offset) \
- *(volatile unsigned char *)(((unsigned char*)(base)) + (offset))
-# define MMIO_IN32(base, offset) \
- read_MMIO_LE32(base, offset)
-# define MMIO_OUT8(base, offset, val) \
- *(volatile unsigned char *)(((unsigned char*)(base)) + (offset)) = (val)
-# define MMIO_OUT32(base, offset, val) \
- *(volatile unsigned int *)(void *)(((unsigned char*)(base)) + (offset)) = CPU_TO_LE32(val)
-
-
- /* Memory mapped register access macros */
-#define INREG8(addr) MMIO_IN8(RADEONMMIO, addr)
-#define INREG(addr) MMIO_IN32(RADEONMMIO, addr)
-#define OUTREG8(addr, val) MMIO_OUT8(RADEONMMIO, addr, val)
-#define OUTREG(addr, val) MMIO_OUT32(RADEONMMIO, addr, val)
-
-#define ADDRREG(addr) ((volatile GLuint *)(pointer)(RADEONMMIO + (addr)))
-
-
-#define OUTREGP(addr, val, mask) \
-do { \
- GLuint tmp = INREG(addr); \
- tmp &= (mask); \
- tmp |= (val); \
- OUTREG(addr, tmp); \
-} while (0)
-
-#define INPLL(dpy, addr) RADEONINPLL(dpy, addr)
-
-#define OUTPLL(addr, val) \
-do { \
- OUTREG8(RADEON_CLOCK_CNTL_INDEX, (((addr) & 0x3f) | \
- RADEON_PLL_WR_EN)); \
- OUTREG(RADEON_CLOCK_CNTL_DATA, val); \
-} while (0)
-
-#define OUTPLLP(dpy, addr, val, mask) \
-do { \
- GLuint tmp = INPLL(dpy, addr); \
- tmp &= (mask); \
- tmp |= (val); \
- OUTPLL(addr, tmp); \
-} while (0)
-
-#define OUTPAL_START(idx) \
-do { \
- OUTREG8(RADEON_PALETTE_INDEX, (idx)); \
-} while (0)
-
-#define OUTPAL_NEXT(r, g, b) \
-do { \
- OUTREG(RADEON_PALETTE_DATA, ((r) << 16) | ((g) << 8) | (b)); \
-} while (0)
-
-#define OUTPAL_NEXT_CARD32(v) \
-do { \
- OUTREG(RADEON_PALETTE_DATA, (v & 0x00ffffff)); \
-} while (0)
-
-#define OUTPAL(idx, r, g, b) \
-do { \
- OUTPAL_START((idx)); \
- OUTPAL_NEXT((r), (g), (b)); \
-} while (0)
-
-#define INPAL_START(idx) \
-do { \
- OUTREG(RADEON_PALETTE_INDEX, (idx) << 16); \
-} while (0)
-
-#define INPAL_NEXT() INREG(RADEON_PALETTE_DATA)
-
-#define PAL_SELECT(idx) \
-do { \
- if (!idx) { \
- OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) & \
- (GLuint)~RADEON_DAC2_PALETTE_ACC_CTL); \
- } else { \
- OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) | \
- RADEON_DAC2_PALETTE_ACC_CTL); \
- } \
-} while (0)
-
-
-#endif
diff --git a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/server/radeon_reg.h b/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/server/radeon_reg.h
deleted file mode 100644
index d290d43cf..000000000
--- a/nx-X11/extras/Mesa/src/mesa/drivers/dri/radeon/server/radeon_reg.h
+++ /dev/null
@@ -1,2142 +0,0 @@
-/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h,v 1.30 2003/10/07 22:47:12 martin Exp $ */
-/*
- * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
- * VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
- * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Authors:
- * Kevin E. Martin <martin@xfree86.org>
- * Rickard E. Faith <faith@valinux.com>
- * Alan Hourihane <alanh@fairlite.demon.co.uk>
- *
- * References:
- *
- * !!!! FIXME !!!!
- * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical
- * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April
- * 1999.
- *
- * !!!! FIXME !!!!
- * RAGE 128 Software Development Manual (Technical Reference Manual P/N
- * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999.
- *
- */
-
-/* !!!! FIXME !!!! NOTE: THIS FILE HAS BEEN CONVERTED FROM r128_reg.h
- * AND CONTAINS REGISTERS AND REGISTER DEFINITIONS THAT ARE NOT CORRECT
- * ON THE RADEON. A FULL AUDIT OF THIS CODE IS NEEDED! */
-
-#ifndef _RADEON_REG_H_
-#define _RADEON_REG_H_
-
- /* Registers for 2D/Video/Overlay */
-#define RADEON_ADAPTER_ID 0x0f2c /* PCI */
-#define RADEON_AGP_BASE 0x0170
-#define RADEON_AGP_CNTL 0x0174
-# define RADEON_AGP_APER_SIZE_256MB (0x00 << 0)
-# define RADEON_AGP_APER_SIZE_128MB (0x20 << 0)
-# define RADEON_AGP_APER_SIZE_64MB (0x30 << 0)
-# define RADEON_AGP_APER_SIZE_32MB (0x38 << 0)
-# define RADEON_AGP_APER_SIZE_16MB (0x3c << 0)
-# define RADEON_AGP_APER_SIZE_8MB (0x3e << 0)
-# define RADEON_AGP_APER_SIZE_4MB (0x3f << 0)
-# define RADEON_AGP_APER_SIZE_MASK (0x3f << 0)
-#define RADEON_AGP_COMMAND 0x0f60 /* PCI */
-#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config*/
-# define RADEON_AGP_ENABLE (1<<8)
-#define RADEON_AGP_PLL_CNTL 0x000b /* PLL */
-#define RADEON_AGP_STATUS 0x0f5c /* PCI */
-# define RADEON_AGP_1X_MODE 0x01
-# define RADEON_AGP_2X_MODE 0x02
-# define RADEON_AGP_4X_MODE 0x04
-# define RADEON_AGP_FW_MODE 0x10
-# define RADEON_AGP_MODE_MASK 0x17
-#define RADEON_ATTRDR 0x03c1 /* VGA */
-#define RADEON_ATTRDW 0x03c0 /* VGA */
-#define RADEON_ATTRX 0x03c0 /* VGA */
-#define RADEON_AUX_SC_CNTL 0x1660
-# define RADEON_AUX1_SC_EN (1 << 0)
-# define RADEON_AUX1_SC_MODE_OR (0 << 1)
-# define RADEON_AUX1_SC_MODE_NAND (1 << 1)
-# define RADEON_AUX2_SC_EN (1 << 2)
-# define RADEON_AUX2_SC_MODE_OR (0 << 3)
-# define RADEON_AUX2_SC_MODE_NAND (1 << 3)
-# define RADEON_AUX3_SC_EN (1 << 4)
-# define RADEON_AUX3_SC_MODE_OR (0 << 5)
-# define RADEON_AUX3_SC_MODE_NAND (1 << 5)
-#define RADEON_AUX1_SC_BOTTOM 0x1670
-#define RADEON_AUX1_SC_LEFT 0x1664
-#define RADEON_AUX1_SC_RIGHT 0x1668
-#define RADEON_AUX1_SC_TOP 0x166c
-#define RADEON_AUX2_SC_BOTTOM 0x1680
-#define RADEON_AUX2_SC_LEFT 0x1674
-#define RADEON_AUX2_SC_RIGHT 0x1678
-#define RADEON_AUX2_SC_TOP 0x167c
-#define RADEON_AUX3_SC_BOTTOM 0x1690
-#define RADEON_AUX3_SC_LEFT 0x1684
-#define RADEON_AUX3_SC_RIGHT 0x1688
-#define RADEON_AUX3_SC_TOP 0x168c
-#define RADEON_AUX_WINDOW_HORZ_CNTL 0x02d8
-#define RADEON_AUX_WINDOW_VERT_CNTL 0x02dc
-
-#define RADEON_BASE_CODE 0x0f0b
-#define RADEON_BIOS_0_SCRATCH 0x0010
-#define RADEON_BIOS_1_SCRATCH 0x0014
-#define RADEON_BIOS_2_SCRATCH 0x0018
-#define RADEON_BIOS_3_SCRATCH 0x001c
-#define RADEON_BIOS_4_SCRATCH 0x0020
-#define RADEON_BIOS_5_SCRATCH 0x0024
-#define RADEON_BIOS_6_SCRATCH 0x0028
-#define RADEON_BIOS_7_SCRATCH 0x002c
-#define RADEON_BIOS_ROM 0x0f30 /* PCI */
-#define RADEON_BIST 0x0f0f /* PCI */
-#define RADEON_BRUSH_DATA0 0x1480
-#define RADEON_BRUSH_DATA1 0x1484
-#define RADEON_BRUSH_DATA10 0x14a8
-#define RADEON_BRUSH_DATA11 0x14ac
-#define RADEON_BRUSH_DATA12 0x14b0
-#define RADEON_BRUSH_DATA13 0x14b4
-#define RADEON_BRUSH_DATA14 0x14b8
-#define RADEON_BRUSH_DATA15 0x14bc
-#define RADEON_BRUSH_DATA16 0x14c0
-#define RADEON_BRUSH_DATA17 0x14c4
-#define RADEON_BRUSH_DATA18 0x14c8
-#define RADEON_BRUSH_DATA19 0x14cc
-#define RADEON_BRUSH_DATA2 0x1488
-#define RADEON_BRUSH_DATA20 0x14d0
-#define RADEON_BRUSH_DATA21 0x14d4
-#define RADEON_BRUSH_DATA22 0x14d8
-#define RADEON_BRUSH_DATA23 0x14dc
-#define RADEON_BRUSH_DATA24 0x14e0
-#define RADEON_BRUSH_DATA25 0x14e4
-#define RADEON_BRUSH_DATA26 0x14e8
-#define RADEON_BRUSH_DATA27 0x14ec
-#define RADEON_BRUSH_DATA28 0x14f0
-#define RADEON_BRUSH_DATA29 0x14f4
-#define RADEON_BRUSH_DATA3 0x148c
-#define RADEON_BRUSH_DATA30 0x14f8
-#define RADEON_BRUSH_DATA31 0x14fc
-#define RADEON_BRUSH_DATA32 0x1500
-#define RADEON_BRUSH_DATA33 0x1504
-#define RADEON_BRUSH_DATA34 0x1508
-#define RADEON_BRUSH_DATA35 0x150c
-#define RADEON_BRUSH_DATA36 0x1510
-#define RADEON_BRUSH_DATA37 0x1514
-#define RADEON_BRUSH_DATA38 0x1518
-#define RADEON_BRUSH_DATA39 0x151c
-#define RADEON_BRUSH_DATA4 0x1490
-#define RADEON_BRUSH_DATA40 0x1520
-#define RADEON_BRUSH_DATA41 0x1524
-#define RADEON_BRUSH_DATA42 0x1528
-#define RADEON_BRUSH_DATA43 0x152c
-#define RADEON_BRUSH_DATA44 0x1530
-#define RADEON_BRUSH_DATA45 0x1534
-#define RADEON_BRUSH_DATA46 0x1538
-#define RADEON_BRUSH_DATA47 0x153c
-#define RADEON_BRUSH_DATA48 0x1540
-#define RADEON_BRUSH_DATA49 0x1544
-#define RADEON_BRUSH_DATA5 0x1494
-#define RADEON_BRUSH_DATA50 0x1548
-#define RADEON_BRUSH_DATA51 0x154c
-#define RADEON_BRUSH_DATA52 0x1550
-#define RADEON_BRUSH_DATA53 0x1554
-#define RADEON_BRUSH_DATA54 0x1558
-#define RADEON_BRUSH_DATA55 0x155c
-#define RADEON_BRUSH_DATA56 0x1560
-#define RADEON_BRUSH_DATA57 0x1564
-#define RADEON_BRUSH_DATA58 0x1568
-#define RADEON_BRUSH_DATA59 0x156c
-#define RADEON_BRUSH_DATA6 0x1498
-#define RADEON_BRUSH_DATA60 0x1570
-#define RADEON_BRUSH_DATA61 0x1574
-#define RADEON_BRUSH_DATA62 0x1578
-#define RADEON_BRUSH_DATA63 0x157c
-#define RADEON_BRUSH_DATA7 0x149c
-#define RADEON_BRUSH_DATA8 0x14a0
-#define RADEON_BRUSH_DATA9 0x14a4
-#define RADEON_BRUSH_SCALE 0x1470
-#define RADEON_BRUSH_Y_X 0x1474
-#define RADEON_BUS_CNTL 0x0030
-# define RADEON_BUS_MASTER_DIS (1 << 6)
-# define RADEON_BUS_RD_DISCARD_EN (1 << 24)
-# define RADEON_BUS_RD_ABORT_EN (1 << 25)
-# define RADEON_BUS_MSTR_DISCONNECT_EN (1 << 28)
-# define RADEON_BUS_WRT_BURST (1 << 29)
-# define RADEON_BUS_READ_BURST (1 << 30)
-#define RADEON_BUS_CNTL1 0x0034
-# define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4)
-
-#define RADEON_CACHE_CNTL 0x1724
-#define RADEON_CACHE_LINE 0x0f0c /* PCI */
-#define RADEON_CAP0_TRIG_CNTL 0x0950 /* ? */
-#define RADEON_CAP1_TRIG_CNTL 0x09c0 /* ? */
-#define RADEON_CAPABILITIES_ID 0x0f50 /* PCI */
-#define RADEON_CAPABILITIES_PTR 0x0f34 /* PCI */
-#define RADEON_CLK_PIN_CNTL 0x0001 /* PLL */
-#define RADEON_CLOCK_CNTL_DATA 0x000c
-#define RADEON_CLOCK_CNTL_INDEX 0x0008
-# define RADEON_PLL_WR_EN (1 << 7)
-# define RADEON_PLL_DIV_SEL (3 << 8)
-# define RADEON_PLL2_DIV_SEL_MASK ~(3 << 8)
-#define RADEON_CLR_CMP_CLR_3D 0x1a24
-#define RADEON_CLR_CMP_CLR_DST 0x15c8
-#define RADEON_CLR_CMP_CLR_SRC 0x15c4
-#define RADEON_CLR_CMP_CNTL 0x15c0
-# define RADEON_SRC_CMP_EQ_COLOR (4 << 0)
-# define RADEON_SRC_CMP_NEQ_COLOR (5 << 0)
-# define RADEON_CLR_CMP_SRC_SOURCE (1 << 24)
-#define RADEON_CLR_CMP_MASK 0x15cc
-# define RADEON_CLR_CMP_MSK 0xffffffff
-#define RADEON_CLR_CMP_MASK_3D 0x1A28
-#define RADEON_COMMAND 0x0f04 /* PCI */
-#define RADEON_COMPOSITE_SHADOW_ID 0x1a0c
-#define RADEON_CONFIG_APER_0_BASE 0x0100
-#define RADEON_CONFIG_APER_1_BASE 0x0104
-#define RADEON_CONFIG_APER_SIZE 0x0108
-#define RADEON_CONFIG_BONDS 0x00e8
-#define RADEON_CONFIG_CNTL 0x00e0
-# define RADEON_CFG_ATI_REV_A11 (0 << 16)
-# define RADEON_CFG_ATI_REV_A12 (1 << 16)
-# define RADEON_CFG_ATI_REV_A13 (2 << 16)
-# define RADEON_CFG_ATI_REV_ID_MASK (0xf << 16)
-#define RADEON_CONFIG_MEMSIZE 0x00f8
-#define RADEON_CONFIG_MEMSIZE_EMBEDDED 0x0114
-#define RADEON_CONFIG_REG_1_BASE 0x010c
-#define RADEON_CONFIG_REG_APER_SIZE 0x0110
-#define RADEON_CONFIG_XSTRAP 0x00e4
-#define RADEON_CONSTANT_COLOR_C 0x1d34
-# define RADEON_CONSTANT_COLOR_MASK 0x00ffffff
-# define RADEON_CONSTANT_COLOR_ONE 0x00ffffff
-# define RADEON_CONSTANT_COLOR_ZERO 0x00000000
-#define RADEON_CRC_CMDFIFO_ADDR 0x0740
-#define RADEON_CRC_CMDFIFO_DOUT 0x0744
-#define RADEON_GRPH_BUFFER_CNTL 0x02f0
-# define RADEON_GRPH_START_REQ_MASK (0x7f)
-# define RADEON_GRPH_START_REQ_SHIFT 0
-# define RADEON_GRPH_STOP_REQ_MASK (0x7f<<8)
-# define RADEON_GRPH_STOP_REQ_SHIFT 8
-# define RADEON_GRPH_CRITICAL_POINT_MASK (0x7f<<16)
-# define RADEON_GRPH_CRITICAL_POINT_SHIFT 16
-# define RADEON_GRPH_CRITICAL_CNTL (1<<28)
-# define RADEON_GRPH_BUFFER_SIZE (1<<29)
-# define RADEON_GRPH_CRITICAL_AT_SOF (1<<30)
-# define RADEON_GRPH_STOP_CNTL (1<<31)
-#define RADEON_GRPH2_BUFFER_CNTL 0x03f0
-# define RADEON_GRPH2_START_REQ_MASK (0x7f)
-# define RADEON_GRPH2_START_REQ_SHIFT 0
-# define RADEON_GRPH2_STOP_REQ_MASK (0x7f<<8)
-# define RADEON_GRPH2_STOP_REQ_SHIFT 8
-# define RADEON_GRPH2_CRITICAL_POINT_MASK (0x7f<<16)
-# define RADEON_GRPH2_CRITICAL_POINT_SHIFT 16
-# define RADEON_GRPH2_CRITICAL_CNTL (1<<28)
-# define RADEON_GRPH2_BUFFER_SIZE (1<<29)
-# define RADEON_GRPH2_CRITICAL_AT_SOF (1<<30)
-# define RADEON_GRPH2_STOP_CNTL (1<<31)
-#define RADEON_CRTC_CRNT_FRAME 0x0214
-#define RADEON_CRTC_EXT_CNTL 0x0054
-# define RADEON_CRTC_VGA_XOVERSCAN (1 << 0)
-# define RADEON_VGA_ATI_LINEAR (1 << 3)
-# define RADEON_XCRT_CNT_EN (1 << 6)
-# define RADEON_CRTC_HSYNC_DIS (1 << 8)
-# define RADEON_CRTC_VSYNC_DIS (1 << 9)
-# define RADEON_CRTC_DISPLAY_DIS (1 << 10)
-# define RADEON_CRTC_SYNC_TRISTAT (1 << 11)
-# define RADEON_CRTC_CRT_ON (1 << 15)
-#define RADEON_CRTC_EXT_CNTL_DPMS_BYTE 0x0055
-# define RADEON_CRTC_HSYNC_DIS_BYTE (1 << 0)
-# define RADEON_CRTC_VSYNC_DIS_BYTE (1 << 1)
-# define RADEON_CRTC_DISPLAY_DIS_BYTE (1 << 2)
-#define RADEON_CRTC_GEN_CNTL 0x0050
-# define RADEON_CRTC_DBL_SCAN_EN (1 << 0)
-# define RADEON_CRTC_INTERLACE_EN (1 << 1)
-# define RADEON_CRTC_CSYNC_EN (1 << 4)
-# define RADEON_CRTC_CUR_EN (1 << 16)
-# define RADEON_CRTC_CUR_MODE_MASK (7 << 17)
-# define RADEON_CRTC_ICON_EN (1 << 20)
-# define RADEON_CRTC_EXT_DISP_EN (1 << 24)
-# define RADEON_CRTC_EN (1 << 25)
-# define RADEON_CRTC_DISP_REQ_EN_B (1 << 26)
-#define RADEON_CRTC2_GEN_CNTL 0x03f8
-# define RADEON_CRTC2_DBL_SCAN_EN (1 << 0)
-# define RADEON_CRTC2_INTERLACE_EN (1 << 1)
-# define RADEON_CRTC2_SYNC_TRISTAT (1 << 4)
-# define RADEON_CRTC2_HSYNC_TRISTAT (1 << 5)
-# define RADEON_CRTC2_VSYNC_TRISTAT (1 << 6)
-# define RADEON_CRTC2_CRT2_ON (1 << 7)
-# define RADEON_CRTC2_ICON_EN (1 << 15)
-# define RADEON_CRTC2_CUR_EN (1 << 16)
-# define RADEON_CRTC2_CUR_MODE_MASK (7 << 20)
-# define RADEON_CRTC2_DISP_DIS (1 << 23)
-# define RADEON_CRTC2_EN (1 << 25)
-# define RADEON_CRTC2_DISP_REQ_EN_B (1 << 26)
-# define RADEON_CRTC2_CSYNC_EN (1 << 27)
-# define RADEON_CRTC2_HSYNC_DIS (1 << 28)
-# define RADEON_CRTC2_VSYNC_DIS (1 << 29)
-#define RADEON_CRTC_MORE_CNTL 0x27c
-# define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4)
-# define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5)
-#define RADEON_CRTC_GUI_TRIG_VLINE 0x0218
-#define RADEON_CRTC_H_SYNC_STRT_WID 0x0204
-# define RADEON_CRTC_H_SYNC_STRT_PIX (0x07 << 0)
-# define RADEON_CRTC_H_SYNC_STRT_CHAR (0x3ff << 3)
-# define RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT 3
-# define RADEON_CRTC_H_SYNC_WID (0x3f << 16)
-# define RADEON_CRTC_H_SYNC_WID_SHIFT 16
-# define RADEON_CRTC_H_SYNC_POL (1 << 23)
-#define RADEON_CRTC2_H_SYNC_STRT_WID 0x0304
-# define RADEON_CRTC2_H_SYNC_STRT_PIX (0x07 << 0)
-# define RADEON_CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3)
-# define RADEON_CRTC2_H_SYNC_STRT_CHAR_SHIFT 3
-# define RADEON_CRTC2_H_SYNC_WID (0x3f << 16)
-# define RADEON_CRTC2_H_SYNC_WID_SHIFT 16
-# define RADEON_CRTC2_H_SYNC_POL (1 << 23)
-#define RADEON_CRTC_H_TOTAL_DISP 0x0200
-# define RADEON_CRTC_H_TOTAL (0x03ff << 0)
-# define RADEON_CRTC_H_TOTAL_SHIFT 0
-# define RADEON_CRTC_H_DISP (0x01ff << 16)
-# define RADEON_CRTC_H_DISP_SHIFT 16
-#define RADEON_CRTC2_H_TOTAL_DISP 0x0300
-# define RADEON_CRTC2_H_TOTAL (0x03ff << 0)
-# define RADEON_CRTC2_H_TOTAL_SHIFT 0
-# define RADEON_CRTC2_H_DISP (0x01ff << 16)
-# define RADEON_CRTC2_H_DISP_SHIFT 16
-#define RADEON_CRTC_OFFSET 0x0224
-#define RADEON_CRTC2_OFFSET 0x0324
-#define RADEON_CRTC_OFFSET_CNTL 0x0228
-# define RADEON_CRTC_TILE_EN (1 << 15)
-#define RADEON_CRTC2_OFFSET_CNTL 0x0328
-# define RADEON_CRTC2_TILE_EN (1 << 15)
-#define RADEON_CRTC_PITCH 0x022c
-#define RADEON_CRTC2_PITCH 0x032c
-#define RADEON_CRTC_STATUS 0x005c
-# define RADEON_CRTC_VBLANK_SAVE (1 << 1)
-# define RADEON_CRTC_VBLANK_SAVE_CLEAR (1 << 1)
-#define RADEON_CRTC2_STATUS 0x03fc
-# define RADEON_CRTC2_VBLANK_SAVE (1 << 1)
-# define RADEON_CRTC2_VBLANK_SAVE_CLEAR (1 << 1)
-#define RADEON_CRTC_V_SYNC_STRT_WID 0x020c
-# define RADEON_CRTC_V_SYNC_STRT (0x7ff << 0)
-# define RADEON_CRTC_V_SYNC_STRT_SHIFT 0
-# define RADEON_CRTC_V_SYNC_WID (0x1f << 16)
-# define RADEON_CRTC_V_SYNC_WID_SHIFT 16
-# define RADEON_CRTC_V_SYNC_POL (1 << 23)
-#define RADEON_CRTC2_V_SYNC_STRT_WID 0x030c
-# define RADEON_CRTC2_V_SYNC_STRT (0x7ff << 0)
-# define RADEON_CRTC2_V_SYNC_STRT_SHIFT 0
-# define RADEON_CRTC2_V_SYNC_WID (0x1f << 16)
-# define RADEON_CRTC2_V_SYNC_WID_SHIFT 16
-# define RADEON_CRTC2_V_SYNC_POL (1 << 23)
-#define RADEON_CRTC_V_TOTAL_DISP 0x0208
-# define RADEON_CRTC_V_TOTAL (0x07ff << 0)
-# define RADEON_CRTC_V_TOTAL_SHIFT 0
-# define RADEON_CRTC_V_DISP (0x07ff << 16)
-# define RADEON_CRTC_V_DISP_SHIFT 16
-#define RADEON_CRTC2_V_TOTAL_DISP 0x0308
-# define RADEON_CRTC2_V_TOTAL (0x07ff << 0)
-# define RADEON_CRTC2_V_TOTAL_SHIFT 0
-# define RADEON_CRTC2_V_DISP (0x07ff << 16)
-# define RADEON_CRTC2_V_DISP_SHIFT 16
-#define RADEON_CRTC_VLINE_CRNT_VLINE 0x0210
-# define RADEON_CRTC_CRNT_VLINE_MASK (0x7ff << 16)
-#define RADEON_CRTC2_CRNT_FRAME 0x0314
-#define RADEON_CRTC2_GUI_TRIG_VLINE 0x0318
-#define RADEON_CRTC2_STATUS 0x03fc
-#define RADEON_CRTC2_VLINE_CRNT_VLINE 0x0310
-#define RADEON_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */
-#define RADEON_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */
-#define RADEON_CUR_CLR0 0x026c
-#define RADEON_CUR_CLR1 0x0270
-#define RADEON_CUR_HORZ_VERT_OFF 0x0268
-#define RADEON_CUR_HORZ_VERT_POSN 0x0264
-#define RADEON_CUR_OFFSET 0x0260
-# define RADEON_CUR_LOCK (1 << 31)
-#define RADEON_CUR2_CLR0 0x036c
-#define RADEON_CUR2_CLR1 0x0370
-#define RADEON_CUR2_HORZ_VERT_OFF 0x0368
-#define RADEON_CUR2_HORZ_VERT_POSN 0x0364
-#define RADEON_CUR2_OFFSET 0x0360
-# define RADEON_CUR2_LOCK (1 << 31)
-
-#define RADEON_DAC_CNTL 0x0058
-# define RADEON_DAC_RANGE_CNTL (3 << 0)
-# define RADEON_DAC_RANGE_CNTL_MASK 0x03
-# define RADEON_DAC_BLANKING (1 << 2)
-# define RADEON_DAC_CMP_EN (1 << 3)
-# define RADEON_DAC_CMP_OUTPUT (1 << 7)
-# define RADEON_DAC_8BIT_EN (1 << 8)
-# define RADEON_DAC_VGA_ADR_EN (1 << 13)
-# define RADEON_DAC_PDWN (1 << 15)
-# define RADEON_DAC_MASK_ALL (0xff << 24)
-#define RADEON_DAC_CNTL2 0x007c
-# define RADEON_DAC2_DAC_CLK_SEL (1 << 0)
-# define RADEON_DAC2_DAC2_CLK_SEL (1 << 1)
-# define RADEON_DAC2_PALETTE_ACC_CTL (1 << 5)
-#define RADEON_DAC_EXT_CNTL 0x0280
-# define RADEON_DAC_FORCE_BLANK_OFF_EN (1 << 4)
-# define RADEON_DAC_FORCE_DATA_EN (1 << 5)
-# define RADEON_DAC_FORCE_DATA_SEL_MASK (3 << 6)
-# define RADEON_DAC_FORCE_DATA_MASK 0x0003ff00
-# define RADEON_DAC_FORCE_DATA_SHIFT 8
-#define RADEON_TV_DAC_CNTL 0x088c
-# define RADEON_TV_DAC_STD_MASK 0x0300
-# define RADEON_TV_DAC_RDACPD (1 << 24)
-# define RADEON_TV_DAC_GDACPD (1 << 25)
-# define RADEON_TV_DAC_BDACPD (1 << 26)
-#define RADEON_DISP_HW_DEBUG 0x0d14
-# define RADEON_CRT2_DISP1_SEL (1 << 5)
-#define RADEON_DISP_OUTPUT_CNTL 0x0d64
-# define RADEON_DISP_DAC_SOURCE_MASK 0x03
-# define RADEON_DISP_DAC2_SOURCE_MASK 0x0c
-# define RADEON_DISP_DAC_SOURCE_CRTC2 0x01
-# define RADEON_DISP_DAC2_SOURCE_CRTC2 0x04
-#define RADEON_DAC_CRC_SIG 0x02cc
-#define RADEON_DAC_DATA 0x03c9 /* VGA */
-#define RADEON_DAC_MASK 0x03c6 /* VGA */
-#define RADEON_DAC_R_INDEX 0x03c7 /* VGA */
-#define RADEON_DAC_W_INDEX 0x03c8 /* VGA */
-#define RADEON_DDA_CONFIG 0x02e0
-#define RADEON_DDA_ON_OFF 0x02e4
-#define RADEON_DEFAULT_OFFSET 0x16e0
-#define RADEON_DEFAULT_PITCH 0x16e4
-#define RADEON_DEFAULT_SC_BOTTOM_RIGHT 0x16e8
-# define RADEON_DEFAULT_SC_RIGHT_MAX (0x1fff << 0)
-# define RADEON_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)
-#define RADEON_DESTINATION_3D_CLR_CMP_VAL 0x1820
-#define RADEON_DESTINATION_3D_CLR_CMP_MSK 0x1824
-#define RADEON_DEVICE_ID 0x0f02 /* PCI */
-#define RADEON_DISP_MISC_CNTL 0x0d00
-# define RADEON_SOFT_RESET_GRPH_PP (1 << 0)
-#define RADEON_DISP_MERGE_CNTL 0x0d60
-# define RADEON_DISP_ALPHA_MODE_MASK 0x03
-# define RADEON_DISP_ALPHA_MODE_KEY 0
-# define RADEON_DISP_ALPHA_MODE_PER_PIXEL 1
-# define RADEON_DISP_ALPHA_MODE_GLOBAL 2
-# define RADEON_DISP_RGB_OFFSET_EN (1<<8)
-# define RADEON_DISP_GRPH_ALPHA_MASK (0xff << 16)
-# define RADEON_DISP_OV0_ALPHA_MASK (0xff << 24)
-# define RADEON_DISP_LIN_TRANS_BYPASS (0x01 << 9)
-#define RADEON_DISP2_MERGE_CNTL 0x0d68
-# define RADEON_DISP2_RGB_OFFSET_EN (1<<8)
-#define RADEON_DISP_LIN_TRANS_GRPH_A 0x0d80
-#define RADEON_DISP_LIN_TRANS_GRPH_B 0x0d84
-#define RADEON_DISP_LIN_TRANS_GRPH_C 0x0d88
-#define RADEON_DISP_LIN_TRANS_GRPH_D 0x0d8c
-#define RADEON_DISP_LIN_TRANS_GRPH_E 0x0d90
-#define RADEON_DISP_LIN_TRANS_GRPH_F 0x0d98
-#define RADEON_DP_BRUSH_BKGD_CLR 0x1478
-#define RADEON_DP_BRUSH_FRGD_CLR 0x147c
-#define RADEON_DP_CNTL 0x16c0
-# define RADEON_DST_X_LEFT_TO_RIGHT (1 << 0)
-# define RADEON_DST_Y_TOP_TO_BOTTOM (1 << 1)
-#define RADEON_DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0
-# define RADEON_DST_Y_MAJOR (1 << 2)
-# define RADEON_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15)
-# define RADEON_DST_X_DIR_LEFT_TO_RIGHT (1 << 31)
-#define RADEON_DP_DATATYPE 0x16c4
-# define RADEON_HOST_BIG_ENDIAN_EN (1 << 29)
-#define RADEON_DP_GUI_MASTER_CNTL 0x146c
-# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
-# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
-# define RADEON_GMC_SRC_CLIPPING (1 << 2)
-# define RADEON_GMC_DST_CLIPPING (1 << 3)
-# define RADEON_GMC_BRUSH_DATATYPE_MASK (0x0f << 4)
-# define RADEON_GMC_BRUSH_8X8_MONO_FG_BG (0 << 4)
-# define RADEON_GMC_BRUSH_8X8_MONO_FG_LA (1 << 4)
-# define RADEON_GMC_BRUSH_1X8_MONO_FG_BG (4 << 4)
-# define RADEON_GMC_BRUSH_1X8_MONO_FG_LA (5 << 4)
-# define RADEON_GMC_BRUSH_32x1_MONO_FG_BG (6 << 4)
-# define RADEON_GMC_BRUSH_32x1_MONO_FG_LA (7 << 4)
-# define RADEON_GMC_BRUSH_32x32_MONO_FG_BG (8 << 4)
-# define RADEON_GMC_BRUSH_32x32_MONO_FG_LA (9 << 4)
-# define RADEON_GMC_BRUSH_8x8_COLOR (10 << 4)
-# define RADEON_GMC_BRUSH_1X8_COLOR (12 << 4)
-# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
-# define RADEON_GMC_BRUSH_NONE (15 << 4)
-# define RADEON_GMC_DST_8BPP_CI (2 << 8)
-# define RADEON_GMC_DST_15BPP (3 << 8)
-# define RADEON_GMC_DST_16BPP (4 << 8)
-# define RADEON_GMC_DST_24BPP (5 << 8)
-# define RADEON_GMC_DST_32BPP (6 << 8)
-# define RADEON_GMC_DST_8BPP_RGB (7 << 8)
-# define RADEON_GMC_DST_Y8 (8 << 8)
-# define RADEON_GMC_DST_RGB8 (9 << 8)
-# define RADEON_GMC_DST_VYUY (11 << 8)
-# define RADEON_GMC_DST_YVYU (12 << 8)
-# define RADEON_GMC_DST_AYUV444 (14 << 8)
-# define RADEON_GMC_DST_ARGB4444 (15 << 8)
-# define RADEON_GMC_DST_DATATYPE_MASK (0x0f << 8)
-# define RADEON_GMC_DST_DATATYPE_SHIFT 8
-# define RADEON_GMC_SRC_DATATYPE_MASK (3 << 12)
-# define RADEON_GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12)
-# define RADEON_GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12)
-# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
-# define RADEON_GMC_BYTE_PIX_ORDER (1 << 14)
-# define RADEON_GMC_BYTE_MSB_TO_LSB (0 << 14)
-# define RADEON_GMC_BYTE_LSB_TO_MSB (1 << 14)
-# define RADEON_GMC_CONVERSION_TEMP (1 << 15)
-# define RADEON_GMC_CONVERSION_TEMP_6500 (0 << 15)
-# define RADEON_GMC_CONVERSION_TEMP_9300 (1 << 15)
-# define RADEON_GMC_ROP3_MASK (0xff << 16)
-# define RADEON_DP_SRC_SOURCE_MASK (7 << 24)
-# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
-# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
-# define RADEON_GMC_3D_FCN_EN (1 << 27)
-# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
-# define RADEON_GMC_AUX_CLIP_DIS (1 << 29)
-# define RADEON_GMC_WR_MSK_DIS (1 << 30)
-# define RADEON_GMC_LD_BRUSH_Y_X (1 << 31)
-# define RADEON_ROP3_ZERO 0x00000000
-# define RADEON_ROP3_DSa 0x00880000
-# define RADEON_ROP3_SDna 0x00440000
-# define RADEON_ROP3_S 0x00cc0000
-# define RADEON_ROP3_DSna 0x00220000
-# define RADEON_ROP3_D 0x00aa0000
-# define RADEON_ROP3_DSx 0x00660000
-# define RADEON_ROP3_DSo 0x00ee0000
-# define RADEON_ROP3_DSon 0x00110000
-# define RADEON_ROP3_DSxn 0x00990000
-# define RADEON_ROP3_Dn 0x00550000
-# define RADEON_ROP3_SDno 0x00dd0000
-# define RADEON_ROP3_Sn 0x00330000
-# define RADEON_ROP3_DSno 0x00bb0000
-# define RADEON_ROP3_DSan 0x00770000
-# define RADEON_ROP3_ONE 0x00ff0000
-# define RADEON_ROP3_DPa 0x00a00000
-# define RADEON_ROP3_PDna 0x00500000
-# define RADEON_ROP3_P 0x00f00000
-# define RADEON_ROP3_DPna 0x000a0000
-# define RADEON_ROP3_D 0x00aa0000
-# define RADEON_ROP3_DPx 0x005a0000
-# define RADEON_ROP3_DPo 0x00fa0000
-# define RADEON_ROP3_DPon 0x00050000
-# define RADEON_ROP3_PDxn 0x00a50000
-# define RADEON_ROP3_PDno 0x00f50000
-# define RADEON_ROP3_Pn 0x000f0000
-# define RADEON_ROP3_DPno 0x00af0000
-# define RADEON_ROP3_DPan 0x005f0000
-#define RADEON_DP_GUI_MASTER_CNTL_C 0x1c84
-#define RADEON_DP_MIX 0x16c8
-#define RADEON_DP_SRC_BKGD_CLR 0x15dc
-#define RADEON_DP_SRC_FRGD_CLR 0x15d8
-#define RADEON_DP_WRITE_MASK 0x16cc
-#define RADEON_DST_BRES_DEC 0x1630
-#define RADEON_DST_BRES_ERR 0x1628
-#define RADEON_DST_BRES_INC 0x162c
-#define RADEON_DST_BRES_LNTH 0x1634
-#define RADEON_DST_BRES_LNTH_SUB 0x1638
-#define RADEON_DST_HEIGHT 0x1410
-#define RADEON_DST_HEIGHT_WIDTH 0x143c
-#define RADEON_DST_HEIGHT_WIDTH_8 0x158c
-#define RADEON_DST_HEIGHT_WIDTH_BW 0x15b4
-#define RADEON_DST_HEIGHT_Y 0x15a0
-#define RADEON_DST_LINE_START 0x1600
-#define RADEON_DST_LINE_END 0x1604
-#define RADEON_DST_LINE_PATCOUNT 0x1608
-# define RADEON_BRES_CNTL_SHIFT 8
-#define RADEON_DST_OFFSET 0x1404
-#define RADEON_DST_PITCH 0x1408
-#define RADEON_DST_PITCH_OFFSET 0x142c
-#define RADEON_DST_PITCH_OFFSET_C 0x1c80
-# define RADEON_PITCH_SHIFT 21
-# define RADEON_DST_TILE_LINEAR (0 << 30)
-# define RADEON_DST_TILE_MACRO (1 << 30)
-# define RADEON_DST_TILE_MICRO (2 << 30)
-# define RADEON_DST_TILE_BOTH (3 << 30)
-#define RADEON_DST_WIDTH 0x140c
-#define RADEON_DST_WIDTH_HEIGHT 0x1598
-#define RADEON_DST_WIDTH_X 0x1588
-#define RADEON_DST_WIDTH_X_INCY 0x159c
-#define RADEON_DST_X 0x141c
-#define RADEON_DST_X_SUB 0x15a4
-#define RADEON_DST_X_Y 0x1594
-#define RADEON_DST_Y 0x1420
-#define RADEON_DST_Y_SUB 0x15a8
-#define RADEON_DST_Y_X 0x1438
-
-#define RADEON_FCP_CNTL 0x0910
-# define RADEON_FCP0_SRC_PCICLK 0
-# define RADEON_FCP0_SRC_PCLK 1
-# define RADEON_FCP0_SRC_PCLKb 2
-# define RADEON_FCP0_SRC_HREF 3
-# define RADEON_FCP0_SRC_GND 4
-# define RADEON_FCP0_SRC_HREFb 5
-#define RADEON_FLUSH_1 0x1704
-#define RADEON_FLUSH_2 0x1708
-#define RADEON_FLUSH_3 0x170c
-#define RADEON_FLUSH_4 0x1710
-#define RADEON_FLUSH_5 0x1714
-#define RADEON_FLUSH_6 0x1718
-#define RADEON_FLUSH_7 0x171c
-#define RADEON_FOG_3D_TABLE_START 0x1810
-#define RADEON_FOG_3D_TABLE_END 0x1814
-#define RADEON_FOG_3D_TABLE_DENSITY 0x181c
-#define RADEON_FOG_TABLE_INDEX 0x1a14
-#define RADEON_FOG_TABLE_DATA 0x1a18
-#define RADEON_FP_CRTC_H_TOTAL_DISP 0x0250
-#define RADEON_FP_CRTC_V_TOTAL_DISP 0x0254
-#define RADEON_FP_CRTC2_H_TOTAL_DISP 0x0350
-#define RADEON_FP_CRTC2_V_TOTAL_DISP 0x0354
-# define RADEON_FP_CRTC_H_TOTAL_MASK 0x000003ff
-# define RADEON_FP_CRTC_H_DISP_MASK 0x01ff0000
-# define RADEON_FP_CRTC_V_TOTAL_MASK 0x00000fff
-# define RADEON_FP_CRTC_V_DISP_MASK 0x0fff0000
-# define RADEON_FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8
-# define RADEON_FP_H_SYNC_WID_MASK 0x003f0000
-# define RADEON_FP_V_SYNC_STRT_MASK 0x00000fff
-# define RADEON_FP_V_SYNC_WID_MASK 0x001f0000
-# define RADEON_FP_CRTC_H_TOTAL_SHIFT 0x00000000
-# define RADEON_FP_CRTC_H_DISP_SHIFT 0x00000010
-# define RADEON_FP_CRTC_V_TOTAL_SHIFT 0x00000000
-# define RADEON_FP_CRTC_V_DISP_SHIFT 0x00000010
-# define RADEON_FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003
-# define RADEON_FP_H_SYNC_WID_SHIFT 0x00000010
-# define RADEON_FP_V_SYNC_STRT_SHIFT 0x00000000
-# define RADEON_FP_V_SYNC_WID_SHIFT 0x00000010
-#define RADEON_FP_GEN_CNTL 0x0284
-# define RADEON_FP_FPON (1 << 0)
-# define RADEON_FP_TMDS_EN (1 << 2)
-# define RADEON_FP_PANEL_FORMAT (1 << 3)
-# define RADEON_FP_EN_TMDS (1 << 7)
-# define RADEON_FP_DETECT_SENSE (1 << 8)
-# define RADEON_FP_SEL_CRTC2 (1 << 13)
-# define RADEON_FP_CRTC_DONT_SHADOW_HPAR (1 << 15)
-# define RADEON_FP_CRTC_DONT_SHADOW_VPAR (1 << 16)
-# define RADEON_FP_CRTC_DONT_SHADOW_HEND (1 << 17)
-# define RADEON_FP_CRTC_USE_SHADOW_VEND (1 << 18)
-# define RADEON_FP_RMX_HVSYNC_CONTROL_EN (1 << 20)
-# define RADEON_FP_DFP_SYNC_SEL (1 << 21)
-# define RADEON_FP_CRTC_LOCK_8DOT (1 << 22)
-# define RADEON_FP_CRT_SYNC_SEL (1 << 23)
-# define RADEON_FP_USE_SHADOW_EN (1 << 24)
-# define RADEON_FP_CRT_SYNC_ALT (1 << 26)
-#define RADEON_FP2_GEN_CNTL 0x0288
-# define RADEON_FP2_BLANK_EN (1 << 1)
-# define RADEON_FP2_ON (1 << 2)
-# define RADEON_FP2_PANEL_FORMAT (1 << 3)
-# define RADEON_FP2_SOURCE_SEL_MASK (3 << 10)
-# define RADEON_FP2_SOURCE_SEL_CRTC2 (1 << 10)
-# define RADEON_FP2_SRC_SEL_MASK (3 << 13)
-# define RADEON_FP2_SRC_SEL_CRTC2 (1 << 13)
-# define RADEON_FP2_FP_POL (1 << 16)
-# define RADEON_FP2_LP_POL (1 << 17)
-# define RADEON_FP2_SCK_POL (1 << 18)
-# define RADEON_FP2_LCD_CNTL_MASK (7 << 19)
-# define RADEON_FP2_PAD_FLOP_EN (1 << 22)
-# define RADEON_FP2_CRC_EN (1 << 23)
-# define RADEON_FP2_CRC_READ_EN (1 << 24)
-# define RADEON_FP2_DV0_EN (1 << 25)
-# define RADEON_FP2_DV0_RATE_SEL_SDR (1 << 26)
-#define RADEON_FP_H_SYNC_STRT_WID 0x02c4
-#define RADEON_FP_H2_SYNC_STRT_WID 0x03c4
-#define RADEON_FP_HORZ_STRETCH 0x028c
-#define RADEON_FP_HORZ2_STRETCH 0x038c
-# define RADEON_HORZ_STRETCH_RATIO_MASK 0xffff
-# define RADEON_HORZ_STRETCH_RATIO_MAX 4096
-# define RADEON_HORZ_PANEL_SIZE (0x1ff << 16)
-# define RADEON_HORZ_PANEL_SHIFT 16
-# define RADEON_HORZ_STRETCH_PIXREP (0 << 25)
-# define RADEON_HORZ_STRETCH_BLEND (1 << 26)
-# define RADEON_HORZ_STRETCH_ENABLE (1 << 25)
-# define RADEON_HORZ_AUTO_RATIO (1 << 27)
-# define RADEON_HORZ_FP_LOOP_STRETCH (0x7 << 28)
-# define RADEON_HORZ_AUTO_RATIO_INC (1 << 31)
-#define RADEON_FP_V_SYNC_STRT_WID 0x02c8
-#define RADEON_FP_VERT_STRETCH 0x0290
-#define RADEON_FP_V2_SYNC_STRT_WID 0x03c8
-#define RADEON_FP_VERT2_STRETCH 0x0390
-# define RADEON_VERT_PANEL_SIZE (0xfff << 12)
-# define RADEON_VERT_PANEL_SHIFT 12
-# define RADEON_VERT_STRETCH_RATIO_MASK 0xfff
-# define RADEON_VERT_STRETCH_RATIO_SHIFT 0
-# define RADEON_VERT_STRETCH_RATIO_MAX 4096
-# define RADEON_VERT_STRETCH_ENABLE (1 << 25)
-# define RADEON_VERT_STRETCH_LINEREP (0 << 26)
-# define RADEON_VERT_STRETCH_BLEND (1 << 26)
-# define RADEON_VERT_AUTO_RATIO_EN (1 << 27)
-# define RADEON_VERT_STRETCH_RESERVED 0xf1000000
-
-#define RADEON_GEN_INT_CNTL 0x0040
-#define RADEON_GEN_INT_STATUS 0x0044
-# define RADEON_VSYNC_INT_AK (1 << 2)
-# define RADEON_VSYNC_INT (1 << 2)
-# define RADEON_VSYNC2_INT_AK (1 << 6)
-# define RADEON_VSYNC2_INT (1 << 6)
-#define RADEON_GENENB 0x03c3 /* VGA */
-#define RADEON_GENFC_RD 0x03ca /* VGA */
-#define RADEON_GENFC_WT 0x03da /* VGA, 0x03ba */
-#define RADEON_GENMO_RD 0x03cc /* VGA */
-#define RADEON_GENMO_WT 0x03c2 /* VGA */
-#define RADEON_GENS0 0x03c2 /* VGA */
-#define RADEON_GENS1 0x03da /* VGA, 0x03ba */
-#define RADEON_GPIO_MONID 0x0068 /* DDC interface via I2C */
-#define RADEON_GPIO_MONIDB 0x006c
-#define RADEON_GPIO_CRT2_DDC 0x006c
-#define RADEON_GPIO_DVI_DDC 0x0064
-#define RADEON_GPIO_VGA_DDC 0x0060
-# define RADEON_GPIO_A_0 (1 << 0)
-# define RADEON_GPIO_A_1 (1 << 1)
-# define RADEON_GPIO_Y_0 (1 << 8)
-# define RADEON_GPIO_Y_1 (1 << 9)
-# define RADEON_GPIO_Y_SHIFT_0 8
-# define RADEON_GPIO_Y_SHIFT_1 9
-# define RADEON_GPIO_EN_0 (1 << 16)
-# define RADEON_GPIO_EN_1 (1 << 17)
-# define RADEON_GPIO_MASK_0 (1 << 24) /*??*/
-# define RADEON_GPIO_MASK_1 (1 << 25) /*??*/
-#define RADEON_GRPH8_DATA 0x03cf /* VGA */
-#define RADEON_GRPH8_IDX 0x03ce /* VGA */
-#define RADEON_GUI_SCRATCH_REG0 0x15e0
-#define RADEON_GUI_SCRATCH_REG1 0x15e4
-#define RADEON_GUI_SCRATCH_REG2 0x15e8
-#define RADEON_GUI_SCRATCH_REG3 0x15ec
-#define RADEON_GUI_SCRATCH_REG4 0x15f0
-#define RADEON_GUI_SCRATCH_REG5 0x15f4
-
-#define RADEON_HEADER 0x0f0e /* PCI */
-#define RADEON_HOST_DATA0 0x17c0
-#define RADEON_HOST_DATA1 0x17c4
-#define RADEON_HOST_DATA2 0x17c8
-#define RADEON_HOST_DATA3 0x17cc
-#define RADEON_HOST_DATA4 0x17d0
-#define RADEON_HOST_DATA5 0x17d4
-#define RADEON_HOST_DATA6 0x17d8
-#define RADEON_HOST_DATA7 0x17dc
-#define RADEON_HOST_DATA_LAST 0x17e0
-#define RADEON_HOST_PATH_CNTL 0x0130
-# define RADEON_HDP_SOFT_RESET (1 << 26)
-#define RADEON_HTOTAL_CNTL 0x0009 /* PLL */
-#define RADEON_HTOTAL2_CNTL 0x002e /* PLL */
-
-#define RADEON_I2C_CNTL_1 0x0094 /* ? */
-#define RADEON_DVI_I2C_CNTL_1 0x02e4 /* ? */
-#define RADEON_INTERRUPT_LINE 0x0f3c /* PCI */
-#define RADEON_INTERRUPT_PIN 0x0f3d /* PCI */
-#define RADEON_IO_BASE 0x0f14 /* PCI */
-
-#define RADEON_LATENCY 0x0f0d /* PCI */
-#define RADEON_LEAD_BRES_DEC 0x1608
-#define RADEON_LEAD_BRES_LNTH 0x161c
-#define RADEON_LEAD_BRES_LNTH_SUB 0x1624
-#define RADEON_LVDS_GEN_CNTL 0x02d0
-# define RADEON_LVDS_ON (1 << 0)
-# define RADEON_LVDS_DISPLAY_DIS (1 << 1)
-# define RADEON_LVDS_PANEL_TYPE (1 << 2)
-# define RADEON_LVDS_PANEL_FORMAT (1 << 3)
-# define RADEON_LVDS_EN (1 << 7)
-# define RADEON_LVDS_DIGON (1 << 18)
-# define RADEON_LVDS_BLON (1 << 19)
-# define RADEON_LVDS_SEL_CRTC2 (1 << 23)
-#define RADEON_LVDS_PLL_CNTL 0x02d4
-# define RADEON_HSYNC_DELAY_SHIFT 28
-# define RADEON_HSYNC_DELAY_MASK (0xf << 28)
-
-#define RADEON_MAX_LATENCY 0x0f3f /* PCI */
-#define RADEON_MC_AGP_LOCATION 0x014c
-#define RADEON_MC_FB_LOCATION 0x0148
-#define RADEON_DISPLAY_BASE_ADDR 0x23c
-#define RADEON_DISPLAY2_BASE_ADDR 0x33c
-#define RADEON_OV0_BASE_ADDR 0x43c
-#define RADEON_NB_TOM 0x15c
-#define RADEON_MCLK_CNTL 0x0012 /* PLL */
-# define RADEON_FORCEON_MCLKA (1 << 16)
-# define RADEON_FORCEON_MCLKB (1 << 17)
-# define RADEON_FORCEON_YCLKA (1 << 18)
-# define RADEON_FORCEON_YCLKB (1 << 19)
-# define RADEON_FORCEON_MC (1 << 20)
-# define RADEON_FORCEON_AIC (1 << 21)
-#define RADEON_MDGPIO_A_REG 0x01ac
-#define RADEON_MDGPIO_EN_REG 0x01b0
-#define RADEON_MDGPIO_MASK 0x0198
-#define RADEON_MDGPIO_Y_REG 0x01b4
-#define RADEON_MEM_ADDR_CONFIG 0x0148
-#define RADEON_MEM_BASE 0x0f10 /* PCI */
-#define RADEON_MEM_CNTL 0x0140
-# define RADEON_MEM_NUM_CHANNELS_MASK 0x01
-# define RADEON_MEM_USE_B_CH_ONLY (1<<1)
-# define RV100_HALF_MODE (1<<3)
-# define R300_MEM_NUM_CHANNELS_MASK 0x03
-# define R300_MEM_USE_CD_CH_ONLY (1<<2)
-#define RADEON_MEM_TIMING_CNTL 0x0144 /* EXT_MEM_CNTL */
-#define RADEON_MEM_INIT_LAT_TIMER 0x0154
-#define RADEON_MEM_INTF_CNTL 0x014c
-#define RADEON_MEM_SDRAM_MODE_REG 0x0158
-#define RADEON_MEM_STR_CNTL 0x0150
-#define RADEON_MEM_VGA_RP_SEL 0x003c
-#define RADEON_MEM_VGA_WP_SEL 0x0038
-#define RADEON_MIN_GRANT 0x0f3e /* PCI */
-#define RADEON_MM_DATA 0x0004
-#define RADEON_MM_INDEX 0x0000
-#define RADEON_MPLL_CNTL 0x000e /* PLL */
-#define RADEON_MPP_TB_CONFIG 0x01c0 /* ? */
-#define RADEON_MPP_GP_CONFIG 0x01c8 /* ? */
-#define R300_MC_IND_INDEX 0x01f8
-# define R300_MC_IND_ADDR_MASK 0x3f
-#define R300_MC_IND_DATA 0x01fc
-#define R300_MC_READ_CNTL_AB 0x017c
-# define R300_MEM_RBS_POSITION_A_MASK 0x03
-#define R300_MC_READ_CNTL_CD_mcind 0x24
-# define R300_MEM_RBS_POSITION_C_MASK 0x03
-
-#define RADEON_N_VIF_COUNT 0x0248
-
-#define RADEON_OV0_AUTO_FLIP_CNTL 0x0470
-#define RADEON_OV0_COLOUR_CNTL 0x04E0
-#define RADEON_OV0_DEINTERLACE_PATTERN 0x0474
-#define RADEON_OV0_EXCLUSIVE_HORZ 0x0408
-# define RADEON_EXCL_HORZ_START_MASK 0x000000ff
-# define RADEON_EXCL_HORZ_END_MASK 0x0000ff00
-# define RADEON_EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000
-# define RADEON_EXCL_HORZ_EXCLUSIVE_EN 0x80000000
-#define RADEON_OV0_EXCLUSIVE_VERT 0x040C
-# define RADEON_EXCL_VERT_START_MASK 0x000003ff
-# define RADEON_EXCL_VERT_END_MASK 0x03ff0000
-#define RADEON_OV0_FILTER_CNTL 0x04A0
-#define RADEON_OV0_FOUR_TAP_COEF_0 0x04B0
-#define RADEON_OV0_FOUR_TAP_COEF_1 0x04B4
-#define RADEON_OV0_FOUR_TAP_COEF_2 0x04B8
-#define RADEON_OV0_FOUR_TAP_COEF_3 0x04BC
-#define RADEON_OV0_FOUR_TAP_COEF_4 0x04C0
-#define RADEON_OV0_GAMMA_000_00F 0x0d40
-#define RADEON_OV0_GAMMA_010_01F 0x0d44
-#define RADEON_OV0_GAMMA_020_03F 0x0d48
-#define RADEON_OV0_GAMMA_040_07F 0x0d4c
-#define RADEON_OV0_GAMMA_080_0BF 0x0e00
-#define RADEON_OV0_GAMMA_0C0_0FF 0x0e04
-#define RADEON_OV0_GAMMA_100_13F 0x0e08
-#define RADEON_OV0_GAMMA_140_17F 0x0e0c
-#define RADEON_OV0_GAMMA_180_1BF 0x0e10
-#define RADEON_OV0_GAMMA_1C0_1FF 0x0e14
-#define RADEON_OV0_GAMMA_200_23F 0x0e18
-#define RADEON_OV0_GAMMA_240_27F 0x0e1c
-#define RADEON_OV0_GAMMA_280_2BF 0x0e20
-#define RADEON_OV0_GAMMA_2C0_2FF 0x0e24
-#define RADEON_OV0_GAMMA_300_33F 0x0e28
-#define RADEON_OV0_GAMMA_340_37F 0x0e2c
-#define RADEON_OV0_GAMMA_380_3BF 0x0d50
-#define RADEON_OV0_GAMMA_3C0_3FF 0x0d54
-#define RADEON_OV0_GRAPHICS_KEY_CLR_LOW 0x04EC
-#define RADEON_OV0_GRAPHICS_KEY_CLR_HIGH 0x04F0
-#define RADEON_OV0_H_INC 0x0480
-#define RADEON_OV0_KEY_CNTL 0x04F4
-# define RADEON_VIDEO_KEY_FN_MASK 0x00000003L
-# define RADEON_VIDEO_KEY_FN_FALSE 0x00000000L
-# define RADEON_VIDEO_KEY_FN_TRUE 0x00000001L
-# define RADEON_VIDEO_KEY_FN_EQ 0x00000002L
-# define RADEON_VIDEO_KEY_FN_NE 0x00000003L
-# define RADEON_GRAPHIC_KEY_FN_MASK 0x00000030L
-# define RADEON_GRAPHIC_KEY_FN_FALSE 0x00000000L
-# define RADEON_GRAPHIC_KEY_FN_TRUE 0x00000010L
-# define RADEON_GRAPHIC_KEY_FN_EQ 0x00000020L
-# define RADEON_GRAPHIC_KEY_FN_NE 0x00000030L
-# define RADEON_CMP_MIX_MASK 0x00000100L
-# define RADEON_CMP_MIX_OR 0x00000000L
-# define RADEON_CMP_MIX_AND 0x00000100L
-#define RADEON_OV0_LIN_TRANS_A 0x0d20
-#define RADEON_OV0_LIN_TRANS_B 0x0d24
-#define RADEON_OV0_LIN_TRANS_C 0x0d28
-#define RADEON_OV0_LIN_TRANS_D 0x0d2c
-#define RADEON_OV0_LIN_TRANS_E 0x0d30
-#define RADEON_OV0_LIN_TRANS_F 0x0d34
-#define RADEON_OV0_P1_BLANK_LINES_AT_TOP 0x0430
-# define RADEON_P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL
-# define RADEON_P1_ACTIVE_LINES_M1 0x0fff0000L
-#define RADEON_OV0_P1_H_ACCUM_INIT 0x0488
-#define RADEON_OV0_P1_V_ACCUM_INIT 0x0428
-# define RADEON_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L
-# define RADEON_OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L
-#define RADEON_OV0_P1_X_START_END 0x0494
-#define RADEON_OV0_P2_X_START_END 0x0498
-#define RADEON_OV0_P23_BLANK_LINES_AT_TOP 0x0434
-# define RADEON_P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL
-# define RADEON_P23_ACTIVE_LINES_M1 0x07ff0000L
-#define RADEON_OV0_P23_H_ACCUM_INIT 0x048C
-#define RADEON_OV0_P23_V_ACCUM_INIT 0x042C
-#define RADEON_OV0_P3_X_START_END 0x049C
-#define RADEON_OV0_REG_LOAD_CNTL 0x0410
-# define RADEON_REG_LD_CTL_LOCK 0x00000001L
-# define RADEON_REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L
-# define RADEON_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L
-# define RADEON_REG_LD_CTL_LOCK_READBACK 0x00000008L
-#define RADEON_OV0_SCALE_CNTL 0x0420
-# define RADEON_SCALER_HORZ_PICK_NEAREST 0x00000004L
-# define RADEON_SCALER_VERT_PICK_NEAREST 0x00000008L
-# define RADEON_SCALER_SIGNED_UV 0x00000010L
-# define RADEON_SCALER_GAMMA_SEL_MASK 0x00000060L
-# define RADEON_SCALER_GAMMA_SEL_BRIGHT 0x00000000L
-# define RADEON_SCALER_GAMMA_SEL_G22 0x00000020L
-# define RADEON_SCALER_GAMMA_SEL_G18 0x00000040L
-# define RADEON_SCALER_GAMMA_SEL_G14 0x00000060L
-# define RADEON_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L
-# define RADEON_SCALER_SURFAC_FORMAT 0x00000f00L
-# define RADEON_SCALER_SOURCE_15BPP 0x00000300L
-# define RADEON_SCALER_SOURCE_16BPP 0x00000400L
-# define RADEON_SCALER_SOURCE_32BPP 0x00000600L
-# define RADEON_SCALER_SOURCE_YUV9 0x00000900L
-# define RADEON_SCALER_SOURCE_YUV12 0x00000A00L
-# define RADEON_SCALER_SOURCE_VYUY422 0x00000B00L
-# define RADEON_SCALER_SOURCE_YVYU422 0x00000C00L
-# define RADEON_SCALER_ADAPTIVE_DEINT 0x00001000L
-# define RADEON_SCALER_TEMPORAL_DEINT 0x00002000L
-# define RADEON_SCALER_SMART_SWITCH 0x00008000L
-# define RADEON_SCALER_BURST_PER_PLANE 0x007F0000L
-# define RADEON_SCALER_DOUBLE_BUFFER 0x01000000L
-# define RADEON_SCALER_DIS_LIMIT 0x08000000L
-# define RADEON_SCALER_INT_EMU 0x20000000L
-# define RADEON_SCALER_ENABLE 0x40000000L
-# define RADEON_SCALER_SOFT_RESET 0x80000000L
-# define RADEON_SCALER_ADAPTIVE_DEINT 0x00001000L
-#define RADEON_OV0_STEP_BY 0x0484
-#define RADEON_OV0_TEST 0x04F8
-#define RADEON_OV0_V_INC 0x0424
-#define RADEON_OV0_VID_BUF_PITCH0_VALUE 0x0460
-#define RADEON_OV0_VID_BUF_PITCH1_VALUE 0x0464
-#define RADEON_OV0_VID_BUF0_BASE_ADRS 0x0440
-# define RADEON_VIF_BUF0_PITCH_SEL 0x00000001L
-# define RADEON_VIF_BUF0_TILE_ADRS 0x00000002L
-# define RADEON_VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L
-# define RADEON_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L
-#define RADEON_OV0_VID_BUF1_BASE_ADRS 0x0444
-# define RADEON_VIF_BUF1_PITCH_SEL 0x00000001L
-# define RADEON_VIF_BUF1_TILE_ADRS 0x00000002L
-# define RADEON_VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L
-# define RADEON_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L
-#define RADEON_OV0_VID_BUF2_BASE_ADRS 0x0448
-# define RADEON_VIF_BUF2_PITCH_SEL 0x00000001L
-# define RADEON_VIF_BUF2_TILE_ADRS 0x00000002L
-# define RADEON_VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L
-# define RADEON_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L
-#define RADEON_OV0_VID_BUF3_BASE_ADRS 0x044C
-#define RADEON_OV0_VID_BUF4_BASE_ADRS 0x0450
-#define RADEON_OV0_VID_BUF5_BASE_ADRS 0x0454
-#define RADEON_OV0_VIDEO_KEY_CLR_HIGH 0x04E8
-#define RADEON_OV0_VIDEO_KEY_CLR_LOW 0x04E4
-#define RADEON_OV0_Y_X_START 0x0400
-#define RADEON_OV0_Y_X_END 0x0404
-#define RADEON_OV1_Y_X_START 0x0600
-#define RADEON_OV1_Y_X_END 0x0604
-#define RADEON_OVR_CLR 0x0230
-#define RADEON_OVR_WID_LEFT_RIGHT 0x0234
-#define RADEON_OVR_WID_TOP_BOTTOM 0x0238
-
-#define RADEON_P2PLL_CNTL 0x002a /* P2PLL */
-# define RADEON_P2PLL_RESET (1 << 0)
-# define RADEON_P2PLL_SLEEP (1 << 1)
-# define RADEON_P2PLL_ATOMIC_UPDATE_EN (1 << 16)
-# define RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17)
-# define RADEON_P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18)
-#define RADEON_P2PLL_DIV_0 0x002c
-# define RADEON_P2PLL_FB0_DIV_MASK 0x07ff
-# define RADEON_P2PLL_POST0_DIV_MASK 0x00070000
-#define RADEON_P2PLL_REF_DIV 0x002B /* PLL */
-# define RADEON_P2PLL_REF_DIV_MASK 0x03ff
-# define RADEON_P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */
-# define RADEON_P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */
-# define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18)
-# define R300_PPLL_REF_DIV_ACC_SHIFT 18
-#define RADEON_PALETTE_DATA 0x00b4
-#define RADEON_PALETTE_30_DATA 0x00b8
-#define RADEON_PALETTE_INDEX 0x00b0
-#define RADEON_PCI_GART_PAGE 0x017c
-#define RADEON_PIXCLKS_CNTL 0x002d
-# define RADEON_PIX2CLK_SRC_SEL_MASK 0x03
-# define RADEON_PIX2CLK_SRC_SEL_CPUCLK 0x00
-# define RADEON_PIX2CLK_SRC_SEL_PSCANCLK 0x01
-# define RADEON_PIX2CLK_SRC_SEL_BYTECLK 0x02
-# define RADEON_PIX2CLK_SRC_SEL_P2PLLCLK 0x03
-# define RADEON_PIX2CLK_ALWAYS_ONb (1<<6)
-# define RADEON_PIX2CLK_DAC_ALWAYS_ONb (1<<7)
-# define RADEON_PIXCLK_TV_SRC_SEL (1 << 8)
-# define RADEON_PIXCLK_LVDS_ALWAYS_ONb (1 << 14)
-# define RADEON_PIXCLK_TMDS_ALWAYS_ONb (1 << 15)
-#define RADEON_PLANE_3D_MASK_C 0x1d44
-#define RADEON_PLL_TEST_CNTL 0x0013 /* PLL */
-#define RADEON_PMI_CAP_ID 0x0f5c /* PCI */
-#define RADEON_PMI_DATA 0x0f63 /* PCI */
-#define RADEON_PMI_NXT_CAP_PTR 0x0f5d /* PCI */
-#define RADEON_PMI_PMC_REG 0x0f5e /* PCI */
-#define RADEON_PMI_PMCSR_REG 0x0f60 /* PCI */
-#define RADEON_PMI_REGISTER 0x0f5c /* PCI */
-#define RADEON_PPLL_CNTL 0x0002 /* PLL */
-# define RADEON_PPLL_RESET (1 << 0)
-# define RADEON_PPLL_SLEEP (1 << 1)
-# define RADEON_PPLL_ATOMIC_UPDATE_EN (1 << 16)
-# define RADEON_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17)
-# define RADEON_PPLL_ATOMIC_UPDATE_VSYNC (1 << 18)
-#define RADEON_PPLL_DIV_0 0x0004 /* PLL */
-#define RADEON_PPLL_DIV_1 0x0005 /* PLL */
-#define RADEON_PPLL_DIV_2 0x0006 /* PLL */
-#define RADEON_PPLL_DIV_3 0x0007 /* PLL */
-# define RADEON_PPLL_FB3_DIV_MASK 0x07ff
-# define RADEON_PPLL_POST3_DIV_MASK 0x00070000
-#define RADEON_PPLL_REF_DIV 0x0003 /* PLL */
-# define RADEON_PPLL_REF_DIV_MASK 0x03ff
-# define RADEON_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */
-# define RADEON_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */
-#define RADEON_PWR_MNGMT_CNTL_STATUS 0x0f60 /* PCI */
-
-#define RADEON_RBBM_GUICNTL 0x172c
-# define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
-# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
-# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
-# define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
-#define RADEON_RBBM_SOFT_RESET 0x00f0
-# define RADEON_SOFT_RESET_CP (1 << 0)
-# define RADEON_SOFT_RESET_HI (1 << 1)
-# define RADEON_SOFT_RESET_SE (1 << 2)
-# define RADEON_SOFT_RESET_RE (1 << 3)
-# define RADEON_SOFT_RESET_PP (1 << 4)
-# define RADEON_SOFT_RESET_E2 (1 << 5)
-# define RADEON_SOFT_RESET_RB (1 << 6)
-# define RADEON_SOFT_RESET_HDP (1 << 7)
-#define RADEON_RBBM_STATUS 0x0e40
-# define RADEON_RBBM_FIFOCNT_MASK 0x007f
-# define RADEON_RBBM_ACTIVE (1 << 31)
-#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
-# define RADEON_RB2D_DC_FLUSH (3 << 0)
-# define RADEON_RB2D_DC_FREE (3 << 2)
-# define RADEON_RB2D_DC_FLUSH_ALL 0xf
-# define RADEON_RB2D_DC_BUSY (1 << 31)
-#define RADEON_RB2D_DSTCACHE_MODE 0x3428
-#define RADEON_REG_BASE 0x0f18 /* PCI */
-#define RADEON_REGPROG_INF 0x0f09 /* PCI */
-#define RADEON_REVISION_ID 0x0f08 /* PCI */
-
-#define RADEON_SC_BOTTOM 0x164c
-#define RADEON_SC_BOTTOM_RIGHT 0x16f0
-#define RADEON_SC_BOTTOM_RIGHT_C 0x1c8c
-#define RADEON_SC_LEFT 0x1640
-#define RADEON_SC_RIGHT 0x1644
-#define RADEON_SC_TOP 0x1648
-#define RADEON_SC_TOP_LEFT 0x16ec
-#define RADEON_SC_TOP_LEFT_C 0x1c88
-# define RADEON_SC_SIGN_MASK_LO 0x8000
-# define RADEON_SC_SIGN_MASK_HI 0x80000000
-#define RADEON_SCLK_CNTL 0x000d /* PLL */
-# define RADEON_DYN_STOP_LAT_MASK 0x00007ff8
-# define RADEON_CP_MAX_DYN_STOP_LAT 0x0008
-# define RADEON_SCLK_FORCEON_MASK 0xffff8000
-#define RADEON_SCLK_MORE_CNTL 0x0035 /* PLL */
-# define RADEON_SCLK_MORE_FORCEON 0x0700
-#define RADEON_SDRAM_MODE_REG 0x0158
-#define RADEON_SEQ8_DATA 0x03c5 /* VGA */
-#define RADEON_SEQ8_IDX 0x03c4 /* VGA */
-#define RADEON_SNAPSHOT_F_COUNT 0x0244
-#define RADEON_SNAPSHOT_VH_COUNTS 0x0240
-#define RADEON_SNAPSHOT_VIF_COUNT 0x024c
-#define RADEON_SRC_OFFSET 0x15ac
-#define RADEON_SRC_PITCH 0x15b0
-#define RADEON_SRC_PITCH_OFFSET 0x1428
-#define RADEON_SRC_SC_BOTTOM 0x165c
-#define RADEON_SRC_SC_BOTTOM_RIGHT 0x16f4
-#define RADEON_SRC_SC_RIGHT 0x1654
-#define RADEON_SRC_X 0x1414
-#define RADEON_SRC_X_Y 0x1590
-#define RADEON_SRC_Y 0x1418
-#define RADEON_SRC_Y_X 0x1434
-#define RADEON_STATUS 0x0f06 /* PCI */
-#define RADEON_SUBPIC_CNTL 0x0540 /* ? */
-#define RADEON_SUB_CLASS 0x0f0a /* PCI */
-#define RADEON_SURFACE_CNTL 0x0b00
-# define RADEON_SURF_TRANSLATION_DIS (1 << 8)
-# define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20)
-# define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21)
-#define RADEON_SURFACE0_INFO 0x0b0c
-# define RADEON_SURF_TILE_COLOR_MACRO (0 << 16)
-# define RADEON_SURF_TILE_COLOR_BOTH (1 << 16)
-# define RADEON_SURF_TILE_DEPTH_32BPP (2 << 16)
-# define RADEON_SURF_TILE_DEPTH_16BPP (3 << 16)
-# define R200_SURF_TILE_NONE (0 << 16)
-# define R200_SURF_TILE_COLOR_MACRO (1 << 16)
-# define R200_SURF_TILE_COLOR_MICRO (2 << 16)
-# define R200_SURF_TILE_COLOR_BOTH (3 << 16)
-# define R200_SURF_TILE_DEPTH_32BPP (4 << 16)
-# define R200_SURF_TILE_DEPTH_16BPP (5 << 16)
-# define RADEON_SURF_AP0_SWP_16BPP (1 << 20)
-# define RADEON_SURF_AP0_SWP_32BPP (1 << 21)
-# define RADEON_SURF_AP1_SWP_16BPP (1 << 22)
-# define RADEON_SURF_AP1_SWP_32BPP (1 << 23)
-#define RADEON_SURFACE0_LOWER_BOUND 0x0b04
-#define RADEON_SURFACE0_UPPER_BOUND 0x0b08
-#define RADEON_SURFACE1_INFO 0x0b1c
-#define RADEON_SURFACE1_LOWER_BOUND 0x0b14
-#define RADEON_SURFACE1_UPPER_BOUND 0x0b18
-#define RADEON_SURFACE2_INFO 0x0b2c
-#define RADEON_SURFACE2_LOWER_BOUND 0x0b24
-#define RADEON_SURFACE2_UPPER_BOUND 0x0b28
-#define RADEON_SURFACE3_INFO 0x0b3c
-#define RADEON_SURFACE3_LOWER_BOUND 0x0b34
-#define RADEON_SURFACE3_UPPER_BOUND 0x0b38
-#define RADEON_SURFACE4_INFO 0x0b4c
-#define RADEON_SURFACE4_LOWER_BOUND 0x0b44
-#define RADEON_SURFACE4_UPPER_BOUND 0x0b48
-#define RADEON_SURFACE5_INFO 0x0b5c
-#define RADEON_SURFACE5_LOWER_BOUND 0x0b54
-#define RADEON_SURFACE5_UPPER_BOUND 0x0b58
-#define RADEON_SURFACE6_INFO 0x0b6c
-#define RADEON_SURFACE6_LOWER_BOUND 0x0b64
-#define RADEON_SURFACE6_UPPER_BOUND 0x0b68
-#define RADEON_SURFACE7_INFO 0x0b7c
-#define RADEON_SURFACE7_LOWER_BOUND 0x0b74
-#define RADEON_SURFACE7_UPPER_BOUND 0x0b78
-#define RADEON_SW_SEMAPHORE 0x013c
-
-#define RADEON_TEST_DEBUG_CNTL 0x0120
-#define RADEON_TEST_DEBUG_MUX 0x0124
-#define RADEON_TEST_DEBUG_OUT 0x012c
-#define RADEON_TMDS_PLL_CNTL 0x02a8
-#define RADEON_TMDS_TRANSMITTER_CNTL 0x02a4
-# define RADEON_TMDS_TRANSMITTER_PLLEN 1
-# define RADEON_TMDS_TRANSMITTER_PLLRST 2
-#define RADEON_TRAIL_BRES_DEC 0x1614
-#define RADEON_TRAIL_BRES_ERR 0x160c
-#define RADEON_TRAIL_BRES_INC 0x1610
-#define RADEON_TRAIL_X 0x1618
-#define RADEON_TRAIL_X_SUB 0x1620
-
-#define RADEON_VCLK_ECP_CNTL 0x0008 /* PLL */
-# define RADEON_VCLK_SRC_SEL_MASK 0x03
-# define RADEON_VCLK_SRC_SEL_CPUCLK 0x00
-# define RADEON_VCLK_SRC_SEL_PSCANCLK 0x01
-# define RADEON_VCLK_SRC_SEL_BYTECLK 0x02
-# define RADEON_VCLK_SRC_SEL_PPLLCLK 0x03
-# define RADEON_PIXCLK_ALWAYS_ONb (1<<6)
-# define RADEON_PIXCLK_DAC_ALWAYS_ONb (1<<7)
-
-#define RADEON_VENDOR_ID 0x0f00 /* PCI */
-#define RADEON_VGA_DDA_CONFIG 0x02e8
-#define RADEON_VGA_DDA_ON_OFF 0x02ec
-#define RADEON_VID_BUFFER_CONTROL 0x0900
-#define RADEON_VIDEOMUX_CNTL 0x0190
-#define RADEON_VIPH_CONTROL 0x0c40 /* ? */
-
-#define RADEON_WAIT_UNTIL 0x1720
-# define RADEON_WAIT_CRTC_PFLIP (1 << 0)
-# define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
-# define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
-# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
-
-#define RADEON_X_MPLL_REF_FB_DIV 0x000a /* PLL */
-#define RADEON_XCLK_CNTL 0x000d /* PLL */
-#define RADEON_XDLL_CNTL 0x000c /* PLL */
-#define RADEON_XPLL_CNTL 0x000b /* PLL */
-
-
-
- /* Registers for 3D/TCL */
-#define RADEON_PP_BORDER_COLOR_0 0x1d40
-#define RADEON_PP_BORDER_COLOR_1 0x1d44
-#define RADEON_PP_BORDER_COLOR_2 0x1d48
-#define RADEON_PP_CNTL 0x1c38
-# define RADEON_STIPPLE_ENABLE (1 << 0)
-# define RADEON_SCISSOR_ENABLE (1 << 1)
-# define RADEON_PATTERN_ENABLE (1 << 2)
-# define RADEON_SHADOW_ENABLE (1 << 3)
-# define RADEON_TEX_ENABLE_MASK (0xf << 4)
-# define RADEON_TEX_0_ENABLE (1 << 4)
-# define RADEON_TEX_1_ENABLE (1 << 5)
-# define RADEON_TEX_2_ENABLE (1 << 6)
-# define RADEON_TEX_3_ENABLE (1 << 7)
-# define RADEON_TEX_BLEND_ENABLE_MASK (0xf << 12)
-# define RADEON_TEX_BLEND_0_ENABLE (1 << 12)
-# define RADEON_TEX_BLEND_1_ENABLE (1 << 13)
-# define RADEON_TEX_BLEND_2_ENABLE (1 << 14)
-# define RADEON_TEX_BLEND_3_ENABLE (1 << 15)
-# define RADEON_PLANAR_YUV_ENABLE (1 << 20)
-# define RADEON_SPECULAR_ENABLE (1 << 21)
-# define RADEON_FOG_ENABLE (1 << 22)
-# define RADEON_ALPHA_TEST_ENABLE (1 << 23)
-# define RADEON_ANTI_ALIAS_NONE (0 << 24)
-# define RADEON_ANTI_ALIAS_LINE (1 << 24)
-# define RADEON_ANTI_ALIAS_POLY (2 << 24)
-# define RADEON_ANTI_ALIAS_LINE_POLY (3 << 24)
-# define RADEON_BUMP_MAP_ENABLE (1 << 26)
-# define RADEON_BUMPED_MAP_T0 (0 << 27)
-# define RADEON_BUMPED_MAP_T1 (1 << 27)
-# define RADEON_BUMPED_MAP_T2 (2 << 27)
-# define RADEON_TEX_3D_ENABLE_0 (1 << 29)
-# define RADEON_TEX_3D_ENABLE_1 (1 << 30)
-# define RADEON_MC_ENABLE (1 << 31)
-#define RADEON_PP_FOG_COLOR 0x1c18
-# define RADEON_FOG_COLOR_MASK 0x00ffffff
-# define RADEON_FOG_VERTEX (0 << 24)
-# define RADEON_FOG_TABLE (1 << 24)
-# define RADEON_FOG_USE_DEPTH (0 << 25)
-# define RADEON_FOG_USE_DIFFUSE_ALPHA (2 << 25)
-# define RADEON_FOG_USE_SPEC_ALPHA (3 << 25)
-#define RADEON_PP_LUM_MATRIX 0x1d00
-#define RADEON_PP_MISC 0x1c14
-# define RADEON_REF_ALPHA_MASK 0x000000ff
-# define RADEON_ALPHA_TEST_FAIL (0 << 8)
-# define RADEON_ALPHA_TEST_LESS (1 << 8)
-# define RADEON_ALPHA_TEST_LEQUAL (2 << 8)
-# define RADEON_ALPHA_TEST_EQUAL (3 << 8)
-# define RADEON_ALPHA_TEST_GEQUAL (4 << 8)
-# define RADEON_ALPHA_TEST_GREATER (5 << 8)
-# define RADEON_ALPHA_TEST_NEQUAL (6 << 8)
-# define RADEON_ALPHA_TEST_PASS (7 << 8)
-# define RADEON_ALPHA_TEST_OP_MASK (7 << 8)
-# define RADEON_CHROMA_FUNC_FAIL (0 << 16)
-# define RADEON_CHROMA_FUNC_PASS (1 << 16)
-# define RADEON_CHROMA_FUNC_NEQUAL (2 << 16)
-# define RADEON_CHROMA_FUNC_EQUAL (3 << 16)
-# define RADEON_CHROMA_KEY_NEAREST (0 << 18)
-# define RADEON_CHROMA_KEY_ZERO (1 << 18)
-# define RADEON_SHADOW_ID_AUTO_INC (1 << 20)
-# define RADEON_SHADOW_FUNC_EQUAL (0 << 21)
-# define RADEON_SHADOW_FUNC_NEQUAL (1 << 21)
-# define RADEON_SHADOW_PASS_1 (0 << 22)
-# define RADEON_SHADOW_PASS_2 (1 << 22)
-# define RADEON_RIGHT_HAND_CUBE_D3D (0 << 24)
-# define RADEON_RIGHT_HAND_CUBE_OGL (1 << 24)
-#define RADEON_PP_ROT_MATRIX_0 0x1d58
-#define RADEON_PP_ROT_MATRIX_1 0x1d5c
-#define RADEON_PP_TXFILTER_0 0x1c54
-#define RADEON_PP_TXFILTER_1 0x1c6c
-#define RADEON_PP_TXFILTER_2 0x1c84
-# define RADEON_MAG_FILTER_NEAREST (0 << 0)
-# define RADEON_MAG_FILTER_LINEAR (1 << 0)
-# define RADEON_MAG_FILTER_MASK (1 << 0)
-# define RADEON_MIN_FILTER_NEAREST (0 << 1)
-# define RADEON_MIN_FILTER_LINEAR (1 << 1)
-# define RADEON_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1)
-# define RADEON_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1)
-# define RADEON_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1)
-# define RADEON_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1)
-# define RADEON_MIN_FILTER_ANISO_NEAREST (8 << 1)
-# define RADEON_MIN_FILTER_ANISO_LINEAR (9 << 1)
-# define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1)
-# define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1)
-# define RADEON_MIN_FILTER_MASK (15 << 1)
-# define RADEON_MAX_ANISO_1_TO_1 (0 << 5)
-# define RADEON_MAX_ANISO_2_TO_1 (1 << 5)
-# define RADEON_MAX_ANISO_4_TO_1 (2 << 5)
-# define RADEON_MAX_ANISO_8_TO_1 (3 << 5)
-# define RADEON_MAX_ANISO_16_TO_1 (4 << 5)
-# define RADEON_MAX_ANISO_MASK (7 << 5)
-# define RADEON_LOD_BIAS_MASK (0xff << 8)
-# define RADEON_LOD_BIAS_SHIFT 8
-# define RADEON_MAX_MIP_LEVEL_MASK (0x0f << 16)
-# define RADEON_MAX_MIP_LEVEL_SHIFT 16
-# define RADEON_YUV_TO_RGB (1 << 20)
-# define RADEON_YUV_TEMPERATURE_COOL (0 << 21)
-# define RADEON_YUV_TEMPERATURE_HOT (1 << 21)
-# define RADEON_YUV_TEMPERATURE_MASK (1 << 21)
-# define RADEON_WRAPEN_S (1 << 22)
-# define RADEON_CLAMP_S_WRAP (0 << 23)
-# define RADEON_CLAMP_S_MIRROR (1 << 23)
-# define RADEON_CLAMP_S_CLAMP_LAST (2 << 23)
-# define RADEON_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23)
-# define RADEON_CLAMP_S_CLAMP_BORDER (4 << 23)
-# define RADEON_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23)
-# define RADEON_CLAMP_S_CLAMP_GL (6 << 23)
-# define RADEON_CLAMP_S_MIRROR_CLAMP_GL (7 << 23)
-# define RADEON_CLAMP_S_MASK (7 << 23)
-# define RADEON_WRAPEN_T (1 << 26)
-# define RADEON_CLAMP_T_WRAP (0 << 27)
-# define RADEON_CLAMP_T_MIRROR (1 << 27)
-# define RADEON_CLAMP_T_CLAMP_LAST (2 << 27)
-# define RADEON_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27)
-# define RADEON_CLAMP_T_CLAMP_BORDER (4 << 27)
-# define RADEON_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27)
-# define RADEON_CLAMP_T_CLAMP_GL (6 << 27)
-# define RADEON_CLAMP_T_MIRROR_CLAMP_GL (7 << 27)
-# define RADEON_CLAMP_T_MASK (7 << 27)
-# define RADEON_BORDER_MODE_OGL (0 << 31)
-# define RADEON_BORDER_MODE_D3D (1 << 31)
-#define RADEON_PP_TXFORMAT_0 0x1c58
-#define RADEON_PP_TXFORMAT_1 0x1c70
-#define RADEON_PP_TXFORMAT_2 0x1c88
-# define RADEON_TXFORMAT_I8 (0 << 0)
-# define RADEON_TXFORMAT_AI88 (1 << 0)
-# define RADEON_TXFORMAT_RGB332 (2 << 0)
-# define RADEON_TXFORMAT_ARGB1555 (3 << 0)
-# define RADEON_TXFORMAT_RGB565 (4 << 0)
-# define RADEON_TXFORMAT_ARGB4444 (5 << 0)
-# define RADEON_TXFORMAT_ARGB8888 (6 << 0)
-# define RADEON_TXFORMAT_RGBA8888 (7 << 0)
-# define RADEON_TXFORMAT_Y8 (8 << 0)
-# define RADEON_TXFORMAT_VYUY422 (10 << 0)
-# define RADEON_TXFORMAT_YVYU422 (11 << 0)
-# define RADEON_TXFORMAT_DXT1 (12 << 0)
-# define RADEON_TXFORMAT_DXT23 (14 << 0)
-# define RADEON_TXFORMAT_DXT45 (15 << 0)
-# define RADEON_TXFORMAT_SHADOW16 (16 << 0)
-# define RADEON_TXFORMAT_SHADOW32 (17 << 0)
-# define RADEON_TXFORMAT_DUDV88 (18 << 0)
-# define RADEON_TXFORMAT_LDUDV655 (19 << 0)
-# define RADEON_TXFORMAT_LDUDUV8888 (20 << 0)
-# define RADEON_TXFORMAT_FORMAT_MASK (31 << 0)
-# define RADEON_TXFORMAT_FORMAT_SHIFT 0
-# define RADEON_TXFORMAT_APPLE_YUV_MODE (1 << 5)
-# define RADEON_TXFORMAT_ALPHA_IN_MAP (1 << 6)
-# define RADEON_TXFORMAT_NON_POWER2 (1 << 7)
-# define RADEON_TXFORMAT_WIDTH_MASK (15 << 8)
-# define RADEON_TXFORMAT_WIDTH_SHIFT 8
-# define RADEON_TXFORMAT_HEIGHT_MASK (15 << 12)
-# define RADEON_TXFORMAT_HEIGHT_SHIFT 12
-# define RADEON_TXFORMAT_F5_WIDTH_MASK (15 << 16)
-# define RADEON_TXFORMAT_F5_WIDTH_SHIFT 16
-# define RADEON_TXFORMAT_F5_HEIGHT_MASK (15 << 20)
-# define RADEON_TXFORMAT_F5_HEIGHT_SHIFT 20
-# define RADEON_TXFORMAT_ST_ROUTE_STQ0 (0 << 24)
-# define RADEON_TXFORMAT_ST_ROUTE_MASK (3 << 24)
-# define RADEON_TXFORMAT_ST_ROUTE_STQ1 (1 << 24)
-# define RADEON_TXFORMAT_ST_ROUTE_STQ2 (2 << 24)
-# define RADEON_TXFORMAT_ENDIAN_NO_SWAP (0 << 26)
-# define RADEON_TXFORMAT_ENDIAN_16BPP_SWAP (1 << 26)
-# define RADEON_TXFORMAT_ENDIAN_32BPP_SWAP (2 << 26)
-# define RADEON_TXFORMAT_ENDIAN_HALFDW_SWAP (3 << 26)
-# define RADEON_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28)
-# define RADEON_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29)
-# define RADEON_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30)
-# define RADEON_TXFORMAT_PERSPECTIVE_ENABLE (1 << 31)
-#define RADEON_PP_CUBIC_FACES_0 0x1d24
-#define RADEON_PP_CUBIC_FACES_1 0x1d28
-#define RADEON_PP_CUBIC_FACES_2 0x1d2c
-# define RADEON_FACE_WIDTH_1_SHIFT 0
-# define RADEON_FACE_HEIGHT_1_SHIFT 4
-# define RADEON_FACE_WIDTH_1_MASK (0xf << 0)
-# define RADEON_FACE_HEIGHT_1_MASK (0xf << 4)
-# define RADEON_FACE_WIDTH_2_SHIFT 8
-# define RADEON_FACE_HEIGHT_2_SHIFT 12
-# define RADEON_FACE_WIDTH_2_MASK (0xf << 8)
-# define RADEON_FACE_HEIGHT_2_MASK (0xf << 12)
-# define RADEON_FACE_WIDTH_3_SHIFT 16
-# define RADEON_FACE_HEIGHT_3_SHIFT 20
-# define RADEON_FACE_WIDTH_3_MASK (0xf << 16)
-# define RADEON_FACE_HEIGHT_3_MASK (0xf << 20)
-# define RADEON_FACE_WIDTH_4_SHIFT 24
-# define RADEON_FACE_HEIGHT_4_SHIFT 28
-# define RADEON_FACE_WIDTH_4_MASK (0xf << 24)
-# define RADEON_FACE_HEIGHT_4_MASK (0xf << 28)
-
-#define RADEON_PP_TXOFFSET_0 0x1c5c
-#define RADEON_PP_TXOFFSET_1 0x1c74
-#define RADEON_PP_TXOFFSET_2 0x1c8c
-# define RADEON_TXO_ENDIAN_NO_SWAP (0 << 0)
-# define RADEON_TXO_ENDIAN_BYTE_SWAP (1 << 0)
-# define RADEON_TXO_ENDIAN_WORD_SWAP (2 << 0)
-# define RADEON_TXO_ENDIAN_HALFDW_SWAP (3 << 0)
-# define RADEON_TXO_MACRO_LINEAR (0 << 2)
-# define RADEON_TXO_MACRO_TILE (1 << 2)
-# define RADEON_TXO_MICRO_LINEAR (0 << 3)
-# define RADEON_TXO_MICRO_TILE_X2 (1 << 3)
-# define RADEON_TXO_MICRO_TILE_OPT (2 << 3)
-# define RADEON_TXO_OFFSET_MASK 0xffffffe0
-# define RADEON_TXO_OFFSET_SHIFT 5
-
-#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
-#define RADEON_PP_CUBIC_OFFSET_T0_1 0x1dd4
-#define RADEON_PP_CUBIC_OFFSET_T0_2 0x1dd8
-#define RADEON_PP_CUBIC_OFFSET_T0_3 0x1ddc
-#define RADEON_PP_CUBIC_OFFSET_T0_4 0x1de0
-#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
-#define RADEON_PP_CUBIC_OFFSET_T1_1 0x1e04
-#define RADEON_PP_CUBIC_OFFSET_T1_2 0x1e08
-#define RADEON_PP_CUBIC_OFFSET_T1_3 0x1e0c
-#define RADEON_PP_CUBIC_OFFSET_T1_4 0x1e10
-#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
-#define RADEON_PP_CUBIC_OFFSET_T2_1 0x1e18
-#define RADEON_PP_CUBIC_OFFSET_T2_2 0x1e1c
-#define RADEON_PP_CUBIC_OFFSET_T2_3 0x1e20
-#define RADEON_PP_CUBIC_OFFSET_T2_4 0x1e24
-
-#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
-#define RADEON_PP_TEX_SIZE_1 0x1d0c
-#define RADEON_PP_TEX_SIZE_2 0x1d14
-# define RADEON_TEX_USIZE_MASK (0x7ff << 0)
-# define RADEON_TEX_USIZE_SHIFT 0
-# define RADEON_TEX_VSIZE_MASK (0x7ff << 16)
-# define RADEON_TEX_VSIZE_SHIFT 16
-# define RADEON_SIGNED_RGB_MASK (1 << 30)
-# define RADEON_SIGNED_RGB_SHIFT 30
-# define RADEON_SIGNED_ALPHA_MASK (1 << 31)
-# define RADEON_SIGNED_ALPHA_SHIFT 31
-#define RADEON_PP_TEX_PITCH_0 0x1d08 /* NPOT */
-#define RADEON_PP_TEX_PITCH_1 0x1d10 /* NPOT */
-#define RADEON_PP_TEX_PITCH_2 0x1d18 /* NPOT */
-/* note: bits 13-5: 32 byte aligned stride of texture map */
-
-#define RADEON_PP_TXCBLEND_0 0x1c60
-#define RADEON_PP_TXCBLEND_1 0x1c78
-#define RADEON_PP_TXCBLEND_2 0x1c90
-# define RADEON_COLOR_ARG_A_SHIFT 0
-# define RADEON_COLOR_ARG_A_MASK (0x1f << 0)
-# define RADEON_COLOR_ARG_A_ZERO (0 << 0)
-# define RADEON_COLOR_ARG_A_CURRENT_COLOR (2 << 0)
-# define RADEON_COLOR_ARG_A_CURRENT_ALPHA (3 << 0)
-# define RADEON_COLOR_ARG_A_DIFFUSE_COLOR (4 << 0)
-# define RADEON_COLOR_ARG_A_DIFFUSE_ALPHA (5 << 0)
-# define RADEON_COLOR_ARG_A_SPECULAR_COLOR (6 << 0)
-# define RADEON_COLOR_ARG_A_SPECULAR_ALPHA (7 << 0)
-# define RADEON_COLOR_ARG_A_TFACTOR_COLOR (8 << 0)
-# define RADEON_COLOR_ARG_A_TFACTOR_ALPHA (9 << 0)
-# define RADEON_COLOR_ARG_A_T0_COLOR (10 << 0)
-# define RADEON_COLOR_ARG_A_T0_ALPHA (11 << 0)
-# define RADEON_COLOR_ARG_A_T1_COLOR (12 << 0)
-# define RADEON_COLOR_ARG_A_T1_ALPHA (13 << 0)
-# define RADEON_COLOR_ARG_A_T2_COLOR (14 << 0)
-# define RADEON_COLOR_ARG_A_T2_ALPHA (15 << 0)
-# define RADEON_COLOR_ARG_A_T3_COLOR (16 << 0)
-# define RADEON_COLOR_ARG_A_T3_ALPHA (17 << 0)
-# define RADEON_COLOR_ARG_B_SHIFT 5
-# define RADEON_COLOR_ARG_B_MASK (0x1f << 5)
-# define RADEON_COLOR_ARG_B_ZERO (0 << 5)
-# define RADEON_COLOR_ARG_B_CURRENT_COLOR (2 << 5)
-# define RADEON_COLOR_ARG_B_CURRENT_ALPHA (3 << 5)
-# define RADEON_COLOR_ARG_B_DIFFUSE_COLOR (4 << 5)
-# define RADEON_COLOR_ARG_B_DIFFUSE_ALPHA (5 << 5)
-# define RADEON_COLOR_ARG_B_SPECULAR_COLOR (6 << 5)
-# define RADEON_COLOR_ARG_B_SPECULAR_ALPHA (7 << 5)
-# define RADEON_COLOR_ARG_B_TFACTOR_COLOR (8 << 5)
-# define RADEON_COLOR_ARG_B_TFACTOR_ALPHA (9 << 5)
-# define RADEON_COLOR_ARG_B_T0_COLOR (10 << 5)
-# define RADEON_COLOR_ARG_B_T0_ALPHA (11 << 5)
-# define RADEON_COLOR_ARG_B_T1_COLOR (12 << 5)
-# define RADEON_COLOR_ARG_B_T1_ALPHA (13 << 5)
-# define RADEON_COLOR_ARG_B_T2_COLOR (14 << 5)
-# define RADEON_COLOR_ARG_B_T2_ALPHA (15 << 5)
-# define RADEON_COLOR_ARG_B_T3_COLOR (16 << 5)
-# define RADEON_COLOR_ARG_B_T3_ALPHA (17 << 5)
-# define RADEON_COLOR_ARG_C_SHIFT 10
-# define RADEON_COLOR_ARG_C_MASK (0x1f << 10)
-# define RADEON_COLOR_ARG_C_ZERO (0 << 10)
-# define RADEON_COLOR_ARG_C_CURRENT_COLOR (2 << 10)
-# define RADEON_COLOR_ARG_C_CURRENT_ALPHA (3 << 10)
-# define RADEON_COLOR_ARG_C_DIFFUSE_COLOR (4 << 10)
-# define RADEON_COLOR_ARG_C_DIFFUSE_ALPHA (5 << 10)
-# define RADEON_COLOR_ARG_C_SPECULAR_COLOR (6 << 10)
-# define RADEON_COLOR_ARG_C_SPECULAR_ALPHA (7 << 10)
-# define RADEON_COLOR_ARG_C_TFACTOR_COLOR (8 << 10)
-# define RADEON_COLOR_ARG_C_TFACTOR_ALPHA (9 << 10)
-# define RADEON_COLOR_ARG_C_T0_COLOR (10 << 10)
-# define RADEON_COLOR_ARG_C_T0_ALPHA (11 << 10)
-# define RADEON_COLOR_ARG_C_T1_COLOR (12 << 10)
-# define RADEON_COLOR_ARG_C_T1_ALPHA (13 << 10)
-# define RADEON_COLOR_ARG_C_T2_COLOR (14 << 10)
-# define RADEON_COLOR_ARG_C_T2_ALPHA (15 << 10)
-# define RADEON_COLOR_ARG_C_T3_COLOR (16 << 10)
-# define RADEON_COLOR_ARG_C_T3_ALPHA (17 << 10)
-# define RADEON_COMP_ARG_A (1 << 15)
-# define RADEON_COMP_ARG_A_SHIFT 15
-# define RADEON_COMP_ARG_B (1 << 16)
-# define RADEON_COMP_ARG_B_SHIFT 16
-# define RADEON_COMP_ARG_C (1 << 17)
-# define RADEON_COMP_ARG_C_SHIFT 17
-# define RADEON_BLEND_CTL_MASK (7 << 18)
-# define RADEON_BLEND_CTL_ADD (0 << 18)
-# define RADEON_BLEND_CTL_SUBTRACT (1 << 18)
-# define RADEON_BLEND_CTL_ADDSIGNED (2 << 18)
-# define RADEON_BLEND_CTL_BLEND (3 << 18)
-# define RADEON_BLEND_CTL_DOT3 (4 << 18)
-# define RADEON_SCALE_SHIFT 21
-# define RADEON_SCALE_MASK (3 << 21)
-# define RADEON_SCALE_1X (0 << 21)
-# define RADEON_SCALE_2X (1 << 21)
-# define RADEON_SCALE_4X (2 << 21)
-# define RADEON_CLAMP_TX (1 << 23)
-# define RADEON_T0_EQ_TCUR (1 << 24)
-# define RADEON_T1_EQ_TCUR (1 << 25)
-# define RADEON_T2_EQ_TCUR (1 << 26)
-# define RADEON_T3_EQ_TCUR (1 << 27)
-# define RADEON_COLOR_ARG_MASK 0x1f
-# define RADEON_COMP_ARG_SHIFT 15
-#define RADEON_PP_TXABLEND_0 0x1c64
-#define RADEON_PP_TXABLEND_1 0x1c7c
-#define RADEON_PP_TXABLEND_2 0x1c94
-# define RADEON_ALPHA_ARG_A_SHIFT 0
-# define RADEON_ALPHA_ARG_A_MASK (0xf << 0)
-# define RADEON_ALPHA_ARG_A_ZERO (0 << 0)
-# define RADEON_ALPHA_ARG_A_CURRENT_ALPHA (1 << 0)
-# define RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA (2 << 0)
-# define RADEON_ALPHA_ARG_A_SPECULAR_ALPHA (3 << 0)
-# define RADEON_ALPHA_ARG_A_TFACTOR_ALPHA (4 << 0)
-# define RADEON_ALPHA_ARG_A_T0_ALPHA (5 << 0)
-# define RADEON_ALPHA_ARG_A_T1_ALPHA (6 << 0)
-# define RADEON_ALPHA_ARG_A_T2_ALPHA (7 << 0)
-# define RADEON_ALPHA_ARG_A_T3_ALPHA (8 << 0)
-# define RADEON_ALPHA_ARG_B_SHIFT 4
-# define RADEON_ALPHA_ARG_B_MASK (0xf << 4)
-# define RADEON_ALPHA_ARG_B_ZERO (0 << 4)
-# define RADEON_ALPHA_ARG_B_CURRENT_ALPHA (1 << 4)
-# define RADEON_ALPHA_ARG_B_DIFFUSE_ALPHA (2 << 4)
-# define RADEON_ALPHA_ARG_B_SPECULAR_ALPHA (3 << 4)
-# define RADEON_ALPHA_ARG_B_TFACTOR_ALPHA (4 << 4)
-# define RADEON_ALPHA_ARG_B_T0_ALPHA (5 << 4)
-# define RADEON_ALPHA_ARG_B_T1_ALPHA (6 << 4)
-# define RADEON_ALPHA_ARG_B_T2_ALPHA (7 << 4)
-# define RADEON_ALPHA_ARG_B_T3_ALPHA (8 << 4)
-# define RADEON_ALPHA_ARG_C_SHIFT 8
-# define RADEON_ALPHA_ARG_C_MASK (0xf << 8)
-# define RADEON_ALPHA_ARG_C_ZERO (0 << 8)
-# define RADEON_ALPHA_ARG_C_CURRENT_ALPHA (1 << 8)
-# define RADEON_ALPHA_ARG_C_DIFFUSE_ALPHA (2 << 8)
-# define RADEON_ALPHA_ARG_C_SPECULAR_ALPHA (3 << 8)
-# define RADEON_ALPHA_ARG_C_TFACTOR_ALPHA (4 << 8)
-# define RADEON_ALPHA_ARG_C_T0_ALPHA (5 << 8)
-# define RADEON_ALPHA_ARG_C_T1_ALPHA (6 << 8)
-# define RADEON_ALPHA_ARG_C_T2_ALPHA (7 << 8)
-# define RADEON_ALPHA_ARG_C_T3_ALPHA (8 << 8)
-# define RADEON_DOT_ALPHA_DONT_REPLICATE (1 << 9)
-# define RADEON_ALPHA_ARG_MASK 0xf
-
-#define RADEON_PP_TFACTOR_0 0x1c68
-#define RADEON_PP_TFACTOR_1 0x1c80
-#define RADEON_PP_TFACTOR_2 0x1c98
-
-#define RADEON_RB3D_BLENDCNTL 0x1c20
-# define RADEON_COMB_FCN_MASK (3 << 12)
-# define RADEON_COMB_FCN_ADD_CLAMP (0 << 12)
-# define RADEON_COMB_FCN_ADD_NOCLAMP (1 << 12)
-# define RADEON_COMB_FCN_SUB_CLAMP (2 << 12)
-# define RADEON_COMB_FCN_SUB_NOCLAMP (3 << 12)
-# define RADEON_SRC_BLEND_GL_ZERO (32 << 16)
-# define RADEON_SRC_BLEND_GL_ONE (33 << 16)
-# define RADEON_SRC_BLEND_GL_SRC_COLOR (34 << 16)
-# define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 16)
-# define RADEON_SRC_BLEND_GL_DST_COLOR (36 << 16)
-# define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 16)
-# define RADEON_SRC_BLEND_GL_SRC_ALPHA (38 << 16)
-# define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 16)
-# define RADEON_SRC_BLEND_GL_DST_ALPHA (40 << 16)
-# define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 16)
-# define RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE (42 << 16)
-# define RADEON_SRC_BLEND_MASK (63 << 16)
-# define RADEON_DST_BLEND_GL_ZERO (32 << 24)
-# define RADEON_DST_BLEND_GL_ONE (33 << 24)
-# define RADEON_DST_BLEND_GL_SRC_COLOR (34 << 24)
-# define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 24)
-# define RADEON_DST_BLEND_GL_DST_COLOR (36 << 24)
-# define RADEON_DST_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 24)
-# define RADEON_DST_BLEND_GL_SRC_ALPHA (38 << 24)
-# define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 24)
-# define RADEON_DST_BLEND_GL_DST_ALPHA (40 << 24)
-# define RADEON_DST_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 24)
-# define RADEON_DST_BLEND_MASK (63 << 24)
-#define RADEON_RB3D_CNTL 0x1c3c
-# define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
-# define RADEON_PLANE_MASK_ENABLE (1 << 1)
-# define RADEON_DITHER_ENABLE (1 << 2)
-# define RADEON_ROUND_ENABLE (1 << 3)
-# define RADEON_SCALE_DITHER_ENABLE (1 << 4)
-# define RADEON_DITHER_INIT (1 << 5)
-# define RADEON_ROP_ENABLE (1 << 6)
-# define RADEON_STENCIL_ENABLE (1 << 7)
-# define RADEON_Z_ENABLE (1 << 8)
-# define RADEON_DEPTH_XZ_OFFEST_ENABLE (1 << 9)
-# define RADEON_COLOR_FORMAT_ARGB1555 (3 << 10)
-# define RADEON_COLOR_FORMAT_RGB565 (4 << 10)
-# define RADEON_COLOR_FORMAT_ARGB8888 (6 << 10)
-# define RADEON_COLOR_FORMAT_RGB332 (7 << 10)
-# define RADEON_COLOR_FORMAT_Y8 (8 << 10)
-# define RADEON_COLOR_FORMAT_RGB8 (9 << 10)
-# define RADEON_COLOR_FORMAT_YUV422_VYUY (11 << 10)
-# define RADEON_COLOR_FORMAT_YUV422_YVYU (12 << 10)
-# define RADEON_COLOR_FORMAT_aYUV444 (14 << 10)
-# define RADEON_COLOR_FORMAT_ARGB4444 (15 << 10)
-# define RADEON_CLRCMP_FLIP_ENABLE (1 << 14)
-# define RADEON_ZBLOCK16 (1 << 15)
-#define RADEON_RB3D_COLOROFFSET 0x1c40
-# define RADEON_COLOROFFSET_MASK 0xfffffff0
-#define RADEON_RB3D_COLORPITCH 0x1c48
-# define RADEON_COLORPITCH_MASK 0x000001ff8
-# define RADEON_COLOR_TILE_ENABLE (1 << 16)
-# define RADEON_COLOR_MICROTILE_ENABLE (1 << 17)
-# define RADEON_COLOR_ENDIAN_NO_SWAP (0 << 18)
-# define RADEON_COLOR_ENDIAN_WORD_SWAP (1 << 18)
-# define RADEON_COLOR_ENDIAN_DWORD_SWAP (2 << 18)
-#define RADEON_RB3D_DEPTHOFFSET 0x1c24
-#define RADEON_RB3D_DEPTHPITCH 0x1c28
-# define RADEON_DEPTHPITCH_MASK 0x00001ff8
-# define RADEON_DEPTH_HYPERZ (3 << 16)
-# define RADEON_DEPTH_ENDIAN_NO_SWAP (0 << 18)
-# define RADEON_DEPTH_ENDIAN_WORD_SWAP (1 << 18)
-# define RADEON_DEPTH_ENDIAN_DWORD_SWAP (2 << 18)
-#define RADEON_RB3D_PLANEMASK 0x1d84
-#define RADEON_RB3D_ROPCNTL 0x1d80
-# define RADEON_ROP_MASK (15 << 8)
-# define RADEON_ROP_CLEAR (0 << 8)
-# define RADEON_ROP_NOR (1 << 8)
-# define RADEON_ROP_AND_INVERTED (2 << 8)
-# define RADEON_ROP_COPY_INVERTED (3 << 8)
-# define RADEON_ROP_AND_REVERSE (4 << 8)
-# define RADEON_ROP_INVERT (5 << 8)
-# define RADEON_ROP_XOR (6 << 8)
-# define RADEON_ROP_NAND (7 << 8)
-# define RADEON_ROP_AND (8 << 8)
-# define RADEON_ROP_EQUIV (9 << 8)
-# define RADEON_ROP_NOOP (10 << 8)
-# define RADEON_ROP_OR_INVERTED (11 << 8)
-# define RADEON_ROP_COPY (12 << 8)
-# define RADEON_ROP_OR_REVERSE (13 << 8)
-# define RADEON_ROP_OR (14 << 8)
-# define RADEON_ROP_SET (15 << 8)
-#define RADEON_RB3D_STENCILREFMASK 0x1d7c
-# define RADEON_STENCIL_REF_SHIFT 0
-# define RADEON_STENCIL_REF_MASK (0xff << 0)
-# define RADEON_STENCIL_MASK_SHIFT 16
-# define RADEON_STENCIL_VALUE_MASK (0xff << 16)
-# define RADEON_STENCIL_WRITEMASK_SHIFT 24
-# define RADEON_STENCIL_WRITE_MASK (0xff << 24)
-#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
-# define RADEON_DEPTH_FORMAT_MASK (0xf << 0)
-# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
-# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
-# define RADEON_DEPTH_FORMAT_24BIT_FLOAT_Z (3 << 0)
-# define RADEON_DEPTH_FORMAT_32BIT_INT_Z (4 << 0)
-# define RADEON_DEPTH_FORMAT_32BIT_FLOAT_Z (5 << 0)
-# define RADEON_DEPTH_FORMAT_16BIT_FLOAT_W (7 << 0)
-# define RADEON_DEPTH_FORMAT_24BIT_FLOAT_W (9 << 0)
-# define RADEON_DEPTH_FORMAT_32BIT_FLOAT_W (11 << 0)
-# define RADEON_Z_TEST_NEVER (0 << 4)
-# define RADEON_Z_TEST_LESS (1 << 4)
-# define RADEON_Z_TEST_LEQUAL (2 << 4)
-# define RADEON_Z_TEST_EQUAL (3 << 4)
-# define RADEON_Z_TEST_GEQUAL (4 << 4)
-# define RADEON_Z_TEST_GREATER (5 << 4)
-# define RADEON_Z_TEST_NEQUAL (6 << 4)
-# define RADEON_Z_TEST_ALWAYS (7 << 4)
-# define RADEON_Z_TEST_MASK (7 << 4)
-# define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
-# define RADEON_STENCIL_TEST_NEVER (0 << 12)
-# define RADEON_STENCIL_TEST_LESS (1 << 12)
-# define RADEON_STENCIL_TEST_LEQUAL (2 << 12)
-# define RADEON_STENCIL_TEST_EQUAL (3 << 12)
-# define RADEON_STENCIL_TEST_GEQUAL (4 << 12)
-# define RADEON_STENCIL_TEST_GREATER (5 << 12)
-# define RADEON_STENCIL_TEST_NEQUAL (6 << 12)
-# define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
-# define RADEON_STENCIL_TEST_MASK (0x7 << 12)
-# define RADEON_STENCIL_FAIL_KEEP (0 << 16)
-# define RADEON_STENCIL_FAIL_ZERO (1 << 16)
-# define RADEON_STENCIL_FAIL_REPLACE (2 << 16)
-# define RADEON_STENCIL_FAIL_INC (3 << 16)
-# define RADEON_STENCIL_FAIL_DEC (4 << 16)
-# define RADEON_STENCIL_FAIL_INVERT (5 << 16)
-# define RADEON_STENCIL_FAIL_INC_WRAP (6 << 16)
-# define RADEON_STENCIL_FAIL_DEC_WRAP (7 << 16)
-# define RADEON_STENCIL_FAIL_MASK (0x7 << 16)
-# define RADEON_STENCIL_ZPASS_KEEP (0 << 20)
-# define RADEON_STENCIL_ZPASS_ZERO (1 << 20)
-# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
-# define RADEON_STENCIL_ZPASS_INC (3 << 20)
-# define RADEON_STENCIL_ZPASS_DEC (4 << 20)
-# define RADEON_STENCIL_ZPASS_INVERT (5 << 20)
-# define RADEON_STENCIL_ZPASS_INC_WRAP (6 << 20)
-# define RADEON_STENCIL_ZPASS_DEC_WRAP (7 << 20)
-# define RADEON_STENCIL_ZPASS_MASK (0x7 << 20)
-# define RADEON_STENCIL_ZFAIL_KEEP (0 << 24)
-# define RADEON_STENCIL_ZFAIL_ZERO (1 << 24)
-# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
-# define RADEON_STENCIL_ZFAIL_INC (3 << 24)
-# define RADEON_STENCIL_ZFAIL_DEC (4 << 24)
-# define RADEON_STENCIL_ZFAIL_INVERT (5 << 24)
-# define RADEON_STENCIL_ZFAIL_INC_WRAP (6 << 24)
-# define RADEON_STENCIL_ZFAIL_DEC_WRAP (7 << 24)
-# define RADEON_STENCIL_ZFAIL_MASK (0x7 << 24)
-# define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
-# define RADEON_FORCE_Z_DIRTY (1 << 29)
-# define RADEON_Z_WRITE_ENABLE (1 << 30)
-# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
-#define RADEON_RE_LINE_PATTERN 0x1cd0
-# define RADEON_LINE_PATTERN_MASK 0x0000ffff
-# define RADEON_LINE_REPEAT_COUNT_SHIFT 16
-# define RADEON_LINE_PATTERN_START_SHIFT 24
-# define RADEON_LINE_PATTERN_LITTLE_BIT_ORDER (0 << 28)
-# define RADEON_LINE_PATTERN_BIG_BIT_ORDER (1 << 28)
-# define RADEON_LINE_PATTERN_AUTO_RESET (1 << 29)
-#define RADEON_RE_LINE_STATE 0x1cd4
-# define RADEON_LINE_CURRENT_PTR_SHIFT 0
-# define RADEON_LINE_CURRENT_COUNT_SHIFT 8
-#define RADEON_RE_MISC 0x26c4
-# define RADEON_STIPPLE_COORD_MASK 0x1f
-# define RADEON_STIPPLE_X_OFFSET_SHIFT 0
-# define RADEON_STIPPLE_X_OFFSET_MASK (0x1f << 0)
-# define RADEON_STIPPLE_Y_OFFSET_SHIFT 8
-# define RADEON_STIPPLE_Y_OFFSET_MASK (0x1f << 8)
-# define RADEON_STIPPLE_LITTLE_BIT_ORDER (0 << 16)
-# define RADEON_STIPPLE_BIG_BIT_ORDER (1 << 16)
-#define RADEON_RE_SOLID_COLOR 0x1c1c
-#define RADEON_RE_TOP_LEFT 0x26c0
-# define RADEON_RE_LEFT_SHIFT 0
-# define RADEON_RE_TOP_SHIFT 16
-#define RADEON_RE_WIDTH_HEIGHT 0x1c44
-# define RADEON_RE_WIDTH_SHIFT 0
-# define RADEON_RE_HEIGHT_SHIFT 16
-
-#define RADEON_SE_CNTL 0x1c4c
-# define RADEON_FFACE_CULL_CW (0 << 0)
-# define RADEON_FFACE_CULL_CCW (1 << 0)
-# define RADEON_FFACE_CULL_DIR_MASK (1 << 0)
-# define RADEON_BFACE_CULL (0 << 1)
-# define RADEON_BFACE_SOLID (3 << 1)
-# define RADEON_FFACE_CULL (0 << 3)
-# define RADEON_FFACE_SOLID (3 << 3)
-# define RADEON_FFACE_CULL_MASK (3 << 3)
-# define RADEON_BADVTX_CULL_DISABLE (1 << 5)
-# define RADEON_FLAT_SHADE_VTX_0 (0 << 6)
-# define RADEON_FLAT_SHADE_VTX_1 (1 << 6)
-# define RADEON_FLAT_SHADE_VTX_2 (2 << 6)
-# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
-# define RADEON_DIFFUSE_SHADE_SOLID (0 << 8)
-# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
-# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
-# define RADEON_DIFFUSE_SHADE_MASK (3 << 8)
-# define RADEON_ALPHA_SHADE_SOLID (0 << 10)
-# define RADEON_ALPHA_SHADE_FLAT (1 << 10)
-# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
-# define RADEON_ALPHA_SHADE_MASK (3 << 10)
-# define RADEON_SPECULAR_SHADE_SOLID (0 << 12)
-# define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
-# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
-# define RADEON_SPECULAR_SHADE_MASK (3 << 12)
-# define RADEON_FOG_SHADE_SOLID (0 << 14)
-# define RADEON_FOG_SHADE_FLAT (1 << 14)
-# define RADEON_FOG_SHADE_GOURAUD (2 << 14)
-# define RADEON_FOG_SHADE_MASK (3 << 14)
-# define RADEON_ZBIAS_ENABLE_POINT (1 << 16)
-# define RADEON_ZBIAS_ENABLE_LINE (1 << 17)
-# define RADEON_ZBIAS_ENABLE_TRI (1 << 18)
-# define RADEON_WIDELINE_ENABLE (1 << 20)
-# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
-# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
-# define RADEON_VTX_PIX_CENTER_D3D (0 << 27)
-# define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
-# define RADEON_ROUND_MODE_TRUNC (0 << 28)
-# define RADEON_ROUND_MODE_ROUND (1 << 28)
-# define RADEON_ROUND_MODE_ROUND_EVEN (2 << 28)
-# define RADEON_ROUND_MODE_ROUND_ODD (3 << 28)
-# define RADEON_ROUND_PREC_16TH_PIX (0 << 30)
-# define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
-# define RADEON_ROUND_PREC_4TH_PIX (2 << 30)
-# define RADEON_ROUND_PREC_HALF_PIX (3 << 30)
-#define RADEON_SE_CNTL_STATUS 0x2140
-# define RADEON_VC_NO_SWAP (0 << 0)
-# define RADEON_VC_16BIT_SWAP (1 << 0)
-# define RADEON_VC_32BIT_SWAP (2 << 0)
-# define RADEON_VC_HALF_DWORD_SWAP (3 << 0)
-# define RADEON_TCL_BYPASS (1 << 8)
-#define RADEON_SE_COORD_FMT 0x1c50
-# define RADEON_VTX_XY_PRE_MULT_1_OVER_W0 (1 << 0)
-# define RADEON_VTX_Z_PRE_MULT_1_OVER_W0 (1 << 1)
-# define RADEON_VTX_ST0_NONPARAMETRIC (1 << 8)
-# define RADEON_VTX_ST1_NONPARAMETRIC (1 << 9)
-# define RADEON_VTX_ST2_NONPARAMETRIC (1 << 10)
-# define RADEON_VTX_ST3_NONPARAMETRIC (1 << 11)
-# define RADEON_VTX_W0_NORMALIZE (1 << 12)
-# define RADEON_VTX_W0_IS_NOT_1_OVER_W0 (1 << 16)
-# define RADEON_VTX_ST0_PRE_MULT_1_OVER_W0 (1 << 17)
-# define RADEON_VTX_ST1_PRE_MULT_1_OVER_W0 (1 << 19)
-# define RADEON_VTX_ST2_PRE_MULT_1_OVER_W0 (1 << 21)
-# define RADEON_VTX_ST3_PRE_MULT_1_OVER_W0 (1 << 23)
-# define RADEON_TEX1_W_ROUTING_USE_W0 (0 << 26)
-# define RADEON_TEX1_W_ROUTING_USE_Q1 (1 << 26)
-#define RADEON_SE_LINE_WIDTH 0x1db8
-#define RADEON_SE_TCL_LIGHT_MODEL_CTL 0x226c
-# define RADEON_LIGHTING_ENABLE (1 << 0)
-# define RADEON_LIGHT_IN_MODELSPACE (1 << 1)
-# define RADEON_LOCAL_VIEWER (1 << 2)
-# define RADEON_NORMALIZE_NORMALS (1 << 3)
-# define RADEON_RESCALE_NORMALS (1 << 4)
-# define RADEON_SPECULAR_LIGHTS (1 << 5)
-# define RADEON_DIFFUSE_SPECULAR_COMBINE (1 << 6)
-# define RADEON_LIGHT_ALPHA (1 << 7)
-# define RADEON_LOCAL_LIGHT_VEC_GL (1 << 8)
-# define RADEON_LIGHT_NO_NORMAL_AMBIENT_ONLY (1 << 9)
-# define RADEON_LM_SOURCE_STATE_PREMULT 0
-# define RADEON_LM_SOURCE_STATE_MULT 1
-# define RADEON_LM_SOURCE_VERTEX_DIFFUSE 2
-# define RADEON_LM_SOURCE_VERTEX_SPECULAR 3
-# define RADEON_EMISSIVE_SOURCE_SHIFT 16
-# define RADEON_AMBIENT_SOURCE_SHIFT 18
-# define RADEON_DIFFUSE_SOURCE_SHIFT 20
-# define RADEON_SPECULAR_SOURCE_SHIFT 22
-#define RADEON_SE_TCL_MATERIAL_AMBIENT_RED 0x2220
-#define RADEON_SE_TCL_MATERIAL_AMBIENT_GREEN 0x2224
-#define RADEON_SE_TCL_MATERIAL_AMBIENT_BLUE 0x2228
-#define RADEON_SE_TCL_MATERIAL_AMBIENT_ALPHA 0x222c
-#define RADEON_SE_TCL_MATERIAL_DIFFUSE_RED 0x2230
-#define RADEON_SE_TCL_MATERIAL_DIFFUSE_GREEN 0x2234
-#define RADEON_SE_TCL_MATERIAL_DIFFUSE_BLUE 0x2238
-#define RADEON_SE_TCL_MATERIAL_DIFFUSE_ALPHA 0x223c
-#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
-#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_GREEN 0x2214
-#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_BLUE 0x2218
-#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_ALPHA 0x221c
-#define RADEON_SE_TCL_MATERIAL_SPECULAR_RED 0x2240
-#define RADEON_SE_TCL_MATERIAL_SPECULAR_GREEN 0x2244
-#define RADEON_SE_TCL_MATERIAL_SPECULAR_BLUE 0x2248
-#define RADEON_SE_TCL_MATERIAL_SPECULAR_ALPHA 0x224c
-#define RADEON_SE_TCL_MATRIX_SELECT_0 0x225c
-# define RADEON_MODELVIEW_0_SHIFT 0
-# define RADEON_MODELVIEW_1_SHIFT 4
-# define RADEON_MODELVIEW_2_SHIFT 8
-# define RADEON_MODELVIEW_3_SHIFT 12
-# define RADEON_IT_MODELVIEW_0_SHIFT 16
-# define RADEON_IT_MODELVIEW_1_SHIFT 20
-# define RADEON_IT_MODELVIEW_2_SHIFT 24
-# define RADEON_IT_MODELVIEW_3_SHIFT 28
-#define RADEON_SE_TCL_MATRIX_SELECT_1 0x2260
-# define RADEON_MODELPROJECT_0_SHIFT 0
-# define RADEON_MODELPROJECT_1_SHIFT 4
-# define RADEON_MODELPROJECT_2_SHIFT 8
-# define RADEON_MODELPROJECT_3_SHIFT 12
-# define RADEON_TEXMAT_0_SHIFT 16
-# define RADEON_TEXMAT_1_SHIFT 20
-# define RADEON_TEXMAT_2_SHIFT 24
-# define RADEON_TEXMAT_3_SHIFT 28
-
-
-#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
-# define RADEON_TCL_VTX_W0 (1 << 0)
-# define RADEON_TCL_VTX_FP_DIFFUSE (1 << 1)
-# define RADEON_TCL_VTX_FP_ALPHA (1 << 2)
-# define RADEON_TCL_VTX_PK_DIFFUSE (1 << 3)
-# define RADEON_TCL_VTX_FP_SPEC (1 << 4)
-# define RADEON_TCL_VTX_FP_FOG (1 << 5)
-# define RADEON_TCL_VTX_PK_SPEC (1 << 6)
-# define RADEON_TCL_VTX_ST0 (1 << 7)
-# define RADEON_TCL_VTX_ST1 (1 << 8)
-# define RADEON_TCL_VTX_Q1 (1 << 9)
-# define RADEON_TCL_VTX_ST2 (1 << 10)
-# define RADEON_TCL_VTX_Q2 (1 << 11)
-# define RADEON_TCL_VTX_ST3 (1 << 12)
-# define RADEON_TCL_VTX_Q3 (1 << 13)
-# define RADEON_TCL_VTX_Q0 (1 << 14)
-# define RADEON_TCL_VTX_WEIGHT_COUNT_SHIFT 15
-# define RADEON_TCL_VTX_NORM0 (1 << 18)
-# define RADEON_TCL_VTX_XY1 (1 << 27)
-# define RADEON_TCL_VTX_Z1 (1 << 28)
-# define RADEON_TCL_VTX_W1 (1 << 29)
-# define RADEON_TCL_VTX_NORM1 (1 << 30)
-# define RADEON_TCL_VTX_Z0 (1 << 31)
-
-#define RADEON_SE_TCL_OUTPUT_VTX_SEL 0x2258
-# define RADEON_TCL_COMPUTE_XYZW (1 << 0)
-# define RADEON_TCL_COMPUTE_DIFFUSE (1 << 1)
-# define RADEON_TCL_COMPUTE_SPECULAR (1 << 2)
-# define RADEON_TCL_FORCE_NAN_IF_COLOR_NAN (1 << 3)
-# define RADEON_TCL_FORCE_INORDER_PROC (1 << 4)
-# define RADEON_TCL_TEX_INPUT_TEX_0 0
-# define RADEON_TCL_TEX_INPUT_TEX_1 1
-# define RADEON_TCL_TEX_INPUT_TEX_2 2
-# define RADEON_TCL_TEX_INPUT_TEX_3 3
-# define RADEON_TCL_TEX_COMPUTED_TEX_0 8
-# define RADEON_TCL_TEX_COMPUTED_TEX_1 9
-# define RADEON_TCL_TEX_COMPUTED_TEX_2 10
-# define RADEON_TCL_TEX_COMPUTED_TEX_3 11
-# define RADEON_TCL_TEX_0_OUTPUT_SHIFT 16
-# define RADEON_TCL_TEX_1_OUTPUT_SHIFT 20
-# define RADEON_TCL_TEX_2_OUTPUT_SHIFT 24
-# define RADEON_TCL_TEX_3_OUTPUT_SHIFT 28
-
-#define RADEON_SE_TCL_PER_LIGHT_CTL_0 0x2270
-# define RADEON_LIGHT_0_ENABLE (1 << 0)
-# define RADEON_LIGHT_0_ENABLE_AMBIENT (1 << 1)
-# define RADEON_LIGHT_0_ENABLE_SPECULAR (1 << 2)
-# define RADEON_LIGHT_0_IS_LOCAL (1 << 3)
-# define RADEON_LIGHT_0_IS_SPOT (1 << 4)
-# define RADEON_LIGHT_0_DUAL_CONE (1 << 5)
-# define RADEON_LIGHT_0_ENABLE_RANGE_ATTEN (1 << 6)
-# define RADEON_LIGHT_0_CONSTANT_RANGE_ATTEN (1 << 7)
-# define RADEON_LIGHT_0_SHIFT 0
-# define RADEON_LIGHT_1_ENABLE (1 << 16)
-# define RADEON_LIGHT_1_ENABLE_AMBIENT (1 << 17)
-# define RADEON_LIGHT_1_ENABLE_SPECULAR (1 << 18)
-# define RADEON_LIGHT_1_IS_LOCAL (1 << 19)
-# define RADEON_LIGHT_1_IS_SPOT (1 << 20)
-# define RADEON_LIGHT_1_DUAL_CONE (1 << 21)
-# define RADEON_LIGHT_1_ENABLE_RANGE_ATTEN (1 << 22)
-# define RADEON_LIGHT_1_CONSTANT_RANGE_ATTEN (1 << 23)
-# define RADEON_LIGHT_1_SHIFT 16
-#define RADEON_SE_TCL_PER_LIGHT_CTL_1 0x2274
-# define RADEON_LIGHT_2_SHIFT 0
-# define RADEON_LIGHT_3_SHIFT 16
-#define RADEON_SE_TCL_PER_LIGHT_CTL_2 0x2278
-# define RADEON_LIGHT_4_SHIFT 0
-# define RADEON_LIGHT_5_SHIFT 16
-#define RADEON_SE_TCL_PER_LIGHT_CTL_3 0x227c
-# define RADEON_LIGHT_6_SHIFT 0
-# define RADEON_LIGHT_7_SHIFT 16
-
-#define RADEON_SE_TCL_SHININESS 0x2250
-
-#define RADEON_SE_TCL_TEXTURE_PROC_CTL 0x2268
-# define RADEON_TEXGEN_TEXMAT_0_ENABLE (1 << 0)
-# define RADEON_TEXGEN_TEXMAT_1_ENABLE (1 << 1)
-# define RADEON_TEXGEN_TEXMAT_2_ENABLE (1 << 2)
-# define RADEON_TEXGEN_TEXMAT_3_ENABLE (1 << 3)
-# define RADEON_TEXMAT_0_ENABLE (1 << 4)
-# define RADEON_TEXMAT_1_ENABLE (1 << 5)
-# define RADEON_TEXMAT_2_ENABLE (1 << 6)
-# define RADEON_TEXMAT_3_ENABLE (1 << 7)
-# define RADEON_TEXGEN_INPUT_MASK 0xf
-# define RADEON_TEXGEN_INPUT_TEXCOORD_0 0
-# define RADEON_TEXGEN_INPUT_TEXCOORD_1 1
-# define RADEON_TEXGEN_INPUT_TEXCOORD_2 2
-# define RADEON_TEXGEN_INPUT_TEXCOORD_3 3
-# define RADEON_TEXGEN_INPUT_OBJ 4
-# define RADEON_TEXGEN_INPUT_EYE 5
-# define RADEON_TEXGEN_INPUT_EYE_NORMAL 6
-# define RADEON_TEXGEN_INPUT_EYE_REFLECT 7
-# define RADEON_TEXGEN_INPUT_EYE_NORMALIZED 8
-# define RADEON_TEXGEN_0_INPUT_SHIFT 16
-# define RADEON_TEXGEN_1_INPUT_SHIFT 20
-# define RADEON_TEXGEN_2_INPUT_SHIFT 24
-# define RADEON_TEXGEN_3_INPUT_SHIFT 28
-
-#define RADEON_SE_TCL_UCP_VERT_BLEND_CTL 0x2264
-# define RADEON_UCP_IN_CLIP_SPACE (1 << 0)
-# define RADEON_UCP_IN_MODEL_SPACE (1 << 1)
-# define RADEON_UCP_ENABLE_0 (1 << 2)
-# define RADEON_UCP_ENABLE_1 (1 << 3)
-# define RADEON_UCP_ENABLE_2 (1 << 4)
-# define RADEON_UCP_ENABLE_3 (1 << 5)
-# define RADEON_UCP_ENABLE_4 (1 << 6)
-# define RADEON_UCP_ENABLE_5 (1 << 7)
-# define RADEON_TCL_FOG_MASK (3 << 8)
-# define RADEON_TCL_FOG_DISABLE (0 << 8)
-# define RADEON_TCL_FOG_EXP (1 << 8)
-# define RADEON_TCL_FOG_EXP2 (2 << 8)
-# define RADEON_TCL_FOG_LINEAR (3 << 8)
-# define RADEON_RNG_BASED_FOG (1 << 10)
-# define RADEON_LIGHT_TWOSIDE (1 << 11)
-# define RADEON_BLEND_OP_COUNT_MASK (7 << 12)
-# define RADEON_BLEND_OP_COUNT_SHIFT 12
-# define RADEON_POSITION_BLEND_OP_ENABLE (1 << 16)
-# define RADEON_NORMAL_BLEND_OP_ENABLE (1 << 17)
-# define RADEON_VERTEX_BLEND_SRC_0_PRIMARY (1 << 18)
-# define RADEON_VERTEX_BLEND_SRC_0_SECONDARY (1 << 18)
-# define RADEON_VERTEX_BLEND_SRC_1_PRIMARY (1 << 19)
-# define RADEON_VERTEX_BLEND_SRC_1_SECONDARY (1 << 19)
-# define RADEON_VERTEX_BLEND_SRC_2_PRIMARY (1 << 20)
-# define RADEON_VERTEX_BLEND_SRC_2_SECONDARY (1 << 20)
-# define RADEON_VERTEX_BLEND_SRC_3_PRIMARY (1 << 21)
-# define RADEON_VERTEX_BLEND_SRC_3_SECONDARY (1 << 21)
-# define RADEON_VERTEX_BLEND_WGT_MINUS_ONE (1 << 22)
-# define RADEON_CULL_FRONT_IS_CW (0 << 28)
-# define RADEON_CULL_FRONT_IS_CCW (1 << 28)
-# define RADEON_CULL_FRONT (1 << 29)
-# define RADEON_CULL_BACK (1 << 30)
-# define RADEON_FORCE_W_TO_ONE (1 << 31)
-
-#define RADEON_SE_VPORT_XSCALE 0x1d98
-#define RADEON_SE_VPORT_XOFFSET 0x1d9c
-#define RADEON_SE_VPORT_YSCALE 0x1da0
-#define RADEON_SE_VPORT_YOFFSET 0x1da4
-#define RADEON_SE_VPORT_ZSCALE 0x1da8
-#define RADEON_SE_VPORT_ZOFFSET 0x1dac
-#define RADEON_SE_ZBIAS_FACTOR 0x1db0
-#define RADEON_SE_ZBIAS_CONSTANT 0x1db4
-
-
-
- /* Registers for CP and Microcode Engine */
-#define RADEON_CP_ME_RAM_ADDR 0x07d4
-#define RADEON_CP_ME_RAM_RADDR 0x07d8
-#define RADEON_CP_ME_RAM_DATAH 0x07dc
-#define RADEON_CP_ME_RAM_DATAL 0x07e0
-
-#define RADEON_CP_RB_BASE 0x0700
-#define RADEON_CP_RB_CNTL 0x0704
-#define RADEON_CP_RB_RPTR_ADDR 0x070c
-#define RADEON_CP_RB_RPTR 0x0710
-#define RADEON_CP_RB_WPTR 0x0714
-
-#define RADEON_CP_IB_BASE 0x0738
-#define RADEON_CP_IB_BUFSZ 0x073c
-
-#define RADEON_CP_CSQ_CNTL 0x0740
-# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
-# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
-# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
-# define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
-# define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
-# define RADEON_CSQ_PRIBM_INDBM (4 << 28)
-# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
-#define RADEON_CP_CSQ_STAT 0x07f8
-# define RADEON_CSQ_RPTR_PRIMARY_MASK (0xff << 0)
-# define RADEON_CSQ_WPTR_PRIMARY_MASK (0xff << 8)
-# define RADEON_CSQ_RPTR_INDIRECT_MASK (0xff << 16)
-# define RADEON_CSQ_WPTR_INDIRECT_MASK (0xff << 24)
-#define RADEON_CP_CSQ_ADDR 0x07f0
-#define RADEON_CP_CSQ_DATA 0x07f4
-#define RADEON_CP_CSQ_APER_PRIMARY 0x1000
-#define RADEON_CP_CSQ_APER_INDIRECT 0x1300
-
-#define RADEON_CP_RB_WPTR_DELAY 0x0718
-# define RADEON_PRE_WRITE_TIMER_SHIFT 0
-# define RADEON_PRE_WRITE_LIMIT_SHIFT 23
-
-#define RADEON_AIC_CNTL 0x01d0
-# define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
-#define RADEON_AIC_LO_ADDR 0x01dc
-
-
-
- /* Constants */
-#define RADEON_LAST_FRAME_REG RADEON_GUI_SCRATCH_REG0
-#define RADEON_LAST_CLEAR_REG RADEON_GUI_SCRATCH_REG2
-
-
-
- /* CP packet types */
-#define RADEON_CP_PACKET0 0x00000000
-#define RADEON_CP_PACKET1 0x40000000
-#define RADEON_CP_PACKET2 0x80000000
-#define RADEON_CP_PACKET3 0xC0000000
-# define RADEON_CP_PACKET_MASK 0xC0000000
-# define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
-# define RADEON_CP_PACKET_MAX_DWORDS (1 << 12)
-# define RADEON_CP_PACKET0_REG_MASK 0x000007ff
-# define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
-# define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
-
-#define RADEON_CP_PACKET0_ONE_REG_WR 0x00008000
-
-#define RADEON_CP_PACKET3_NOP 0xC0001000
-#define RADEON_CP_PACKET3_NEXT_CHAR 0xC0001900
-#define RADEON_CP_PACKET3_PLY_NEXTSCAN 0xC0001D00
-#define RADEON_CP_PACKET3_SET_SCISSORS 0xC0001E00
-#define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300
-#define RADEON_CP_PACKET3_LOAD_MICROCODE 0xC0002400
-#define RADEON_CP_PACKET3_WAIT_FOR_IDLE 0xC0002600
-#define RADEON_CP_PACKET3_3D_DRAW_VBUF 0xC0002800
-#define RADEON_CP_PACKET3_3D_DRAW_IMMD 0xC0002900
-#define RADEON_CP_PACKET3_3D_DRAW_INDX 0xC0002A00
-#define RADEON_CP_PACKET3_LOAD_PALETTE 0xC0002C00
-#define RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00
-#define RADEON_CP_PACKET3_CNTL_PAINT 0xC0009100
-#define RADEON_CP_PACKET3_CNTL_BITBLT 0xC0009200
-#define RADEON_CP_PACKET3_CNTL_SMALLTEXT 0xC0009300
-#define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400
-#define RADEON_CP_PACKET3_CNTL_POLYLINE 0xC0009500
-#define RADEON_CP_PACKET3_CNTL_POLYSCANLINES 0xC0009800
-#define RADEON_CP_PACKET3_CNTL_PAINT_MULTI 0xC0009A00
-#define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00
-#define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00
-
-
-#define RADEON_CP_VC_FRMT_XY 0x00000000
-#define RADEON_CP_VC_FRMT_W0 0x00000001
-#define RADEON_CP_VC_FRMT_FPCOLOR 0x00000002
-#define RADEON_CP_VC_FRMT_FPALPHA 0x00000004
-#define RADEON_CP_VC_FRMT_PKCOLOR 0x00000008
-#define RADEON_CP_VC_FRMT_FPSPEC 0x00000010
-#define RADEON_CP_VC_FRMT_FPFOG 0x00000020
-#define RADEON_CP_VC_FRMT_PKSPEC 0x00000040
-#define RADEON_CP_VC_FRMT_ST0 0x00000080
-#define RADEON_CP_VC_FRMT_ST1 0x00000100
-#define RADEON_CP_VC_FRMT_Q1 0x00000200
-#define RADEON_CP_VC_FRMT_ST2 0x00000400
-#define RADEON_CP_VC_FRMT_Q2 0x00000800
-#define RADEON_CP_VC_FRMT_ST3 0x00001000
-#define RADEON_CP_VC_FRMT_Q3 0x00002000
-#define RADEON_CP_VC_FRMT_Q0 0x00004000
-#define RADEON_CP_VC_FRMT_BLND_WEIGHT_CNT_MASK 0x00038000
-#define RADEON_CP_VC_FRMT_N0 0x00040000
-#define RADEON_CP_VC_FRMT_XY1 0x08000000
-#define RADEON_CP_VC_FRMT_Z1 0x10000000
-#define RADEON_CP_VC_FRMT_W1 0x20000000
-#define RADEON_CP_VC_FRMT_N1 0x40000000
-#define RADEON_CP_VC_FRMT_Z 0x80000000
-
-#define RADEON_CP_VC_CNTL_PRIM_TYPE_NONE 0x00000000
-#define RADEON_CP_VC_CNTL_PRIM_TYPE_POINT 0x00000001
-#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE 0x00000002
-#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP 0x00000003
-#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004
-#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005
-#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006
-#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_TYPE_2 0x00000007
-#define RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST 0x00000008
-#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST 0x00000009
-#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST 0x0000000a
-#define RADEON_CP_VC_CNTL_PRIM_WALK_IND 0x00000010
-#define RADEON_CP_VC_CNTL_PRIM_WALK_LIST 0x00000020
-#define RADEON_CP_VC_CNTL_PRIM_WALK_RING 0x00000030
-#define RADEON_CP_VC_CNTL_COLOR_ORDER_BGRA 0x00000000
-#define RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA 0x00000040
-#define RADEON_CP_VC_CNTL_MAOS_ENABLE 0x00000080
-#define RADEON_CP_VC_CNTL_VTX_FMT_NON_RADEON_MODE 0x00000000
-#define RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE 0x00000100
-#define RADEON_CP_VC_CNTL_TCL_DISABLE 0x00000000
-#define RADEON_CP_VC_CNTL_TCL_ENABLE 0x00000200
-#define RADEON_CP_VC_CNTL_NUM_SHIFT 16
-
-#define RADEON_VS_MATRIX_0_ADDR 0
-#define RADEON_VS_MATRIX_1_ADDR 4
-#define RADEON_VS_MATRIX_2_ADDR 8
-#define RADEON_VS_MATRIX_3_ADDR 12
-#define RADEON_VS_MATRIX_4_ADDR 16
-#define RADEON_VS_MATRIX_5_ADDR 20
-#define RADEON_VS_MATRIX_6_ADDR 24
-#define RADEON_VS_MATRIX_7_ADDR 28
-#define RADEON_VS_MATRIX_8_ADDR 32
-#define RADEON_VS_MATRIX_9_ADDR 36
-#define RADEON_VS_MATRIX_10_ADDR 40
-#define RADEON_VS_MATRIX_11_ADDR 44
-#define RADEON_VS_MATRIX_12_ADDR 48
-#define RADEON_VS_MATRIX_13_ADDR 52
-#define RADEON_VS_MATRIX_14_ADDR 56
-#define RADEON_VS_MATRIX_15_ADDR 60
-#define RADEON_VS_LIGHT_AMBIENT_ADDR 64
-#define RADEON_VS_LIGHT_DIFFUSE_ADDR 72
-#define RADEON_VS_LIGHT_SPECULAR_ADDR 80
-#define RADEON_VS_LIGHT_DIRPOS_ADDR 88
-#define RADEON_VS_LIGHT_HWVSPOT_ADDR 96
-#define RADEON_VS_LIGHT_ATTENUATION_ADDR 104
-#define RADEON_VS_MATRIX_EYE2CLIP_ADDR 112
-#define RADEON_VS_UCP_ADDR 116
-#define RADEON_VS_GLOBAL_AMBIENT_ADDR 122
-#define RADEON_VS_FOG_PARAM_ADDR 123
-#define RADEON_VS_EYE_VECTOR_ADDR 124
-
-#define RADEON_SS_LIGHT_DCD_ADDR 0
-#define RADEON_SS_LIGHT_SPOT_EXPONENT_ADDR 8
-#define RADEON_SS_LIGHT_SPOT_CUTOFF_ADDR 16
-#define RADEON_SS_LIGHT_SPECULAR_THRESH_ADDR 24
-#define RADEON_SS_LIGHT_RANGE_CUTOFF_ADDR 32
-#define RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR 48
-#define RADEON_SS_VERT_GUARD_DISCARD_ADJ_ADDR 49
-#define RADEON_SS_HORZ_GUARD_CLIP_ADJ_ADDR 50
-#define RADEON_SS_HORZ_GUARD_DISCARD_ADJ_ADDR 51
-#define RADEON_SS_SHININESS 60
-
-#define RADEON_TV_MASTER_CNTL 0x0800
-# define RADEON_TVCLK_ALWAYS_ONb (1 << 30)
-#define RADEON_TV_DAC_CNTL 0x088c
-# define RADEON_TV_DAC_CMPOUT (1 << 5)
-#define RADEON_TV_PRE_DAC_MUX_CNTL 0x0888
-# define RADEON_Y_RED_EN (1 << 0)
-# define RADEON_C_GRN_EN (1 << 1)
-# define RADEON_CMP_BLU_EN (1 << 2)
-# define RADEON_RED_MX_FORCE_DAC_DATA (6 << 4)
-# define RADEON_GRN_MX_FORCE_DAC_DATA (6 << 8)
-# define RADEON_BLU_MX_FORCE_DAC_DATA (6 << 12)
-# define RADEON_TV_FORCE_DAC_DATA_SHIFT 16
-#endif