From b16b9e4656e7199c2aec74a4c8ebc7a875d3ba73 Mon Sep 17 00:00:00 2001 From: Mike Gabriel Date: Mon, 2 Feb 2015 15:02:49 +0100 Subject: massive reduction of unneeded files --- nx-X11/extras/drm/shared/drm.h | 735 -- nx-X11/extras/drm/shared/drm_pciids.txt | 211 - nx-X11/extras/drm/shared/drm_sarea.h | 78 - nx-X11/extras/drm/shared/i915.h | 49 - nx-X11/extras/drm/shared/i915_dma.c | 769 -- nx-X11/extras/drm/shared/i915_drm.h | 154 - nx-X11/extras/drm/shared/i915_drv.h | 219 - nx-X11/extras/drm/shared/i915_irq.c | 165 - nx-X11/extras/drm/shared/i915_mem.c | 347 - nx-X11/extras/drm/shared/mach64.h | 69 - nx-X11/extras/drm/shared/mach64_dma.c | 1343 ---- nx-X11/extras/drm/shared/mach64_drm.h | 258 - nx-X11/extras/drm/shared/mach64_drv.h | 1040 --- nx-X11/extras/drm/shared/mach64_irq.c | 130 - nx-X11/extras/drm/shared/mach64_state.c | 896 --- nx-X11/extras/drm/shared/mga.h | 63 - nx-X11/extras/drm/shared/mga_dma.c | 829 --- nx-X11/extras/drm/shared/mga_drm.h | 425 -- nx-X11/extras/drm/shared/mga_drv.h | 636 -- nx-X11/extras/drm/shared/mga_irq.c | 103 - nx-X11/extras/drm/shared/mga_state.c | 1110 --- nx-X11/extras/drm/shared/mga_ucode.h | 11645 ------------------------------ nx-X11/extras/drm/shared/mga_warp.c | 211 - nx-X11/extras/drm/shared/r128.h | 75 - nx-X11/extras/drm/shared/r128_cce.c | 946 --- nx-X11/extras/drm/shared/r128_drm.h | 345 - nx-X11/extras/drm/shared/r128_drv.h | 516 -- nx-X11/extras/drm/shared/r128_irq.c | 103 - nx-X11/extras/drm/shared/r128_state.c | 1724 ----- nx-X11/extras/drm/shared/radeon.h | 124 - nx-X11/extras/drm/shared/radeon_cp.c | 2092 ------ nx-X11/extras/drm/shared/radeon_drm.h | 661 -- nx-X11/extras/drm/shared/radeon_drv.h | 1011 --- nx-X11/extras/drm/shared/radeon_irq.c | 258 - nx-X11/extras/drm/shared/radeon_mem.c | 323 - nx-X11/extras/drm/shared/radeon_state.c | 3093 -------- nx-X11/extras/drm/shared/sis.h | 57 - nx-X11/extras/drm/shared/sis_drm.h | 33 - nx-X11/extras/drm/shared/sis_drv.h | 48 - nx-X11/extras/drm/shared/sis_ds.c | 386 - nx-X11/extras/drm/shared/sis_ds.h | 164 - nx-X11/extras/drm/shared/sis_mm.c | 417 -- nx-X11/extras/drm/shared/tdfx.h | 50 - nx-X11/extras/drm/shared/via.h | 54 - nx-X11/extras/drm/shared/via_3d_reg.h | 1651 ----- nx-X11/extras/drm/shared/via_dma.c | 742 -- nx-X11/extras/drm/shared/via_drm.h | 243 - nx-X11/extras/drm/shared/via_drv.c | 31 - nx-X11/extras/drm/shared/via_drv.h | 111 - nx-X11/extras/drm/shared/via_ds.c | 390 - nx-X11/extras/drm/shared/via_ds.h | 113 - nx-X11/extras/drm/shared/via_irq.c | 340 - nx-X11/extras/drm/shared/via_map.c | 112 - nx-X11/extras/drm/shared/via_mm.c | 372 - nx-X11/extras/drm/shared/via_mm.h | 45 - nx-X11/extras/drm/shared/via_verifier.c | 1063 --- nx-X11/extras/drm/shared/via_verifier.h | 61 - nx-X11/extras/drm/shared/via_video.c | 102 - 58 files changed, 39341 deletions(-) delete mode 100644 nx-X11/extras/drm/shared/drm.h delete mode 100644 nx-X11/extras/drm/shared/drm_pciids.txt delete mode 100644 nx-X11/extras/drm/shared/drm_sarea.h delete mode 100644 nx-X11/extras/drm/shared/i915.h delete mode 100644 nx-X11/extras/drm/shared/i915_dma.c delete mode 100644 nx-X11/extras/drm/shared/i915_drm.h delete mode 100644 nx-X11/extras/drm/shared/i915_drv.h delete mode 100644 nx-X11/extras/drm/shared/i915_irq.c delete mode 100644 nx-X11/extras/drm/shared/i915_mem.c delete mode 100644 nx-X11/extras/drm/shared/mach64.h delete mode 100644 nx-X11/extras/drm/shared/mach64_dma.c delete mode 100644 nx-X11/extras/drm/shared/mach64_drm.h delete mode 100644 nx-X11/extras/drm/shared/mach64_drv.h delete mode 100644 nx-X11/extras/drm/shared/mach64_irq.c delete mode 100644 nx-X11/extras/drm/shared/mach64_state.c delete mode 100644 nx-X11/extras/drm/shared/mga.h delete mode 100644 nx-X11/extras/drm/shared/mga_dma.c delete mode 100644 nx-X11/extras/drm/shared/mga_drm.h delete mode 100644 nx-X11/extras/drm/shared/mga_drv.h delete mode 100644 nx-X11/extras/drm/shared/mga_irq.c delete mode 100644 nx-X11/extras/drm/shared/mga_state.c delete mode 100644 nx-X11/extras/drm/shared/mga_ucode.h delete mode 100644 nx-X11/extras/drm/shared/mga_warp.c delete mode 100644 nx-X11/extras/drm/shared/r128.h delete mode 100644 nx-X11/extras/drm/shared/r128_cce.c delete mode 100644 nx-X11/extras/drm/shared/r128_drm.h delete mode 100644 nx-X11/extras/drm/shared/r128_drv.h delete mode 100644 nx-X11/extras/drm/shared/r128_irq.c delete mode 100644 nx-X11/extras/drm/shared/r128_state.c delete mode 100644 nx-X11/extras/drm/shared/radeon.h delete mode 100644 nx-X11/extras/drm/shared/radeon_cp.c delete mode 100644 nx-X11/extras/drm/shared/radeon_drm.h delete mode 100644 nx-X11/extras/drm/shared/radeon_drv.h delete mode 100644 nx-X11/extras/drm/shared/radeon_irq.c delete mode 100644 nx-X11/extras/drm/shared/radeon_mem.c delete mode 100644 nx-X11/extras/drm/shared/radeon_state.c delete mode 100644 nx-X11/extras/drm/shared/sis.h delete mode 100644 nx-X11/extras/drm/shared/sis_drm.h delete mode 100644 nx-X11/extras/drm/shared/sis_drv.h delete mode 100644 nx-X11/extras/drm/shared/sis_ds.c delete mode 100644 nx-X11/extras/drm/shared/sis_ds.h delete mode 100644 nx-X11/extras/drm/shared/sis_mm.c delete mode 100644 nx-X11/extras/drm/shared/tdfx.h delete mode 100644 nx-X11/extras/drm/shared/via.h delete mode 100644 nx-X11/extras/drm/shared/via_3d_reg.h delete mode 100644 nx-X11/extras/drm/shared/via_dma.c delete mode 100644 nx-X11/extras/drm/shared/via_drm.h delete mode 100644 nx-X11/extras/drm/shared/via_drv.c delete mode 100644 nx-X11/extras/drm/shared/via_drv.h delete mode 100644 nx-X11/extras/drm/shared/via_ds.c delete mode 100644 nx-X11/extras/drm/shared/via_ds.h delete mode 100644 nx-X11/extras/drm/shared/via_irq.c delete mode 100644 nx-X11/extras/drm/shared/via_map.c delete mode 100644 nx-X11/extras/drm/shared/via_mm.c delete mode 100644 nx-X11/extras/drm/shared/via_mm.h delete mode 100644 nx-X11/extras/drm/shared/via_verifier.c delete mode 100644 nx-X11/extras/drm/shared/via_verifier.h delete mode 100644 nx-X11/extras/drm/shared/via_video.c (limited to 'nx-X11/extras/drm/shared') diff --git a/nx-X11/extras/drm/shared/drm.h b/nx-X11/extras/drm/shared/drm.h deleted file mode 100644 index c490baed5..000000000 --- a/nx-X11/extras/drm/shared/drm.h +++ /dev/null @@ -1,735 +0,0 @@ -/** - * \file drm.h - * Header for the Direct Rendering Manager - * - * \author Rickard E. (Rik) Faith - * - * \par Acknowledgments: - * Dec 1999, Richard Henderson , move to generic \c cmpxchg. - */ - -/* - * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. - * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. - * All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/** - * \mainpage - * - * The Direct Rendering Manager (DRM) is a device-independent kernel-level - * device driver that provides support for the XFree86 Direct Rendering - * Infrastructure (DRI). - * - * The DRM supports the Direct Rendering Infrastructure (DRI) in four major - * ways: - * -# The DRM provides synchronized access to the graphics hardware via - * the use of an optimized two-tiered lock. - * -# The DRM enforces the DRI security policy for access to the graphics - * hardware by only allowing authenticated X11 clients access to - * restricted regions of memory. - * -# The DRM provides a generic DMA engine, complete with multiple - * queues and the ability to detect the need for an OpenGL context - * switch. - * -# The DRM is extensible via the use of small device-specific modules - * that rely extensively on the API exported by the DRM module. - * - */ - -#ifndef _DRM_H_ -#define _DRM_H_ - -#ifndef __user -#define __user -#endif - -#if defined(__linux__) -#if defined(__KERNEL__) -#include -#endif -#include /* For _IO* macros */ -#define DRM_IOCTL_NR(n) _IOC_NR(n) -#define DRM_IOC_VOID _IOC_NONE -#define DRM_IOC_READ _IOC_READ -#define DRM_IOC_WRITE _IOC_WRITE -#define DRM_IOC_READWRITE _IOC_READ|_IOC_WRITE -#define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size) -#elif defined(__FreeBSD__) || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__DragonFly__) -#if defined(__FreeBSD__) && defined(IN_MODULE) -/* Prevent name collision when including sys/ioccom.h */ -#undef ioctl -#include -#define ioctl(a,b,c) xf86ioctl(a,b,c) -#else -#include -#endif /* __FreeBSD__ && xf86ioctl */ -#define DRM_IOCTL_NR(n) ((n) & 0xff) -#define DRM_IOC_VOID IOC_VOID -#define DRM_IOC_READ IOC_OUT -#define DRM_IOC_WRITE IOC_IN -#define DRM_IOC_READWRITE IOC_INOUT -#define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size) -#endif - -#define XFREE86_VERSION(major,minor,patch,snap) \ - ((major << 16) | (minor << 8) | patch) - -#ifndef CONFIG_XFREE86_VERSION -#define CONFIG_XFREE86_VERSION XFREE86_VERSION(4,1,0,0) -#endif - -#if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0) -#define DRM_PROC_DEVICES "/proc/devices" -#define DRM_PROC_MISC "/proc/misc" -#define DRM_PROC_DRM "/proc/drm" -#define DRM_DEV_DRM "/dev/drm" -#define DRM_DEV_MODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP) -#define DRM_DEV_UID 0 -#define DRM_DEV_GID 0 -#endif - -#if CONFIG_XFREE86_VERSION >= XFREE86_VERSION(4,1,0,0) -#ifdef __OpenBSD__ -#define DRM_MAJOR 81 -#endif -#if defined(__linux__) || defined(__NetBSD__) -#define DRM_MAJOR 226 -#endif -#define DRM_MAX_MINOR 255 -#endif -#define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */ -#define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */ -#define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */ -#define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */ - -#define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */ -#define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */ -#define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD) -#define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT) -#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT)) - - -typedef unsigned long drm_handle_t; /**< To mapped regions */ -typedef unsigned int drm_context_t; /**< GLXContext handle */ -typedef unsigned int drm_drawable_t; -typedef unsigned int drm_magic_t; /**< Magic for authentication */ - - -/** - * Cliprect. - * - * \warning If you change this structure, make sure you change - * XF86DRIClipRectRec in the server as well - * - * \note KW: Actually it's illegal to change either for - * backwards-compatibility reasons. - */ -typedef struct drm_clip_rect { - unsigned short x1; - unsigned short y1; - unsigned short x2; - unsigned short y2; -} drm_clip_rect_t; - - -/** - * Texture region, - */ -typedef struct drm_tex_region { - unsigned char next; - unsigned char prev; - unsigned char in_use; - unsigned char padding; - unsigned int age; -} drm_tex_region_t; - -/** - * Hardware lock. - * - * The lock structure is a simple cache-line aligned integer. To avoid - * processor bus contention on a multiprocessor system, there should not be any - * other data stored in the same cache line. - */ -typedef struct drm_hw_lock { - __volatile__ unsigned int lock; /**< lock variable */ - char padding[60]; /**< Pad to cache line */ -} drm_hw_lock_t; - - -/* This is beyond ugly, and only works on GCC. However, it allows me to use - * drm.h in places (i.e., in the X-server) where I can't use size_t. The real - * fix is to use uint32_t instead of size_t, but that fix will break existing - * LP64 (i.e., PowerPC64, SPARC64, IA-64, Alpha, etc.) systems. That *will* - * eventually happen, though. I chose 'unsigned long' to be the fallback type - * because that works on all the platforms I know about. Hopefully, the - * real fix will happen before that bites us. - */ - -#ifdef __SIZE_TYPE__ -# define DRM_SIZE_T __SIZE_TYPE__ -#else -# warning "__SIZE_TYPE__ not defined. Assuming sizeof(size_t) == sizeof(unsigned long)!" -# define DRM_SIZE_T unsigned long -#endif - -/** - * DRM_IOCTL_VERSION ioctl argument type. - * - * \sa drmGetVersion(). - */ -typedef struct drm_version { - int version_major; /**< Major version */ - int version_minor; /**< Minor version */ - int version_patchlevel;/**< Patch level */ - DRM_SIZE_T name_len; /**< Length of name buffer */ - char __user *name; /**< Name of driver */ - DRM_SIZE_T date_len; /**< Length of date buffer */ - char __user *date; /**< User-space buffer to hold date */ - DRM_SIZE_T desc_len; /**< Length of desc buffer */ - char __user *desc; /**< User-space buffer to hold desc */ -} drm_version_t; - - -/** - * DRM_IOCTL_GET_UNIQUE ioctl argument type. - * - * \sa drmGetBusid() and drmSetBusId(). - */ -typedef struct drm_unique { - DRM_SIZE_T unique_len; /**< Length of unique */ - char __user *unique; /**< Unique name for driver instantiation */ -} drm_unique_t; - -#undef DRM_SIZE_T - -typedef struct drm_list { - int count; /**< Length of user-space structures */ - drm_version_t __user *version; -} drm_list_t; - - -typedef struct drm_block { - int unused; -} drm_block_t; - - -/** - * DRM_IOCTL_CONTROL ioctl argument type. - * - * \sa drmCtlInstHandler() and drmCtlUninstHandler(). - */ -typedef struct drm_control { - enum { - DRM_ADD_COMMAND, - DRM_RM_COMMAND, - DRM_INST_HANDLER, - DRM_UNINST_HANDLER - } func; - int irq; -} drm_control_t; - - -/** - * Type of memory to map. - */ -typedef enum drm_map_type { - _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */ - _DRM_REGISTERS = 1, /**< no caching, no core dump */ - _DRM_SHM = 2, /**< shared, cached */ - _DRM_AGP = 3, /**< AGP/GART */ - _DRM_SCATTER_GATHER = 4 /**< Scatter/gather memory for PCI DMA */ -} drm_map_type_t; - - -/** - * Memory mapping flags. - */ -typedef enum drm_map_flags { - _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */ - _DRM_READ_ONLY = 0x02, - _DRM_LOCKED = 0x04, /**< shared, cached, locked */ - _DRM_KERNEL = 0x08, /**< kernel requires access */ - _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */ - _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */ - _DRM_REMOVABLE = 0x40 /**< Removable mapping */ -} drm_map_flags_t; - - -typedef struct drm_ctx_priv_map { - unsigned int ctx_id; /**< Context requesting private mapping */ - void *handle; /**< Handle of map */ -} drm_ctx_priv_map_t; - - -/** - * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls - * argument type. - * - * \sa drmAddMap(). - */ -typedef struct drm_map { - unsigned long offset; /**< Requested physical address (0 for SAREA)*/ - unsigned long size; /**< Requested physical size (bytes) */ - drm_map_type_t type; /**< Type of memory to map */ - drm_map_flags_t flags; /**< Flags */ - void *handle; /**< User-space: "Handle" to pass to mmap() */ - /**< Kernel-space: kernel-virtual address */ - int mtrr; /**< MTRR slot used */ - /* Private data */ -} drm_map_t; - - -/** - * DRM_IOCTL_GET_CLIENT ioctl argument type. - */ -typedef struct drm_client { - int idx; /**< Which client desired? */ - int auth; /**< Is client authenticated? */ - unsigned long pid; /**< Process ID */ - unsigned long uid; /**< User ID */ - unsigned long magic; /**< Magic */ - unsigned long iocs; /**< Ioctl count */ -} drm_client_t; - - -typedef enum { - _DRM_STAT_LOCK, - _DRM_STAT_OPENS, - _DRM_STAT_CLOSES, - _DRM_STAT_IOCTLS, - _DRM_STAT_LOCKS, - _DRM_STAT_UNLOCKS, - _DRM_STAT_VALUE, /**< Generic value */ - _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */ - _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */ - - _DRM_STAT_IRQ, /**< IRQ */ - _DRM_STAT_PRIMARY, /**< Primary DMA bytes */ - _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */ - _DRM_STAT_DMA, /**< DMA */ - _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */ - _DRM_STAT_MISSED /**< Missed DMA opportunity */ - - /* Add to the *END* of the list */ -} drm_stat_type_t; - - -/** - * DRM_IOCTL_GET_STATS ioctl argument type. - */ -typedef struct drm_stats { - unsigned long count; - struct { - unsigned long value; - drm_stat_type_t type; - } data[15]; -} drm_stats_t; - - -/** - * Hardware locking flags. - */ -typedef enum drm_lock_flags { - _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */ - _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */ - _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */ - _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */ - /* These *HALT* flags aren't supported yet - -- they will be used to support the - full-screen DGA-like mode. */ - _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */ - _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */ -} drm_lock_flags_t; - - -/** - * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type. - * - * \sa drmGetLock() and drmUnlock(). - */ -typedef struct drm_lock { - int context; - drm_lock_flags_t flags; -} drm_lock_t; - - -/** - * DMA flags - * - * \warning - * These values \e must match xf86drm.h. - * - * \sa drm_dma. - */ -typedef enum drm_dma_flags { - /* Flags for DMA buffer dispatch */ - _DRM_DMA_BLOCK = 0x01, /**< - * Block until buffer dispatched. - * - * \note The buffer may not yet have - * been processed by the hardware -- - * getting a hardware lock with the - * hardware quiescent will ensure - * that the buffer has been - * processed. - */ - _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */ - _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */ - - /* Flags for DMA buffer request */ - _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */ - _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */ - _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */ -} drm_dma_flags_t; - - -/** - * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type. - * - * \sa drmAddBufs(). - */ -typedef struct drm_buf_desc { - int count; /**< Number of buffers of this size */ - int size; /**< Size in bytes */ - int low_mark; /**< Low water mark */ - int high_mark; /**< High water mark */ - enum { - _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */ - _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */ - _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */ - _DRM_FB_BUFFER = 0x08 /**< Buffer is in frame buffer */ - } flags; - unsigned long agp_start; /**< - * Start address of where the AGP buffers are - * in the AGP aperture - */ -} drm_buf_desc_t; - - -/** - * DRM_IOCTL_INFO_BUFS ioctl argument type. - */ -typedef struct drm_buf_info { - int count; /**< Number of buffers described in list */ - drm_buf_desc_t __user *list; /**< List of buffer descriptions */ -} drm_buf_info_t; - - -/** - * DRM_IOCTL_FREE_BUFS ioctl argument type. - */ -typedef struct drm_buf_free { - int count; - int __user *list; -} drm_buf_free_t; - - -/** - * Buffer information - * - * \sa drm_buf_map. - */ -typedef struct drm_buf_pub { - int idx; /**< Index into the master buffer list */ - int total; /**< Buffer size */ - int used; /**< Amount of buffer in use (for DMA) */ - void __user *address; /**< Address of buffer */ -} drm_buf_pub_t; - - -/** - * DRM_IOCTL_MAP_BUFS ioctl argument type. - */ -typedef struct drm_buf_map { - int count; /**< Length of the buffer list */ - void __user *virtual; /**< Mmap'd area in user-virtual */ - drm_buf_pub_t __user *list; /**< Buffer information */ -} drm_buf_map_t; - - -/** - * DRM_IOCTL_DMA ioctl argument type. - * - * Indices here refer to the offset into the buffer list in drm_buf_get. - * - * \sa drmDMA(). - */ -typedef struct drm_dma { - int context; /**< Context handle */ - int send_count; /**< Number of buffers to send */ - int __user *send_indices; /**< List of handles to buffers */ - int __user *send_sizes; /**< Lengths of data to send */ - drm_dma_flags_t flags; /**< Flags */ - int request_count; /**< Number of buffers requested */ - int request_size; /**< Desired size for buffers */ - int __user *request_indices; /**< Buffer information */ - int __user *request_sizes; - int granted_count; /**< Number of buffers granted */ -} drm_dma_t; - - -typedef enum { - _DRM_CONTEXT_PRESERVED = 0x01, - _DRM_CONTEXT_2DONLY = 0x02 -} drm_ctx_flags_t; - - -/** - * DRM_IOCTL_ADD_CTX ioctl argument type. - * - * \sa drmCreateContext() and drmDestroyContext(). - */ -typedef struct drm_ctx { - drm_context_t handle; - drm_ctx_flags_t flags; -} drm_ctx_t; - - -/** - * DRM_IOCTL_RES_CTX ioctl argument type. - */ -typedef struct drm_ctx_res { - int count; - drm_ctx_t __user *contexts; -} drm_ctx_res_t; - - -/** - * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type. - */ -typedef struct drm_draw { - drm_drawable_t handle; -} drm_draw_t; - - -/** - * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type. - */ -typedef struct drm_auth { - drm_magic_t magic; -} drm_auth_t; - - -/** - * DRM_IOCTL_IRQ_BUSID ioctl argument type. - * - * \sa drmGetInterruptFromBusID(). - */ -typedef struct drm_irq_busid { - int irq; /**< IRQ number */ - int busnum; /**< bus number */ - int devnum; /**< device number */ - int funcnum; /**< function number */ -} drm_irq_busid_t; - - -typedef enum { - _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ - _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ - _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking */ -} drm_vblank_seq_type_t; - - -#define _DRM_VBLANK_FLAGS_MASK _DRM_VBLANK_SIGNAL - - -struct drm_wait_vblank_request { - drm_vblank_seq_type_t type; - unsigned int sequence; - unsigned long signal; -}; - - -struct drm_wait_vblank_reply { - drm_vblank_seq_type_t type; - unsigned int sequence; - long tval_sec; - long tval_usec; -}; - - -/** - * DRM_IOCTL_WAIT_VBLANK ioctl argument type. - * - * \sa drmWaitVBlank(). - */ -typedef union drm_wait_vblank { - struct drm_wait_vblank_request request; - struct drm_wait_vblank_reply reply; -} drm_wait_vblank_t; - - -/** - * DRM_IOCTL_AGP_ENABLE ioctl argument type. - * - * \sa drmAgpEnable(). - */ -typedef struct drm_agp_mode { - unsigned long mode; /**< AGP mode */ -} drm_agp_mode_t; - - -/** - * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type. - * - * \sa drmAgpAlloc() and drmAgpFree(). - */ -typedef struct drm_agp_buffer { - unsigned long size; /**< In bytes -- will round to page boundary */ - unsigned long handle; /**< Used for binding / unbinding */ - unsigned long type; /**< Type of memory to allocate */ - unsigned long physical; /**< Physical used by i810 */ -} drm_agp_buffer_t; - - -/** - * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type. - * - * \sa drmAgpBind() and drmAgpUnbind(). - */ -typedef struct drm_agp_binding { - unsigned long handle; /**< From drm_agp_buffer */ - unsigned long offset; /**< In bytes -- will round to page boundary */ -} drm_agp_binding_t; - - -/** - * DRM_IOCTL_AGP_INFO ioctl argument type. - * - * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(), - * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(), - * drmAgpVendorId() and drmAgpDeviceId(). - */ -typedef struct drm_agp_info { - int agp_version_major; - int agp_version_minor; - unsigned long mode; - unsigned long aperture_base; /**< physical address */ - unsigned long aperture_size; /**< bytes */ - unsigned long memory_allowed; /**< bytes */ - unsigned long memory_used; - - /** \name PCI information */ - /*@{*/ - unsigned short id_vendor; - unsigned short id_device; - /*@}*/ -} drm_agp_info_t; - - -/** - * DRM_IOCTL_SG_ALLOC ioctl argument type. - */ -typedef struct drm_scatter_gather { - unsigned long size; /**< In bytes -- will round to page boundary */ - unsigned long handle; /**< Used for mapping / unmapping */ -} drm_scatter_gather_t; - -/** - * DRM_IOCTL_SET_VERSION ioctl argument type. - */ -typedef struct drm_set_version { - int drm_di_major; - int drm_di_minor; - int drm_dd_major; - int drm_dd_minor; -} drm_set_version_t; - - -/** - * \name Ioctls Definitions - */ -/*@{*/ - -#define DRM_IOCTL_BASE 'd' -#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr) -#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type) -#define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type) -#define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type) - -#define DRM_IOCTL_VERSION DRM_IOWR(0x00, drm_version_t) -#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, drm_unique_t) -#define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, drm_auth_t) -#define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, drm_irq_busid_t) -#define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, drm_map_t) -#define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, drm_client_t) -#define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, drm_stats_t) -#define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, drm_set_version_t) - -#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, drm_unique_t) -#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, drm_auth_t) -#define DRM_IOCTL_BLOCK DRM_IOWR(0x12, drm_block_t) -#define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, drm_block_t) -#define DRM_IOCTL_CONTROL DRM_IOW( 0x14, drm_control_t) -#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, drm_map_t) -#define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, drm_buf_desc_t) -#define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, drm_buf_desc_t) -#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, drm_buf_info_t) -#define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, drm_buf_map_t) -#define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, drm_buf_free_t) - -#define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, drm_map_t) - -#define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, drm_ctx_priv_map_t) -#define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, drm_ctx_priv_map_t) - -#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, drm_ctx_t) -#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, drm_ctx_t) -#define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, drm_ctx_t) -#define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, drm_ctx_t) -#define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, drm_ctx_t) -#define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, drm_ctx_t) -#define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, drm_ctx_res_t) -#define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, drm_draw_t) -#define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, drm_draw_t) -#define DRM_IOCTL_DMA DRM_IOWR(0x29, drm_dma_t) -#define DRM_IOCTL_LOCK DRM_IOW( 0x2a, drm_lock_t) -#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, drm_lock_t) -#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, drm_lock_t) - -#define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30) -#define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31) -#define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, drm_agp_mode_t) -#define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, drm_agp_info_t) -#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, drm_agp_buffer_t) -#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, drm_agp_buffer_t) -#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, drm_agp_binding_t) -#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, drm_agp_binding_t) - -#define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, drm_scatter_gather_t) -#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, drm_scatter_gather_t) - -#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, drm_wait_vblank_t) - -/*@}*/ - - -/** - * Device specific ioctls should only be in their respective headers - * The device specific ioctl range is from 0x40 to 0x79. - * - * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and - * drmCommandReadWrite(). - */ -#define DRM_COMMAND_BASE 0x40 - -#endif diff --git a/nx-X11/extras/drm/shared/drm_pciids.txt b/nx-X11/extras/drm/shared/drm_pciids.txt deleted file mode 100644 index e03d71b6b..000000000 --- a/nx-X11/extras/drm/shared/drm_pciids.txt +++ /dev/null @@ -1,211 +0,0 @@ -[radeon] -0x1002 0x4136 CHIP_RS100|CHIP_IS_IGP "ATI Radeon RS100 IGP 320M" -0x1002 0x4137 CHIP_RS200|CHIP_IS_IGP "ATI Radeon RS200 IGP" -0x1002 0x4144 CHIP_R300 "ATI Radeon AD 9500 Pro" -0x1002 0x4145 CHIP_R300 "ATI Radeon AE 9700 Pro" -0x1002 0x4146 CHIP_R300 "ATI Radeon AF 9700 Pro" -0x1002 0x4147 CHIP_R300 "ATI FireGL AG Z1/X1" -0x1002 0x4150 CHIP_RV350 "ATI Radeon AP 9600" -0x1002 0x4151 CHIP_RV350 "ATI Radeon AQ 9600" -0x1002 0x4152 CHIP_RV350 "ATI Radeon AR 9600" -0x1002 0x4153 CHIP_RV350 "ATI Radeon AS 9600 AS" -0x1002 0x4154 CHIP_RV350 "ATI FireGL AT T2" -0x1002 0x4156 CHIP_RV350 "ATI FireGL AV T2" -0x1002 0x4237 CHIP_RS250|CHIP_IS_IGP "ATI Radeon RS250 IGP" -0x1002 0x4242 CHIP_R200 "ATI Radeon BB R200 AIW 8500DV" -0x1002 0x4243 CHIP_R200 "ATI Radeon BC R200" -0x1002 0x4336 CHIP_RS100|CHIP_IS_IGP|CHIP_IS_MOBILITY "ATI Radeon RS100 Mobility U1" -0x1002 0x4337 CHIP_RS200|CHIP_IS_IGP|CHIP_IS_MOBILITY "ATI Radeon RS200 Mobility IGP 340M" -0x1002 0x4437 CHIP_RS250|CHIP_IS_IGP|CHIP_IS_MOBILITY "ATI Radeon RS250 Mobility IGP" -0x1002 0x4964 CHIP_R250 "ATI Radeon Id R250 9000" -0x1002 0x4965 CHIP_R250 "ATI Radeon Ie R250 9000" -0x1002 0x4966 CHIP_R250 "ATI Radeon If R250 9000" -0x1002 0x4967 CHIP_R250 "ATI Radeon Ig R250 9000" -0x1002 0x4C57 CHIP_RV200|CHIP_IS_MOBILITY "ATI Radeon LW RV200 Mobility 7500 M7" -0x1002 0x4C58 CHIP_RV200|CHIP_IS_MOBILITY "ATI Radeon LX RV200 Mobility FireGL 7800 M7" -0x1002 0x4C59 CHIP_RV100|CHIP_IS_MOBILITY "ATI Radeon LY RV100 Mobility M6" -0x1002 0x4C5A CHIP_RV100|CHIP_IS_MOBILITY "ATI Radeon LZ RV100 Mobility M6" -0x1002 0x4C64 CHIP_R250|CHIP_IS_MOBILITY "ATI Radeon Ld R250 Mobility 9000 M9" -0x1002 0x4C65 CHIP_R250|CHIP_IS_MOBILITY "ATI Radeon Le R250 Mobility 9000 M9" -0x1002 0x4C66 CHIP_R250|CHIP_IS_MOBILITY "ATI Radeon Lf R250 Mobility 9000 M9" -0x1002 0x4C67 CHIP_R250|CHIP_IS_MOBILITY "ATI Radeon Lg R250 Mobility 9000 M9" -0x1002 0x4E50 CHIP_RV350|CHIP_IS_MOBILITY "ATI Radeon RV300 Mobility 9600 M10" -0x1002 0x5144 CHIP_R100|CHIP_SINGLE_CRTC "ATI Radeon QD R100" -0x1002 0x5145 CHIP_R100|CHIP_SINGLE_CRTC "ATI Radeon QE R100" -0x1002 0x5146 CHIP_R100|CHIP_SINGLE_CRTC "ATI Radeon QF R100" -0x1002 0x5147 CHIP_R100|CHIP_SINGLE_CRTC "ATI Radeon QG R100" -0x1002 0x5148 CHIP_R200 "ATI Radeon QH R200 8500" -0x1002 0x5149 CHIP_R200 "ATI Radeon QI R200" -0x1002 0x514A CHIP_R200 "ATI Radeon QJ R200" -0x1002 0x514B CHIP_R200 "ATI Radeon QK R200" -0x1002 0x514C CHIP_R200 "ATI Radeon QL R200 8500 LE" -0x1002 0x514D CHIP_R200 "ATI Radeon QM R200 9100" -0x1002 0x514E CHIP_R200 "ATI Radeon QN R200 8500 LE" -0x1002 0x514F CHIP_R200 "ATI Radeon QO R200 8500 LE" -0x1002 0x5157 CHIP_RV200 "ATI Radeon QW RV200 7500" -0x1002 0x5158 CHIP_RV200 "ATI Radeon QX RV200 7500" -0x1002 0x5159 CHIP_RV100 "ATI Radeon QY RV100 7000/VE" -0x1002 0x515A CHIP_RV100 "ATI Radeon QZ RV100 7000/VE" -0x1002 0x515E CHIP_RV100 "ATI ES1000 RN50" -0x1002 0x5168 CHIP_R200 "ATI Radeon Qh R200" -0x1002 0x5169 CHIP_R200 "ATI Radeon Qi R200" -0x1002 0x516A CHIP_R200 "ATI Radeon Qj R200" -0x1002 0x516B CHIP_R200 "ATI Radeon Qk R200" -0x1002 0x516C CHIP_R200 "ATI Radeon Ql R200" -0x1002 0x5834 CHIP_RS300|CHIP_IS_IGP "ATI Radeon RS300 IGP" -0x1002 0x5835 CHIP_RS300|CHIP_IS_IGP|CHIP_IS_MOBILITY "ATI Radeon RS300 Mobility IGP" -0x1002 0x5836 CHIP_RS300|CHIP_IS_IGP "ATI Radeon RS300 IGP" -0x1002 0x5837 CHIP_RS300|CHIP_IS_IGP "ATI Radeon RS300 IGP" -0x1002 0x5960 CHIP_RV280 "ATI Radeon RV280 9200" -0x1002 0x5961 CHIP_RV280 "ATI Radeon RV280 9200 SE" -0x1002 0x5962 CHIP_RV280 "ATI Radeon RV280 9200" -0x1002 0x5963 CHIP_RV280 "ATI Radeon RV280 9200" -0x1002 0x5964 CHIP_RV280 "ATI Radeon RV280 9200 SE" -0x1002 0x5968 CHIP_RV280 "ATI Radeon RV280 9200" -0x1002 0x5969 CHIP_RV100 "ATI ES1000 RN50" -0x1002 0x596A CHIP_RV280 "ATI Radeon RV280 9200" -0x1002 0x596B CHIP_RV280 "ATI Radeon RV280 9200" -0x1002 0x5c61 CHIP_RV280|CHIP_IS_MOBILITY "ATI Radeon RV280 Mobility" -0x1002 0x5c62 CHIP_RV280 "ATI Radeon RV280" -0x1002 0x5c63 CHIP_RV280|CHIP_IS_MOBILITY "ATI Radeon RV280 Mobility" -0x1002 0x5c64 CHIP_RV280 "ATI Radeon RV280" - -[r128] -0x1002 0x4c45 0 "ATI Rage 128 Mobility LE (PCI)" -0x1002 0x4c46 0 "ATI Rage 128 Mobility LF (AGP)" -0x1002 0x4d46 0 "ATI Rage 128 Mobility MF (AGP)" -0x1002 0x4d4c 0 "ATI Rage 128 Mobility ML (AGP)" -0x1002 0x5041 0 "ATI Rage 128 Pro PA (PCI)" -0x1002 0x5042 0 "ATI Rage 128 Pro PB (AGP)" -0x1002 0x5043 0 "ATI Rage 128 Pro PC (AGP)" -0x1002 0x5044 0 "ATI Rage 128 Pro PD (PCI)" -0x1002 0x5045 0 "ATI Rage 128 Pro PE (AGP)" -0x1002 0x5046 0 "ATI Rage 128 Pro PF (AGP)" -0x1002 0x5047 0 "ATI Rage 128 Pro PG (PCI)" -0x1002 0x5048 0 "ATI Rage 128 Pro PH (AGP)" -0x1002 0x5049 0 "ATI Rage 128 Pro PI (AGP)" -0x1002 0x504A 0 "ATI Rage 128 Pro PJ (PCI)" -0x1002 0x504B 0 "ATI Rage 128 Pro PK (AGP)" -0x1002 0x504C 0 "ATI Rage 128 Pro PL (AGP)" -0x1002 0x504D 0 "ATI Rage 128 Pro PM (PCI)" -0x1002 0x504E 0 "ATI Rage 128 Pro PN (AGP)" -0x1002 0x504F 0 "ATI Rage 128 Pro PO (AGP)" -0x1002 0x5050 0 "ATI Rage 128 Pro PP (PCI)" -0x1002 0x5051 0 "ATI Rage 128 Pro PQ (AGP)" -0x1002 0x5052 0 "ATI Rage 128 Pro PR (PCI)" -0x1002 0x5053 0 "ATI Rage 128 Pro PS (PCI)" -0x1002 0x5054 0 "ATI Rage 128 Pro PT (AGP)" -0x1002 0x5055 0 "ATI Rage 128 Pro PU (AGP)" -0x1002 0x5056 0 "ATI Rage 128 Pro PV (PCI)" -0x1002 0x5057 0 "ATI Rage 128 Pro PW (AGP)" -0x1002 0x5058 0 "ATI Rage 128 Pro PX (AGP)" -0x1002 0x5245 0 "ATI Rage 128 RE (PCI)" -0x1002 0x5246 0 "ATI Rage 128 RF (AGP)" -0x1002 0x5247 0 "ATI Rage 128 RG (AGP)" -0x1002 0x524b 0 "ATI Rage 128 RK (PCI)" -0x1002 0x524c 0 "ATI Rage 128 RL (AGP)" -0x1002 0x534d 0 "ATI Rage 128 SM (AGP)" -0x1002 0x5446 0 "ATI Rage 128 Pro Ultra TF (AGP)" -0x1002 0x544C 0 "ATI Rage 128 Pro Ultra TL (AGP)" -0x1002 0x5452 0 "ATI Rage 128 Pro Ultra TR (AGP)" - -[mga] -0x102b 0x0521 0 "Matrox G200 (AGP)" -0x102b 0x0525 0 "Matrox G400/G450 (AGP)" -0x102b 0x2527 0 "Matrox G550 (AGP)" - -[mach64] -0x1002 0x4749 0 "3D Rage Pro" -0x1002 0x4750 0 "3D Rage Pro 215GP" -0x1002 0x4751 0 "3D Rage Pro 215GQ" -0x1002 0x4742 0 "3D Rage Pro AGP 1X/2X" -0x1002 0x4744 0 "3D Rage Pro AGP 1X" -0x1002 0x4c49 0 "3D Rage LT Pro" -0x1002 0x4c50 0 "3D Rage LT Pro" -0x1002 0x4c51 0 "3D Rage LT Pro" -0x1002 0x4c42 0 "3D Rage LT Pro AGP-133" -0x1002 0x4c44 0 "3D Rage LT Pro AGP-66" -0x1002 0x474c 0 "Rage XC" -0x1002 0x474f 0 "Rage XL" -0x1002 0x4752 0 "Rage XL" -0x1002 0x4753 0 "Rage XC" -0x1002 0x474d 0 "Rage XL AGP 2X" -0x1002 0x474e 0 "Rage XC AGP" -0x1002 0x4c52 0 "Rage Mobility P/M" -0x1002 0x4c53 0 "Rage Mobility L" -0x1002 0x4c4d 0 "Rage Mobility P/M AGP 2X" -0x1002 0x4c4e 0 "Rage Mobility L AGP 2X" - -[sisdrv] -0x1039 0x0300 0 "SiS 300/305" -0x1039 0x5300 0 "SiS 540" -0x1039 0x6300 0 "SiS 630" -0x1039 0x7300 0 "SiS 730" - -[tdfx] -0x121a 0x0003 0 "3dfx Voodoo Banshee" -0x121a 0x0004 0 "3dfx Voodoo3 2000" -0x121a 0x0005 0 "3dfx Voodoo3 3000" -0x121a 0x0007 0 "3dfx Voodoo4 4500" -0x121a 0x0009 0 "3dfx Voodoo5 5500" -0x121a 0x000b 0 "3dfx Voodoo4 4200" - -[viadrv] -0x1106 0x3022 0 "VIA CLE266 3022" -0x1106 0x3118 0 "VIA CN400 / PM8X0" -0x1106 0x3122 0 "VIA CLE266" -0x1106 0x7205 0 "VIA KM400" -0x1106 0x3108 0 "VIA K8M800" - -[i810] -0x8086 0x7121 0 "Intel i810 GMCH" -0x8086 0x7123 0 "Intel i810-DC100 GMCH" -0x8086 0x7125 0 "Intel i810E GMCH" -0x8086 0x1132 0 "Intel i815 GMCH" - -[i830] -0x8086 0x3577 0 "Intel i830M GMCH" -0x8086 0x2562 0 "Intel i845G GMCH" -0x8086 0x3582 0 "Intel i852GM/i855GM GMCH" -0x8086 0x2572 0 "Intel i865G GMCH" - -[gamma] -0x3d3d 0x0008 0 "3DLabs GLINT Gamma G1" - -[savage] -0x5333 0x8a20 S3_SAVAGE3D "Savage 3D" -0x5333 0x8a21 S3_SAVAGE3D "Savage 3D/MV" -0x5333 0x8a22 S3_SAVAGE4 "Savage4" -0x5333 0x8a23 S3_SAVAGE4 "Savage4" -0x5333 0x8c10 S3_SAVAGE_MX "Savage/MX-MV" -0x5333 0x8c11 S3_SAVAGE_MX "Savage/MX" -0x5333 0x8c12 S3_SAVAGE_MX "Savage/IX-MV" -0x5333 0x8c13 S3_SAVAGE_MX "Savage/IX" -0x5333 0x8c22 S3_SUPERSAVAGE "SuperSavage MX/128" -0x5333 0x8c24 S3_SUPERSAVAGE "SuperSavage MX/64" -0x5333 0x8c26 S3_SUPERSAVAGE "SuperSavage MX/64C" -0x5333 0x8c2a S3_SUPERSAVAGE "SuperSavage IX/128 SDR" -0x5333 0x8c2b S3_SUPERSAVAGE "SuperSavage IX/128 DDR" -0x5333 0x8c2c S3_SUPERSAVAGE "SuperSavage IX/64 SDR" -0x5333 0x8c2d S3_SUPERSAVAGE "SuperSavage IX/64 DDR" -0x5333 0x8c2e S3_SUPERSAVAGE "SuperSavage IX/C SDR" -0x5333 0x8c2f S3_SUPERSAVAGE "SuperSavage IX/C DDR" -0x5333 0x8a25 S3_PROSAVAGE "ProSavage PM133" -0x5333 0x8a26 S3_PROSAVAGE "ProSavage KM133" -0x5333 0x8d01 S3_TWISTER "ProSavage Twister PN133" -0x5333 0x8d02 S3_TWISTER "ProSavage Twister KN133" -0x5333 0x8d03 S3_PROSAVAGEDDR "ProSavage DDR" -0x5333 0x8d04 S3_PROSAVAGEDDR "ProSavage DDR-K" - -[ffb] - -[i915] -0x8086 0x3577 0 "Intel i830M GMCH" -0x8086 0x2562 0 "Intel i845G GMCH" -0x8086 0x3582 0 "Intel i852GM/i855GM GMCH" -0x8086 0x2572 0 "Intel i865G GMCH" -0x8086 0x2582 0 "Intel i915G" -0x8086 0x2592 0 "Intel i915GM" -0x8086 0x2772 0 "Intel i945G" - - diff --git a/nx-X11/extras/drm/shared/drm_sarea.h b/nx-X11/extras/drm/shared/drm_sarea.h deleted file mode 100644 index 40f7d5f19..000000000 --- a/nx-X11/extras/drm/shared/drm_sarea.h +++ /dev/null @@ -1,78 +0,0 @@ -/** - * \file drm_sarea.h - * \brief SAREA definitions - * - * \author Michel D�zer - */ - -/* - * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DRM_SAREA_H_ -#define _DRM_SAREA_H_ - -#include "drm.h" - -/* SAREA area needs to be at least a page */ -#if defined(__alpha__) -#define SAREA_MAX 0x2000 -#elif defined(__ia64__) -#define SAREA_MAX 0x10000 /* 64kB */ -#else -/* Intel 830M driver needs at least 8k SAREA */ -#define SAREA_MAX 0x2000 -#endif - -/** Maximum number of drawables in the SAREA */ -#define SAREA_MAX_DRAWABLES 256 - -#define SAREA_DRAWABLE_CLAIMED_ENTRY 0x80000000 - -/** SAREA drawable */ -typedef struct drm_sarea_drawable { - unsigned int stamp; - unsigned int flags; -} drm_sarea_drawable_t; - -/** SAREA frame */ -typedef struct drm_sarea_frame { - unsigned int x; - unsigned int y; - unsigned int width; - unsigned int height; - unsigned int fullscreen; -} drm_sarea_frame_t; - -/** SAREA */ -typedef struct drm_sarea { - /** first thing is always the DRM locking structure */ - drm_hw_lock_t lock; - /** \todo Use readers/writer lock for drm_sarea::drawable_lock */ - drm_hw_lock_t drawable_lock; - drm_sarea_drawable_t drawableTable[SAREA_MAX_DRAWABLES]; /**< drawables */ - drm_sarea_frame_t frame; /**< frame */ - drm_context_t dummy_context; -} drm_sarea_t; - -#endif /* _DRM_SAREA_H_ */ diff --git a/nx-X11/extras/drm/shared/i915.h b/nx-X11/extras/drm/shared/i915.h deleted file mode 100644 index 360665ae9..000000000 --- a/nx-X11/extras/drm/shared/i915.h +++ /dev/null @@ -1,49 +0,0 @@ -/* i915.h -- Intel I915 DRM template customization -*- linux-c -*- - */ -/************************************************************************** - * - * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. - * All Rights Reserved. - * - **************************************************************************/ - -#ifndef __I915_H__ -#define __I915_H__ - -/* This remains constant for all DRM template files. - */ -#define DRM(x) i915_##x - -/* General customization: - */ - -#define DRIVER_AUTHOR "Tungsten Graphics, Inc." - -#define DRIVER_NAME "i915" -#define DRIVER_DESC "Intel Graphics" -#define DRIVER_DATE "20041217" - -/* Interface history: - * - * 1.1: Original. - * 1.2: Add Power Management - */ -#define DRIVER_MAJOR 1 -#define DRIVER_MINOR 2 -#define DRIVER_PATCHLEVEL 0 - -#define DRIVER_IOCTLS \ - [DRM_IOCTL_NR(DRM_IOCTL_I915_INIT)] = { i915_dma_init, 1, 1 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_I915_FLUSH)] = { i915_flush_ioctl, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_I915_FLIP)] = { i915_flip_bufs, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_I915_BATCHBUFFER)] = { i915_batchbuffer, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_I915_IRQ_EMIT)] = { i915_irq_emit, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_I915_IRQ_WAIT)] = { i915_irq_wait, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_I915_GETPARAM)] = { i915_getparam, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_I915_SETPARAM)] = { i915_setparam, 1, 1 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_I915_ALLOC)] = { i915_mem_alloc, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_I915_FREE)] = { i915_mem_free, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_I915_INIT_HEAP)] = { i915_mem_init_heap, 1, 1 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_I915_CMDBUFFER)] = { i915_cmdbuffer, 1, 0 } - -#endif diff --git a/nx-X11/extras/drm/shared/i915_dma.c b/nx-X11/extras/drm/shared/i915_dma.c deleted file mode 100644 index 14f7fd6eb..000000000 --- a/nx-X11/extras/drm/shared/i915_dma.c +++ /dev/null @@ -1,769 +0,0 @@ -/* i915_dma.c -- DMA support for the I915 -*- linux-c -*- - */ -/************************************************************************** - * - * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. - * All Rights Reserved. - * - **************************************************************************/ - -#include "i915.h" -#include "drmP.h" -#include "drm.h" -#include "i915_drm.h" -#include "i915_drv.h" - -static inline void i915_print_status_page(drm_device_t * dev) -{ - drm_i915_private_t *dev_priv = dev->dev_private; - u32 *temp = dev_priv->hw_status_page; - - if (!temp) { - DRM_DEBUG("no status page\n"); - return; - } - - DRM_DEBUG("hw_status: Interrupt Status : %x\n", temp[0]); - DRM_DEBUG("hw_status: LpRing Head ptr : %x\n", temp[1]); - DRM_DEBUG("hw_status: IRing Head ptr : %x\n", temp[2]); - DRM_DEBUG("hw_status: Reserved : %x\n", temp[3]); - DRM_DEBUG("hw_status: Driver Counter : %d\n", temp[5]); - -} - -/* Really want an OS-independent resettable timer. Would like to have - * this loop run for (eg) 3 sec, but have the timer reset every time - * the head pointer changes, so that EBUSY only happens if the ring - * actually stalls for (eg) 3 seconds. - */ -int i915_wait_ring(drm_device_t * dev, int n, const char *caller) -{ - drm_i915_private_t *dev_priv = dev->dev_private; - drm_i915_ring_buffer_t *ring = &(dev_priv->ring); - u32 last_head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR; - int i; - - for (i = 0; i < 10000; i++) { - ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR; - ring->space = ring->head - (ring->tail + 8); - if (ring->space < 0) - ring->space += ring->Size; - if (ring->space >= n) - return 0; - - dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; - - if (ring->head != last_head) - i = 0; - - last_head = ring->head; - } - - return DRM_ERR(EBUSY); -} - -void i915_kernel_lost_context(drm_device_t * dev) -{ - drm_i915_private_t *dev_priv = dev->dev_private; - drm_i915_ring_buffer_t *ring = &(dev_priv->ring); - - ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR; - ring->tail = I915_READ(LP_RING + RING_TAIL) & TAIL_ADDR; - ring->space = ring->head - (ring->tail + 8); - if (ring->space < 0) - ring->space += ring->Size; - - if (ring->head == ring->tail) - dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY; -} - -int i915_dma_cleanup(drm_device_t * dev) -{ - /* Make sure interrupts are disabled here because the uninstall ioctl - * may not have been called from userspace and after dev_private - * is freed, it's too late. - */ - if (dev->irq) - DRM(irq_uninstall) (dev); - - if (dev->dev_private) { - drm_i915_private_t *dev_priv = - (drm_i915_private_t *) dev->dev_private; - - if (dev_priv->ring.virtual_start) { - drm_core_ioremapfree(&dev_priv->ring.map, dev); - } - - if (dev_priv->hw_status_page) { -#ifdef __FreeBSD__ -#if __FreeBSD_version > 500000 - contigfree(dev_priv->hw_status_page, PAGE_SIZE, M_DRM); -#endif -#else - pci_free_consistent(dev->pdev, PAGE_SIZE, - dev_priv->hw_status_page, - dev_priv->dma_status_page); -#endif - /* Need to rewrite hardware status page */ - I915_WRITE(0x02080, 0x1ffff000); - } - - DRM(free) (dev->dev_private, sizeof(drm_i915_private_t), - DRM_MEM_DRIVER); - - dev->dev_private = NULL; - } - - return 0; -} - -static int i915_initialize(drm_device_t * dev, - drm_i915_private_t * dev_priv, - drm_i915_init_t * init) -{ - memset(dev_priv, 0, sizeof(drm_i915_private_t)); - - DRM_GETSAREA(); - if (!dev_priv->sarea) { - DRM_ERROR("can not find sarea!\n"); - dev->dev_private = (void *)dev_priv; - i915_dma_cleanup(dev); - return DRM_ERR(EINVAL); - } - - dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset); - if (!dev_priv->mmio_map) { - dev->dev_private = (void *)dev_priv; - i915_dma_cleanup(dev); - DRM_ERROR("can not find mmio map!\n"); - return DRM_ERR(EINVAL); - } - - dev_priv->sarea_priv = (drm_i915_sarea_t *) - ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset); - - dev_priv->ring.Start = init->ring_start; - dev_priv->ring.End = init->ring_end; - dev_priv->ring.Size = init->ring_size; - dev_priv->ring.tail_mask = dev_priv->ring.Size - 1; - - dev_priv->ring.map.offset = init->ring_start; - dev_priv->ring.map.size = init->ring_size; - dev_priv->ring.map.type = 0; - dev_priv->ring.map.flags = 0; - dev_priv->ring.map.mtrr = 0; - - drm_core_ioremap(&dev_priv->ring.map, dev); - - if (dev_priv->ring.map.handle == NULL) { - dev->dev_private = (void *)dev_priv; - i915_dma_cleanup(dev); - DRM_ERROR("can not ioremap virtual address for" - " ring buffer\n"); - return DRM_ERR(ENOMEM); - } - - dev_priv->ring.virtual_start = dev_priv->ring.map.handle; - - dev_priv->back_offset = init->back_offset; - dev_priv->front_offset = init->front_offset; - dev_priv->current_page = 0; - dev_priv->sarea_priv->pf_current_page = dev_priv->current_page; - - /* We are using separate values as placeholders for mechanisms for - * private backbuffer/depthbuffer usage. - */ - dev_priv->use_mi_batchbuffer_start = 0; - - /* Allow hardware batchbuffers unless told otherwise. - */ - dev_priv->allow_batchbuffer = 1; - - /* Program Hardware Status Page */ -#ifdef __FreeBSD__ - dev_priv->hw_status_page = - contigmalloc(PAGE_SIZE, DRM(M_DRM), M_NOWAIT, 0ul, 0, 0, 0); - dev_priv->dma_status_page = vtophys(dev_priv->hw_status_page); -#else - dev_priv->hw_status_page = - pci_alloc_consistent(dev->pdev, PAGE_SIZE, - &dev_priv->dma_status_page); -#endif - - if (!dev_priv->hw_status_page) { - dev->dev_private = (void *)dev_priv; - i915_dma_cleanup(dev); - DRM_ERROR("Can not allocate hardware status page\n"); - return DRM_ERR(ENOMEM); - } - memset(dev_priv->hw_status_page, 0, PAGE_SIZE); - DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page); - - I915_WRITE(0x02080, dev_priv->dma_status_page); - DRM_DEBUG("Enabled hardware status page\n"); - - dev->dev_private = (void *)dev_priv; - - return 0; -} - -static int i915_dma_resume(drm_device_t * dev) -{ - drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; - - DRM_DEBUG("%s\n", __FUNCTION__); - - if (!dev_priv->sarea) { - DRM_ERROR("can not find sarea!\n"); - return DRM_ERR(EINVAL); - } - - if (!dev_priv->mmio_map) { - DRM_ERROR("can not find mmio map!\n"); - return DRM_ERR(EINVAL); - } - - if (dev_priv->ring.map.handle == NULL) { - DRM_ERROR("can not ioremap virtual address for" - " ring buffer\n"); - return DRM_ERR(ENOMEM); - } - - /* Program Hardware Status Page */ - if (!dev_priv->hw_status_page) { - DRM_ERROR("Can not find hardware status page\n"); - return DRM_ERR(EINVAL); - } - DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page); - - I915_WRITE(0x02080, dev_priv->dma_status_page); - DRM_DEBUG("Enabled hardware status page\n"); - - return 0; -} - -int i915_dma_init(DRM_IOCTL_ARGS) -{ - DRM_DEVICE; - drm_i915_private_t *dev_priv; - drm_i915_init_t init; - int retcode = 0; - - DRM_COPY_FROM_USER_IOCTL(init, (drm_i915_init_t __user *) data, - sizeof(init)); - - switch (init.func) { - case I915_INIT_DMA: - dev_priv = DRM(alloc) (sizeof(drm_i915_private_t), - DRM_MEM_DRIVER); - if (dev_priv == NULL) - return DRM_ERR(ENOMEM); - retcode = i915_initialize(dev, dev_priv, &init); - break; - case I915_CLEANUP_DMA: - retcode = i915_dma_cleanup(dev); - break; - case I915_RESUME_DMA: - retcode = i915_dma_resume(dev); - break; - default: - retcode = -EINVAL; - break; - } - - return retcode; -} - -/* Implement basically the same security restrictions as hardware does - * for MI_BATCH_NON_SECURE. These can be made stricter at any time. - * - * Most of the calculations below involve calculating the size of a - * particular instruction. It's important to get the size right as - * that tells us where the next instruction to check is. Any illegal - * instruction detected will be given a size of zero, which is a - * signal to abort the rest of the buffer. - */ -static int do_validate_cmd(int cmd) -{ - switch (((cmd >> 29) & 0x7)) { - case 0x0: - switch ((cmd >> 23) & 0x3f) { - case 0x0: - return 1; /* MI_NOOP */ - case 0x4: - return 1; /* MI_FLUSH */ - default: - return 0; /* disallow everything else */ - } - break; - case 0x1: - return 0; /* reserved */ - case 0x2: - return (cmd & 0xff) + 2; /* 2d commands */ - case 0x3: - if (((cmd >> 24) & 0x1f) <= 0x18) - return 1; - - switch ((cmd >> 24) & 0x1f) { - case 0x1c: - return 1; - case 0x1d: - switch ((cmd >> 16) & 0xff) { - case 0x3: - return (cmd & 0x1f) + 2; - case 0x4: - return (cmd & 0xf) + 2; - default: - return (cmd & 0xffff) + 2; - } - case 0x1e: - if (cmd & (1 << 23)) - return (cmd & 0xffff) + 1; - else - return 1; - case 0x1f: - if ((cmd & (1 << 23)) == 0) /* inline vertices */ - return (cmd & 0x1ffff) + 2; - else if (cmd & (1 << 17)) /* indirect random */ - if ((cmd & 0xffff) == 0) - return 0; /* unknown length, too hard */ - else - return (((cmd & 0xffff) + 1) / 2) + 1; - else - return 2; /* indirect sequential */ - default: - return 0; - } - default: - return 0; - } - - return 0; -} - -static int validate_cmd(int cmd) -{ - int ret = do_validate_cmd(cmd); - -/* printk("validate_cmd( %x ): %d\n", cmd, ret); */ - - return ret; -} - -static int i915_emit_cmds(drm_device_t * dev, int __user * buffer, int dwords) -{ - drm_i915_private_t *dev_priv = dev->dev_private; - int i; - RING_LOCALS; - - for (i = 0; i < dwords;) { - int cmd, sz; - - if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd))) - return DRM_ERR(EINVAL); - -/* printk("%d/%d ", i, dwords); */ - - if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords) - return DRM_ERR(EINVAL); - - BEGIN_LP_RING(sz); - OUT_RING(cmd); - - while (++i, --sz) { - if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], - sizeof(cmd))) { - return DRM_ERR(EINVAL); - } - OUT_RING(cmd); - } - ADVANCE_LP_RING(); - } - - return 0; -} - -static int i915_emit_box(drm_device_t * dev, - drm_clip_rect_t __user * boxes, - int i, int DR1, int DR4) -{ - drm_i915_private_t *dev_priv = dev->dev_private; - drm_clip_rect_t box; - RING_LOCALS; - - if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) { - return EFAULT; - } - - if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) { - DRM_ERROR("Bad box %d,%d..%d,%d\n", - box.x1, box.y1, box.x2, box.y2); - return DRM_ERR(EINVAL); - } - - BEGIN_LP_RING(6); - OUT_RING(GFX_OP_DRAWRECT_INFO); - OUT_RING(DR1); - OUT_RING((box.x1 & 0xffff) | (box.y1 << 16)); - OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16)); - OUT_RING(DR4); - OUT_RING(0); - ADVANCE_LP_RING(); - - return 0; -} - -static int i915_dispatch_cmdbuffer(drm_device_t * dev, - drm_i915_cmdbuffer_t * cmd) -{ - int nbox = cmd->num_cliprects; - int i = 0, count, ret; - - if (cmd->sz & 0x3) { - DRM_ERROR("alignment"); - return DRM_ERR(EINVAL); - } - - i915_kernel_lost_context(dev); - - count = nbox ? nbox : 1; - - for (i = 0; i < count; i++) { - if (i < nbox) { - ret = i915_emit_box(dev, cmd->cliprects, i, - cmd->DR1, cmd->DR4); - if (ret) - return ret; - } - - ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4); - if (ret) - return ret; - } - - return 0; -} - -static int i915_dispatch_batchbuffer(drm_device_t * dev, - drm_i915_batchbuffer_t * batch) -{ - drm_i915_private_t *dev_priv = dev->dev_private; - drm_clip_rect_t __user *boxes = batch->cliprects; - int nbox = batch->num_cliprects; - int i = 0, count; - RING_LOCALS; - - if ((batch->start | batch->used) & 0x7) { - DRM_ERROR("alignment"); - return DRM_ERR(EINVAL); - } - - i915_kernel_lost_context(dev); - - count = nbox ? nbox : 1; - - for (i = 0; i < count; i++) { - if (i < nbox) { - int ret = i915_emit_box(dev, boxes, i, - batch->DR1, batch->DR4); - if (ret) - return ret; - } - - if (dev_priv->use_mi_batchbuffer_start) { - BEGIN_LP_RING(2); - OUT_RING(MI_BATCH_BUFFER_START | (2 << 6)); - OUT_RING(batch->start | MI_BATCH_NON_SECURE); - ADVANCE_LP_RING(); - } else { - BEGIN_LP_RING(4); - OUT_RING(MI_BATCH_BUFFER); - OUT_RING(batch->start | MI_BATCH_NON_SECURE); - OUT_RING(batch->start + batch->used - 4); - OUT_RING(0); - ADVANCE_LP_RING(); - } - } - - dev_priv->sarea_priv->last_enqueue = dev_priv->counter++; - - BEGIN_LP_RING(4); - OUT_RING(CMD_STORE_DWORD_IDX); - OUT_RING(20); - OUT_RING(dev_priv->counter); - OUT_RING(0); - ADVANCE_LP_RING(); - - return 0; -} - -static int i915_dispatch_flip(drm_device_t * dev) -{ - drm_i915_private_t *dev_priv = dev->dev_private; - RING_LOCALS; - - DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n", - __FUNCTION__, - dev_priv->current_page, - dev_priv->sarea_priv->pf_current_page); - - i915_kernel_lost_context(dev); - - BEGIN_LP_RING(2); - OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE); - OUT_RING(0); - ADVANCE_LP_RING(); - - BEGIN_LP_RING(6); - OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP); - OUT_RING(0); - if (dev_priv->current_page == 0) { - OUT_RING(dev_priv->back_offset); - dev_priv->current_page = 1; - } else { - OUT_RING(dev_priv->front_offset); - dev_priv->current_page = 0; - } - OUT_RING(0); - ADVANCE_LP_RING(); - - BEGIN_LP_RING(2); - OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP); - OUT_RING(0); - ADVANCE_LP_RING(); - - dev_priv->sarea_priv->last_enqueue = dev_priv->counter++; - - BEGIN_LP_RING(4); - OUT_RING(CMD_STORE_DWORD_IDX); - OUT_RING(20); - OUT_RING(dev_priv->counter); - OUT_RING(0); - ADVANCE_LP_RING(); - - dev_priv->sarea_priv->pf_current_page = dev_priv->current_page; - return 0; -} - -static int i915_quiescent(drm_device_t * dev) -{ - drm_i915_private_t *dev_priv = dev->dev_private; - - i915_kernel_lost_context(dev); - return i915_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__); -} - -int i915_flush_ioctl(DRM_IOCTL_ARGS) -{ - DRM_DEVICE; - - if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { - DRM_ERROR("i915_flush_ioctl called without lock held\n"); - return DRM_ERR(EINVAL); - } - - return i915_quiescent(dev); -} - -int i915_batchbuffer(DRM_IOCTL_ARGS) -{ - DRM_DEVICE; - drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; - u32 *hw_status = dev_priv->hw_status_page; - drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) - dev_priv->sarea_priv; - drm_i915_batchbuffer_t batch; - int ret; - - if (!dev_priv->allow_batchbuffer) { - DRM_ERROR("Batchbuffer ioctl disabled\n"); - return DRM_ERR(EINVAL); - } - - DRM_COPY_FROM_USER_IOCTL(batch, (drm_i915_batchbuffer_t __user *) data, - sizeof(batch)); - - DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n", - batch.start, batch.used, batch.num_cliprects); - - if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { - DRM_ERROR("i915_batchbuffer called without lock held\n"); - return DRM_ERR(EINVAL); - } - - if (batch.num_cliprects && DRM_VERIFYAREA_READ(batch.cliprects, - batch.num_cliprects * - sizeof(drm_clip_rect_t))) - return DRM_ERR(EFAULT); - - ret = i915_dispatch_batchbuffer(dev, &batch); - - sarea_priv->last_dispatch = (int)hw_status[5]; - return ret; -} - -int i915_cmdbuffer(DRM_IOCTL_ARGS) -{ - DRM_DEVICE; - drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; - u32 *hw_status = dev_priv->hw_status_page; - drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) - dev_priv->sarea_priv; - drm_i915_cmdbuffer_t cmdbuf; - int ret; - - DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_i915_cmdbuffer_t __user *) data, - sizeof(cmdbuf)); - - DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n", - cmdbuf.buf, cmdbuf.sz, cmdbuf.num_cliprects); - - if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { - DRM_ERROR("i915_cmdbuffer called without lock held\n"); - return DRM_ERR(EINVAL); - } - - if (cmdbuf.num_cliprects && - DRM_VERIFYAREA_READ(cmdbuf.cliprects, - cmdbuf.num_cliprects * - sizeof(drm_clip_rect_t))) { - DRM_ERROR("Fault accessing cliprects\n"); - return DRM_ERR(EFAULT); - } - - ret = i915_dispatch_cmdbuffer(dev, &cmdbuf); - if (ret) { - DRM_ERROR("i915_dispatch_cmdbuffer failed\n"); - return ret; - } - - sarea_priv->last_dispatch = (int)hw_status[5]; - return 0; -} - -int i915_do_cleanup_pageflip(drm_device_t * dev) -{ - drm_i915_private_t *dev_priv = dev->dev_private; - - DRM_DEBUG("%s\n", __FUNCTION__); - if (dev_priv->current_page != 0) - i915_dispatch_flip(dev); - - return 0; -} - -int i915_flip_bufs(DRM_IOCTL_ARGS) -{ - DRM_DEVICE; - - DRM_DEBUG("%s\n", __FUNCTION__); - if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { - DRM_ERROR("i915_flip_buf called without lock held\n"); - return DRM_ERR(EINVAL); - } - - return i915_dispatch_flip(dev); -} - -int i915_getparam(DRM_IOCTL_ARGS) -{ - DRM_DEVICE; - drm_i915_private_t *dev_priv = dev->dev_private; - drm_i915_getparam_t param; - int value; - - if (!dev_priv) { - DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); - } - - DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_getparam_t __user *) data, - sizeof(param)); - - switch (param.param) { - case I915_PARAM_IRQ_ACTIVE: - value = dev->irq ? 1 : 0; - break; - case I915_PARAM_ALLOW_BATCHBUFFER: - value = dev_priv->allow_batchbuffer ? 1 : 0; - break; - default: - DRM_ERROR("Unkown parameter %d\n", param.param); - return DRM_ERR(EINVAL); - } - - if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) { - DRM_ERROR("DRM_COPY_TO_USER failed\n"); - return DRM_ERR(EFAULT); - } - - return 0; -} - -int i915_setparam(DRM_IOCTL_ARGS) -{ - DRM_DEVICE; - drm_i915_private_t *dev_priv = dev->dev_private; - drm_i915_setparam_t param; - - if (!dev_priv) { - DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); - } - - DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_setparam_t __user *) data, - sizeof(param)); - - switch (param.param) { - case I915_SETPARAM_USE_MI_BATCHBUFFER_START: - dev_priv->use_mi_batchbuffer_start = param.value; - break; - case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY: - dev_priv->tex_lru_log_granularity = param.value; - break; - case I915_SETPARAM_ALLOW_BATCHBUFFER: - dev_priv->allow_batchbuffer = param.value; - break; - default: - DRM_ERROR("unknown parameter %d\n", param.param); - return DRM_ERR(EINVAL); - } - - return 0; -} - -static void i915_driver_pretakedown(drm_device_t *dev) -{ - if (dev->dev_private) { - drm_i915_private_t *dev_priv = dev->dev_private; - i915_mem_takedown(&(dev_priv->agp_heap)); - } - i915_dma_cleanup(dev); -} - -static void i915_driver_prerelease(drm_device_t *dev, DRMFILE filp) -{ - if (dev->dev_private) { - drm_i915_private_t *dev_priv = dev->dev_private; - i915_mem_release(dev, filp, dev_priv->agp_heap); - } -} - -void i915_driver_register_fns(drm_device_t *dev) -{ - dev->driver_features = - DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | DRIVER_USE_MTRR | - DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED; - dev->fn_tbl.pretakedown = i915_driver_pretakedown; - dev->fn_tbl.prerelease = i915_driver_prerelease; - dev->fn_tbl.irq_preinstall = i915_driver_irq_preinstall; - dev->fn_tbl.irq_postinstall = i915_driver_irq_postinstall; - dev->fn_tbl.irq_uninstall = i915_driver_irq_uninstall; - dev->fn_tbl.irq_handler = i915_driver_irq_handler; - - dev->counters += 4; - dev->types[6] = _DRM_STAT_IRQ; - dev->types[7] = _DRM_STAT_PRIMARY; - dev->types[8] = _DRM_STAT_SECONDARY; - dev->types[9] = _DRM_STAT_DMA; -} diff --git a/nx-X11/extras/drm/shared/i915_drm.h b/nx-X11/extras/drm/shared/i915_drm.h deleted file mode 100644 index 24f4cd622..000000000 --- a/nx-X11/extras/drm/shared/i915_drm.h +++ /dev/null @@ -1,154 +0,0 @@ -#ifndef _I915_DRM_H_ -#define _I915_DRM_H_ - -/* Please note that modifications to all structs defined here are - * subject to backwards-compatibility constraints. - */ - -#include "drm.h" - -/* Each region is a minimum of 16k, and there are at most 255 of them. - */ -#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use - * of chars for next/prev indices */ -#define I915_LOG_MIN_TEX_REGION_SIZE 14 - -typedef struct _drm_i915_init { - enum { - I915_INIT_DMA = 0x01, - I915_CLEANUP_DMA = 0x02, - I915_RESUME_DMA = 0x03 - } func; - unsigned int mmio_offset; - int sarea_priv_offset; - unsigned int ring_start; - unsigned int ring_end; - unsigned int ring_size; - unsigned int front_offset; - unsigned int back_offset; - unsigned int depth_offset; - unsigned int w; - unsigned int h; - unsigned int pitch; - unsigned int pitch_bits; - unsigned int back_pitch; - unsigned int depth_pitch; - unsigned int cpp; - unsigned int chipset; -} drm_i915_init_t; - -typedef struct _drm_i915_sarea { - drm_tex_region_t texList[I915_NR_TEX_REGIONS + 1]; - int last_upload; /* last time texture was uploaded */ - int last_enqueue; /* last time a buffer was enqueued */ - int last_dispatch; /* age of the most recently dispatched buffer */ - int ctxOwner; /* last context to upload state */ - int texAge; - int pf_enabled; /* is pageflipping allowed? */ - int pf_active; - int pf_current_page; /* which buffer is being displayed? */ - int perf_boxes; /* performance boxes to be displayed */ -} drm_i915_sarea_t; - -/* Flags for perf_boxes - */ -#define I915_BOX_RING_EMPTY 0x1 -#define I915_BOX_FLIP 0x2 -#define I915_BOX_WAIT 0x4 -#define I915_BOX_TEXTURE_LOAD 0x8 -#define I915_BOX_LOST_CONTEXT 0x10 - -/* I915 specific ioctls - * The device specific ioctl range is 0x40 to 0x79. - */ -#define DRM_IOCTL_I915_INIT DRM_IOW( 0x40, drm_i915_init_t) -#define DRM_IOCTL_I915_FLUSH DRM_IO ( 0x41) -#define DRM_IOCTL_I915_FLIP DRM_IO ( 0x42) -#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( 0x43, drm_i915_batchbuffer_t) -#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(0x44, drm_i915_irq_emit_t) -#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( 0x45, drm_i915_irq_wait_t) -#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(0x46, drm_i915_getparam_t) -#define DRM_IOCTL_I915_SETPARAM DRM_IOW( 0x47, drm_i915_setparam_t) -#define DRM_IOCTL_I915_ALLOC DRM_IOWR(0x48, drm_i915_mem_alloc_t) -#define DRM_IOCTL_I915_FREE DRM_IOW( 0x49, drm_i915_mem_free_t) -#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( 0x4a, drm_i915_mem_init_heap_t) -#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( 0x4b, drm_i915_cmdbuffer_t) - -/* Allow drivers to submit batchbuffers directly to hardware, relying - * on the security mechanisms provided by hardware. - */ -typedef struct _drm_i915_batchbuffer { - int start; /* agp offset */ - int used; /* nr bytes in use */ - int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ - int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ - int num_cliprects; /* mulitpass with multiple cliprects? */ - drm_clip_rect_t __user *cliprects; /* pointer to userspace cliprects */ -} drm_i915_batchbuffer_t; - -/* As above, but pass a pointer to userspace buffer which can be - * validated by the kernel prior to sending to hardware. - */ -typedef struct _drm_i915_cmdbuffer { - char __user *buf; /* pointer to userspace command buffer */ - int sz; /* nr bytes in buf */ - int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ - int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ - int num_cliprects; /* mulitpass with multiple cliprects? */ - drm_clip_rect_t __user *cliprects; /* pointer to userspace cliprects */ -} drm_i915_cmdbuffer_t; - -/* Userspace can request & wait on irq's: - */ -typedef struct drm_i915_irq_emit { - int __user *irq_seq; -} drm_i915_irq_emit_t; - -typedef struct drm_i915_irq_wait { - int irq_seq; -} drm_i915_irq_wait_t; - -/* Ioctl to query kernel params: - */ -#define I915_PARAM_IRQ_ACTIVE 1 -#define I915_PARAM_ALLOW_BATCHBUFFER 2 - -typedef struct drm_i915_getparam { - int param; - int __user *value; -} drm_i915_getparam_t; - -/* Ioctl to set kernel params: - */ -#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 -#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 -#define I915_SETPARAM_ALLOW_BATCHBUFFER 3 - -typedef struct drm_i915_setparam { - int param; - int value; -} drm_i915_setparam_t; - -/* A memory manager for regions of shared memory: - */ -#define I915_MEM_REGION_AGP 1 - -typedef struct drm_i915_mem_alloc { - int region; - int alignment; - int size; - int __user *region_offset; /* offset from start of fb or agp */ -} drm_i915_mem_alloc_t; - -typedef struct drm_i915_mem_free { - int region; - int region_offset; -} drm_i915_mem_free_t; - -typedef struct drm_i915_mem_init_heap { - int region; - int size; - int start; -} drm_i915_mem_init_heap_t; - -#endif /* _I915_DRM_H_ */ diff --git a/nx-X11/extras/drm/shared/i915_drv.h b/nx-X11/extras/drm/shared/i915_drv.h deleted file mode 100644 index 073b7070e..000000000 --- a/nx-X11/extras/drm/shared/i915_drv.h +++ /dev/null @@ -1,219 +0,0 @@ -/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- - */ -/************************************************************************** - * - * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. - * All Rights Reserved. - * - **************************************************************************/ - -#ifndef _I915_DRV_H_ -#define _I915_DRV_H_ - -typedef struct _drm_i915_ring_buffer { - int tail_mask; - unsigned long Start; - unsigned long End; - unsigned long Size; - u8 *virtual_start; - int head; - int tail; - int space; - drm_local_map_t map; -} drm_i915_ring_buffer_t; - -struct mem_block { - struct mem_block *next; - struct mem_block *prev; - int start; - int size; - DRMFILE filp; /* 0: free, -1: heap, other: real files */ -}; - -typedef struct drm_i915_private { - drm_local_map_t *sarea; - drm_local_map_t *mmio_map; - - drm_i915_sarea_t *sarea_priv; - drm_i915_ring_buffer_t ring; - - void *hw_status_page; - unsigned long counter; - dma_addr_t dma_status_page; - - int back_offset; - int front_offset; - int current_page; - int page_flipping; - int use_mi_batchbuffer_start; - - wait_queue_head_t irq_queue; - atomic_t irq_received; - atomic_t irq_emitted; - - int tex_lru_log_granularity; - int allow_batchbuffer; - struct mem_block *agp_heap; -} drm_i915_private_t; - - /* i915_dma.c */ -extern int i915_dma_init(DRM_IOCTL_ARGS); -extern int i915_dma_cleanup(drm_device_t * dev); -extern int i915_flush_ioctl(DRM_IOCTL_ARGS); -extern int i915_batchbuffer(DRM_IOCTL_ARGS); -extern int i915_flip_bufs(DRM_IOCTL_ARGS); -extern int i915_getparam(DRM_IOCTL_ARGS); -extern int i915_setparam(DRM_IOCTL_ARGS); -extern int i915_cmdbuffer(DRM_IOCTL_ARGS); -extern void i915_kernel_lost_context(drm_device_t * dev); - -/* i915_irq.c */ -extern int i915_irq_emit(DRM_IOCTL_ARGS); -extern int i915_irq_wait(DRM_IOCTL_ARGS); -extern int i915_wait_irq(drm_device_t * dev, int irq_nr); -extern int i915_emit_irq(drm_device_t * dev); - -extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); -extern void i915_driver_irq_preinstall(drm_device_t *dev); -extern void i915_driver_irq_postinstall(drm_device_t *dev); -extern void i915_driver_irq_uninstall(drm_device_t *dev); - -/* i915_mem.c */ -extern int i915_mem_alloc(DRM_IOCTL_ARGS); -extern int i915_mem_free(DRM_IOCTL_ARGS); -extern int i915_mem_init_heap(DRM_IOCTL_ARGS); -extern void i915_mem_takedown(struct mem_block **heap); -extern void i915_mem_release(drm_device_t * dev, - DRMFILE filp, struct mem_block *heap); - -#define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg)) -#define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val)) -#define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg)) -#define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val)) - -#define I915_VERBOSE 0 - -#define RING_LOCALS unsigned int outring, ringmask, outcount; \ - volatile char *virt; - -#define BEGIN_LP_RING(n) do { \ - if (I915_VERBOSE) \ - DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n", \ - n, __FUNCTION__); \ - if (dev_priv->ring.space < n*4) \ - i915_wait_ring(dev, n*4, __FUNCTION__); \ - outcount = 0; \ - outring = dev_priv->ring.tail; \ - ringmask = dev_priv->ring.tail_mask; \ - virt = dev_priv->ring.virtual_start; \ -} while (0) - -#define OUT_RING(n) do { \ - if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \ - *(volatile unsigned int *)(virt + outring) = n; \ - outcount++; \ - outring += 4; \ - outring &= ringmask; \ -} while (0) - -#define ADVANCE_LP_RING() do { \ - if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \ - dev_priv->ring.tail = outring; \ - dev_priv->ring.space -= outcount * 4; \ - I915_WRITE(LP_RING + RING_TAIL, outring); \ -} while(0) - -extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller); - -#define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23)) -#define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23)) -#define CMD_REPORT_HEAD (7<<23) -#define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1) -#define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1) - -#define INST_PARSER_CLIENT 0x00000000 -#define INST_OP_FLUSH 0x02000000 -#define INST_FLUSH_MAP_CACHE 0x00000001 - -#define BB1_START_ADDR_MASK (~0x7) -#define BB1_PROTECTED (1<<0) -#define BB1_UNPROTECTED (0<<0) -#define BB2_END_ADDR_MASK (~0x7) - -#define I915REG_HWSTAM 0x02098 -#define I915REG_INT_IDENTITY_R 0x020a4 -#define I915REG_INT_MASK_R 0x020a8 -#define I915REG_INT_ENABLE_R 0x020a0 - -#define SRX_INDEX 0x3c4 -#define SRX_DATA 0x3c5 -#define SR01 1 -#define SR01_SCREEN_OFF (1<<5) - -#define PPCR 0x61204 -#define PPCR_ON (1<<0) - -#define ADPA 0x61100 -#define ADPA_DPMS_MASK (~(3<<10)) -#define ADPA_DPMS_ON (0<<10) -#define ADPA_DPMS_SUSPEND (1<<10) -#define ADPA_DPMS_STANDBY (2<<10) -#define ADPA_DPMS_OFF (3<<10) - -#define NOPID 0x2094 -#define LP_RING 0x2030 -#define HP_RING 0x2040 -#define RING_TAIL 0x00 -#define TAIL_ADDR 0x001FFFF8 -#define RING_HEAD 0x04 -#define HEAD_WRAP_COUNT 0xFFE00000 -#define HEAD_WRAP_ONE 0x00200000 -#define HEAD_ADDR 0x001FFFFC -#define RING_START 0x08 -#define START_ADDR 0x0xFFFFF000 -#define RING_LEN 0x0C -#define RING_NR_PAGES 0x001FF000 -#define RING_REPORT_MASK 0x00000006 -#define RING_REPORT_64K 0x00000002 -#define RING_REPORT_128K 0x00000004 -#define RING_NO_REPORT 0x00000000 -#define RING_VALID_MASK 0x00000001 -#define RING_VALID 0x00000001 -#define RING_INVALID 0x00000000 - -#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) -#define SC_UPDATE_SCISSOR (0x1<<1) -#define SC_ENABLE_MASK (0x1<<0) -#define SC_ENABLE (0x1<<0) - -#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) -#define SCI_YMIN_MASK (0xffff<<16) -#define SCI_XMIN_MASK (0xffff<<0) -#define SCI_YMAX_MASK (0xffff<<16) -#define SCI_XMAX_MASK (0xffff<<0) - -#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) -#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) -#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) -#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) -#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) -#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) -#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) - -#define MI_BATCH_BUFFER ((0x30<<23)|1) -#define MI_BATCH_BUFFER_START (0x31<<23) -#define MI_BATCH_BUFFER_END (0xA<<23) -#define MI_BATCH_NON_SECURE (1) - -#define MI_WAIT_FOR_EVENT ((0x3<<23)) -#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) -#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) - -#define MI_LOAD_SCAN_LINES_INCL ((0x12<<23)) - -#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) -#define ASYNC_FLIP (1<<22) - -#define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) - -#endif diff --git a/nx-X11/extras/drm/shared/i915_irq.c b/nx-X11/extras/drm/shared/i915_irq.c deleted file mode 100644 index de91aba58..000000000 --- a/nx-X11/extras/drm/shared/i915_irq.c +++ /dev/null @@ -1,165 +0,0 @@ -/* i915_dma.c -- DMA support for the I915 -*- linux-c -*- - */ -/************************************************************************** - * - * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. - * All Rights Reserved. - * - **************************************************************************/ - -#include "i915.h" -#include "drmP.h" -#include "drm.h" -#include "i915_drm.h" -#include "i915_drv.h" - -#define USER_INT_FLAG 0x2 -#define MAX_NOPID ((u32)~0) -#define READ_BREADCRUMB(dev_priv) (((u32*)(dev_priv->hw_status_page))[5]) - -irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) -{ - drm_device_t *dev = (drm_device_t *) arg; - drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; - u16 temp; - - temp = I915_READ16(I915REG_INT_IDENTITY_R); - temp &= USER_INT_FLAG; - - DRM_DEBUG("%s flag=%08x\n", __FUNCTION__, temp); - - if (temp == 0) - return IRQ_NONE; - - I915_WRITE16(I915REG_INT_IDENTITY_R, temp); - DRM_WAKEUP(&dev_priv->irq_queue); - - return IRQ_HANDLED; -} - -int i915_emit_irq(drm_device_t * dev) -{ - drm_i915_private_t *dev_priv = dev->dev_private; - u32 ret; - RING_LOCALS; - - i915_kernel_lost_context(dev); - - DRM_DEBUG("%s\n", __FUNCTION__); - - ret = dev_priv->counter; - - BEGIN_LP_RING(2); - OUT_RING(0); - OUT_RING(GFX_OP_USER_INTERRUPT); - ADVANCE_LP_RING(); - - return ret; -} - -int i915_wait_irq(drm_device_t * dev, int irq_nr) -{ - drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; - int ret = 0; - - DRM_DEBUG("%s irq_nr=%d breadcrumb=%d\n", __FUNCTION__, irq_nr, - READ_BREADCRUMB(dev_priv)); - - if (READ_BREADCRUMB(dev_priv) >= irq_nr) - return 0; - - dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; - - DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ, - READ_BREADCRUMB(dev_priv) >= irq_nr); - - if (ret == DRM_ERR(EBUSY)) { - DRM_ERROR("%s: EBUSY -- rec: %d emitted: %d\n", - __FUNCTION__, - READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); - } - - dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); - return ret; -} - -/* Needs the lock as it touches the ring. - */ -int i915_irq_emit(DRM_IOCTL_ARGS) -{ - DRM_DEVICE; - drm_i915_private_t *dev_priv = dev->dev_private; - drm_i915_irq_emit_t emit; - int result; - - if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { - DRM_ERROR("i915_irq_emit called without lock held\n"); - return DRM_ERR(EINVAL); - } - - if (!dev_priv) { - DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); - } - - DRM_COPY_FROM_USER_IOCTL(emit, (drm_i915_irq_emit_t __user *) data, - sizeof(emit)); - - result = i915_emit_irq(dev); - - if (DRM_COPY_TO_USER(emit.irq_seq, &result, sizeof(int))) { - DRM_ERROR("copy_to_user\n"); - return DRM_ERR(EFAULT); - } - - return 0; -} - -/* Doesn't need the hardware lock. - */ -int i915_irq_wait(DRM_IOCTL_ARGS) -{ - DRM_DEVICE; - drm_i915_private_t *dev_priv = dev->dev_private; - drm_i915_irq_wait_t irqwait; - - if (!dev_priv) { - DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); - } - - DRM_COPY_FROM_USER_IOCTL(irqwait, (drm_i915_irq_wait_t __user *) data, - sizeof(irqwait)); - - return i915_wait_irq(dev, irqwait.irq_seq); -} - -/* drm_dma.h hooks -*/ -void i915_driver_irq_preinstall(drm_device_t * dev) -{ - drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; - - I915_WRITE16(I915REG_HWSTAM, 0xfffe); - I915_WRITE16(I915REG_INT_MASK_R, 0x0); - I915_WRITE16(I915REG_INT_ENABLE_R, 0x0); -} - -void i915_driver_irq_postinstall(drm_device_t * dev) -{ - drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; - - I915_WRITE16(I915REG_INT_ENABLE_R, USER_INT_FLAG); - DRM_INIT_WAITQUEUE(&dev_priv->irq_queue); -} - -void i915_driver_irq_uninstall(drm_device_t * dev) -{ - drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; - if (!dev_priv) - return; - - I915_WRITE16(I915REG_HWSTAM, 0xffff); - I915_WRITE16(I915REG_INT_MASK_R, 0xffff); - I915_WRITE16(I915REG_INT_ENABLE_R, 0x0); -} diff --git a/nx-X11/extras/drm/shared/i915_mem.c b/nx-X11/extras/drm/shared/i915_mem.c deleted file mode 100644 index c6115b7e1..000000000 --- a/nx-X11/extras/drm/shared/i915_mem.c +++ /dev/null @@ -1,347 +0,0 @@ -/* i915_mem.c -- Simple agp/fb memory manager for i915 -*- linux-c -*- - */ -/************************************************************************** - * - * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. - * All Rights Reserved. - * - **************************************************************************/ - -#include "i915.h" -#include "drmP.h" -#include "drm.h" -#include "i915_drm.h" -#include "i915_drv.h" - -/* This memory manager is integrated into the global/local lru - * mechanisms used by the clients. Specifically, it operates by - * setting the 'in_use' fields of the global LRU to indicate whether - * this region is privately allocated to a client. - * - * This does require the client to actually respect that field. - * - * Currently no effort is made to allocate 'private' memory in any - * clever way - the LRU information isn't used to determine which - * block to allocate, and the ring is drained prior to allocations -- - * in other words allocation is expensive. - */ -static void mark_block(drm_device_t * dev, struct mem_block *p, int in_use) -{ - drm_i915_private_t *dev_priv = dev->dev_private; - drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_tex_region_t *list; - unsigned shift, nr; - unsigned start; - unsigned end; - unsigned i; - int age; - - shift = dev_priv->tex_lru_log_granularity; - nr = I915_NR_TEX_REGIONS; - - start = p->start >> shift; - end = (p->start + p->size - 1) >> shift; - - age = ++sarea_priv->texAge; - list = sarea_priv->texList; - - /* Mark the regions with the new flag and update their age. Move - * them to head of list to preserve LRU semantics. - */ - for (i = start; i <= end; i++) { - list[i].in_use = in_use; - list[i].age = age; - - /* remove_from_list(i) - */ - list[(unsigned)list[i].next].prev = list[i].prev; - list[(unsigned)list[i].prev].next = list[i].next; - - /* insert_at_head(list, i) - */ - list[i].prev = nr; - list[i].next = list[nr].next; - list[(unsigned)list[nr].next].prev = i; - list[nr].next = i; - } -} - -/* Very simple allocator for agp memory, working on a static range - * already mapped into each client's address space. - */ - -static struct mem_block *split_block(struct mem_block *p, int start, int size, - DRMFILE filp) -{ - /* Maybe cut off the start of an existing block */ - if (start > p->start) { - struct mem_block *newblock = DRM(alloc)(sizeof(*newblock), DRM_MEM_BUFLISTS); - if (!newblock) - goto out; - newblock->start = start; - newblock->size = p->size - (start - p->start); - newblock->filp = NULL; - newblock->next = p->next; - newblock->prev = p; - p->next->prev = newblock; - p->next = newblock; - p->size -= newblock->size; - p = newblock; - } - - /* Maybe cut off the end of an existing block */ - if (size < p->size) { - struct mem_block *newblock = DRM(alloc)(sizeof(*newblock), DRM_MEM_BUFLISTS); - if (!newblock) - goto out; - newblock->start = start + size; - newblock->size = p->size - size; - newblock->filp = NULL; - newblock->next = p->next; - newblock->prev = p; - p->next->prev = newblock; - p->next = newblock; - p->size = size; - } - - out: - /* Our block is in the middle */ - p->filp = filp; - return p; -} - -static struct mem_block *alloc_block(struct mem_block *heap, int size, - int align2, DRMFILE filp) -{ - struct mem_block *p; - int mask = (1 << align2) - 1; - - for (p = heap->next; p != heap; p = p->next) { - int start = (p->start + mask) & ~mask; - if (p->filp == NULL && start + size <= p->start + p->size) - return split_block(p, start, size, filp); - } - - return NULL; -} - -static struct mem_block *find_block(struct mem_block *heap, int start) -{ - struct mem_block *p; - - for (p = heap->next; p != heap; p = p->next) - if (p->start == start) - return p; - - return NULL; -} - -static void free_block(struct mem_block *p) -{ - p->filp = NULL; - - /* Assumes a single contiguous range. Needs a special filp in - * 'heap' to stop it being subsumed. - */ - if (p->next->filp == NULL) { - struct mem_block *q = p->next; - p->size += q->size; - p->next = q->next; - p->next->prev = p; - DRM(free)(q, sizeof(*q), DRM_MEM_BUFLISTS); - } - - if (p->prev->filp == NULL) { - struct mem_block *q = p->prev; - q->size += p->size; - q->next = p->next; - q->next->prev = q; - DRM(free)(p, sizeof(*q), DRM_MEM_BUFLISTS); - } -} - -/* Initialize. How to check for an uninitialized heap? - */ -static int init_heap(struct mem_block **heap, int start, int size) -{ - struct mem_block *blocks = DRM(alloc)(sizeof(*blocks), DRM_MEM_BUFLISTS); - - if (!blocks) - return -ENOMEM; - - *heap = DRM(alloc)(sizeof(**heap), DRM_MEM_BUFLISTS); - if (!*heap) { - DRM(free)(blocks, sizeof(*blocks), DRM_MEM_BUFLISTS); - return -ENOMEM; - } - - blocks->start = start; - blocks->size = size; - blocks->filp = NULL; - blocks->next = blocks->prev = *heap; - - memset(*heap, 0, sizeof(**heap)); - (*heap)->filp = (DRMFILE) - 1; - (*heap)->next = (*heap)->prev = blocks; - return 0; -} - -/* Free all blocks associated with the releasing file. - */ -void i915_mem_release(drm_device_t * dev, DRMFILE filp, struct mem_block *heap) -{ - struct mem_block *p; - - if (!heap || !heap->next) - return; - - for (p = heap->next; p != heap; p = p->next) { - if (p->filp == filp) { - p->filp = NULL; - mark_block(dev, p, 0); - } - } - - /* Assumes a single contiguous range. Needs a special filp in - * 'heap' to stop it being subsumed. - */ - for (p = heap->next; p != heap; p = p->next) { - while (p->filp == NULL && p->next->filp == NULL) { - struct mem_block *q = p->next; - p->size += q->size; - p->next = q->next; - p->next->prev = p; - DRM(free)(q, sizeof(*q), DRM_MEM_BUFLISTS); - } - } -} - -/* Shutdown. - */ -void i915_mem_takedown(struct mem_block **heap) -{ - struct mem_block *p; - - if (!*heap) - return; - - for (p = (*heap)->next; p != *heap;) { - struct mem_block *q = p; - p = p->next; - DRM(free)(q, sizeof(*q), DRM_MEM_BUFLISTS); - } - - DRM(free)(*heap, sizeof(**heap), DRM_MEM_BUFLISTS); - *heap = NULL; -} - -static struct mem_block **get_heap(drm_i915_private_t * dev_priv, int region) -{ - switch (region) { - case I915_MEM_REGION_AGP: - return &dev_priv->agp_heap; - default: - return NULL; - } -} - -/* IOCTL HANDLERS */ - -int i915_mem_alloc(DRM_IOCTL_ARGS) -{ - DRM_DEVICE; - drm_i915_private_t *dev_priv = dev->dev_private; - drm_i915_mem_alloc_t alloc; - struct mem_block *block, **heap; - - if (!dev_priv) { - DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); - } - - DRM_COPY_FROM_USER_IOCTL(alloc, (drm_i915_mem_alloc_t __user *) data, - sizeof(alloc)); - - heap = get_heap(dev_priv, alloc.region); - if (!heap || !*heap) - return DRM_ERR(EFAULT); - - /* Make things easier on ourselves: all allocations at least - * 4k aligned. - */ - if (alloc.alignment < 12) - alloc.alignment = 12; - - block = alloc_block(*heap, alloc.size, alloc.alignment, filp); - - if (!block) - return DRM_ERR(ENOMEM); - - mark_block(dev, block, 1); - - if (DRM_COPY_TO_USER(alloc.region_offset, &block->start, sizeof(int))) { - DRM_ERROR("copy_to_user\n"); - return DRM_ERR(EFAULT); - } - - return 0; -} - -int i915_mem_free(DRM_IOCTL_ARGS) -{ - DRM_DEVICE; - drm_i915_private_t *dev_priv = dev->dev_private; - drm_i915_mem_free_t memfree; - struct mem_block *block, **heap; - - if (!dev_priv) { - DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); - } - - DRM_COPY_FROM_USER_IOCTL(memfree, (drm_i915_mem_free_t __user *) data, - sizeof(memfree)); - - heap = get_heap(dev_priv, memfree.region); - if (!heap || !*heap) - return DRM_ERR(EFAULT); - - block = find_block(*heap, memfree.region_offset); - if (!block) - return DRM_ERR(EFAULT); - - if (block->filp != filp) - return DRM_ERR(EPERM); - - mark_block(dev, block, 0); - free_block(block); - return 0; -} - -int i915_mem_init_heap(DRM_IOCTL_ARGS) -{ - DRM_DEVICE; - drm_i915_private_t *dev_priv = dev->dev_private; - drm_i915_mem_init_heap_t initheap; - struct mem_block **heap; - - if (!dev_priv) { - DRM_ERROR("%s called with no initialization\n", __FUNCTION__); - return DRM_ERR(EINVAL); - } - - DRM_COPY_FROM_USER_IOCTL(initheap, - (drm_i915_mem_init_heap_t __user *) data, - sizeof(initheap)); - - heap = get_heap(dev_priv, initheap.region); - if (!heap) - return DRM_ERR(EFAULT); - - if (*heap) { - DRM_ERROR("heap already initialized?"); - return DRM_ERR(EFAULT); - } - - return init_heap(heap, initheap.start, initheap.size); -} diff --git a/nx-X11/extras/drm/shared/mach64.h b/nx-X11/extras/drm/shared/mach64.h deleted file mode 100644 index 9fae34335..000000000 --- a/nx-X11/extras/drm/shared/mach64.h +++ /dev/null @@ -1,69 +0,0 @@ -/* mach64.h -- ATI Mach 64 DRM template customization -*- linux-c -*- - * Created: Wed Feb 14 16:07:10 2001 by gareth@valinux.com - * - * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. - * Copyright 2002-2003 Leif Delgass - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Gareth Hughes - * Leif Delgass - */ - -#ifndef __MACH64_H__ -#define __MACH64_H__ - -/* This remains constant for all DRM template files. - */ -#define DRM(x) mach64_##x - -/* General customization: - */ - -#define DRIVER_AUTHOR "Gareth Hughes, Leif Delgass, José Fonseca" - -#define DRIVER_NAME "mach64" -#define DRIVER_DESC "DRM module for the ATI Rage Pro" -#define DRIVER_DATE "20020904" - -#define DRIVER_MAJOR 1 -#define DRIVER_MINOR 0 -#define DRIVER_PATCHLEVEL 0 - -/* Interface history: - * - * 1.0 - Initial mach64 DRM - * - */ -#define DRIVER_IOCTLS \ - [DRM_IOCTL_NR(DRM_IOCTL_DMA)] = { mach64_dma_buffers, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_MACH64_INIT)] = { mach64_dma_init, 1, 1 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_MACH64_CLEAR)] = { mach64_dma_clear, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_MACH64_SWAP)] = { mach64_dma_swap, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_MACH64_IDLE)] = { mach64_dma_idle, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_MACH64_RESET)] = { mach64_engine_reset, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_MACH64_VERTEX)] = { mach64_dma_vertex, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_MACH64_BLIT)] = { mach64_dma_blit, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_MACH64_FLUSH)] = { mach64_dma_flush, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_MACH64_GETPARAM)] = { mach64_get_param, 1, 0 } - -#endif diff --git a/nx-X11/extras/drm/shared/mach64_dma.c b/nx-X11/extras/drm/shared/mach64_dma.c deleted file mode 100644 index 210a6103c..000000000 --- a/nx-X11/extras/drm/shared/mach64_dma.c +++ /dev/null @@ -1,1343 +0,0 @@ -/* mach64_dma.c -- DMA support for mach64 (Rage Pro) driver -*- linux-c -*- - * Created: Sun Dec 03 19:20:26 2000 by gareth@valinux.com - * - * Copyright 2000 Gareth Hughes - * Copyright 2002 Frank C. Earl - * Copyright 2002-2003 Leif Delgass - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT OWNER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Gareth Hughes - * Frank C. Earl - * Leif Delgass - * José Fonseca - */ - -#include "mach64.h" -#include "drmP.h" -#include "drm.h" -#include "mach64_drm.h" -#include "mach64_drv.h" - - -/* ================================================================ - * Engine, FIFO control - */ - -int mach64_do_wait_for_fifo( drm_mach64_private_t *dev_priv, int entries ) -{ - int slots = 0, i; - - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - slots = (MACH64_READ( MACH64_FIFO_STAT ) & - MACH64_FIFO_SLOT_MASK); - if ( slots <= (0x8000 >> entries) ) return 0; - DRM_UDELAY( 1 ); - } - - DRM_INFO( "%s failed! slots=%d entries=%d\n", __FUNCTION__, slots, entries ); - return DRM_ERR(EBUSY); -} - -int mach64_do_wait_for_idle( drm_mach64_private_t *dev_priv ) -{ - int i, ret; - - ret = mach64_do_wait_for_fifo( dev_priv, 16 ); - if ( ret < 0 ) return ret; - - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - if ( !(MACH64_READ( MACH64_GUI_STAT ) & MACH64_GUI_ACTIVE) ) { - return 0; - } - DRM_UDELAY( 1 ); - } - - DRM_INFO( "%s failed! GUI_STAT=0x%08x\n", __FUNCTION__, - MACH64_READ( MACH64_GUI_STAT ) ); - mach64_dump_ring_info( dev_priv ); - return DRM_ERR(EBUSY); -} - -int mach64_wait_ring( drm_mach64_private_t *dev_priv, int n ) -{ - drm_mach64_descriptor_ring_t *ring = &dev_priv->ring; - int i; - - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - mach64_update_ring_snapshot( dev_priv ); - if ( ring->space >= n ) { - if (i > 0) { - DRM_DEBUG( "%s: %d usecs\n", __FUNCTION__, i ); - } - return 0; - } - DRM_UDELAY( 1 ); - } - - /* FIXME: This is being ignored... */ - DRM_ERROR( "failed!\n" ); - mach64_dump_ring_info( dev_priv ); - return DRM_ERR(EBUSY); -} - -/* Wait until all DMA requests have been processed... */ -static int mach64_ring_idle( drm_mach64_private_t *dev_priv ) -{ - drm_mach64_descriptor_ring_t *ring = &dev_priv->ring; - u32 head; - int i; - - head = ring->head; - i = 0; - while ( i < dev_priv->usec_timeout ) { - mach64_update_ring_snapshot( dev_priv ); - if ( ring->head == ring->tail && - !(MACH64_READ(MACH64_GUI_STAT) & MACH64_GUI_ACTIVE) ) { - if (i > 0) { - DRM_DEBUG( "%s: %d usecs\n", __FUNCTION__, i ); - } - return 0; - } - if ( ring->head == head ) { - ++i; - } else { - head = ring->head; - i = 0; - } - DRM_UDELAY( 1 ); - } - - DRM_INFO( "%s failed! GUI_STAT=0x%08x\n", __FUNCTION__, - MACH64_READ( MACH64_GUI_STAT ) ); - mach64_dump_ring_info( dev_priv ); - return DRM_ERR(EBUSY); -} - -static void mach64_ring_reset( drm_mach64_private_t *dev_priv ) -{ - drm_mach64_descriptor_ring_t *ring = &dev_priv->ring; - - mach64_do_release_used_buffers( dev_priv ); - ring->head_addr = ring->start_addr; - ring->head = ring->tail = 0; - ring->space = ring->size; - - MACH64_WRITE( MACH64_BM_GUI_TABLE_CMD, - ring->head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB ); - - dev_priv->ring_running = 0; -} - -int mach64_do_dma_flush( drm_mach64_private_t *dev_priv ) -{ - /* FIXME: It's not necessary to wait for idle when flushing - * we just need to ensure the ring will be completely processed - * in finite time without another ioctl - */ - return mach64_ring_idle( dev_priv ); -} - -int mach64_do_dma_idle( drm_mach64_private_t *dev_priv ) -{ - int ret; - - /* wait for completion */ - if ( (ret = mach64_ring_idle( dev_priv )) < 0 ) { - DRM_ERROR( "%s failed BM_GUI_TABLE=0x%08x tail: %u\n", __FUNCTION__, - MACH64_READ(MACH64_BM_GUI_TABLE), dev_priv->ring.tail ); - return ret; - } - - mach64_ring_stop( dev_priv ); - - /* clean up after pass */ - mach64_do_release_used_buffers( dev_priv ); - return 0; -} - -/* Reset the engine. This will stop the DMA if it is running. - */ -int mach64_do_engine_reset( drm_mach64_private_t *dev_priv ) -{ - u32 tmp; - - DRM_DEBUG( "%s\n", __FUNCTION__ ); - - /* Kill off any outstanding DMA transfers. - */ - tmp = MACH64_READ( MACH64_BUS_CNTL ); - MACH64_WRITE( MACH64_BUS_CNTL, - tmp | MACH64_BUS_MASTER_DIS ); - - /* Reset the GUI engine (high to low transition). - */ - tmp = MACH64_READ( MACH64_GEN_TEST_CNTL ); - MACH64_WRITE( MACH64_GEN_TEST_CNTL, - tmp & ~MACH64_GUI_ENGINE_ENABLE ); - /* Enable the GUI engine - */ - tmp = MACH64_READ( MACH64_GEN_TEST_CNTL ); - MACH64_WRITE( MACH64_GEN_TEST_CNTL, - tmp | MACH64_GUI_ENGINE_ENABLE ); - - /* ensure engine is not locked up by clearing any FIFO or HOST errors - */ - tmp = MACH64_READ( MACH64_BUS_CNTL ); - MACH64_WRITE( MACH64_BUS_CNTL, tmp | 0x00a00000 ); - - /* Once GUI engine is restored, disable bus mastering */ - MACH64_WRITE( MACH64_SRC_CNTL, 0 ); - - /* Reset descriptor ring */ - mach64_ring_reset( dev_priv ); - - return 0; -} - -/* ================================================================ - * Debugging output - */ - -void mach64_dump_engine_info( drm_mach64_private_t *dev_priv ) -{ - DRM_INFO( "\n" ); - if ( !dev_priv->is_pci ) - { - DRM_INFO( " AGP_BASE = 0x%08x\n", MACH64_READ( MACH64_AGP_BASE ) ); - DRM_INFO( " AGP_CNTL = 0x%08x\n", MACH64_READ( MACH64_AGP_CNTL ) ); - } - DRM_INFO( " ALPHA_TST_CNTL = 0x%08x\n", MACH64_READ( MACH64_ALPHA_TST_CNTL ) ); - DRM_INFO( "\n" ); - DRM_INFO( " BM_COMMAND = 0x%08x\n", MACH64_READ( MACH64_BM_COMMAND ) ); - DRM_INFO( "BM_FRAME_BUF_OFFSET = 0x%08x\n", MACH64_READ( MACH64_BM_FRAME_BUF_OFFSET ) ); - DRM_INFO( " BM_GUI_TABLE = 0x%08x\n", MACH64_READ( MACH64_BM_GUI_TABLE ) ); - DRM_INFO( " BM_STATUS = 0x%08x\n", MACH64_READ( MACH64_BM_STATUS ) ); - DRM_INFO( " BM_SYSTEM_MEM_ADDR = 0x%08x\n", MACH64_READ( MACH64_BM_SYSTEM_MEM_ADDR ) ); - DRM_INFO( " BM_SYSTEM_TABLE = 0x%08x\n", MACH64_READ( MACH64_BM_SYSTEM_TABLE ) ); - DRM_INFO( " BUS_CNTL = 0x%08x\n", MACH64_READ( MACH64_BUS_CNTL ) ); - DRM_INFO( "\n" ); - /* DRM_INFO( " CLOCK_CNTL = 0x%08x\n", MACH64_READ( MACH64_CLOCK_CNTL ) ); */ - DRM_INFO( " CLR_CMP_CLR = 0x%08x\n", MACH64_READ( MACH64_CLR_CMP_CLR ) ); - DRM_INFO( " CLR_CMP_CNTL = 0x%08x\n", MACH64_READ( MACH64_CLR_CMP_CNTL ) ); - /* DRM_INFO( " CLR_CMP_MSK = 0x%08x\n", MACH64_READ( MACH64_CLR_CMP_MSK ) ); */ - DRM_INFO( " CONFIG_CHIP_ID = 0x%08x\n", MACH64_READ( MACH64_CONFIG_CHIP_ID ) ); - DRM_INFO( " CONFIG_CNTL = 0x%08x\n", MACH64_READ( MACH64_CONFIG_CNTL ) ); - DRM_INFO( " CONFIG_STAT0 = 0x%08x\n", MACH64_READ( MACH64_CONFIG_STAT0 ) ); - DRM_INFO( " CONFIG_STAT1 = 0x%08x\n", MACH64_READ( MACH64_CONFIG_STAT1 ) ); - DRM_INFO( " CONFIG_STAT2 = 0x%08x\n", MACH64_READ( MACH64_CONFIG_STAT2 ) ); - DRM_INFO( " CRC_SIG = 0x%08x\n", MACH64_READ( MACH64_CRC_SIG ) ); - DRM_INFO( " CUSTOM_MACRO_CNTL = 0x%08x\n", MACH64_READ( MACH64_CUSTOM_MACRO_CNTL ) ); - DRM_INFO( "\n" ); - /* DRM_INFO( " DAC_CNTL = 0x%08x\n", MACH64_READ( MACH64_DAC_CNTL ) ); */ - /* DRM_INFO( " DAC_REGS = 0x%08x\n", MACH64_READ( MACH64_DAC_REGS ) ); */ - DRM_INFO( " DP_BKGD_CLR = 0x%08x\n", MACH64_READ( MACH64_DP_BKGD_CLR ) ); - DRM_INFO( " DP_FRGD_CLR = 0x%08x\n", MACH64_READ( MACH64_DP_FRGD_CLR ) ); - DRM_INFO( " DP_MIX = 0x%08x\n", MACH64_READ( MACH64_DP_MIX ) ); - DRM_INFO( " DP_PIX_WIDTH = 0x%08x\n", MACH64_READ( MACH64_DP_PIX_WIDTH ) ); - DRM_INFO( " DP_SRC = 0x%08x\n", MACH64_READ( MACH64_DP_SRC ) ); - DRM_INFO( " DP_WRITE_MASK = 0x%08x\n", MACH64_READ( MACH64_DP_WRITE_MASK ) ); - DRM_INFO( " DSP_CONFIG = 0x%08x\n", MACH64_READ( MACH64_DSP_CONFIG ) ); - DRM_INFO( " DSP_ON_OFF = 0x%08x\n", MACH64_READ( MACH64_DSP_ON_OFF ) ); - DRM_INFO( " DST_CNTL = 0x%08x\n", MACH64_READ( MACH64_DST_CNTL ) ); - DRM_INFO( " DST_OFF_PITCH = 0x%08x\n", MACH64_READ( MACH64_DST_OFF_PITCH ) ); - DRM_INFO( "\n" ); - /* DRM_INFO( " EXT_DAC_REGS = 0x%08x\n", MACH64_READ( MACH64_EXT_DAC_REGS ) ); */ - DRM_INFO( " EXT_MEM_CNTL = 0x%08x\n", MACH64_READ( MACH64_EXT_MEM_CNTL ) ); - DRM_INFO( "\n" ); - DRM_INFO( " FIFO_STAT = 0x%08x\n", MACH64_READ( MACH64_FIFO_STAT ) ); - DRM_INFO( "\n" ); - DRM_INFO( " GEN_TEST_CNTL = 0x%08x\n", MACH64_READ( MACH64_GEN_TEST_CNTL ) ); - /* DRM_INFO( " GP_IO = 0x%08x\n", MACH64_READ( MACH64_GP_IO ) ); */ - DRM_INFO( " GUI_CMDFIFO_DATA = 0x%08x\n", MACH64_READ( MACH64_GUI_CMDFIFO_DATA ) ); - DRM_INFO( " GUI_CMDFIFO_DEBUG = 0x%08x\n", MACH64_READ( MACH64_GUI_CMDFIFO_DEBUG ) ); - DRM_INFO( " GUI_CNTL = 0x%08x\n", MACH64_READ( MACH64_GUI_CNTL ) ); - DRM_INFO( " GUI_STAT = 0x%08x\n", MACH64_READ( MACH64_GUI_STAT ) ); - DRM_INFO( " GUI_TRAJ_CNTL = 0x%08x\n", MACH64_READ( MACH64_GUI_TRAJ_CNTL ) ); - DRM_INFO( "\n" ); - DRM_INFO( " HOST_CNTL = 0x%08x\n", MACH64_READ( MACH64_HOST_CNTL ) ); - DRM_INFO( " HW_DEBUG = 0x%08x\n", MACH64_READ( MACH64_HW_DEBUG ) ); - DRM_INFO( "\n" ); - DRM_INFO( " MEM_ADDR_CONFIG = 0x%08x\n", MACH64_READ( MACH64_MEM_ADDR_CONFIG ) ); - DRM_INFO( " MEM_BUF_CNTL = 0x%08x\n", MACH64_READ( MACH64_MEM_BUF_CNTL ) ); - DRM_INFO( "\n" ); - DRM_INFO( " PAT_REG0 = 0x%08x\n", MACH64_READ( MACH64_PAT_REG0 ) ); - DRM_INFO( " PAT_REG1 = 0x%08x\n", MACH64_READ( MACH64_PAT_REG1 ) ); - DRM_INFO( "\n" ); - DRM_INFO( " SC_LEFT = 0x%08x\n", MACH64_READ( MACH64_SC_LEFT ) ); - DRM_INFO( " SC_RIGHT = 0x%08x\n", MACH64_READ( MACH64_SC_RIGHT ) ); - DRM_INFO( " SC_TOP = 0x%08x\n", MACH64_READ( MACH64_SC_TOP ) ); - DRM_INFO( " SC_BOTTOM = 0x%08x\n", MACH64_READ( MACH64_SC_BOTTOM ) ); - DRM_INFO( "\n" ); - DRM_INFO( " SCALE_3D_CNTL = 0x%08x\n", MACH64_READ( MACH64_SCALE_3D_CNTL ) ); - DRM_INFO( " SCRATCH_REG0 = 0x%08x\n", MACH64_READ( MACH64_SCRATCH_REG0 ) ); - DRM_INFO( " SCRATCH_REG1 = 0x%08x\n", MACH64_READ( MACH64_SCRATCH_REG1 ) ); - DRM_INFO( " SETUP_CNTL = 0x%08x\n", MACH64_READ( MACH64_SETUP_CNTL ) ); - DRM_INFO( " SRC_CNTL = 0x%08x\n", MACH64_READ( MACH64_SRC_CNTL ) ); - DRM_INFO( "\n" ); - DRM_INFO( " TEX_CNTL = 0x%08x\n", MACH64_READ( MACH64_TEX_CNTL ) ); - DRM_INFO( " TEX_SIZE_PITCH = 0x%08x\n", MACH64_READ( MACH64_TEX_SIZE_PITCH ) ); - DRM_INFO( " TIMER_CONFIG = 0x%08x\n", MACH64_READ( MACH64_TIMER_CONFIG ) ); - DRM_INFO( "\n" ); - DRM_INFO( " Z_CNTL = 0x%08x\n", MACH64_READ( MACH64_Z_CNTL ) ); - DRM_INFO( " Z_OFF_PITCH = 0x%08x\n", MACH64_READ( MACH64_Z_OFF_PITCH ) ); - DRM_INFO( "\n" ); -} - -#define MACH64_DUMP_CONTEXT 3 - -static void mach64_dump_buf_info( drm_mach64_private_t *dev_priv, drm_buf_t *buf) -{ - u32 addr = GETBUFADDR( buf ); - u32 used = buf->used >> 2; - u32 sys_addr = MACH64_READ( MACH64_BM_SYSTEM_MEM_ADDR ); - u32 *p = GETBUFPTR( buf ); - int skipped = 0; - - DRM_INFO( "buffer contents:\n" ); - - while ( used ) { - u32 reg, count; - - reg = le32_to_cpu(*p++); - if( addr <= GETBUFADDR( buf ) + MACH64_DUMP_CONTEXT * 4 || - (addr >= sys_addr - MACH64_DUMP_CONTEXT * 4 && - addr <= sys_addr + MACH64_DUMP_CONTEXT * 4) || - addr >= GETBUFADDR( buf ) + buf->used - MACH64_DUMP_CONTEXT * 4) { - DRM_INFO("%08x: 0x%08x\n", addr, reg); - } - addr += 4; - used--; - - count = (reg >> 16) + 1; - reg = reg & 0xffff; - reg = MMSELECT( reg ); - while ( count && used ) { - if( addr <= GETBUFADDR( buf ) + MACH64_DUMP_CONTEXT * 4 || - (addr >= sys_addr - MACH64_DUMP_CONTEXT * 4 && - addr <= sys_addr + MACH64_DUMP_CONTEXT * 4) || - addr >= GETBUFADDR( buf ) + buf->used - MACH64_DUMP_CONTEXT * 4) { - DRM_INFO("%08x: 0x%04x = 0x%08x\n", addr, reg, le32_to_cpu(*p)); - skipped = 0; - } else { - if( !skipped ) { - DRM_INFO( " ...\n" ); - skipped = 1; - } - } - p++; - addr += 4; - used--; - - reg += 4; - count--; - } - } - - DRM_INFO( "\n" ); -} - -void mach64_dump_ring_info( drm_mach64_private_t *dev_priv ) -{ - drm_mach64_descriptor_ring_t *ring = &dev_priv->ring; - int i, skipped; - - DRM_INFO( "\n" ); - - DRM_INFO("ring contents:\n"); - DRM_INFO(" head_addr: 0x%08x head: %u tail: %u\n\n", - ring->head_addr, ring->head, ring->tail ); - - skipped = 0; - for ( i = 0; i < ring->size / sizeof(u32); i += 4) { - if( i <= MACH64_DUMP_CONTEXT * 4 || - i >= ring->size / sizeof(u32) - MACH64_DUMP_CONTEXT * 4 || - (i >= ring->tail - MACH64_DUMP_CONTEXT * 4 && - i <= ring->tail + MACH64_DUMP_CONTEXT * 4) || - (i >= ring->head - MACH64_DUMP_CONTEXT * 4 && - i <= ring->head + MACH64_DUMP_CONTEXT * 4)) { - DRM_INFO( " 0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x%s%s\n", - ring->start_addr + i * sizeof(u32), - le32_to_cpu(((u32*) ring->start)[i + 0]), - le32_to_cpu(((u32*) ring->start)[i + 1]), - le32_to_cpu(((u32*) ring->start)[i + 2]), - le32_to_cpu(((u32*) ring->start)[i + 3]), - i == ring->head ? " (head)" : "", - i == ring->tail ? " (tail)" : "" - ); - skipped = 0; - } else { - if( !skipped ) { - DRM_INFO( " ...\n" ); - skipped = 1; - } - } - } - - DRM_INFO( "\n" ); - - if( ring->head >= 0 && ring->head < ring->size / sizeof(u32) ) { - struct list_head *ptr; - u32 addr = le32_to_cpu(((u32 *)ring->start)[ring->head + 1]); - - list_for_each(ptr, &dev_priv->pending) { - drm_mach64_freelist_t *entry = - list_entry(ptr, drm_mach64_freelist_t, list); - drm_buf_t *buf = entry->buf; - - u32 buf_addr = GETBUFADDR( buf ); - - if ( buf_addr <= addr && addr < buf_addr + buf->used ) { - mach64_dump_buf_info ( dev_priv, buf ); - } - } - } - - DRM_INFO( "\n" ); - DRM_INFO( " BM_GUI_TABLE = 0x%08x\n", MACH64_READ( MACH64_BM_GUI_TABLE ) ); - DRM_INFO( "\n" ); - DRM_INFO( "BM_FRAME_BUF_OFFSET = 0x%08x\n", MACH64_READ( MACH64_BM_FRAME_BUF_OFFSET ) ); - DRM_INFO( " BM_SYSTEM_MEM_ADDR = 0x%08x\n", MACH64_READ( MACH64_BM_SYSTEM_MEM_ADDR ) ); - DRM_INFO( " BM_COMMAND = 0x%08x\n", MACH64_READ( MACH64_BM_COMMAND ) ); - DRM_INFO( "\n" ); - DRM_INFO( " BM_STATUS = 0x%08x\n", MACH64_READ( MACH64_BM_STATUS ) ); - DRM_INFO( " BUS_CNTL = 0x%08x\n", MACH64_READ( MACH64_BUS_CNTL ) ); - DRM_INFO( " FIFO_STAT = 0x%08x\n", MACH64_READ( MACH64_FIFO_STAT ) ); - DRM_INFO( " GUI_STAT = 0x%08x\n", MACH64_READ( MACH64_GUI_STAT ) ); - DRM_INFO( " SRC_CNTL = 0x%08x\n", MACH64_READ( MACH64_SRC_CNTL ) ); -} - - -/* ================================================================ - * DMA test and initialization - */ - -static int mach64_bm_dma_test( drm_device_t *dev ) -{ - drm_mach64_private_t *dev_priv = dev->dev_private; - dma_addr_t data_handle; - void *cpu_addr_data; - u32 data_addr; - u32 *table, *data; - u32 expected[2]; - u32 src_cntl, pat_reg0, pat_reg1; - int i, count, failed; - - DRM_DEBUG( "%s\n", __FUNCTION__ ); - - table = (u32 *) dev_priv->ring.start; - - /* FIXME: get a dma buffer from the freelist here */ - DRM_DEBUG( "Allocating data memory ...\n" ); - cpu_addr_data = DRM(pci_alloc)( dev, 0x1000, 0x1000, 0xfffffffful, &data_handle ); - if (!cpu_addr_data || !data_handle) { - DRM_INFO( "data-memory allocation failed!\n" ); - return DRM_ERR(ENOMEM); - } else { - data = (u32 *) cpu_addr_data; - data_addr = (u32) data_handle; - } - - /* Save the X server's value for SRC_CNTL and restore it - * in case our test fails. This prevents the X server - * from disabling it's cache for this register - */ - src_cntl = MACH64_READ( MACH64_SRC_CNTL ); - pat_reg0 = MACH64_READ( MACH64_PAT_REG0 ); - pat_reg1 = MACH64_READ( MACH64_PAT_REG1 ); - - mach64_do_wait_for_fifo( dev_priv, 3 ); - - MACH64_WRITE( MACH64_SRC_CNTL, 0 ); - MACH64_WRITE( MACH64_PAT_REG0, 0x11111111 ); - MACH64_WRITE( MACH64_PAT_REG1, 0x11111111 ); - - mach64_do_wait_for_idle( dev_priv ); - - for (i=0; i < 2; i++) { - u32 reg; - reg = MACH64_READ( (MACH64_PAT_REG0 + i*4) ); - DRM_DEBUG( "(Before DMA Transfer) reg %d = 0x%08x\n", i, reg ); - if ( reg != 0x11111111 ) { - DRM_INFO( "Error initializing test registers\n" ); - DRM_INFO( "resetting engine ...\n"); - mach64_do_engine_reset( dev_priv ); - DRM_INFO( "freeing data buffer memory.\n" ); - DRM(pci_free)( dev, 0x1000, cpu_addr_data, data_handle ); - return DRM_ERR(EIO); - } - } - - /* fill up a buffer with sets of 2 consecutive writes starting with PAT_REG0 */ - count = 0; - - data[count++] = cpu_to_le32(DMAREG(MACH64_PAT_REG0) | (1 << 16)); - data[count++] = expected[0] = 0x22222222; - data[count++] = expected[1] = 0xaaaaaaaa; - - while (count < 1020) { - data[count++] = cpu_to_le32(DMAREG(MACH64_PAT_REG0) | (1 << 16)); - data[count++] = 0x22222222; - data[count++] = 0xaaaaaaaa; - } - data[count++] = cpu_to_le32(DMAREG(MACH64_SRC_CNTL) | (0 << 16)); - data[count++] = 0; - - DRM_DEBUG( "Preparing table ...\n" ); - table[MACH64_DMA_FRAME_BUF_OFFSET] = cpu_to_le32(MACH64_BM_ADDR + - MACH64_APERTURE_OFFSET); - table[MACH64_DMA_SYS_MEM_ADDR] = cpu_to_le32(data_addr); - table[MACH64_DMA_COMMAND] = cpu_to_le32(count * sizeof( u32 ) - | MACH64_DMA_HOLD_OFFSET - | MACH64_DMA_EOL); - table[MACH64_DMA_RESERVED] = 0; - - DRM_DEBUG( "table[0] = 0x%08x\n", table[0] ); - DRM_DEBUG( "table[1] = 0x%08x\n", table[1] ); - DRM_DEBUG( "table[2] = 0x%08x\n", table[2] ); - DRM_DEBUG( "table[3] = 0x%08x\n", table[3] ); - - for ( i = 0 ; i < 6 ; i++ ) { - DRM_DEBUG( " data[%d] = 0x%08x\n", i, data[i] ); - } - DRM_DEBUG( " ...\n" ); - for ( i = count-5 ; i < count ; i++ ) { - DRM_DEBUG( " data[%d] = 0x%08x\n", i, data[i] ); - } - - DRM_MEMORYBARRIER(); - - DRM_DEBUG( "waiting for idle...\n" ); - if ( ( i = mach64_do_wait_for_idle( dev_priv ) ) ) { - DRM_INFO( "mach64_do_wait_for_idle failed (result=%d)\n", i); - DRM_INFO( "resetting engine ...\n"); - mach64_do_engine_reset( dev_priv ); - mach64_do_wait_for_fifo( dev_priv, 3 ); - MACH64_WRITE( MACH64_SRC_CNTL, src_cntl ); - MACH64_WRITE( MACH64_PAT_REG0, pat_reg0 ); - MACH64_WRITE( MACH64_PAT_REG1, pat_reg1 ); - DRM_INFO( "freeing data buffer memory.\n" ); - DRM(pci_free)( dev, 0x1000, cpu_addr_data, data_handle ); - return i; - } - DRM_DEBUG( "waiting for idle...done\n" ); - - DRM_DEBUG( "BUS_CNTL = 0x%08x\n", MACH64_READ( MACH64_BUS_CNTL ) ); - DRM_DEBUG( "SRC_CNTL = 0x%08x\n", MACH64_READ( MACH64_SRC_CNTL ) ); - DRM_DEBUG( "\n" ); - DRM_DEBUG( "data bus addr = 0x%08x\n", data_addr ); - DRM_DEBUG( "table bus addr = 0x%08x\n", dev_priv->ring.start_addr ); - - DRM_DEBUG( "starting DMA transfer...\n" ); - MACH64_WRITE( MACH64_BM_GUI_TABLE_CMD, - dev_priv->ring.start_addr | - MACH64_CIRCULAR_BUF_SIZE_16KB ); - - MACH64_WRITE( MACH64_SRC_CNTL, - MACH64_SRC_BM_ENABLE | MACH64_SRC_BM_SYNC | - MACH64_SRC_BM_OP_SYSTEM_TO_REG ); - - /* Kick off the transfer */ - DRM_DEBUG( "starting DMA transfer... done.\n" ); - MACH64_WRITE( MACH64_DST_HEIGHT_WIDTH, 0 ); - - DRM_DEBUG( "waiting for idle...\n" ); - - if ( ( i = mach64_do_wait_for_idle( dev_priv ) ) ) { - /* engine locked up, dump register state and reset */ - DRM_INFO( "mach64_do_wait_for_idle failed (result=%d)\n", i); - mach64_dump_engine_info( dev_priv ); - DRM_INFO( "resetting engine ...\n"); - mach64_do_engine_reset( dev_priv ); - mach64_do_wait_for_fifo( dev_priv, 3 ); - MACH64_WRITE( MACH64_SRC_CNTL, src_cntl ); - MACH64_WRITE( MACH64_PAT_REG0, pat_reg0 ); - MACH64_WRITE( MACH64_PAT_REG1, pat_reg1 ); - DRM_INFO( "freeing data buffer memory.\n" ); - DRM(pci_free)( dev, 0x1000, cpu_addr_data, data_handle ); - return i; - } - - DRM_DEBUG( "waiting for idle...done\n" ); - - /* restore SRC_CNTL */ - mach64_do_wait_for_fifo( dev_priv, 1 ); - MACH64_WRITE( MACH64_SRC_CNTL, src_cntl ); - - failed = 0; - - /* Check register values to see if the GUI master operation succeeded */ - for ( i = 0; i < 2; i++ ) { - u32 reg; - reg = MACH64_READ( (MACH64_PAT_REG0 + i*4) ); - DRM_DEBUG( "(After DMA Transfer) reg %d = 0x%08x\n", i, reg ); - if (reg != expected[i]) { - failed = -1; - } - } - - /* restore pattern registers */ - mach64_do_wait_for_fifo( dev_priv, 2 ); - MACH64_WRITE( MACH64_PAT_REG0, pat_reg0 ); - MACH64_WRITE( MACH64_PAT_REG1, pat_reg1 ); - - DRM_DEBUG( "freeing data buffer memory.\n" ); - DRM(pci_free)( dev, 0x1000, cpu_addr_data, data_handle ); - DRM_DEBUG( "returning ...\n" ); - - return failed; -} - - -static int mach64_do_dma_init( drm_device_t *dev, drm_mach64_init_t *init ) -{ - drm_mach64_private_t *dev_priv; - u32 tmp; - int i, ret; - - DRM_DEBUG( "%s\n", __FUNCTION__ ); - - dev_priv = DRM(alloc)( sizeof(drm_mach64_private_t), DRM_MEM_DRIVER ); - if ( dev_priv == NULL ) - return DRM_ERR(ENOMEM); - - memset( dev_priv, 0, sizeof(drm_mach64_private_t) ); - - dev_priv->is_pci = init->is_pci; - - dev_priv->fb_bpp = init->fb_bpp; - dev_priv->front_offset = init->front_offset; - dev_priv->front_pitch = init->front_pitch; - dev_priv->back_offset = init->back_offset; - dev_priv->back_pitch = init->back_pitch; - - dev_priv->depth_bpp = init->depth_bpp; - dev_priv->depth_offset = init->depth_offset; - dev_priv->depth_pitch = init->depth_pitch; - - dev_priv->front_offset_pitch = (((dev_priv->front_pitch/8) << 22) | - (dev_priv->front_offset >> 3)); - dev_priv->back_offset_pitch = (((dev_priv->back_pitch/8) << 22) | - (dev_priv->back_offset >> 3)); - dev_priv->depth_offset_pitch = (((dev_priv->depth_pitch/8) << 22) | - (dev_priv->depth_offset >> 3)); - - dev_priv->usec_timeout = 1000000; - - /* Set up the freelist, placeholder list and pending list */ - INIT_LIST_HEAD(&dev_priv->free_list); - INIT_LIST_HEAD(&dev_priv->placeholders); - INIT_LIST_HEAD(&dev_priv->pending); - - DRM_GETSAREA(); - - if (!dev_priv->sarea) { - DRM_ERROR("can not find sarea!\n"); - dev->dev_private = (void *)dev_priv; - mach64_do_cleanup_dma(dev); - return DRM_ERR(EINVAL); - } - dev_priv->fb = drm_core_findmap(dev, init->fb_offset); - if (!dev_priv->fb) { - DRM_ERROR("can not find frame buffer map!\n"); - dev->dev_private = (void *)dev_priv; - mach64_do_cleanup_dma(dev); - return DRM_ERR(EINVAL); - } - dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset); - if (!dev_priv->mmio) { - DRM_ERROR("can not find mmio map!\n"); - dev->dev_private = (void *)dev_priv; - mach64_do_cleanup_dma(dev); - return DRM_ERR(EINVAL); - } - - dev_priv->sarea_priv = (drm_mach64_sarea_t *) - ((u8 *)dev_priv->sarea->handle + - init->sarea_priv_offset); - - if( !dev_priv->is_pci ) { - dev_priv->ring_map = drm_core_findmap(dev, init->ring_offset); - if ( !dev_priv->ring_map ) { - DRM_ERROR( "can not find ring map!\n" ); - dev->dev_private = (void *)dev_priv; - mach64_do_cleanup_dma(dev); - return DRM_ERR(EINVAL); - } - drm_core_ioremap( dev_priv->ring_map, dev ); - if ( !dev_priv->ring_map->handle ) { - DRM_ERROR( "can not ioremap virtual address for" - " descriptor ring\n" ); - dev->dev_private = (void *) dev_priv; - mach64_do_cleanup_dma( dev ); - return DRM_ERR(ENOMEM); - } - dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); - if ( !dev->agp_buffer_map ) { - DRM_ERROR( "can not find dma buffer map!\n" ); - dev->dev_private = (void *)dev_priv; - mach64_do_cleanup_dma( dev ); - return DRM_ERR(EINVAL); - } - /* there might be a nicer way to do this - - dev isn't passed all the way though the mach64 - DA */ - dev_priv->dev_buffers = dev->agp_buffer_map; - - drm_core_ioremap( dev->agp_buffer_map, dev ); - if ( !dev->agp_buffer_map->handle ) { - DRM_ERROR( "can not ioremap virtual address for" - " dma buffer\n" ); - dev->dev_private = (void *) dev_priv; - mach64_do_cleanup_dma( dev ); - return DRM_ERR(ENOMEM); - } - dev_priv->agp_textures = drm_core_findmap(dev, init->agp_textures_offset); - if (!dev_priv->agp_textures) { - DRM_ERROR( "can not find agp texture region!\n" ); - dev->dev_private = (void *)dev_priv; - mach64_do_cleanup_dma( dev ); - return DRM_ERR(EINVAL); - } - } - - dev->dev_private = (void *) dev_priv; - - dev_priv->driver_mode = init->dma_mode; - - /* changing the FIFO size from the default causes problems with DMA */ - tmp = MACH64_READ( MACH64_GUI_CNTL ); - if ( (tmp & MACH64_CMDFIFO_SIZE_MASK) != MACH64_CMDFIFO_SIZE_128 ) { - DRM_INFO( "Setting FIFO size to 128 entries\n"); - /* FIFO must be empty to change the FIFO depth */ - if ((ret=mach64_do_wait_for_idle( dev_priv ))) { - DRM_ERROR("wait for idle failed before changing FIFO depth!\n"); - mach64_do_cleanup_dma( dev ); - return ret; - } - MACH64_WRITE( MACH64_GUI_CNTL, ( ( tmp & ~MACH64_CMDFIFO_SIZE_MASK ) \ - | MACH64_CMDFIFO_SIZE_128 ) ); - /* need to read GUI_STAT for proper sync according to docs */ - if ((ret=mach64_do_wait_for_idle( dev_priv ))) { - DRM_ERROR("wait for idle failed when changing FIFO depth!\n"); - mach64_do_cleanup_dma( dev ); - return ret; - } - } - - /* allocate descriptor memory from pci pool */ - DRM_DEBUG( "Allocating dma descriptor ring\n" ); - dev_priv->ring.size = 0x4000; /* 16KB */ - - if ( dev_priv->is_pci ) { - dev_priv->ring.start = DRM(pci_alloc)( dev, dev_priv->ring.size, - dev_priv->ring.size, 0xfffffffful, - &dev_priv->ring.handle ); - - if (!dev_priv->ring.start || !dev_priv->ring.handle) { - DRM_ERROR( "Allocating dma descriptor ring failed\n"); - return DRM_ERR(ENOMEM); - } else { - dev_priv->ring.start_addr = (u32) dev_priv->ring.handle; - } - } else { - dev_priv->ring.start = dev_priv->ring_map->handle; - dev_priv->ring.start_addr = (u32) dev_priv->ring_map->offset; - } - - memset( dev_priv->ring.start, 0, dev_priv->ring.size ); - DRM_INFO( "descriptor ring: cpu addr 0x%08x, bus addr: 0x%08x\n", - (u32) dev_priv->ring.start, dev_priv->ring.start_addr ); - - ret = 0; - if ( dev_priv->driver_mode != MACH64_MODE_MMIO ) { - - /* enable block 1 registers and bus mastering */ - MACH64_WRITE( MACH64_BUS_CNTL, - ( ( MACH64_READ(MACH64_BUS_CNTL) - | MACH64_BUS_EXT_REG_EN ) - & ~MACH64_BUS_MASTER_DIS ) ); - - /* try a DMA GUI-mastering pass and fall back to MMIO if it fails */ - DRM_DEBUG( "Starting DMA test...\n"); - if ( (ret=mach64_bm_dma_test( dev )) ) { - dev_priv->driver_mode = MACH64_MODE_MMIO; - } - } - - switch (dev_priv->driver_mode) { - case MACH64_MODE_MMIO: - MACH64_WRITE( MACH64_BUS_CNTL, ( MACH64_READ(MACH64_BUS_CNTL) - | MACH64_BUS_EXT_REG_EN - | MACH64_BUS_MASTER_DIS ) ); - if ( init->dma_mode == MACH64_MODE_MMIO ) - DRM_INFO( "Forcing pseudo-DMA mode\n" ); - else - DRM_INFO( "DMA test failed (ret=%d), using pseudo-DMA mode\n", ret ); - break; - case MACH64_MODE_DMA_SYNC: - DRM_INFO( "DMA test succeeded, using synchronous DMA mode\n"); - break; - case MACH64_MODE_DMA_ASYNC: - default: - DRM_INFO( "DMA test succeeded, using asynchronous DMA mode\n"); - } - - dev_priv->ring_running = 0; - - /* setup offsets for physical address of table start and end */ - dev_priv->ring.head_addr = dev_priv->ring.start_addr; - dev_priv->ring.head = dev_priv->ring.tail = 0; - dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; - dev_priv->ring.space = dev_priv->ring.size; - - /* setup physical address and size of descriptor table */ - mach64_do_wait_for_fifo( dev_priv, 1 ); - MACH64_WRITE( MACH64_BM_GUI_TABLE_CMD, - ( dev_priv->ring.head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB ) ); - - /* init frame counter */ - dev_priv->sarea_priv->frames_queued = 0; - for (i = 0; i < MACH64_MAX_QUEUED_FRAMES; i++) { - dev_priv->frame_ofs[i] = ~0; /* All ones indicates placeholder */ - } - - /* Allocate the DMA buffer freelist */ - if ( (ret=mach64_init_freelist( dev )) ) { - DRM_ERROR("Freelist allocation failed\n"); - mach64_do_cleanup_dma( dev ); - return ret; - } - - return 0; -} - -/* =================================================================== - * MMIO Pseudo-DMA (intended primarily for debugging, not performance) - */ - -int mach64_do_dispatch_pseudo_dma( drm_mach64_private_t *dev_priv ) -{ - drm_mach64_descriptor_ring_t *ring = &dev_priv->ring; - volatile u32 *ring_read; - struct list_head *ptr; - drm_mach64_freelist_t *entry; - drm_buf_t *buf = NULL; - u32 *buf_ptr; - u32 used, reg, target; - int fifo, count, found, ret, no_idle_wait; - - fifo = count = reg = no_idle_wait = 0; - target = MACH64_BM_ADDR; - - if ( (ret=mach64_do_wait_for_idle( dev_priv )) < 0) { - DRM_INFO( "%s: idle failed before pseudo-dma dispatch, resetting engine\n", - __FUNCTION__); - mach64_dump_engine_info( dev_priv ); - mach64_do_engine_reset( dev_priv ); - return ret; - } - - ring_read = (u32 *) ring->start; - - while ( ring->tail != ring->head ) { - u32 buf_addr, new_target, offset; - u32 bytes, remaining, head, eol; - - head = ring->head; - - new_target = le32_to_cpu( ring_read[head++] ) - MACH64_APERTURE_OFFSET; - buf_addr = le32_to_cpu( ring_read[head++] ); - eol = le32_to_cpu( ring_read[head] ) & MACH64_DMA_EOL; - bytes = le32_to_cpu( ring_read[head++] ) - & ~(MACH64_DMA_HOLD_OFFSET | MACH64_DMA_EOL); - head++; - head &= ring->tail_mask; - - /* can't wait for idle between a blit setup descriptor - * and a HOSTDATA descriptor or the engine will lock - */ - if (new_target == MACH64_BM_HOSTDATA && target == MACH64_BM_ADDR) - no_idle_wait = 1; - - target = new_target; - - found = 0; - offset = 0; - list_for_each(ptr, &dev_priv->pending) - { - entry = list_entry(ptr, drm_mach64_freelist_t, list); - buf = entry->buf; - offset = buf_addr - GETBUFADDR( buf ); - if (offset >= 0 && offset < MACH64_BUFFER_SIZE) { - found = 1; - break; - } - } - - if (!found || buf == NULL) { - DRM_ERROR("Couldn't find pending buffer: head: %u tail: %u buf_addr: 0x%08x %s\n", - head, ring->tail, buf_addr, (eol ? "eol" : "")); - mach64_dump_ring_info( dev_priv ); - mach64_do_engine_reset( dev_priv ); - return DRM_ERR(EINVAL); - } - - /* Hand feed the buffer to the card via MMIO, waiting for the fifo - * every 16 writes - */ - DRM_DEBUG("target: (0x%08x) %s\n", target, - (target == MACH64_BM_HOSTDATA ? "BM_HOSTDATA" : "BM_ADDR")); - DRM_DEBUG("offset: %u bytes: %u used: %u\n", offset, bytes, buf->used); - - remaining = (buf->used - offset) >> 2; /* dwords remaining in buffer */ - used = bytes >> 2; /* dwords in buffer for this descriptor */ - buf_ptr = (u32 *)((char *)GETBUFPTR( buf ) + offset); - - while ( used ) { - - if (count == 0) { - if (target == MACH64_BM_HOSTDATA) { - reg = DMAREG(MACH64_HOST_DATA0); - count = (remaining > 16) ? 16 : remaining; - fifo = 0; - } else { - reg = le32_to_cpu(*buf_ptr++); - used--; - count = (reg >> 16) + 1; - } - - reg = reg & 0xffff; - reg = MMSELECT( reg ); - } - while ( count && used ) { - if ( !fifo ) { - if (no_idle_wait) { - if ( (ret=mach64_do_wait_for_fifo( dev_priv, 16 )) < 0 ) { - no_idle_wait = 0; - return ret; - } - } else { - if ( (ret=mach64_do_wait_for_idle( dev_priv )) < 0 ) { - return ret; - } - } - fifo = 16; - } - --fifo; - MACH64_WRITE(reg, le32_to_cpu(*buf_ptr++)); - used--; remaining--; - - reg += 4; - count--; - } - } - ring->head = head; - ring->head_addr = ring->start_addr + (ring->head * sizeof(u32)); - ring->space += (4 * sizeof(u32)); - } - - if ( (ret=mach64_do_wait_for_idle( dev_priv )) < 0 ) { - return ret; - } - MACH64_WRITE( MACH64_BM_GUI_TABLE_CMD, - ring->head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB ); - - DRM_DEBUG( "%s completed\n", __FUNCTION__ ); - return 0; -} - -/* ================================================================ - * DMA cleanup - */ - -int mach64_do_cleanup_dma( drm_device_t *dev ) -{ - DRM_DEBUG( "%s\n", __FUNCTION__ ); - - /* Make sure interrupts are disabled here because the uninstall ioctl - * may not have been called from userspace and after dev_private - * is freed, it's too late. - */ - if ( dev->irq ) DRM(irq_uninstall)(dev); - - if ( dev->dev_private ) { - drm_mach64_private_t *dev_priv = dev->dev_private; - - if ( dev_priv->is_pci ) { - if ( (dev_priv->ring.start != NULL) && dev_priv->ring.handle ) { - DRM(pci_free)( dev, dev_priv->ring.size, - dev_priv->ring.start, dev_priv->ring.handle ); - } - } else { - if ( dev_priv->ring_map ) - drm_core_ioremapfree( dev_priv->ring_map, dev ); - } - - if ( dev->agp_buffer_map ) { - drm_core_ioremapfree( dev->agp_buffer_map, dev ); - dev->agp_buffer_map = NULL; - } - - mach64_destroy_freelist( dev ); - - DRM(free)( dev_priv, sizeof(drm_mach64_private_t), - DRM_MEM_DRIVER ); - dev->dev_private = NULL; - } - - return 0; -} - -/* ================================================================ - * IOCTL handlers - */ - -int mach64_dma_init( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_mach64_init_t init; - - DRM_DEBUG( "%s\n", __FUNCTION__ ); - - LOCK_TEST_WITH_RETURN( dev, filp ); - - DRM_COPY_FROM_USER_IOCTL( init, (drm_mach64_init_t *)data, - sizeof(init) ); - - switch ( init.func ) { - case DRM_MACH64_INIT_DMA: - return mach64_do_dma_init( dev, &init ); - case DRM_MACH64_CLEANUP_DMA: - return mach64_do_cleanup_dma( dev ); - } - - return DRM_ERR(EINVAL); -} - -int mach64_dma_idle( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_mach64_private_t *dev_priv = dev->dev_private; - - DRM_DEBUG( "%s\n", __FUNCTION__ ); - - LOCK_TEST_WITH_RETURN( dev, filp ); - - return mach64_do_dma_idle( dev_priv ); -} - -int mach64_dma_flush( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_mach64_private_t *dev_priv = dev->dev_private; - - DRM_DEBUG( "%s\n", __FUNCTION__ ); - - LOCK_TEST_WITH_RETURN( dev, filp ); - - return mach64_do_dma_flush( dev_priv ); -} - -int mach64_engine_reset( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_mach64_private_t *dev_priv = dev->dev_private; - - DRM_DEBUG( "%s\n", __FUNCTION__ ); - - LOCK_TEST_WITH_RETURN( dev, filp ); - - return mach64_do_engine_reset( dev_priv ); -} - - -/* ================================================================ - * Freelist management - */ - -int mach64_init_freelist( drm_device_t *dev ) -{ - drm_device_dma_t *dma = dev->dma; - drm_mach64_private_t *dev_priv = dev->dev_private; - drm_mach64_freelist_t *entry; - struct list_head *ptr; - int i; - - DRM_DEBUG("%s: adding %d buffers to freelist\n", __FUNCTION__, dma->buf_count); - - for ( i = 0 ; i < dma->buf_count ; i++ ) { - if ((entry = - (drm_mach64_freelist_t *) DRM(alloc)(sizeof(drm_mach64_freelist_t), - DRM_MEM_BUFLISTS)) == NULL) - return DRM_ERR(ENOMEM); - memset( entry, 0, sizeof(drm_mach64_freelist_t) ); - entry->buf = dma->buflist[i]; - ptr = &entry->list; - list_add_tail(ptr, &dev_priv->free_list); - } - - return 0; -} - -void mach64_destroy_freelist( drm_device_t *dev ) -{ - drm_mach64_private_t *dev_priv = dev->dev_private; - drm_mach64_freelist_t *entry; - struct list_head *ptr; - struct list_head *tmp; - - DRM_DEBUG("%s\n", __FUNCTION__); - - list_for_each_safe(ptr, tmp, &dev_priv->pending) - { - list_del(ptr); - entry = list_entry(ptr, drm_mach64_freelist_t, list); - DRM(free)(entry, sizeof(*entry), DRM_MEM_BUFLISTS); - } - list_for_each_safe(ptr, tmp, &dev_priv->placeholders) - { - list_del(ptr); - entry = list_entry(ptr, drm_mach64_freelist_t, list); - DRM(free)(entry, sizeof(*entry), DRM_MEM_BUFLISTS); - } - - list_for_each_safe(ptr, tmp, &dev_priv->free_list) - { - list_del(ptr); - entry = list_entry(ptr, drm_mach64_freelist_t, list); - DRM(free)(entry, sizeof(*entry), DRM_MEM_BUFLISTS); - } -} - -/* IMPORTANT: This function should only be called when the engine is idle or locked up, - * as it assumes all buffers in the pending list have been completed by the hardware. - */ -int mach64_do_release_used_buffers( drm_mach64_private_t *dev_priv ) -{ - struct list_head *ptr; - struct list_head *tmp; - drm_mach64_freelist_t *entry; - int i; - - if ( list_empty(&dev_priv->pending) ) - return 0; - - /* Iterate the pending list and move all buffers into the freelist... */ - i = 0; - list_for_each_safe(ptr, tmp, &dev_priv->pending) - { - entry = list_entry(ptr, drm_mach64_freelist_t, list); - if (entry->discard) { - entry->buf->pending = 0; - list_del(ptr); - list_add_tail(ptr, &dev_priv->free_list); - i++; - } - } - - DRM_DEBUG( "%s: released %d buffers from pending list\n", __FUNCTION__, i ); - - return 0; -} - -drm_buf_t *mach64_freelist_get( drm_mach64_private_t *dev_priv ) -{ - drm_mach64_descriptor_ring_t *ring = &dev_priv->ring; - drm_mach64_freelist_t *entry; - struct list_head *ptr; - struct list_head *tmp; - int t; - - if ( list_empty(&dev_priv->free_list) ) { - u32 head, tail, ofs; - - if ( list_empty( &dev_priv->pending ) ) { - DRM_ERROR( "Couldn't get buffer - pending and free lists empty\n" ); - t = 0; - list_for_each( ptr, &dev_priv->placeholders ) { - t++; - } - DRM_INFO( "Placeholders: %d\n", t ); - return NULL; - } - - tail = ring->tail; - for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) { - mach64_ring_tick( dev_priv, ring ); - head = ring->head; - - if ( head == tail ) { -#if MACH64_EXTRA_CHECKING - if ( MACH64_READ(MACH64_GUI_STAT) & MACH64_GUI_ACTIVE ) { - DRM_ERROR( "Empty ring with non-idle engine!\n" ); - mach64_dump_ring_info( dev_priv ); - return NULL; - } -#endif - /* last pass is complete, so release everything */ - mach64_do_release_used_buffers( dev_priv ); - DRM_DEBUG( "%s: idle engine, freed all buffers.\n", __FUNCTION__ ); - if ( list_empty(&dev_priv->free_list) ) { - DRM_ERROR( "Freelist empty with idle engine\n" ); - return NULL; - } - goto _freelist_entry_found; - } - /* Look for a completed buffer and bail out of the loop - * as soon as we find one -- don't waste time trying - * to free extra bufs here, leave that to do_release_used_buffers - */ - list_for_each_safe(ptr, tmp, &dev_priv->pending) { - entry = list_entry(ptr, drm_mach64_freelist_t, list); - ofs = entry->ring_ofs; - if ( entry->discard && - ((head < tail && (ofs < head || ofs >= tail)) || - (head > tail && (ofs < head && ofs >= tail))) ) { -#if MACH64_EXTRA_CHECKING - int i; - - for ( i = head ; i != tail ; i = (i + 4) & ring->tail_mask ) { - u32 o1 = le32_to_cpu(((u32 *)ring->start)[i + 1]); - u32 o2 = GETBUFADDR( entry->buf ); - - if ( o1 == o2 ) { - DRM_ERROR ( "Attempting to free used buffer: " - "i=%d buf=0x%08x\n", i, o1 ); - mach64_dump_ring_info( dev_priv ); - return NULL; - } - } -#endif - /* found a processed buffer */ - entry->buf->pending = 0; - list_del(ptr); - entry->buf->used = 0; - list_add_tail(ptr, &dev_priv->placeholders); - DRM_DEBUG( "%s: freed processed buffer (head=%d tail=%d " - "buf ring ofs=%d).\n", __FUNCTION__, head, tail, ofs ); - return entry->buf; - } - } - DRM_UDELAY( 1 ); - } - mach64_dump_ring_info( dev_priv ); - DRM_ERROR( "timeout waiting for buffers: ring head_addr: 0x%08x head: %d tail: %d\n", - ring->head_addr, ring->head, ring->tail ); - return NULL; - } - -_freelist_entry_found: - ptr = dev_priv->free_list.next; - list_del(ptr); - entry = list_entry(ptr, drm_mach64_freelist_t, list); - entry->buf->used = 0; - list_add_tail(ptr, &dev_priv->placeholders); - return entry->buf; -} - -/* ================================================================ - * DMA buffer request and submission IOCTL handler - */ - -static int mach64_dma_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d ) -{ - int i; - drm_buf_t *buf; - drm_mach64_private_t *dev_priv = dev->dev_private; - - for ( i = d->granted_count ; i < d->request_count ; i++ ) { - buf = mach64_freelist_get( dev_priv ); -#if MACH64_EXTRA_CHECKING - if ( !buf ) return DRM_ERR(EFAULT); -#else - if ( !buf ) return DRM_ERR(EAGAIN); -#endif - - buf->filp = filp; - - if ( DRM_COPY_TO_USER( &d->request_indices[i], &buf->idx, - sizeof(buf->idx) ) ) - return DRM_ERR(EFAULT); - if ( DRM_COPY_TO_USER( &d->request_sizes[i], &buf->total, - sizeof(buf->total) ) ) - return DRM_ERR(EFAULT); - - d->granted_count++; - } - return 0; -} - -int mach64_dma_buffers( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_device_dma_t *dma = dev->dma; - drm_dma_t d; - int ret = 0; - - LOCK_TEST_WITH_RETURN( dev, filp ); - - DRM_COPY_FROM_USER_IOCTL( d, (drm_dma_t *)data, sizeof(d) ); - - /* Please don't send us buffers. - */ - if ( d.send_count != 0 ) - { - DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n", - DRM_CURRENTPID, d.send_count ); - return DRM_ERR(EINVAL); - } - - /* We'll send you buffers. - */ - if ( d.request_count < 0 || d.request_count > dma->buf_count ) - { - DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n", - DRM_CURRENTPID, d.request_count, dma->buf_count ); - ret = DRM_ERR(EINVAL); - } - - d.granted_count = 0; - - if ( d.request_count ) - { - ret = mach64_dma_get_buffers( filp, dev, &d ); - } - - DRM_COPY_TO_USER_IOCTL( (drm_dma_t *)data, d, sizeof(d) ); - - return ret; -} - -static void mach64_driver_pretakedown(drm_device_t *dev) -{ - mach64_do_cleanup_dma( dev ); -} - -void mach64_driver_register_fns(drm_device_t *dev) -{ - dev->driver_features = DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_HAVE_DMA | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_IRQ_VBL; - dev->fn_tbl.pretakedown = mach64_driver_pretakedown; - dev->fn_tbl.vblank_wait = mach64_driver_vblank_wait; - dev->fn_tbl.irq_preinstall = mach64_driver_irq_preinstall; - dev->fn_tbl.irq_postinstall = mach64_driver_irq_postinstall; - dev->fn_tbl.irq_uninstall = mach64_driver_irq_uninstall; - dev->fn_tbl.irq_handler = mach64_driver_irq_handler; -} diff --git a/nx-X11/extras/drm/shared/mach64_drm.h b/nx-X11/extras/drm/shared/mach64_drm.h deleted file mode 100644 index 9d748a37e..000000000 --- a/nx-X11/extras/drm/shared/mach64_drm.h +++ /dev/null @@ -1,258 +0,0 @@ -/* mach64_drm.h -- Public header for the mach64 driver -*- linux-c -*- - * Created: Thu Nov 30 20:04:32 2000 by gareth@valinux.com - * - * Copyright 2000 Gareth Hughes - * Copyright 2002 Frank C. Earl - * Copyright 2002-2003 Leif Delgass - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT OWNER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Gareth Hughes - * Frank C. Earl - * Leif Delgass - */ - -#ifndef __MACH64_DRM_H__ -#define __MACH64_DRM_H__ - - -/* WARNING: If you change any of these defines, make sure to change the - * defines in the Xserver file (mach64_sarea.h) - */ -#ifndef __MACH64_SAREA_DEFINES__ -#define __MACH64_SAREA_DEFINES__ - -/* What needs to be changed for the current vertex buffer? - * GH: We're going to be pedantic about this. We want the card to do as - * little as possible, so let's avoid having it fetch a whole bunch of - * register values that don't change all that often, if at all. - */ -#define MACH64_UPLOAD_DST_OFF_PITCH 0x0001 -#define MACH64_UPLOAD_Z_OFF_PITCH 0x0002 -#define MACH64_UPLOAD_Z_ALPHA_CNTL 0x0004 -#define MACH64_UPLOAD_SCALE_3D_CNTL 0x0008 -#define MACH64_UPLOAD_DP_FOG_CLR 0x0010 -#define MACH64_UPLOAD_DP_WRITE_MASK 0x0020 -#define MACH64_UPLOAD_DP_PIX_WIDTH 0x0040 -#define MACH64_UPLOAD_SETUP_CNTL 0x0080 -#define MACH64_UPLOAD_MISC 0x0100 -#define MACH64_UPLOAD_TEXTURE 0x0200 -#define MACH64_UPLOAD_TEX0IMAGE 0x0400 -#define MACH64_UPLOAD_TEX1IMAGE 0x0800 -#define MACH64_UPLOAD_CLIPRECTS 0x1000 /* handled client-side */ -#define MACH64_UPLOAD_CONTEXT 0x00ff -#define MACH64_UPLOAD_ALL 0x1fff - -/* DMA buffer size - */ -#define MACH64_BUFFER_SIZE 16384 - -/* Max number of swaps allowed on the ring - * before the client must wait - */ -#define MACH64_MAX_QUEUED_FRAMES 3 - -/* Byte offsets for host blit buffer data - */ -#define MACH64_HOSTDATA_BLIT_OFFSET 104 - -/* Keep these small for testing. - */ -#define MACH64_NR_SAREA_CLIPRECTS 8 - - -#define MACH64_CARD_HEAP 0 -#define MACH64_AGP_HEAP 1 -#define MACH64_NR_TEX_HEAPS 2 -#define MACH64_NR_TEX_REGIONS 64 -#define MACH64_LOG_TEX_GRANULARITY 16 - -#define MACH64_TEX_MAXLEVELS 1 - -#define MACH64_NR_CONTEXT_REGS 15 -#define MACH64_NR_TEXTURE_REGS 4 - -#endif /* __MACH64_SAREA_DEFINES__ */ - -typedef struct { - unsigned int dst_off_pitch; - - unsigned int z_off_pitch; - unsigned int z_cntl; - unsigned int alpha_tst_cntl; - - unsigned int scale_3d_cntl; - - unsigned int sc_left_right; - unsigned int sc_top_bottom; - - unsigned int dp_fog_clr; - unsigned int dp_write_mask; - unsigned int dp_pix_width; - unsigned int dp_mix; - unsigned int dp_src; - - unsigned int clr_cmp_cntl; - unsigned int gui_traj_cntl; - - unsigned int setup_cntl; - - unsigned int tex_size_pitch; - unsigned int tex_cntl; - unsigned int secondary_tex_off; - unsigned int tex_offset; -} drm_mach64_context_regs_t; - -typedef struct drm_mach64_sarea { - /* The channel for communication of state information to the kernel - * on firing a vertex dma buffer. - */ - drm_mach64_context_regs_t context_state; - unsigned int dirty; - unsigned int vertsize; - - /* The current cliprects, or a subset thereof. - */ - drm_clip_rect_t boxes[MACH64_NR_SAREA_CLIPRECTS]; - unsigned int nbox; - - /* Counters for client-side throttling of rendering clients. - */ - unsigned int frames_queued; - - /* Texture memory LRU. - */ - drm_tex_region_t tex_list[MACH64_NR_TEX_HEAPS][MACH64_NR_TEX_REGIONS+1]; - unsigned int tex_age[MACH64_NR_TEX_HEAPS]; - int ctx_owner; -} drm_mach64_sarea_t; - - -/* WARNING: If you change any of these defines, make sure to change the - * defines in the Xserver file (mach64_common.h) - */ - -/* Mach64 specific ioctls - * The device specific ioctl range is 0x40 to 0x79. - */ - -#define DRM_MACH64_INIT 0x00 -#define DRM_MACH64_IDLE 0x01 -#define DRM_MACH64_RESET 0x02 -#define DRM_MACH64_SWAP 0x03 -#define DRM_MACH64_CLEAR 0x04 -#define DRM_MACH64_VERTEX 0x05 -#define DRM_MACH64_BLIT 0x06 -#define DRM_MACH64_FLUSH 0x07 -#define DRM_MACH64_GETPARAM 0x08 - -#define DRM_IOCTL_MACH64_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_INIT, drm_mach64_init_t) -#define DRM_IOCTL_MACH64_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_IDLE ) -#define DRM_IOCTL_MACH64_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_RESET ) -#define DRM_IOCTL_MACH64_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_SWAP ) -#define DRM_IOCTL_MACH64_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_CLEAR, drm_mach64_clear_t) -#define DRM_IOCTL_MACH64_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_VERTEX, drm_mach64_vertex_t) -#define DRM_IOCTL_MACH64_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_BLIT, drm_mach64_blit_t) -#define DRM_IOCTL_MACH64_FLUSH DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_FLUSH ) -#define DRM_IOCTL_MACH64_GETPARAM DRM_IOWR( DRM_COMMAND_BASE + DRM_MACH64_GETPARAM, drm_mach64_getparam_t) - -/* Buffer flags for clears - */ -#define MACH64_FRONT 0x1 -#define MACH64_BACK 0x2 -#define MACH64_DEPTH 0x4 - -/* Primitive types for vertex buffers - */ -#define MACH64_PRIM_POINTS 0x00000000 -#define MACH64_PRIM_LINES 0x00000001 -#define MACH64_PRIM_LINE_LOOP 0x00000002 -#define MACH64_PRIM_LINE_STRIP 0x00000003 -#define MACH64_PRIM_TRIANGLES 0x00000004 -#define MACH64_PRIM_TRIANGLE_STRIP 0x00000005 -#define MACH64_PRIM_TRIANGLE_FAN 0x00000006 -#define MACH64_PRIM_QUADS 0x00000007 -#define MACH64_PRIM_QUAD_STRIP 0x00000008 -#define MACH64_PRIM_POLYGON 0x00000009 - - -typedef enum _drm_mach64_dma_mode_t { - MACH64_MODE_DMA_ASYNC, - MACH64_MODE_DMA_SYNC, - MACH64_MODE_MMIO -} drm_mach64_dma_mode_t; - -typedef struct drm_mach64_init { - enum { - DRM_MACH64_INIT_DMA = 0x01, - DRM_MACH64_CLEANUP_DMA = 0x02 - } func; - - unsigned long sarea_priv_offset; - int is_pci; - drm_mach64_dma_mode_t dma_mode; - - unsigned int fb_bpp; - unsigned int front_offset, front_pitch; - unsigned int back_offset, back_pitch; - - unsigned int depth_bpp; - unsigned int depth_offset, depth_pitch; - - unsigned long fb_offset; - unsigned long mmio_offset; - unsigned long ring_offset; - unsigned long buffers_offset; - unsigned long agp_textures_offset; -} drm_mach64_init_t; - -typedef struct drm_mach64_clear { - unsigned int flags; - int x, y, w, h; - unsigned int clear_color; - unsigned int clear_depth; -} drm_mach64_clear_t; - -typedef struct drm_mach64_vertex { - int prim; - void *buf; /* Address of vertex buffer */ - unsigned long used; /* Number of bytes in buffer */ - int discard; /* Client finished with buffer? */ -} drm_mach64_vertex_t; - -typedef struct drm_mach64_blit { - int idx; - int pitch; - int offset; - int format; - unsigned short x, y; - unsigned short width, height; -} drm_mach64_blit_t; - -typedef struct drm_mach64_getparam { - enum { - MACH64_PARAM_FRAMES_QUEUED = 0x01, - MACH64_PARAM_IRQ_NR = 0x02 - } param; - void *value; -} drm_mach64_getparam_t; - -#endif diff --git a/nx-X11/extras/drm/shared/mach64_drv.h b/nx-X11/extras/drm/shared/mach64_drv.h deleted file mode 100644 index b49e6f655..000000000 --- a/nx-X11/extras/drm/shared/mach64_drv.h +++ /dev/null @@ -1,1040 +0,0 @@ -/* mach64_drv.h -- Private header for mach64 driver -*- linux-c -*- - * Created: Fri Nov 24 22:07:58 2000 by gareth@valinux.com - * - * Copyright 2000 Gareth Hughes - * Copyright 2002 Frank C. Earl - * Copyright 2002-2003 Leif Delgass - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT OWNER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Gareth Hughes - * Frank C. Earl - * Leif Delgass - * José Fonseca - */ - -#ifndef __MACH64_DRV_H__ -#define __MACH64_DRV_H__ - - -/* FIXME: remove these when not needed */ -/* Development driver options */ -#define MACH64_EXTRA_CHECKING 0 /* Extra sanity checks for DMA/freelist management */ -#define MACH64_VERBOSE 0 /* Verbose debugging output */ - -typedef struct drm_mach64_freelist { - struct list_head list; /* List pointers for free_list, placeholders, or pending list */ - drm_buf_t *buf; /* Pointer to the buffer */ - int discard; /* This flag is set when we're done (re)using a buffer */ - u32 ring_ofs; /* dword offset in ring of last descriptor for this buffer */ -} drm_mach64_freelist_t; - -typedef struct drm_mach64_descriptor_ring { - dma_addr_t handle; /* handle (bus address) of ring returned by pci_alloc_consistent() */ - void *start; /* write pointer (cpu address) to start of descriptor ring */ - u32 start_addr; /* bus address of beginning of descriptor ring */ - int size; /* size of ring in bytes */ - - u32 head_addr; /* bus address of descriptor ring head */ - u32 head; /* dword offset of descriptor ring head */ - u32 tail; /* dword offset of descriptor ring tail */ - u32 tail_mask; /* mask used to wrap ring */ - int space; /* number of free bytes in ring */ -} drm_mach64_descriptor_ring_t; - -typedef struct drm_mach64_private { - drm_mach64_sarea_t *sarea_priv; - - int is_pci; - drm_mach64_dma_mode_t driver_mode; /* Async DMA, sync DMA, or MMIO */ - - int usec_timeout; /* Timeout for the wait functions */ - - drm_mach64_descriptor_ring_t ring; /* DMA descriptor table (ring buffer) */ - int ring_running; /* Is bus mastering is enabled */ - - struct list_head free_list; /* Free-list head */ - struct list_head placeholders; /* Placeholder list for buffers held by clients */ - struct list_head pending; /* Buffers pending completion */ - - u32 frame_ofs[MACH64_MAX_QUEUED_FRAMES]; /* dword ring offsets of most recent frame swaps */ - - unsigned int fb_bpp; - unsigned int front_offset, front_pitch; - unsigned int back_offset, back_pitch; - - unsigned int depth_bpp; - unsigned int depth_offset, depth_pitch; - - u32 front_offset_pitch; - u32 back_offset_pitch; - u32 depth_offset_pitch; - - drm_local_map_t *sarea; - drm_local_map_t *fb; - drm_local_map_t *mmio; - drm_local_map_t *ring_map; - drm_local_map_t *dev_buffers; /* this is a pointer to a structure in dev */ - drm_local_map_t *agp_textures; -} drm_mach64_private_t; - - /* mach64_dma.c */ -extern int mach64_dma_init( DRM_IOCTL_ARGS ); -extern int mach64_dma_idle( DRM_IOCTL_ARGS ); -extern int mach64_dma_flush( DRM_IOCTL_ARGS ); -extern int mach64_engine_reset( DRM_IOCTL_ARGS ); -extern int mach64_dma_buffers( DRM_IOCTL_ARGS ); - -extern int mach64_init_freelist( drm_device_t *dev ); -extern void mach64_destroy_freelist( drm_device_t *dev ); -extern drm_buf_t *mach64_freelist_get( drm_mach64_private_t *dev_priv ); - -extern int mach64_do_wait_for_fifo( drm_mach64_private_t *dev_priv, - int entries ); -extern int mach64_do_wait_for_idle( drm_mach64_private_t *dev_priv ); -extern int mach64_wait_ring( drm_mach64_private_t *dev_priv, int n ); -extern int mach64_do_dispatch_pseudo_dma( drm_mach64_private_t *dev_priv ); -extern int mach64_do_release_used_buffers( drm_mach64_private_t *dev_priv ); -extern void mach64_dump_engine_info( drm_mach64_private_t *dev_priv ); -extern void mach64_dump_ring_info( drm_mach64_private_t *dev_priv ); -extern int mach64_do_engine_reset( drm_mach64_private_t *dev_priv ); - -extern int mach64_do_dma_idle( drm_mach64_private_t *dev_priv ); -extern int mach64_do_dma_flush( drm_mach64_private_t *dev_priv ); -extern int mach64_do_cleanup_dma( drm_device_t *dev ); - - /* mach64_state.c */ -extern int mach64_dma_clear( DRM_IOCTL_ARGS ); -extern int mach64_dma_swap( DRM_IOCTL_ARGS ); -extern int mach64_dma_vertex( DRM_IOCTL_ARGS ); -extern int mach64_dma_blit( DRM_IOCTL_ARGS ); -extern int mach64_get_param( DRM_IOCTL_ARGS ); -extern int mach64_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence); - -extern irqreturn_t mach64_driver_irq_handler( DRM_IRQ_ARGS ); -extern void mach64_driver_irq_preinstall( drm_device_t *dev ); -extern void mach64_driver_irq_postinstall( drm_device_t *dev ); -extern void mach64_driver_irq_uninstall( drm_device_t *dev ); - -/* ================================================================ - * Registers - */ - -#define MACH64_AGP_BASE 0x0148 -#define MACH64_AGP_CNTL 0x014c -#define MACH64_ALPHA_TST_CNTL 0x0550 - - -#define MACH64_DSP_CONFIG 0x0420 -#define MACH64_DSP_ON_OFF 0x0424 -#define MACH64_EXT_MEM_CNTL 0x04ac -#define MACH64_GEN_TEST_CNTL 0x04d0 -#define MACH64_HW_DEBUG 0x047c -#define MACH64_MEM_ADDR_CONFIG 0x0434 -#define MACH64_MEM_BUF_CNTL 0x042c -#define MACH64_MEM_CNTL 0x04b0 - - -#define MACH64_BM_ADDR 0x0648 -#define MACH64_BM_COMMAND 0x0188 -#define MACH64_BM_DATA 0x0648 -#define MACH64_BM_FRAME_BUF_OFFSET 0x0180 -#define MACH64_BM_GUI_TABLE 0x01b8 -#define MACH64_BM_GUI_TABLE_CMD 0x064c -# define MACH64_CIRCULAR_BUF_SIZE_16KB (0 << 0) -# define MACH64_CIRCULAR_BUF_SIZE_32KB (1 << 0) -# define MACH64_CIRCULAR_BUF_SIZE_64KB (2 << 0) -# define MACH64_CIRCULAR_BUF_SIZE_128KB (3 << 0) -# define MACH64_LAST_DESCRIPTOR (1 << 31) -#define MACH64_BM_HOSTDATA 0x0644 -#define MACH64_BM_STATUS 0x018c -#define MACH64_BM_SYSTEM_MEM_ADDR 0x0184 -#define MACH64_BM_SYSTEM_TABLE 0x01bc -#define MACH64_BUS_CNTL 0x04a0 -# define MACH64_BUS_MSTR_RESET (1 << 1) -# define MACH64_BUS_APER_REG_DIS (1 << 4) -# define MACH64_BUS_FLUSH_BUF (1 << 2) -# define MACH64_BUS_MASTER_DIS (1 << 6) -# define MACH64_BUS_EXT_REG_EN (1 << 27) - -#define MACH64_CLR_CMP_CLR 0x0700 -#define MACH64_CLR_CMP_CNTL 0x0708 -#define MACH64_CLR_CMP_MASK 0x0704 -#define MACH64_CONFIG_CHIP_ID 0x04e0 -#define MACH64_CONFIG_CNTL 0x04dc -#define MACH64_CONFIG_STAT0 0x04e4 -#define MACH64_CONFIG_STAT1 0x0494 -#define MACH64_CONFIG_STAT2 0x0498 -#define MACH64_CONTEXT_LOAD_CNTL 0x072c -#define MACH64_CONTEXT_MASK 0x0720 -#define MACH64_COMPOSITE_SHADOW_ID 0x0798 -#define MACH64_CRC_SIG 0x04e8 -#define MACH64_CUSTOM_MACRO_CNTL 0x04d4 - -#define MACH64_DP_BKGD_CLR 0x06c0 -#define MACH64_DP_FOG_CLR 0x06c4 -#define MACH64_DP_FGRD_BKGD_CLR 0x06e0 -#define MACH64_DP_FRGD_CLR 0x06c4 -#define MACH64_DP_FGRD_CLR_MIX 0x06dc - -#define MACH64_DP_MIX 0x06d4 -# define BKGD_MIX_NOT_D (0 << 0) -# define BKGD_MIX_ZERO (1 << 0) -# define BKGD_MIX_ONE (2 << 0) -# define MACH64_BKGD_MIX_D (3 << 0) -# define BKGD_MIX_NOT_S (4 << 0) -# define BKGD_MIX_D_XOR_S (5 << 0) -# define BKGD_MIX_NOT_D_XOR_S (6 << 0) -# define MACH64_BKGD_MIX_S (7 << 0) -# define BKGD_MIX_NOT_D_OR_NOT_S (8 << 0) -# define BKGD_MIX_D_OR_NOT_S (9 << 0) -# define BKGD_MIX_NOT_D_OR_S (10 << 0) -# define BKGD_MIX_D_OR_S (11 << 0) -# define BKGD_MIX_D_AND_S (12 << 0) -# define BKGD_MIX_NOT_D_AND_S (13 << 0) -# define BKGD_MIX_D_AND_NOT_S (14 << 0) -# define BKGD_MIX_NOT_D_AND_NOT_S (15 << 0) -# define BKGD_MIX_D_PLUS_S_DIV2 (23 << 0) -# define FRGD_MIX_NOT_D (0 << 16) -# define FRGD_MIX_ZERO (1 << 16) -# define FRGD_MIX_ONE (2 << 16) -# define FRGD_MIX_D (3 << 16) -# define FRGD_MIX_NOT_S (4 << 16) -# define FRGD_MIX_D_XOR_S (5 << 16) -# define FRGD_MIX_NOT_D_XOR_S (6 << 16) -# define MACH64_FRGD_MIX_S (7 << 16) -# define FRGD_MIX_NOT_D_OR_NOT_S (8 << 16) -# define FRGD_MIX_D_OR_NOT_S (9 << 16) -# define FRGD_MIX_NOT_D_OR_S (10 << 16) -# define FRGD_MIX_D_OR_S (11 << 16) -# define FRGD_MIX_D_AND_S (12 << 16) -# define FRGD_MIX_NOT_D_AND_S (13 << 16) -# define FRGD_MIX_D_AND_NOT_S (14 << 16) -# define FRGD_MIX_NOT_D_AND_NOT_S (15 << 16) -# define FRGD_MIX_D_PLUS_S_DIV2 (23 << 16) - -#define MACH64_DP_PIX_WIDTH 0x06d0 -# define MACH64_HOST_TRIPLE_ENABLE (1 << 13) -# define MACH64_BYTE_ORDER_MSB_TO_LSB (0 << 24) -# define MACH64_BYTE_ORDER_LSB_TO_MSB (1 << 24) - -#define MACH64_DP_SRC 0x06d8 -# define MACH64_BKGD_SRC_BKGD_CLR (0 << 0) -# define MACH64_BKGD_SRC_FRGD_CLR (1 << 0) -# define MACH64_BKGD_SRC_HOST (2 << 0) -# define MACH64_BKGD_SRC_BLIT (3 << 0) -# define MACH64_BKGD_SRC_PATTERN (4 << 0) -# define MACH64_BKGD_SRC_3D (5 << 0) -# define MACH64_FRGD_SRC_BKGD_CLR (0 << 8) -# define MACH64_FRGD_SRC_FRGD_CLR (1 << 8) -# define MACH64_FRGD_SRC_HOST (2 << 8) -# define MACH64_FRGD_SRC_BLIT (3 << 8) -# define MACH64_FRGD_SRC_PATTERN (4 << 8) -# define MACH64_FRGD_SRC_3D (5 << 8) -# define MACH64_MONO_SRC_ONE (0 << 16) -# define MACH64_MONO_SRC_PATTERN (1 << 16) -# define MACH64_MONO_SRC_HOST (2 << 16) -# define MACH64_MONO_SRC_BLIT (3 << 16) - -#define MACH64_DP_WRITE_MASK 0x06c8 - -#define MACH64_DST_CNTL 0x0530 -# define MACH64_DST_X_RIGHT_TO_LEFT (0 << 0) -# define MACH64_DST_X_LEFT_TO_RIGHT (1 << 0) -# define MACH64_DST_Y_BOTTOM_TO_TOP (0 << 1) -# define MACH64_DST_Y_TOP_TO_BOTTOM (1 << 1) -# define MACH64_DST_X_MAJOR (0 << 2) -# define MACH64_DST_Y_MAJOR (1 << 2) -# define MACH64_DST_X_TILE (1 << 3) -# define MACH64_DST_Y_TILE (1 << 4) -# define MACH64_DST_LAST_PEL (1 << 5) -# define MACH64_DST_POLYGON_ENABLE (1 << 6) -# define MACH64_DST_24_ROTATION_ENABLE (1 << 7) - -#define MACH64_DST_HEIGHT_WIDTH 0x0518 -#define MACH64_DST_OFF_PITCH 0x0500 -#define MACH64_DST_WIDTH_HEIGHT 0x06ec -#define MACH64_DST_X_Y 0x06e8 -#define MACH64_DST_Y_X 0x050c - -#define MACH64_FIFO_STAT 0x0710 -# define MACH64_FIFO_SLOT_MASK 0x0000ffff -# define MACH64_FIFO_ERR (1 << 31) - -#define MACH64_GEN_TEST_CNTL 0x04d0 -# define MACH64_GUI_ENGINE_ENABLE (1 << 8) -#define MACH64_GUI_CMDFIFO_DEBUG 0x0170 -#define MACH64_GUI_CMDFIFO_DATA 0x0174 -#define MACH64_GUI_CNTL 0x0178 -# define MACH64_CMDFIFO_SIZE_MASK 0x00000003ul -# define MACH64_CMDFIFO_SIZE_192 0x00000000ul -# define MACH64_CMDFIFO_SIZE_128 0x00000001ul -# define MACH64_CMDFIFO_SIZE_64 0x00000002ul -#define MACH64_GUI_STAT 0x0738 -# define MACH64_GUI_ACTIVE (1 << 0) -#define MACH64_GUI_TRAJ_CNTL 0x0730 - -#define MACH64_HOST_CNTL 0x0640 -#define MACH64_HOST_DATA0 0x0600 - -#define MACH64_ONE_OVER_AREA 0x029c -#define MACH64_ONE_OVER_AREA_UC 0x0300 - -#define MACH64_PAT_REG0 0x0680 -#define MACH64_PAT_REG1 0x0684 - -#define MACH64_SC_LEFT 0x06a0 -#define MACH64_SC_RIGHT 0x06a4 -#define MACH64_SC_LEFT_RIGHT 0x06a8 -#define MACH64_SC_TOP 0x06ac -#define MACH64_SC_BOTTOM 0x06b0 -#define MACH64_SC_TOP_BOTTOM 0x06b4 - -#define MACH64_SCALE_3D_CNTL 0x05fc -#define MACH64_SCRATCH_REG0 0x0480 -#define MACH64_SCRATCH_REG1 0x0484 -#define MACH64_SECONDARY_TEX_OFF 0x0778 -#define MACH64_SETUP_CNTL 0x0304 -#define MACH64_SRC_CNTL 0x05b4 -# define MACH64_SRC_BM_ENABLE (1 << 8) -# define MACH64_SRC_BM_SYNC (1 << 9) -# define MACH64_SRC_BM_OP_FRAME_TO_SYSTEM (0 << 10) -# define MACH64_SRC_BM_OP_SYSTEM_TO_FRAME (1 << 10) -# define MACH64_SRC_BM_OP_REG_TO_SYSTEM (2 << 10) -# define MACH64_SRC_BM_OP_SYSTEM_TO_REG (3 << 10) -#define MACH64_SRC_HEIGHT1 0x0594 -#define MACH64_SRC_HEIGHT2 0x05ac -#define MACH64_SRC_HEIGHT1_WIDTH1 0x0598 -#define MACH64_SRC_HEIGHT2_WIDTH2 0x05b0 -#define MACH64_SRC_OFF_PITCH 0x0580 -#define MACH64_SRC_WIDTH1 0x0590 -#define MACH64_SRC_Y_X 0x058c - -#define MACH64_TEX_0_OFF 0x05c0 -#define MACH64_TEX_CNTL 0x0774 -#define MACH64_TEX_SIZE_PITCH 0x0770 -#define MACH64_TIMER_CONFIG 0x0428 - -#define MACH64_VERTEX_1_ARGB 0x0254 -#define MACH64_VERTEX_1_S 0x0240 -#define MACH64_VERTEX_1_SECONDARY_S 0x0328 -#define MACH64_VERTEX_1_SECONDARY_T 0x032c -#define MACH64_VERTEX_1_SECONDARY_W 0x0330 -#define MACH64_VERTEX_1_SPEC_ARGB 0x024c -#define MACH64_VERTEX_1_T 0x0244 -#define MACH64_VERTEX_1_W 0x0248 -#define MACH64_VERTEX_1_X_Y 0x0258 -#define MACH64_VERTEX_1_Z 0x0250 -#define MACH64_VERTEX_2_ARGB 0x0274 -#define MACH64_VERTEX_2_S 0x0260 -#define MACH64_VERTEX_2_SECONDARY_S 0x0334 -#define MACH64_VERTEX_2_SECONDARY_T 0x0338 -#define MACH64_VERTEX_2_SECONDARY_W 0x033c -#define MACH64_VERTEX_2_SPEC_ARGB 0x026c -#define MACH64_VERTEX_2_T 0x0264 -#define MACH64_VERTEX_2_W 0x0268 -#define MACH64_VERTEX_2_X_Y 0x0278 -#define MACH64_VERTEX_2_Z 0x0270 -#define MACH64_VERTEX_3_ARGB 0x0294 -#define MACH64_VERTEX_3_S 0x0280 -#define MACH64_VERTEX_3_SECONDARY_S 0x02a0 -#define MACH64_VERTEX_3_SECONDARY_T 0x02a4 -#define MACH64_VERTEX_3_SECONDARY_W 0x02a8 -#define MACH64_VERTEX_3_SPEC_ARGB 0x028c -#define MACH64_VERTEX_3_T 0x0284 -#define MACH64_VERTEX_3_W 0x0288 -#define MACH64_VERTEX_3_X_Y 0x0298 -#define MACH64_VERTEX_3_Z 0x0290 - -#define MACH64_Z_CNTL 0x054c -#define MACH64_Z_OFF_PITCH 0x0548 - -#define MACH64_CRTC_VLINE_CRNT_VLINE 0x0410 -# define MACH64_CRTC_VLINE_MASK 0x000007ff -# define MACH64_CRTC_CRNT_VLINE_MASK 0x07ff0000 -#define MACH64_CRTC_OFF_PITCH 0x0414 -#define MACH64_CRTC_INT_CNTL 0x0418 -# define MACH64_CRTC_VBLANK (1 << 0) -# define MACH64_CRTC_VBLANK_INT_EN (1 << 1) -# define MACH64_CRTC_VBLANK_INT (1 << 2) -# define MACH64_CRTC_VLINE_INT_EN (1 << 3) -# define MACH64_CRTC_VLINE_INT (1 << 4) -# define MACH64_CRTC_VLINE_SYNC (1 << 5) /* 0=even, 1=odd */ -# define MACH64_CRTC_FRAME (1 << 6) /* 0=even, 1=odd */ -# define MACH64_CRTC_SNAPSHOT_INT_EN (1 << 7) -# define MACH64_CRTC_SNAPSHOT_INT (1 << 8) -# define MACH64_CRTC_I2C_INT_EN (1 << 9) -# define MACH64_CRTC_I2C_INT (1 << 10) -# define MACH64_CRTC2_VBLANK (1 << 11) /* LT Pro */ -# define MACH64_CRTC2_VBLANK_INT_EN (1 << 12) /* LT Pro */ -# define MACH64_CRTC2_VBLANK_INT (1 << 13) /* LT Pro */ -# define MACH64_CRTC2_VLINE_INT_EN (1 << 14) /* LT Pro */ -# define MACH64_CRTC2_VLINE_INT (1 << 15) /* LT Pro */ -# define MACH64_CRTC_CAPBUF0_INT_EN (1 << 16) -# define MACH64_CRTC_CAPBUF0_INT (1 << 17) -# define MACH64_CRTC_CAPBUF1_INT_EN (1 << 18) -# define MACH64_CRTC_CAPBUF1_INT (1 << 19) -# define MACH64_CRTC_OVERLAY_EOF_INT_EN (1 << 20) -# define MACH64_CRTC_OVERLAY_EOF_INT (1 << 21) -# define MACH64_CRTC_ONESHOT_CAP_INT_EN (1 << 22) -# define MACH64_CRTC_ONESHOT_CAP_INT (1 << 23) -# define MACH64_CRTC_BUSMASTER_EOL_INT_EN (1 << 24) -# define MACH64_CRTC_BUSMASTER_EOL_INT (1 << 25) -# define MACH64_CRTC_GP_INT_EN (1 << 26) -# define MACH64_CRTC_GP_INT (1 << 27) -# define MACH64_CRTC2_VLINE_SYNC (1 << 28) /* LT Pro */ /* 0=even, 1=odd */ -# define MACH64_CRTC_SNAPSHOT2_INT_EN (1 << 29) /* LT Pro */ -# define MACH64_CRTC_SNAPSHOT2_INT (1 << 30) /* LT Pro */ -# define MACH64_CRTC_VBLANK2_INT (1 << 31) -# define MACH64_CRTC_INT_ENS \ - ( \ - MACH64_CRTC_VBLANK_INT_EN | \ - MACH64_CRTC_VLINE_INT_EN | \ - MACH64_CRTC_SNAPSHOT_INT_EN | \ - MACH64_CRTC_I2C_INT_EN | \ - MACH64_CRTC2_VBLANK_INT_EN | \ - MACH64_CRTC2_VLINE_INT_EN | \ - MACH64_CRTC_CAPBUF0_INT_EN | \ - MACH64_CRTC_CAPBUF1_INT_EN | \ - MACH64_CRTC_OVERLAY_EOF_INT_EN | \ - MACH64_CRTC_ONESHOT_CAP_INT_EN | \ - MACH64_CRTC_BUSMASTER_EOL_INT_EN | \ - MACH64_CRTC_GP_INT_EN | \ - MACH64_CRTC_SNAPSHOT2_INT_EN | \ - 0 \ - ) -# define MACH64_CRTC_INT_ACKS \ - ( \ - MACH64_CRTC_VBLANK_INT | \ - MACH64_CRTC_VLINE_INT | \ - MACH64_CRTC_SNAPSHOT_INT | \ - MACH64_CRTC_I2C_INT | \ - MACH64_CRTC2_VBLANK_INT | \ - MACH64_CRTC2_VLINE_INT | \ - MACH64_CRTC_CAPBUF0_INT | \ - MACH64_CRTC_CAPBUF1_INT | \ - MACH64_CRTC_OVERLAY_EOF_INT | \ - MACH64_CRTC_ONESHOT_CAP_INT | \ - MACH64_CRTC_BUSMASTER_EOL_INT | \ - MACH64_CRTC_GP_INT | \ - MACH64_CRTC_SNAPSHOT2_INT | \ - MACH64_CRTC_VBLANK2_INT | \ - 0 \ - ) - -#define MACH64_DATATYPE_CI8 2 -#define MACH64_DATATYPE_ARGB1555 3 -#define MACH64_DATATYPE_RGB565 4 -#define MACH64_DATATYPE_ARGB8888 6 -#define MACH64_DATATYPE_RGB332 7 -#define MACH64_DATATYPE_Y8 8 -#define MACH64_DATATYPE_RGB8 9 -#define MACH64_DATATYPE_VYUY422 11 -#define MACH64_DATATYPE_YVYU422 12 -#define MACH64_DATATYPE_AYUV444 14 -#define MACH64_DATATYPE_ARGB4444 15 - -#define MACH64_READ(reg) DRM_READ32(dev_priv->mmio, (reg) ) -#define MACH64_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio, (reg), (val) ) - - -#define DWMREG0 0x0400 -#define DWMREG0_END 0x07ff -#define DWMREG1 0x0000 -#define DWMREG1_END 0x03ff - -#define ISREG0(r) (((r) >= DWMREG0) && ((r) <= DWMREG0_END)) -#define DMAREG0(r) (((r) - DWMREG0) >> 2) -#define DMAREG1(r) ((((r) - DWMREG1) >> 2 ) | 0x0100) -#define DMAREG(r) (ISREG0(r) ? DMAREG0(r) : DMAREG1(r)) - -#define MMREG0 0x0000 -#define MMREG0_END 0x00ff - -#define ISMMREG0(r) (((r) >= MMREG0) && ((r) <= MMREG0_END)) -#define MMSELECT0(r) (((r) << 2) + DWMREG0) -#define MMSELECT1(r) (((((r) & 0xff) << 2) + DWMREG1)) -#define MMSELECT(r) (ISMMREG0(r) ? MMSELECT0(r) : MMSELECT1(r)) - -/* ================================================================ - * DMA constants - */ - -/* DMA descriptor field indices: - * The descriptor fields are loaded into the read-only - * BM_* system bus master registers during a bus-master operation - */ -#define MACH64_DMA_FRAME_BUF_OFFSET 0 /* BM_FRAME_BUF_OFFSET */ -#define MACH64_DMA_SYS_MEM_ADDR 1 /* BM_SYSTEM_MEM_ADDR */ -#define MACH64_DMA_COMMAND 2 /* BM_COMMAND */ -#define MACH64_DMA_RESERVED 3 /* BM_STATUS */ - -/* BM_COMMAND descriptor field flags */ -#define MACH64_DMA_HOLD_OFFSET (1<<30) /* Don't increment DMA_FRAME_BUF_OFFSET */ -#define MACH64_DMA_EOL (1<<31) /* End of descriptor list flag */ - -#define MACH64_DMA_CHUNKSIZE 0x1000 /* 4kB per DMA descriptor */ -#define MACH64_APERTURE_OFFSET 0x7ff800 /* frame-buffer offset for gui-masters */ - - -/* ================================================================ - * Misc helper macros - */ - -static __inline__ void mach64_set_dma_eol( volatile u32 * addr ) -{ -#if defined(__i386__) - int nr = 31; - - /* Taken from include/asm-i386/bitops.h linux header */ - __asm__ __volatile__( "lock;" - "btsl %1,%0" - :"=m" (*addr) - :"Ir" (nr)); -#elif defined(__powerpc__) - u32 old; - u32 mask = cpu_to_le32( MACH64_DMA_EOL ); - - /* Taken from the include/asm-ppc/bitops.h linux header */ - __asm__ __volatile__("\n\ -1: lwarx %0,0,%3 \n\ - or %0,%0,%2 \n\ - stwcx. %0,0,%3 \n\ - bne- 1b" - : "=&r" (old), "=m" (*addr) - : "r" (mask), "r" (addr), "m" (*addr) - : "cc"); -#elif defined(__alpha__) - u32 temp; - u32 mask = MACH64_DMA_EOL; - - /* Taken from the include/asm-alpha/bitops.h linux header */ - __asm__ __volatile__( - "1: ldl_l %0,%3\n" - " bis %0,%2,%0\n" - " stl_c %0,%1\n" - " beq %0,2f\n" - ".subsection 2\n" - "2: br 1b\n" - ".previous" - :"=&r" (temp), "=m" (*addr) - :"Ir" (mask), "m" (*addr)); -#else - u32 mask = cpu_to_le32( MACH64_DMA_EOL ); - - *addr |= mask; -#endif -} - -static __inline__ void mach64_clear_dma_eol( volatile u32 * addr ) -{ -#if defined(__i386__) - int nr = 31; - - /* Taken from include/asm-i386/bitops.h linux header */ - __asm__ __volatile__( "lock;" - "btrl %1,%0" - :"=m" (*addr) - :"Ir" (nr)); -#elif defined(__powerpc__) - u32 old; - u32 mask = cpu_to_le32( MACH64_DMA_EOL ); - - /* Taken from the include/asm-ppc/bitops.h linux header */ - __asm__ __volatile__("\n\ -1: lwarx %0,0,%3 \n\ - andc %0,%0,%2 \n\ - stwcx. %0,0,%3 \n\ - bne- 1b" - : "=&r" (old), "=m" (*addr) - : "r" (mask), "r" (addr), "m" (*addr) - : "cc"); -#elif defined(__alpha__) - u32 temp; - u32 mask = ~MACH64_DMA_EOL; - - /* Taken from the include/asm-alpha/bitops.h linux header */ - __asm__ __volatile__( - "1: ldl_l %0,%3\n" - " and %0,%2,%0\n" - " stl_c %0,%1\n" - " beq %0,2f\n" - ".subsection 2\n" - "2: br 1b\n" - ".previous" - :"=&r" (temp), "=m" (*addr) - :"Ir" (mask), "m" (*addr)); -#else - u32 mask = cpu_to_le32( ~MACH64_DMA_EOL ); - - *addr &= mask; -#endif -} - -static __inline__ void mach64_ring_start( drm_mach64_private_t *dev_priv ) -{ - drm_mach64_descriptor_ring_t *ring = &dev_priv->ring; - - DRM_DEBUG( "%s: head_addr: 0x%08x head: %d tail: %d space: %d\n", - __FUNCTION__, - ring->head_addr, ring->head, ring->tail, ring->space ); - - if ( mach64_do_wait_for_idle( dev_priv ) < 0 ) { - mach64_do_engine_reset( dev_priv ); - } - - if (dev_priv->driver_mode != MACH64_MODE_MMIO ) { - /* enable bus mastering and block 1 registers */ - MACH64_WRITE( MACH64_BUS_CNTL, - ( MACH64_READ(MACH64_BUS_CNTL) & ~MACH64_BUS_MASTER_DIS ) - | MACH64_BUS_EXT_REG_EN ); - mach64_do_wait_for_idle( dev_priv ); - } - - /* reset descriptor table ring head */ - MACH64_WRITE( MACH64_BM_GUI_TABLE_CMD, - ring->head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB ); - - dev_priv->ring_running = 1; -} - -static __inline__ void mach64_ring_resume( drm_mach64_private_t *dev_priv, - drm_mach64_descriptor_ring_t *ring ) -{ - DRM_DEBUG( "%s: head_addr: 0x%08x head: %d tail: %d space: %d\n", - __FUNCTION__, - ring->head_addr, ring->head, ring->tail, ring->space ); - - /* reset descriptor table ring head */ - MACH64_WRITE( MACH64_BM_GUI_TABLE_CMD, - ring->head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB ); - - if ( dev_priv->driver_mode == MACH64_MODE_MMIO ) { - mach64_do_dispatch_pseudo_dma( dev_priv ); - } else { - /* enable GUI bus mastering, and sync the bus master to the GUI */ - MACH64_WRITE( MACH64_SRC_CNTL, - MACH64_SRC_BM_ENABLE | MACH64_SRC_BM_SYNC | - MACH64_SRC_BM_OP_SYSTEM_TO_REG ); - - /* kick off the transfer */ - MACH64_WRITE( MACH64_DST_HEIGHT_WIDTH, 0 ); - if ( dev_priv->driver_mode == MACH64_MODE_DMA_SYNC ) { - if ( (mach64_do_wait_for_idle( dev_priv )) < 0 ) { - DRM_ERROR( "%s: idle failed, resetting engine\n", - __FUNCTION__); - mach64_dump_engine_info( dev_priv ); - mach64_do_engine_reset( dev_priv ); - return; - } - mach64_do_release_used_buffers( dev_priv ); - } - } -} - -static __inline__ void mach64_ring_tick( drm_mach64_private_t *dev_priv, - drm_mach64_descriptor_ring_t *ring ) -{ - DRM_DEBUG( "%s: head_addr: 0x%08x head: %d tail: %d space: %d\n", - __FUNCTION__, - ring->head_addr, ring->head, ring->tail, ring->space ); - - if ( !dev_priv->ring_running ) { - mach64_ring_start( dev_priv ); - - if ( ring->head != ring->tail ) { - mach64_ring_resume( dev_priv, ring ); - } - } else { - /* GUI_ACTIVE must be read before BM_GUI_TABLE to - * correctly determine the ring head - */ - int gui_active = MACH64_READ(MACH64_GUI_STAT) & MACH64_GUI_ACTIVE; - - ring->head_addr = MACH64_READ(MACH64_BM_GUI_TABLE) & 0xfffffff0; - - if ( gui_active ) { - /* If not idle, BM_GUI_TABLE points one descriptor - * past the current head - */ - if ( ring->head_addr == ring->start_addr ) { - ring->head_addr += ring->size; - } - ring->head_addr -= 4 * sizeof(u32); - } - - if( ring->head_addr < ring->start_addr || - ring->head_addr >= ring->start_addr + ring->size ) { - DRM_ERROR( "bad ring head address: 0x%08x\n", ring->head_addr ); - mach64_dump_ring_info( dev_priv ); - mach64_do_engine_reset( dev_priv ); - return; - } - - ring->head = (ring->head_addr - ring->start_addr) / sizeof(u32); - - if ( !gui_active && ring->head != ring->tail ) { - mach64_ring_resume( dev_priv, ring ); - } - } -} - -static __inline__ void mach64_ring_stop( drm_mach64_private_t *dev_priv ) -{ - DRM_DEBUG( "%s: head_addr: 0x%08x head: %d tail: %d space: %d\n", - __FUNCTION__, - dev_priv->ring.head_addr, dev_priv->ring.head, - dev_priv->ring.tail, dev_priv->ring.space ); - - /* restore previous SRC_CNTL to disable busmastering */ - mach64_do_wait_for_fifo( dev_priv, 1 ); - MACH64_WRITE( MACH64_SRC_CNTL, 0 ); - - /* disable busmastering but keep the block 1 registers enabled */ - mach64_do_wait_for_idle( dev_priv ); - MACH64_WRITE( MACH64_BUS_CNTL, MACH64_READ( MACH64_BUS_CNTL ) - | MACH64_BUS_MASTER_DIS | MACH64_BUS_EXT_REG_EN ); - - dev_priv->ring_running = 0; -} - -static __inline__ void -mach64_update_ring_snapshot( drm_mach64_private_t *dev_priv ) -{ - drm_mach64_descriptor_ring_t *ring = &dev_priv->ring; - - DRM_DEBUG( "%s\n", __FUNCTION__ ); - - mach64_ring_tick( dev_priv, ring ); - - ring->space = (ring->head - ring->tail) * sizeof(u32); - if ( ring->space <= 0 ) { - ring->space += ring->size; - } -} - -/* ================================================================ - * DMA descriptor ring macros - */ - -#define RING_LOCALS \ - int _ring_tail, _ring_write; unsigned int _ring_mask; volatile u32 *_ring - -#define RING_WRITE_OFS _ring_write - -#define BEGIN_RING( n ) \ -do { \ - if ( MACH64_VERBOSE ) { \ - DRM_INFO( "BEGIN_RING( %d ) in %s\n", \ - (n), __FUNCTION__ ); \ - } \ - if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \ - int ret; \ - if ((ret=mach64_wait_ring( dev_priv, (n) * sizeof(u32))) < 0 ) { \ - DRM_ERROR( "wait_ring failed, resetting engine\n"); \ - mach64_dump_engine_info( dev_priv ); \ - mach64_do_engine_reset( dev_priv ); \ - return ret; \ - } \ - } \ - dev_priv->ring.space -= (n) * sizeof(u32); \ - _ring = (u32 *) dev_priv->ring.start; \ - _ring_tail = _ring_write = dev_priv->ring.tail; \ - _ring_mask = dev_priv->ring.tail_mask; \ -} while (0) - -#define OUT_RING( x ) \ -do { \ - if ( MACH64_VERBOSE ) { \ - DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ - (unsigned int)(x), _ring_write ); \ - } \ - _ring[_ring_write++] = cpu_to_le32( x ); \ - _ring_write &= _ring_mask; \ -} while (0) - -#define ADVANCE_RING() \ -do { \ - if ( MACH64_VERBOSE ) { \ - DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \ - _ring_write, _ring_tail ); \ - } \ - DRM_MEMORYBARRIER(); \ - mach64_clear_dma_eol( &_ring[(_ring_tail - 2) & _ring_mask] ); \ - DRM_MEMORYBARRIER(); \ - dev_priv->ring.tail = _ring_write; \ - mach64_ring_tick( dev_priv, &(dev_priv)->ring ); \ -} while (0) - - -/* ================================================================ - * DMA macros - */ - -#define DMALOCALS \ - drm_mach64_freelist_t *_entry = NULL; \ - drm_buf_t *_buf = NULL; \ - u32 *_buf_wptr; int _outcount - -#define GETBUFPTR( __buf ) \ -((dev_priv->is_pci) ? \ - ((u32 *)(__buf)->address) : \ - ((u32 *)((char *)dev_priv->dev_buffers->handle + (__buf)->offset))) - -#define GETBUFADDR( __buf ) ((u32)(__buf)->bus_address) - -#define GETRINGOFFSET() (_entry->ring_ofs) - -static __inline__ int mach64_find_pending_buf_entry ( drm_mach64_private_t *dev_priv, - drm_mach64_freelist_t **entry, - drm_buf_t *buf ) -{ - struct list_head *ptr; -#if MACH64_EXTRA_CHECKING - if (list_empty(&dev_priv->pending)) { - DRM_ERROR("Empty pending list in %s\n", __FUNCTION__); - return DRM_ERR(EINVAL); - } -#endif - ptr = dev_priv->pending.prev; - *entry = list_entry(ptr, drm_mach64_freelist_t, list); - while ((*entry)->buf != buf) { - if (ptr == &dev_priv->pending) { - return DRM_ERR(EFAULT); - } - ptr = ptr->prev; - *entry = list_entry(ptr, drm_mach64_freelist_t, list); - } - return 0; -} - -#define DMASETPTR( _p ) \ -do { \ - _buf = (_p); \ - _outcount = 0; \ - _buf_wptr = GETBUFPTR( _buf ); \ -} while(0) - -/* FIXME: use a private set of smaller buffers for state emits, clears, and swaps? */ -#define DMAGETPTR( filp, dev_priv, n ) \ -do { \ - if ( MACH64_VERBOSE ) { \ - DRM_INFO( "DMAGETPTR( %d ) in %s\n", \ - n, __FUNCTION__ ); \ - } \ - _buf = mach64_freelist_get( dev_priv ); \ - if (_buf == NULL) { \ - DRM_ERROR("%s: couldn't get buffer in DMAGETPTR\n", \ - __FUNCTION__ ); \ - return DRM_ERR(EAGAIN); \ - } \ - if (_buf->pending) { \ - DRM_ERROR("%s: pending buf in DMAGETPTR\n", \ - __FUNCTION__ ); \ - return DRM_ERR(EFAULT); \ - } \ - _buf->filp = filp; \ - _outcount = 0; \ - \ - _buf_wptr = GETBUFPTR( _buf ); \ -} while (0) - -#define DMAOUTREG( reg, val ) \ -do { \ - if ( MACH64_VERBOSE ) { \ - DRM_INFO( " DMAOUTREG( 0x%x = 0x%08x )\n", \ - reg, val ); \ - } \ - _buf_wptr[_outcount++] = cpu_to_le32(DMAREG(reg)); \ - _buf_wptr[_outcount++] = cpu_to_le32((val)); \ - _buf->used += 8; \ -} while (0) - -#define DMAADVANCE( dev_priv, _discard ) \ -do { \ - struct list_head *ptr; \ - RING_LOCALS; \ - \ - if ( MACH64_VERBOSE ) { \ - DRM_INFO( "DMAADVANCE() in %s\n", __FUNCTION__ ); \ - } \ - \ - if (_buf->used <= 0) { \ - DRM_ERROR( "DMAADVANCE() in %s: sending empty buf %d\n", \ - __FUNCTION__, _buf->idx ); \ - return DRM_ERR(EFAULT); \ - } \ - if (_buf->pending) { \ - /* This is a resued buffer, so we need to find it in the pending list */ \ - int ret; \ - if ( (ret=mach64_find_pending_buf_entry(dev_priv, &_entry, _buf)) ) { \ - DRM_ERROR( "DMAADVANCE() in %s: couldn't find pending buf %d\n", \ - __FUNCTION__, _buf->idx ); \ - return ret; \ - } \ - if (_entry->discard) { \ - DRM_ERROR( "DMAADVANCE() in %s: sending discarded pending buf %d\n", \ - __FUNCTION__, _buf->idx ); \ - return DRM_ERR(EFAULT); \ - } \ - } else { \ - if (list_empty(&dev_priv->placeholders)) { \ - DRM_ERROR( "DMAADVANCE() in %s: empty placeholder list\n", \ - __FUNCTION__ ); \ - return DRM_ERR(EFAULT); \ - } \ - ptr = dev_priv->placeholders.next; \ - list_del(ptr); \ - _entry = list_entry(ptr, drm_mach64_freelist_t, list); \ - _buf->pending = 1; \ - _entry->buf = _buf; \ - list_add_tail(ptr, &dev_priv->pending); \ - } \ - _entry->discard = (_discard); \ - ADD_BUF_TO_RING( dev_priv ); \ -} while (0) - -#define DMADISCARDBUF() \ -do { \ - if (_entry == NULL) { \ - int ret; \ - if ( (ret=mach64_find_pending_buf_entry(dev_priv, &_entry, _buf)) ) { \ - DRM_ERROR( "%s: couldn't find pending buf %d\n", \ - __FUNCTION__, _buf->idx ); \ - return ret; \ - } \ - } \ - _entry->discard = 1; \ -} while(0) - -#define ADD_BUF_TO_RING( dev_priv ) \ -do { \ - int bytes, pages, remainder; \ - u32 address, page; \ - int i; \ - \ - bytes = _buf->used; \ - address = GETBUFADDR( _buf ); \ - \ - pages = (bytes + MACH64_DMA_CHUNKSIZE - 1) / MACH64_DMA_CHUNKSIZE; \ - \ - BEGIN_RING( pages * 4 ); \ - \ - for ( i = 0 ; i < pages-1 ; i++ ) { \ - page = address + i * MACH64_DMA_CHUNKSIZE; \ - OUT_RING( MACH64_APERTURE_OFFSET + MACH64_BM_ADDR ); \ - OUT_RING( page ); \ - OUT_RING( MACH64_DMA_CHUNKSIZE | MACH64_DMA_HOLD_OFFSET ); \ - OUT_RING( 0 ); \ - } \ - \ - /* generate the final descriptor for any remaining commands in this buffer */ \ - page = address + i * MACH64_DMA_CHUNKSIZE; \ - remainder = bytes - i * MACH64_DMA_CHUNKSIZE; \ - \ - /* Save dword offset of last descriptor for this buffer. \ - * This is needed to check for completion of the buffer in freelist_get \ - */ \ - _entry->ring_ofs = RING_WRITE_OFS; \ - \ - OUT_RING( MACH64_APERTURE_OFFSET + MACH64_BM_ADDR ); \ - OUT_RING( page ); \ - OUT_RING( remainder | MACH64_DMA_HOLD_OFFSET | MACH64_DMA_EOL ); \ - OUT_RING( 0 ); \ - \ - ADVANCE_RING(); \ -} while(0) - -#define DMAADVANCEHOSTDATA( dev_priv ) \ -do { \ - struct list_head *ptr; \ - RING_LOCALS; \ - \ - if ( MACH64_VERBOSE ) { \ - DRM_INFO( "DMAADVANCEHOSTDATA() in %s\n", __FUNCTION__ ); \ - } \ - \ - if (_buf->used <= 0) { \ - DRM_ERROR( "DMAADVANCEHOSTDATA() in %s: sending empty buf %d\n", \ - __FUNCTION__, _buf->idx ); \ - return DRM_ERR(EFAULT); \ - } \ - if (list_empty(&dev_priv->placeholders)) { \ - DRM_ERROR( "%s: empty placeholder list in DMAADVANCEHOSTDATA()\n", \ - __FUNCTION__ ); \ - return DRM_ERR(EFAULT); \ - } \ - \ - ptr = dev_priv->placeholders.next; \ - list_del(ptr); \ - _entry = list_entry(ptr, drm_mach64_freelist_t, list); \ - _entry->buf = _buf; \ - _entry->buf->pending = 1; \ - list_add_tail(ptr, &dev_priv->pending); \ - _entry->discard = 1; \ - ADD_HOSTDATA_BUF_TO_RING( dev_priv ); \ -} while (0) - -#define ADD_HOSTDATA_BUF_TO_RING( dev_priv ) \ -do { \ - int bytes, pages, remainder; \ - u32 address, page; \ - int i; \ - \ - bytes = _buf->used - MACH64_HOSTDATA_BLIT_OFFSET; \ - pages = (bytes + MACH64_DMA_CHUNKSIZE - 1) / MACH64_DMA_CHUNKSIZE; \ - address = GETBUFADDR( _buf ); \ - \ - BEGIN_RING( 4 + pages * 4 ); \ - \ - OUT_RING( MACH64_APERTURE_OFFSET + MACH64_BM_ADDR ); \ - OUT_RING( address ); \ - OUT_RING( MACH64_HOSTDATA_BLIT_OFFSET | MACH64_DMA_HOLD_OFFSET ); \ - OUT_RING( 0 ); \ - \ - address += MACH64_HOSTDATA_BLIT_OFFSET; \ - \ - for ( i = 0 ; i < pages-1 ; i++ ) { \ - page = address + i * MACH64_DMA_CHUNKSIZE; \ - OUT_RING( MACH64_APERTURE_OFFSET + MACH64_BM_HOSTDATA ); \ - OUT_RING( page ); \ - OUT_RING( MACH64_DMA_CHUNKSIZE | MACH64_DMA_HOLD_OFFSET ); \ - OUT_RING( 0 ); \ - } \ - \ - /* generate the final descriptor for any remaining commands in this buffer */ \ - page = address + i * MACH64_DMA_CHUNKSIZE; \ - remainder = bytes - i * MACH64_DMA_CHUNKSIZE; \ - \ - /* Save dword offset of last descriptor for this buffer. \ - * This is needed to check for completion of the buffer in freelist_get \ - */ \ - _entry->ring_ofs = RING_WRITE_OFS; \ - \ - OUT_RING( MACH64_APERTURE_OFFSET + MACH64_BM_HOSTDATA ); \ - OUT_RING( page ); \ - OUT_RING( remainder | MACH64_DMA_HOLD_OFFSET | MACH64_DMA_EOL ); \ - OUT_RING( 0 ); \ - \ - ADVANCE_RING(); \ -} while(0) - -#endif /* __MACH64_DRV_H__ */ diff --git a/nx-X11/extras/drm/shared/mach64_irq.c b/nx-X11/extras/drm/shared/mach64_irq.c deleted file mode 100644 index efa0641f7..000000000 --- a/nx-X11/extras/drm/shared/mach64_irq.c +++ /dev/null @@ -1,130 +0,0 @@ -/* mach64_irq.c -- IRQ handling for ATI Mach64 -*- linux-c -*- - * Created: Tue Feb 25, 2003 by Leif Delgass, based on radeon_irq.c/r128_irq.c - * - * Copyright (C) The Weather Channel, Inc. 2002. - * Copyright 2003 Leif Delgass - * All Rights Reserved. - * - * The Weather Channel (TM) funded Tungsten Graphics to develop the - * initial release of the Radeon 8500 driver under the XFree86 license. - * This notice must be preserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Keith Whitwell - * Eric Anholt - * Leif Delgass - */ - -#include "mach64.h" -#include "drmP.h" -#include "drm.h" -#include "mach64_drm.h" -#include "mach64_drv.h" - -irqreturn_t mach64_driver_irq_handler( DRM_IRQ_ARGS ) -{ - drm_device_t *dev = (drm_device_t *) arg; - drm_mach64_private_t *dev_priv = - (drm_mach64_private_t *)dev->dev_private; - int status; - - status = MACH64_READ( MACH64_CRTC_INT_CNTL ); - - /* VBLANK interrupt */ - if (status & MACH64_CRTC_VBLANK_INT) { - /* Mask off all interrupt ack bits before setting the ack bit, since - * there may be other handlers outside the DRM. - * - * NOTE: On mach64, you need to keep the enable bits set when doing - * the ack, despite what the docs say about not acking and enabling - * in a single write. - */ - MACH64_WRITE( MACH64_CRTC_INT_CNTL, (status & ~MACH64_CRTC_INT_ACKS) - | MACH64_CRTC_VBLANK_INT ); - - atomic_inc(&dev->vbl_received); - DRM_WAKEUP(&dev->vbl_queue); - DRM(vbl_send_signals)( dev ); - return IRQ_HANDLED; - } - return IRQ_NONE; -} - -int mach64_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence) -{ - unsigned int cur_vblank; - int ret = 0; - - /* Assume that the user has missed the current sequence number - * by about a day rather than she wants to wait for years - * using vertical blanks... - */ - DRM_WAIT_ON( ret, dev->vbl_queue, 3*DRM_HZ, - ( ( ( cur_vblank = atomic_read(&dev->vbl_received ) ) - - *sequence ) <= (1<<23) ) ); - - *sequence = cur_vblank; - - return ret; -} - -/* drm_dma.h hooks -*/ -void mach64_driver_irq_preinstall( drm_device_t *dev ) { - drm_mach64_private_t *dev_priv = - (drm_mach64_private_t *)dev->dev_private; - - u32 status = MACH64_READ( MACH64_CRTC_INT_CNTL ); - - DRM_DEBUG("before install CRTC_INT_CTNL: 0x%08x\n", status ); - - /* Disable and clear VBLANK interrupt */ - MACH64_WRITE( MACH64_CRTC_INT_CNTL, (status & ~MACH64_CRTC_VBLANK_INT_EN) - | MACH64_CRTC_VBLANK_INT ); -} - -void mach64_driver_irq_postinstall( drm_device_t *dev ) { - drm_mach64_private_t *dev_priv = - (drm_mach64_private_t *)dev->dev_private; - - /* Turn on VBLANK interrupt */ - MACH64_WRITE( MACH64_CRTC_INT_CNTL, MACH64_READ( MACH64_CRTC_INT_CNTL ) - | MACH64_CRTC_VBLANK_INT_EN ); - - DRM_DEBUG("after install CRTC_INT_CTNL: 0x%08x\n", MACH64_READ( MACH64_CRTC_INT_CNTL )); - -} - -void mach64_driver_irq_uninstall( drm_device_t *dev ) { - drm_mach64_private_t *dev_priv = - (drm_mach64_private_t *)dev->dev_private; - if ( !dev_priv ) - return; - - /* Disable and clear VBLANK interrupt */ - MACH64_WRITE( MACH64_CRTC_INT_CNTL, - (MACH64_READ( MACH64_CRTC_INT_CNTL ) & ~MACH64_CRTC_VBLANK_INT_EN) - | MACH64_CRTC_VBLANK_INT ); - - DRM_DEBUG("after uninstall CRTC_INT_CTNL: 0x%08x\n", - MACH64_READ( MACH64_CRTC_INT_CNTL )); -} diff --git a/nx-X11/extras/drm/shared/mach64_state.c b/nx-X11/extras/drm/shared/mach64_state.c deleted file mode 100644 index ef85ffd8d..000000000 --- a/nx-X11/extras/drm/shared/mach64_state.c +++ /dev/null @@ -1,896 +0,0 @@ -/* mach64_state.c -- State support for mach64 (Rage Pro) driver -*- linux-c -*- - * Created: Sun Dec 03 19:20:26 2000 by gareth@valinux.com - * - * Copyright 2000 Gareth Hughes - * Copyright 2002-2003 Leif Delgass - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT OWNER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Gareth Hughes - * Leif Delgass - * José Fonseca - */ - -#include "mach64.h" -#include "drmP.h" -#include "drm.h" -#include "mach64_drm.h" -#include "mach64_drv.h" - - -/* ================================================================ - * DMA hardware state programming functions - */ - -static void mach64_print_dirty( const char *msg, unsigned int flags ) -{ - DRM_DEBUG( "%s: (0x%x) %s%s%s%s%s%s%s%s%s%s%s%s\n", - msg, - flags, - (flags & MACH64_UPLOAD_DST_OFF_PITCH) ? "dst_off_pitch, " : "", - (flags & MACH64_UPLOAD_Z_ALPHA_CNTL) ? "z_alpha_cntl, " : "", - (flags & MACH64_UPLOAD_SCALE_3D_CNTL) ? "scale_3d_cntl, " : "", - (flags & MACH64_UPLOAD_DP_FOG_CLR) ? "dp_fog_clr, " : "", - (flags & MACH64_UPLOAD_DP_WRITE_MASK) ? "dp_write_mask, " : "", - (flags & MACH64_UPLOAD_DP_PIX_WIDTH) ? "dp_pix_width, " : "", - (flags & MACH64_UPLOAD_SETUP_CNTL) ? "setup_cntl, " : "", - (flags & MACH64_UPLOAD_MISC) ? "misc, " : "", - (flags & MACH64_UPLOAD_TEXTURE) ? "texture, " : "", - (flags & MACH64_UPLOAD_TEX0IMAGE) ? "tex0 image, " : "", - (flags & MACH64_UPLOAD_TEX1IMAGE) ? "tex1 image, " : "", - (flags & MACH64_UPLOAD_CLIPRECTS) ? "cliprects, " : "" ); -} - -/* Mach64 doesn't have hardware cliprects, just one hardware scissor, - * so the GL scissor is intersected with each cliprect here - */ -/* This function returns 0 on success, 1 for no intersection, and - * negative for an error - */ -static int mach64_emit_cliprect( DRMFILE filp, drm_mach64_private_t *dev_priv, - drm_clip_rect_t *box ) -{ - u32 sc_left_right, sc_top_bottom; - drm_clip_rect_t scissor; - drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mach64_context_regs_t *regs = &sarea_priv->context_state; - DMALOCALS; - - DRM_DEBUG( "%s: box=%p\n", __FUNCTION__, box ); - - /* Get GL scissor */ - /* FIXME: store scissor in SAREA as a cliprect instead of in - * hardware format, or do intersection client-side - */ - scissor.x1 = regs->sc_left_right & 0xffff; - scissor.x2 = (regs->sc_left_right & 0xffff0000) >> 16; - scissor.y1 = regs->sc_top_bottom & 0xffff; - scissor.y2 = (regs->sc_top_bottom & 0xffff0000) >> 16; - - /* Intersect GL scissor with cliprect */ - if ( box->x1 > scissor.x1 ) scissor.x1 = box->x1; - if ( box->y1 > scissor.y1 ) scissor.y1 = box->y1; - if ( box->x2 < scissor.x2 ) scissor.x2 = box->x2; - if ( box->y2 < scissor.y2 ) scissor.y2 = box->y2; - /* positive return means skip */ - if ( scissor.x1 >= scissor.x2 ) return 1; - if ( scissor.y1 >= scissor.y2 ) return 1; - - DMAGETPTR( filp, dev_priv, 2 ); /* returns on failure to get buffer */ - - sc_left_right = ( (scissor.x1 << 0) | (scissor.x2 << 16) ); - sc_top_bottom = ( (scissor.y1 << 0) | (scissor.y2 << 16) ); - - DMAOUTREG( MACH64_SC_LEFT_RIGHT, sc_left_right ); - DMAOUTREG( MACH64_SC_TOP_BOTTOM, sc_top_bottom ); - - DMAADVANCE( dev_priv, 1 ); - - return 0; -} - -static __inline__ int mach64_emit_state( DRMFILE filp, drm_mach64_private_t *dev_priv ) -{ - drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mach64_context_regs_t *regs = &sarea_priv->context_state; - unsigned int dirty = sarea_priv->dirty; - u32 offset = ((regs->tex_size_pitch & 0xf0) >> 2); - DMALOCALS; - - if ( MACH64_VERBOSE ) { - mach64_print_dirty( __FUNCTION__, dirty ); - } else { - DRM_DEBUG( "%s: dirty=0x%08x\n", __FUNCTION__, dirty ); - } - - DMAGETPTR( filp, dev_priv, 17 ); /* returns on failure to get buffer */ - - if ( dirty & MACH64_UPLOAD_MISC ) { - DMAOUTREG( MACH64_DP_MIX, regs->dp_mix ); - DMAOUTREG( MACH64_DP_SRC, regs->dp_src ); - DMAOUTREG( MACH64_CLR_CMP_CNTL, regs->clr_cmp_cntl ); - DMAOUTREG( MACH64_GUI_TRAJ_CNTL, regs->gui_traj_cntl ); - sarea_priv->dirty &= ~MACH64_UPLOAD_MISC; - } - - if ( dirty & MACH64_UPLOAD_DST_OFF_PITCH ) { - DMAOUTREG( MACH64_DST_OFF_PITCH, regs->dst_off_pitch ); - sarea_priv->dirty &= ~MACH64_UPLOAD_DST_OFF_PITCH; - } - if ( dirty & MACH64_UPLOAD_Z_OFF_PITCH ) { - DMAOUTREG( MACH64_Z_OFF_PITCH, regs->z_off_pitch ); - sarea_priv->dirty &= ~MACH64_UPLOAD_Z_OFF_PITCH; - } - if ( dirty & MACH64_UPLOAD_Z_ALPHA_CNTL ) { - DMAOUTREG( MACH64_Z_CNTL, regs->z_cntl ); - DMAOUTREG( MACH64_ALPHA_TST_CNTL, regs->alpha_tst_cntl ); - sarea_priv->dirty &= ~MACH64_UPLOAD_Z_ALPHA_CNTL; - } - if ( dirty & MACH64_UPLOAD_SCALE_3D_CNTL ) { - DMAOUTREG( MACH64_SCALE_3D_CNTL, regs->scale_3d_cntl ); - sarea_priv->dirty &= ~MACH64_UPLOAD_SCALE_3D_CNTL; - } - if ( dirty & MACH64_UPLOAD_DP_FOG_CLR ) { - DMAOUTREG( MACH64_DP_FOG_CLR, regs->dp_fog_clr ); - sarea_priv->dirty &= ~MACH64_UPLOAD_DP_FOG_CLR; - } - if ( dirty & MACH64_UPLOAD_DP_WRITE_MASK ) { - DMAOUTREG( MACH64_DP_WRITE_MASK, regs->dp_write_mask ); - sarea_priv->dirty &= ~MACH64_UPLOAD_DP_WRITE_MASK; - } - if ( dirty & MACH64_UPLOAD_DP_PIX_WIDTH ) { - DMAOUTREG( MACH64_DP_PIX_WIDTH, regs->dp_pix_width ); - sarea_priv->dirty &= ~MACH64_UPLOAD_DP_PIX_WIDTH; - } - if ( dirty & MACH64_UPLOAD_SETUP_CNTL ) { - DMAOUTREG( MACH64_SETUP_CNTL, regs->setup_cntl ); - sarea_priv->dirty &= ~MACH64_UPLOAD_SETUP_CNTL; - } - - if ( dirty & MACH64_UPLOAD_TEXTURE ) { - DMAOUTREG( MACH64_TEX_SIZE_PITCH, regs->tex_size_pitch ); - DMAOUTREG( MACH64_TEX_CNTL, regs->tex_cntl ); - DMAOUTREG( MACH64_SECONDARY_TEX_OFF, regs->secondary_tex_off ); - DMAOUTREG( MACH64_TEX_0_OFF + offset, regs->tex_offset ); - sarea_priv->dirty &= ~MACH64_UPLOAD_TEXTURE; - } - - DMAADVANCE( dev_priv, 1 ); - - sarea_priv->dirty &= MACH64_UPLOAD_CLIPRECTS; - - return 0; - -} - - -/* ================================================================ - * DMA command dispatch functions - */ - -static int mach64_dma_dispatch_clear( DRMFILE filp, drm_device_t *dev, - unsigned int flags, - int cx, int cy, int cw, int ch, - unsigned int clear_color, - unsigned int clear_depth ) -{ - drm_mach64_private_t *dev_priv = dev->dev_private; - drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mach64_context_regs_t *ctx = &sarea_priv->context_state; - int nbox = sarea_priv->nbox; - drm_clip_rect_t *pbox = sarea_priv->boxes; - u32 fb_bpp, depth_bpp; - int i; - DMALOCALS; - - DRM_DEBUG( "%s\n", __FUNCTION__ ); - - switch ( dev_priv->fb_bpp ) { - case 16: - fb_bpp = MACH64_DATATYPE_RGB565; - break; - case 32: - fb_bpp = MACH64_DATATYPE_ARGB8888; - break; - default: - return DRM_ERR(EINVAL); - } - switch ( dev_priv->depth_bpp ) { - case 16: - depth_bpp = MACH64_DATATYPE_RGB565; - break; - case 24: - case 32: - depth_bpp = MACH64_DATATYPE_ARGB8888; - break; - default: - return DRM_ERR(EINVAL); - } - - if ( !nbox ) - return 0; - - DMAGETPTR( filp, dev_priv, nbox * 31 ); /* returns on failure to get buffer */ - - for ( i = 0 ; i < nbox ; i++ ) { - int x = pbox[i].x1; - int y = pbox[i].y1; - int w = pbox[i].x2 - x; - int h = pbox[i].y2 - y; - - DRM_DEBUG( "dispatch clear %d,%d-%d,%d flags 0x%x\n", - pbox[i].x1, pbox[i].y1, - pbox[i].x2, pbox[i].y2, flags ); - - if ( flags & (MACH64_FRONT | MACH64_BACK) ) { - /* Setup for color buffer clears - */ - - DMAOUTREG( MACH64_Z_CNTL, 0 ); - DMAOUTREG( MACH64_SCALE_3D_CNTL, 0 ); - - DMAOUTREG( MACH64_SC_LEFT_RIGHT, ctx->sc_left_right ); - DMAOUTREG( MACH64_SC_TOP_BOTTOM, ctx->sc_top_bottom ); - - DMAOUTREG( MACH64_CLR_CMP_CNTL, 0 ); - DMAOUTREG( MACH64_GUI_TRAJ_CNTL, - (MACH64_DST_X_LEFT_TO_RIGHT | - MACH64_DST_Y_TOP_TO_BOTTOM) ); - - DMAOUTREG( MACH64_DP_PIX_WIDTH, ((fb_bpp << 0) | - (fb_bpp << 4) | - (fb_bpp << 8) | - (fb_bpp << 16) | - (fb_bpp << 28)) ); - - DMAOUTREG( MACH64_DP_FRGD_CLR, clear_color ); - DMAOUTREG( MACH64_DP_WRITE_MASK, ctx->dp_write_mask ); - DMAOUTREG( MACH64_DP_MIX, (MACH64_BKGD_MIX_D | - MACH64_FRGD_MIX_S) ); - DMAOUTREG( MACH64_DP_SRC, (MACH64_BKGD_SRC_FRGD_CLR | - MACH64_FRGD_SRC_FRGD_CLR | - MACH64_MONO_SRC_ONE) ); - - - } - - if ( flags & MACH64_FRONT ) { - - DMAOUTREG( MACH64_DST_OFF_PITCH, - dev_priv->front_offset_pitch ); - DMAOUTREG( MACH64_DST_X_Y, - (y << 16) | x ); - DMAOUTREG( MACH64_DST_WIDTH_HEIGHT, - (h << 16) | w ); - - } - - if ( flags & MACH64_BACK ) { - - DMAOUTREG( MACH64_DST_OFF_PITCH, - dev_priv->back_offset_pitch ); - DMAOUTREG( MACH64_DST_X_Y, - (y << 16) | x ); - DMAOUTREG( MACH64_DST_WIDTH_HEIGHT, - (h << 16) | w ); - - } - - if ( flags & MACH64_DEPTH ) { - /* Setup for depth buffer clear - */ - DMAOUTREG( MACH64_Z_CNTL, 0 ); - DMAOUTREG( MACH64_SCALE_3D_CNTL, 0 ); - - DMAOUTREG( MACH64_SC_LEFT_RIGHT, ctx->sc_left_right ); - DMAOUTREG( MACH64_SC_TOP_BOTTOM, ctx->sc_top_bottom ); - - DMAOUTREG( MACH64_CLR_CMP_CNTL, 0 ); - DMAOUTREG( MACH64_GUI_TRAJ_CNTL, - (MACH64_DST_X_LEFT_TO_RIGHT | - MACH64_DST_Y_TOP_TO_BOTTOM) ); - - DMAOUTREG( MACH64_DP_PIX_WIDTH, ((depth_bpp << 0) | - (depth_bpp << 4) | - (depth_bpp << 8) | - (depth_bpp << 16) | - (depth_bpp << 28)) ); - - DMAOUTREG( MACH64_DP_FRGD_CLR, clear_depth ); - DMAOUTREG( MACH64_DP_WRITE_MASK, 0xffffffff ); - DMAOUTREG( MACH64_DP_MIX, (MACH64_BKGD_MIX_D | - MACH64_FRGD_MIX_S) ); - DMAOUTREG( MACH64_DP_SRC, (MACH64_BKGD_SRC_FRGD_CLR | - MACH64_FRGD_SRC_FRGD_CLR | - MACH64_MONO_SRC_ONE) ); - - DMAOUTREG( MACH64_DST_OFF_PITCH, - dev_priv->depth_offset_pitch ); - DMAOUTREG( MACH64_DST_X_Y, - (y << 16) | x ); - DMAOUTREG( MACH64_DST_WIDTH_HEIGHT, - (h << 16) | w ); - } - } - - DMAADVANCE( dev_priv, 1 ); - - return 0; -} - -static int mach64_dma_dispatch_swap( DRMFILE filp, drm_device_t *dev ) -{ - drm_mach64_private_t *dev_priv = dev->dev_private; - drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv; - int nbox = sarea_priv->nbox; - drm_clip_rect_t *pbox = sarea_priv->boxes; - u32 fb_bpp; - int i; - DMALOCALS; - - DRM_DEBUG( "%s\n", __FUNCTION__ ); - - switch ( dev_priv->fb_bpp ) { - case 16: - fb_bpp = MACH64_DATATYPE_RGB565; - break; - case 32: - default: - fb_bpp = MACH64_DATATYPE_ARGB8888; - break; - } - - if ( !nbox ) - return 0; - - DMAGETPTR( filp, dev_priv, 13 + nbox * 4 ); /* returns on failure to get buffer */ - - DMAOUTREG( MACH64_Z_CNTL, 0 ); - DMAOUTREG( MACH64_SCALE_3D_CNTL, 0 ); - - DMAOUTREG( MACH64_SC_LEFT_RIGHT, 0 | ( 8191 << 16 ) ); /* no scissor */ - DMAOUTREG( MACH64_SC_TOP_BOTTOM, 0 | ( 16383 << 16 ) ); - - DMAOUTREG( MACH64_CLR_CMP_CNTL, 0 ); - DMAOUTREG( MACH64_GUI_TRAJ_CNTL, (MACH64_DST_X_LEFT_TO_RIGHT | - MACH64_DST_Y_TOP_TO_BOTTOM) ); - - DMAOUTREG( MACH64_DP_PIX_WIDTH, ((fb_bpp << 0) | - (fb_bpp << 4) | - (fb_bpp << 8) | - (fb_bpp << 16) | - (fb_bpp << 28)) ); - - DMAOUTREG( MACH64_DP_WRITE_MASK, 0xffffffff ); - DMAOUTREG( MACH64_DP_MIX, (MACH64_BKGD_MIX_D | - MACH64_FRGD_MIX_S) ); - DMAOUTREG( MACH64_DP_SRC, (MACH64_BKGD_SRC_BKGD_CLR | - MACH64_FRGD_SRC_BLIT | - MACH64_MONO_SRC_ONE) ); - - DMAOUTREG( MACH64_SRC_OFF_PITCH, dev_priv->back_offset_pitch ); - DMAOUTREG( MACH64_DST_OFF_PITCH, dev_priv->front_offset_pitch ); - - for ( i = 0 ; i < nbox ; i++ ) { - int x = pbox[i].x1; - int y = pbox[i].y1; - int w = pbox[i].x2 - x; - int h = pbox[i].y2 - y; - - DRM_DEBUG( "dispatch swap %d,%d-%d,%d\n", - pbox[i].x1, pbox[i].y1, - pbox[i].x2, pbox[i].y2 ); - - DMAOUTREG( MACH64_SRC_WIDTH1, w ); - DMAOUTREG( MACH64_SRC_Y_X, (x << 16) | y ); - DMAOUTREG( MACH64_DST_Y_X, (x << 16) | y ); - DMAOUTREG( MACH64_DST_WIDTH_HEIGHT, (h << 16) | w ); - - } - - DMAADVANCE( dev_priv, 1 ); - - if (dev_priv->driver_mode == MACH64_MODE_DMA_ASYNC) { - for (i = 0; i < MACH64_MAX_QUEUED_FRAMES - 1; i++) { - dev_priv->frame_ofs[i] = dev_priv->frame_ofs[i+1]; - } - dev_priv->frame_ofs[i] = GETRINGOFFSET(); - - dev_priv->sarea_priv->frames_queued++; - } - - return 0; -} - -static int mach64_do_get_frames_queued( drm_mach64_private_t *dev_priv ) -{ - drm_mach64_descriptor_ring_t *ring = &dev_priv->ring; - drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv; - int i, start; - u32 head, tail, ofs; - - DRM_DEBUG( "%s\n", __FUNCTION__ ); - - if (sarea_priv->frames_queued == 0) - return 0; - - tail = ring->tail; - mach64_ring_tick( dev_priv, ring ); - head = ring->head; - - start = ( MACH64_MAX_QUEUED_FRAMES - - DRM_MIN(MACH64_MAX_QUEUED_FRAMES, sarea_priv->frames_queued) ); - - if ( head == tail ) { - sarea_priv->frames_queued = 0; - for (i = start; i < MACH64_MAX_QUEUED_FRAMES; i++) { - dev_priv->frame_ofs[i] = ~0; - } - return 0; - } - - for ( i = start; i < MACH64_MAX_QUEUED_FRAMES; i++ ) { - ofs = dev_priv->frame_ofs[i]; - DRM_DEBUG( "frame_ofs[%d] ofs: %d\n", i, ofs ); - if ( ofs == ~0 || - ( head < tail && (ofs < head || ofs >= tail) ) || - ( head > tail && (ofs < head && ofs >= tail) ) ) { - sarea_priv->frames_queued = (MACH64_MAX_QUEUED_FRAMES - 1) - i; - dev_priv->frame_ofs[i] = ~0; - } - } - - return sarea_priv->frames_queued; -} - -/* Copy and verify a client submited buffer. - * FIXME: Make an assembly optimized version - */ -static __inline__ int copy_and_verify_from_user( u32 *to, const u32 *from, unsigned long bytes ) -{ - unsigned long n = bytes; /* dwords remaining in buffer */ - - if ( DRM_VERIFYAREA_READ( from, n ) ) { - DRM_ERROR( "%s: verify_area\n", __FUNCTION__ ); - return DRM_ERR(EFAULT); - } - - n >>= 2; - - while ( n > 1 ) { - u32 data, reg, count; - - if ( DRM_GET_USER_UNCHECKED( data, from++ ) ) { - DRM_ERROR( "%s: get_user\n", __FUNCTION__ ); - return DRM_ERR(EFAULT); - } - - n--; - - reg = le32_to_cpu(data); - count = (reg >> 16) + 1; - if( count <= n ) { - n -= count; - reg &= 0xffff; - - /* This is an exact match of Mach64's Setup Engine registers, - * excluding SETUP_CNTL (1_C1). - */ - if( (reg >= 0x0190 && reg < 0x01c1) || - (reg >= 0x01ca && reg <= 0x01cf) ) { - *to++ = data; - if ( DRM_COPY_FROM_USER_UNCHECKED( to, from, count << 2 ) ) { - DRM_ERROR( "%s: copy_from_user\n", __FUNCTION__ ); - return DRM_ERR(EFAULT); - } - to += count; - } else { - DRM_ERROR( "%s: Got bad command: 0x%04x\n", __FUNCTION__, reg ); - return DRM_ERR(EACCES); - } - - from += count; - } else { - DRM_ERROR( "%s: Got bad command count(=%u) dwords remaining=%lu\n", - __FUNCTION__, count, n ); - return DRM_ERR(EINVAL); - } - } - - if (n == 0) - return 0; - else { - DRM_ERROR( "%s: Bad buf->used(=%lu)\n", __FUNCTION__, bytes ); - return DRM_ERR(EINVAL); - } -} - -static int mach64_dma_dispatch_vertex( DRMFILE filp, drm_device_t *dev, int prim, void *buf, - unsigned long used, int discard ) -{ - drm_mach64_private_t *dev_priv = dev->dev_private; - drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_buf_t *copy_buf; - int done = 0; - int verify_ret = 0; - DMALOCALS; - - DRM_DEBUG( "%s: buf=%p used=%lu nbox=%d\n", - __FUNCTION__, buf, used, sarea_priv->nbox ); - - if ( used ) { - int ret = 0; - int i = 0; - - copy_buf = mach64_freelist_get( dev_priv ); - if (copy_buf == NULL) { - DRM_ERROR("%s: couldn't get buffer in DMAGETPTR\n", - __FUNCTION__ ); - return DRM_ERR(EAGAIN); - } - - if ( (verify_ret = - copy_and_verify_from_user( GETBUFPTR( copy_buf ), buf, used )) == 0 ) { - - copy_buf->used = used; - - DMASETPTR( copy_buf ); - - if ( sarea_priv->dirty & ~MACH64_UPLOAD_CLIPRECTS ) { - ret = mach64_emit_state( filp, dev_priv ); - if (ret < 0) return ret; - } - - do { - /* Emit the next cliprect */ - if ( i < sarea_priv->nbox ) { - ret = mach64_emit_cliprect(filp, dev_priv, - &sarea_priv->boxes[i]); - if ( ret < 0 ) { - /* failed to get buffer */ - return ret; - } else if ( ret != 0 ) { - /* null intersection with scissor */ - continue; - } - } - if ((i >= sarea_priv->nbox - 1)) - done = 1; - - /* Add the buffer to the DMA queue */ - DMAADVANCE( dev_priv, done ); - - } while ( ++i < sarea_priv->nbox ); - } - - if (copy_buf->pending && !done) { - DMADISCARDBUF(); - } else if (!done) { - /* This buffer wasn't used (no cliprects or verify failed), so place it back - * on the free list - */ - struct list_head *ptr; - drm_mach64_freelist_t *entry; -#if MACH64_EXTRA_CHECKING - list_for_each(ptr, &dev_priv->pending) { - entry = list_entry(ptr, drm_mach64_freelist_t, list); - if (copy_buf == entry->buf) { - DRM_ERROR( "%s: Trying to release a pending buf\n", - __FUNCTION__ ); - return DRM_ERR(EFAULT); - } - } -#endif - ptr = dev_priv->placeholders.next; - entry = list_entry(ptr, drm_mach64_freelist_t, list); - copy_buf->pending = 0; - copy_buf->used = 0; - entry->buf = copy_buf; - entry->discard = 1; - list_del(ptr); - list_add_tail(ptr, &dev_priv->free_list); - } - } - - sarea_priv->dirty &= ~MACH64_UPLOAD_CLIPRECTS; - sarea_priv->nbox = 0; - - return verify_ret; -} - - -static int mach64_dma_dispatch_blit( DRMFILE filp, drm_device_t *dev, - drm_mach64_blit_t *blit ) -{ - drm_mach64_private_t *dev_priv = dev->dev_private; - drm_device_dma_t *dma = dev->dma; - int dword_shift, dwords; - drm_buf_t *buf; - DMALOCALS; - - /* The compiler won't optimize away a division by a variable, - * even if the only legal values are powers of two. Thus, we'll - * use a shift instead. - */ - switch ( blit->format ) { - case MACH64_DATATYPE_ARGB8888: - dword_shift = 0; - break; - case MACH64_DATATYPE_ARGB1555: - case MACH64_DATATYPE_RGB565: - case MACH64_DATATYPE_VYUY422: - case MACH64_DATATYPE_YVYU422: - case MACH64_DATATYPE_ARGB4444: - dword_shift = 1; - break; - case MACH64_DATATYPE_CI8: - case MACH64_DATATYPE_RGB8: - dword_shift = 2; - break; - default: - DRM_ERROR( "invalid blit format %d\n", blit->format ); - return DRM_ERR(EINVAL); - } - - /* Dispatch the blit buffer. - */ - buf = dma->buflist[blit->idx]; - - if ( buf->filp != filp ) { - DRM_ERROR( "process %d (filp %p) using buffer with filp %p\n", - DRM_CURRENTPID, filp, buf->filp ); - return DRM_ERR(EINVAL); - } - - if ( buf->pending ) { - DRM_ERROR( "sending pending buffer %d\n", blit->idx ); - return DRM_ERR(EINVAL); - } - - /* Set buf->used to the bytes of blit data based on the blit dimensions - * and verify the size. When the setup is emitted to the buffer with - * the DMA* macros below, buf->used is incremented to include the bytes - * used for setup as well as the blit data. - */ - dwords = (blit->width * blit->height) >> dword_shift; - buf->used = dwords << 2; - if ( buf->used <= 0 || - buf->used > MACH64_BUFFER_SIZE - MACH64_HOSTDATA_BLIT_OFFSET ) { - DRM_ERROR( "Invalid blit size: %d bytes\n", buf->used ); - return DRM_ERR(EINVAL); - } - - /* FIXME: Use a last buffer flag and reduce the state emitted for subsequent, - * continuation buffers? - */ - - /* Blit via BM_HOSTDATA (gui-master) - like HOST_DATA[0-15], but doesn't require - * a register command every 16 dwords. State setup is added at the start of the - * buffer -- the client leaves space for this based on MACH64_HOSTDATA_BLIT_OFFSET - */ - DMASETPTR( buf ); - - DMAOUTREG( MACH64_Z_CNTL, 0 ); - DMAOUTREG( MACH64_SCALE_3D_CNTL, 0 ); - - DMAOUTREG( MACH64_SC_LEFT_RIGHT, 0 | ( 8191 << 16 ) ); /* no scissor */ - DMAOUTREG( MACH64_SC_TOP_BOTTOM, 0 | ( 16383 << 16 ) ); - - DMAOUTREG( MACH64_CLR_CMP_CNTL, 0 ); /* disable */ - DMAOUTREG( MACH64_GUI_TRAJ_CNTL, - MACH64_DST_X_LEFT_TO_RIGHT - | MACH64_DST_Y_TOP_TO_BOTTOM ); - - DMAOUTREG( MACH64_DP_PIX_WIDTH, - ( blit->format << 0 ) /* dst pix width */ - | ( blit->format << 4 ) /* composite pix width */ - | ( blit->format << 8 ) /* src pix width */ - | ( blit->format << 16 ) /* host data pix width */ - | ( blit->format << 28 ) /* scaler/3D pix width */ - ); - - DMAOUTREG( MACH64_DP_WRITE_MASK, 0xffffffff ); /* enable all planes */ - DMAOUTREG( MACH64_DP_MIX, - MACH64_BKGD_MIX_D - | MACH64_FRGD_MIX_S ); - DMAOUTREG( MACH64_DP_SRC, - MACH64_BKGD_SRC_BKGD_CLR - | MACH64_FRGD_SRC_HOST - | MACH64_MONO_SRC_ONE ); - - DMAOUTREG( MACH64_DST_OFF_PITCH, (blit->pitch << 22) | (blit->offset >> 3) ); - DMAOUTREG( MACH64_DST_X_Y, (blit->y << 16) | blit->x ); - DMAOUTREG( MACH64_DST_WIDTH_HEIGHT, (blit->height << 16) | blit->width ); - - DRM_DEBUG( "%s: %d bytes\n", __FUNCTION__, buf->used ); - - /* Add the buffer to the queue */ - DMAADVANCEHOSTDATA( dev_priv ); - - return 0; -} - -/* ================================================================ - * IOCTL functions - */ - -int mach64_dma_clear( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_mach64_private_t *dev_priv = dev->dev_private; - drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mach64_clear_t clear; - int ret; - - DRM_DEBUG( "%s: pid=%d\n", __FUNCTION__, DRM_CURRENTPID ); - - LOCK_TEST_WITH_RETURN( dev, filp ); - - DRM_COPY_FROM_USER_IOCTL( clear, (drm_mach64_clear_t *)data, - sizeof(clear) ); - - if ( sarea_priv->nbox > MACH64_NR_SAREA_CLIPRECTS ) - sarea_priv->nbox = MACH64_NR_SAREA_CLIPRECTS; - - ret = mach64_dma_dispatch_clear( filp, dev, clear.flags, - clear.x, clear.y, clear.w, clear.h, - clear.clear_color, clear.clear_depth ); - - /* Make sure we restore the 3D state next time. - */ - sarea_priv->dirty |= (MACH64_UPLOAD_CONTEXT | - MACH64_UPLOAD_MISC); - return ret; -} - -int mach64_dma_swap( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_mach64_private_t *dev_priv = dev->dev_private; - drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv; - int ret; - - DRM_DEBUG( "%s: pid=%d\n", __FUNCTION__, DRM_CURRENTPID ); - - LOCK_TEST_WITH_RETURN( dev, filp ); - - if ( sarea_priv->nbox > MACH64_NR_SAREA_CLIPRECTS ) - sarea_priv->nbox = MACH64_NR_SAREA_CLIPRECTS; - - ret = mach64_dma_dispatch_swap( filp, dev ); - - /* Make sure we restore the 3D state next time. - */ - sarea_priv->dirty |= (MACH64_UPLOAD_CONTEXT | - MACH64_UPLOAD_MISC); - return ret; -} - -int mach64_dma_vertex( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_mach64_private_t *dev_priv = dev->dev_private; - drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mach64_vertex_t vertex; - - LOCK_TEST_WITH_RETURN( dev, filp ); - - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); - return DRM_ERR(EINVAL); - } - - DRM_COPY_FROM_USER_IOCTL( vertex, (drm_mach64_vertex_t *)data, - sizeof(vertex) ); - - DRM_DEBUG( "%s: pid=%d buf=%p used=%lu discard=%d\n", - __FUNCTION__, DRM_CURRENTPID, - vertex.buf, vertex.used, vertex.discard ); - - if ( vertex.prim < 0 || - vertex.prim > MACH64_PRIM_POLYGON ) { - DRM_ERROR( "buffer prim %d\n", vertex.prim ); - return DRM_ERR(EINVAL); - } - - if ( vertex.used > MACH64_BUFFER_SIZE || (vertex.used & 3) != 0) { - DRM_ERROR( "Invalid vertex buffer size: %lu bytes\n", vertex.used ); - return DRM_ERR(EINVAL); - } - - if ( sarea_priv->nbox > MACH64_NR_SAREA_CLIPRECTS ) - sarea_priv->nbox = MACH64_NR_SAREA_CLIPRECTS; - - return mach64_dma_dispatch_vertex( filp, dev, vertex.prim, vertex.buf, - vertex.used, vertex.discard ); -} - -int mach64_dma_blit( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_device_dma_t *dma = dev->dma; - drm_mach64_private_t *dev_priv = dev->dev_private; - drm_mach64_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mach64_blit_t blit; - int ret; - - LOCK_TEST_WITH_RETURN( dev, filp ); - - DRM_COPY_FROM_USER_IOCTL( blit, (drm_mach64_blit_t *)data, - sizeof(blit) ); - - DRM_DEBUG( "%s: pid=%d index=%d\n", - __FUNCTION__, DRM_CURRENTPID, blit.idx ); - - if ( blit.idx < 0 || blit.idx >= dma->buf_count ) { - DRM_ERROR( "buffer index %d (of %d max)\n", - blit.idx, dma->buf_count - 1 ); - return DRM_ERR(EINVAL); - } - - ret = mach64_dma_dispatch_blit( filp, dev, &blit ); - - /* Make sure we restore the 3D state next time. - */ - sarea_priv->dirty |= (MACH64_UPLOAD_CONTEXT | - MACH64_UPLOAD_MISC | - MACH64_UPLOAD_CLIPRECTS); - - return ret; -} - -int mach64_get_param( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_mach64_private_t *dev_priv = dev->dev_private; - drm_mach64_getparam_t param; - int value; - - DRM_DEBUG( "%s\n", __FUNCTION__ ); - - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); - return DRM_ERR(EINVAL); - } - - DRM_COPY_FROM_USER_IOCTL( param, (drm_mach64_getparam_t *)data, - sizeof(param) ); - - switch ( param.param ) { - case MACH64_PARAM_FRAMES_QUEUED: - /* Needs lock since it calls mach64_ring_tick() */ - LOCK_TEST_WITH_RETURN( dev, filp ); - value = mach64_do_get_frames_queued( dev_priv ); - break; - case MACH64_PARAM_IRQ_NR: - value = dev->irq; - break; - default: - return DRM_ERR(EINVAL); - } - - if ( DRM_COPY_TO_USER( param.value, &value, sizeof(int) ) ) { - DRM_ERROR( "copy_to_user\n" ); - return DRM_ERR(EFAULT); - } - - return 0; -} diff --git a/nx-X11/extras/drm/shared/mga.h b/nx-X11/extras/drm/shared/mga.h deleted file mode 100644 index 5356519e5..000000000 --- a/nx-X11/extras/drm/shared/mga.h +++ /dev/null @@ -1,63 +0,0 @@ -/* mga.h -- Matrox G200/G400 DRM template customization -*- linux-c -*- - * Created: Thu Jan 11 21:29:32 2001 by gareth@valinux.com - * - * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Gareth Hughes - */ - -#ifndef __MGA_H__ -#define __MGA_H__ - -/* This remains constant for all DRM template files. - */ -#define DRM(x) mga_##x - -/* General customization: - */ - -#define DRIVER_AUTHOR "Gareth Hughes, VA Linux Systems Inc." - -#define DRIVER_NAME "mga" -#define DRIVER_DESC "Matrox G200/G400" -#define DRIVER_DATE "20021029" - -#define DRIVER_MAJOR 3 -#define DRIVER_MINOR 1 -#define DRIVER_PATCHLEVEL 0 - -#define DRIVER_IOCTLS \ - [DRM_IOCTL_NR(DRM_IOCTL_DMA)] = { mga_dma_buffers, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_MGA_INIT)] = { mga_dma_init, 1, 1 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_MGA_FLUSH)] = { mga_dma_flush, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_MGA_RESET)] = { mga_dma_reset, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_MGA_SWAP)] = { mga_dma_swap, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_MGA_CLEAR)] = { mga_dma_clear, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_MGA_VERTEX)] = { mga_dma_vertex, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_MGA_INDICES)] = { mga_dma_indices, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_MGA_ILOAD)] = { mga_dma_iload, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_MGA_BLIT)] = { mga_dma_blit, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_MGA_GETPARAM)]= { mga_getparam, 1, 0 }, - -#endif diff --git a/nx-X11/extras/drm/shared/mga_dma.c b/nx-X11/extras/drm/shared/mga_dma.c deleted file mode 100644 index 0288f1c2c..000000000 --- a/nx-X11/extras/drm/shared/mga_dma.c +++ /dev/null @@ -1,829 +0,0 @@ -/* mga_dma.c -- DMA support for mga g200/g400 -*- linux-c -*- - * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com - * - * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. - * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Rickard E. (Rik) Faith - * Jeff Hartmann - * Keith Whitwell - * - * Rewritten by: - * Gareth Hughes - */ - -#include "mga.h" -#include "drmP.h" -#include "drm.h" -#include "mga_drm.h" -#include "mga_drv.h" - -#define MGA_DEFAULT_USEC_TIMEOUT 10000 -#define MGA_FREELIST_DEBUG 0 - - -/* ================================================================ - * Engine control - */ - -int mga_do_wait_for_idle( drm_mga_private_t *dev_priv ) -{ - u32 status = 0; - int i; - DRM_DEBUG( "\n" ); - - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK; - if ( status == MGA_ENDPRDMASTS ) { - MGA_WRITE8( MGA_CRTC_INDEX, 0 ); - return 0; - } - DRM_UDELAY( 1 ); - } - -#if MGA_DMA_DEBUG - DRM_ERROR( "failed!\n" ); - DRM_INFO( " status=0x%08x\n", status ); -#endif - return DRM_ERR(EBUSY); -} - -int mga_do_dma_idle( drm_mga_private_t *dev_priv ) -{ - u32 status = 0; - int i; - DRM_DEBUG( "\n" ); - - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - status = MGA_READ( MGA_STATUS ) & MGA_DMA_IDLE_MASK; - if ( status == MGA_ENDPRDMASTS ) return 0; - DRM_UDELAY( 1 ); - } - -#if MGA_DMA_DEBUG - DRM_ERROR( "failed! status=0x%08x\n", status ); -#endif - return DRM_ERR(EBUSY); -} - -int mga_do_dma_reset( drm_mga_private_t *dev_priv ) -{ - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mga_primary_buffer_t *primary = &dev_priv->prim; - - DRM_DEBUG( "\n" ); - - /* The primary DMA stream should look like new right about now. - */ - primary->tail = 0; - primary->space = primary->size; - primary->last_flush = 0; - - sarea_priv->last_wrap = 0; - - /* FIXME: Reset counters, buffer ages etc... - */ - - /* FIXME: What else do we need to reinitialize? WARP stuff? - */ - - return 0; -} - -int mga_do_engine_reset( drm_mga_private_t *dev_priv ) -{ - DRM_DEBUG( "\n" ); - - /* Okay, so we've completely screwed up and locked the engine. - * How about we clean up after ourselves? - */ - MGA_WRITE( MGA_RST, MGA_SOFTRESET ); - DRM_UDELAY( 15 ); /* Wait at least 10 usecs */ - MGA_WRITE( MGA_RST, 0 ); - - /* Initialize the registers that get clobbered by the soft - * reset. Many of the core register values survive a reset, - * but the drawing registers are basically all gone. - * - * 3D clients should probably die after calling this. The X - * server should reset the engine state to known values. - */ -#if 0 - MGA_WRITE( MGA_PRIMPTR, - virt_to_bus((void *)dev_priv->prim.status_page) | - MGA_PRIMPTREN0 | - MGA_PRIMPTREN1 ); -#endif - - MGA_WRITE( MGA_ICLEAR, MGA_SOFTRAPICLR ); - MGA_WRITE( MGA_IEN, MGA_SOFTRAPIEN ); - - /* The primary DMA stream should look like new right about now. - */ - mga_do_dma_reset( dev_priv ); - - /* This bad boy will never fail. - */ - return 0; -} - - -/* ================================================================ - * Primary DMA stream - */ - -void mga_do_dma_flush( drm_mga_private_t *dev_priv ) -{ - drm_mga_primary_buffer_t *primary = &dev_priv->prim; - u32 head, tail; - u32 status = 0; - int i; - DMA_LOCALS; - DRM_DEBUG( "\n" ); - - /* We need to wait so that we can do an safe flush */ - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK; - if ( status == MGA_ENDPRDMASTS ) break; - DRM_UDELAY( 1 ); - } - - if ( primary->tail == primary->last_flush ) { - DRM_DEBUG( " bailing out...\n" ); - return; - } - - tail = primary->tail + dev_priv->primary->offset; - - /* We need to pad the stream between flushes, as the card - * actually (partially?) reads the first of these commands. - * See page 4-16 in the G400 manual, middle of the page or so. - */ - BEGIN_DMA( 1 ); - - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000 ); - - ADVANCE_DMA(); - - primary->last_flush = primary->tail; - - head = MGA_READ( MGA_PRIMADDRESS ); - - if ( head <= tail ) { - primary->space = primary->size - primary->tail; - } else { - primary->space = head - tail; - } - - DRM_DEBUG( " head = 0x%06lx\n", head - dev_priv->primary->offset ); - DRM_DEBUG( " tail = 0x%06lx\n", tail - dev_priv->primary->offset ); - DRM_DEBUG( " space = 0x%06x\n", primary->space ); - - mga_flush_write_combine(); - MGA_WRITE( MGA_PRIMEND, tail | MGA_PAGPXFER ); - - DRM_DEBUG( "done.\n" ); -} - -void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv ) -{ - drm_mga_primary_buffer_t *primary = &dev_priv->prim; - u32 head, tail; - DMA_LOCALS; - DRM_DEBUG( "\n" ); - - BEGIN_DMA_WRAP(); - - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000 ); - - ADVANCE_DMA(); - - tail = primary->tail + dev_priv->primary->offset; - - primary->tail = 0; - primary->last_flush = 0; - primary->last_wrap++; - - head = MGA_READ( MGA_PRIMADDRESS ); - - if ( head == dev_priv->primary->offset ) { - primary->space = primary->size; - } else { - primary->space = head - dev_priv->primary->offset; - } - - DRM_DEBUG( " head = 0x%06lx\n", - head - dev_priv->primary->offset ); - DRM_DEBUG( " tail = 0x%06x\n", primary->tail ); - DRM_DEBUG( " wrap = %d\n", primary->last_wrap ); - DRM_DEBUG( " space = 0x%06x\n", primary->space ); - - mga_flush_write_combine(); - MGA_WRITE( MGA_PRIMEND, tail | MGA_PAGPXFER ); - - set_bit( 0, &primary->wrapped ); - DRM_DEBUG( "done.\n" ); -} - -void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv ) -{ - drm_mga_primary_buffer_t *primary = &dev_priv->prim; - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - u32 head = dev_priv->primary->offset; - DRM_DEBUG( "\n" ); - - sarea_priv->last_wrap++; - DRM_DEBUG( " wrap = %d\n", sarea_priv->last_wrap ); - - mga_flush_write_combine(); - MGA_WRITE( MGA_PRIMADDRESS, head | MGA_DMA_GENERAL ); - - clear_bit( 0, &primary->wrapped ); - DRM_DEBUG( "done.\n" ); -} - - -/* ================================================================ - * Freelist management - */ - -#define MGA_BUFFER_USED ~0 -#define MGA_BUFFER_FREE 0 - -#if MGA_FREELIST_DEBUG -static void mga_freelist_print( drm_device_t *dev ) -{ - drm_mga_private_t *dev_priv = dev->dev_private; - drm_mga_freelist_t *entry; - - DRM_INFO( "\n" ); - DRM_INFO( "current dispatch: last=0x%x done=0x%x\n", - dev_priv->sarea_priv->last_dispatch, - (unsigned int)(MGA_READ( MGA_PRIMADDRESS ) - - dev_priv->primary->offset) ); - DRM_INFO( "current freelist:\n" ); - - for ( entry = dev_priv->head->next ; entry ; entry = entry->next ) { - DRM_INFO( " %p idx=%2d age=0x%x 0x%06lx\n", - entry, entry->buf->idx, entry->age.head, - entry->age.head - dev_priv->primary->offset ); - } - DRM_INFO( "\n" ); -} -#endif - -static int mga_freelist_init( drm_device_t *dev, drm_mga_private_t *dev_priv ) -{ - drm_device_dma_t *dma = dev->dma; - drm_buf_t *buf; - drm_mga_buf_priv_t *buf_priv; - drm_mga_freelist_t *entry; - int i; - DRM_DEBUG( "count=%d\n", dma->buf_count ); - - dev_priv->head = DRM(alloc)( sizeof(drm_mga_freelist_t), - DRM_MEM_DRIVER ); - if ( dev_priv->head == NULL ) - return DRM_ERR(ENOMEM); - - memset( dev_priv->head, 0, sizeof(drm_mga_freelist_t) ); - SET_AGE( &dev_priv->head->age, MGA_BUFFER_USED, 0 ); - - for ( i = 0 ; i < dma->buf_count ; i++ ) { - buf = dma->buflist[i]; - buf_priv = buf->dev_private; - - entry = DRM(alloc)( sizeof(drm_mga_freelist_t), - DRM_MEM_DRIVER ); - if ( entry == NULL ) - return DRM_ERR(ENOMEM); - - memset( entry, 0, sizeof(drm_mga_freelist_t) ); - - entry->next = dev_priv->head->next; - entry->prev = dev_priv->head; - SET_AGE( &entry->age, MGA_BUFFER_FREE, 0 ); - entry->buf = buf; - - if ( dev_priv->head->next != NULL ) - dev_priv->head->next->prev = entry; - if ( entry->next == NULL ) - dev_priv->tail = entry; - - buf_priv->list_entry = entry; - buf_priv->discard = 0; - buf_priv->dispatched = 0; - - dev_priv->head->next = entry; - } - - return 0; -} - -static void mga_freelist_cleanup( drm_device_t *dev ) -{ - drm_mga_private_t *dev_priv = dev->dev_private; - drm_mga_freelist_t *entry; - drm_mga_freelist_t *next; - DRM_DEBUG( "\n" ); - - entry = dev_priv->head; - while ( entry ) { - next = entry->next; - DRM(free)( entry, sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER ); - entry = next; - } - - dev_priv->head = dev_priv->tail = NULL; -} - -#if 0 -/* FIXME: Still needed? - */ -static void mga_freelist_reset( drm_device_t *dev ) -{ - drm_device_dma_t *dma = dev->dma; - drm_buf_t *buf; - drm_mga_buf_priv_t *buf_priv; - int i; - - for ( i = 0 ; i < dma->buf_count ; i++ ) { - buf = dma->buflist[i]; - buf_priv = buf->dev_private; - SET_AGE( &buf_priv->list_entry->age, - MGA_BUFFER_FREE, 0 ); - } -} -#endif - -static drm_buf_t *mga_freelist_get( drm_device_t *dev ) -{ - drm_mga_private_t *dev_priv = dev->dev_private; - drm_mga_freelist_t *next; - drm_mga_freelist_t *prev; - drm_mga_freelist_t *tail = dev_priv->tail; - u32 head, wrap; - DRM_DEBUG( "\n" ); - - head = MGA_READ( MGA_PRIMADDRESS ); - wrap = dev_priv->sarea_priv->last_wrap; - - DRM_DEBUG( " tail=0x%06lx %d\n", - tail->age.head ? - tail->age.head - dev_priv->primary->offset : 0, - tail->age.wrap ); - DRM_DEBUG( " head=0x%06lx %d\n", - head - dev_priv->primary->offset, wrap ); - - if ( TEST_AGE( &tail->age, head, wrap ) ) { - prev = dev_priv->tail->prev; - next = dev_priv->tail; - prev->next = NULL; - next->prev = next->next = NULL; - dev_priv->tail = prev; - SET_AGE( &next->age, MGA_BUFFER_USED, 0 ); - return next->buf; - } - - DRM_DEBUG( "returning NULL!\n" ); - return NULL; -} - -int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf ) -{ - drm_mga_private_t *dev_priv = dev->dev_private; - drm_mga_buf_priv_t *buf_priv = buf->dev_private; - drm_mga_freelist_t *head, *entry, *prev; - - DRM_DEBUG( "age=0x%06lx wrap=%d\n", - buf_priv->list_entry->age.head - - dev_priv->primary->offset, - buf_priv->list_entry->age.wrap ); - - entry = buf_priv->list_entry; - head = dev_priv->head; - - if ( buf_priv->list_entry->age.head == MGA_BUFFER_USED ) { - SET_AGE( &entry->age, MGA_BUFFER_FREE, 0 ); - prev = dev_priv->tail; - prev->next = entry; - entry->prev = prev; - entry->next = NULL; - } else { - prev = head->next; - head->next = entry; - prev->prev = entry; - entry->prev = head; - entry->next = prev; - } - - return 0; -} - - -/* ================================================================ - * DMA initialization, cleanup - */ - -static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init ) -{ - drm_mga_private_t *dev_priv; - int ret; - DRM_DEBUG( "\n" ); - - dev_priv = DRM(alloc)( sizeof(drm_mga_private_t), DRM_MEM_DRIVER ); - if ( !dev_priv ) - return DRM_ERR(ENOMEM); - - memset( dev_priv, 0, sizeof(drm_mga_private_t) ); - - dev_priv->chipset = init->chipset; - - dev_priv->usec_timeout = MGA_DEFAULT_USEC_TIMEOUT; - - if ( init->sgram ) { - dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_BLK; - } else { - dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_RSTR; - } - dev_priv->maccess = init->maccess; - - dev_priv->fb_cpp = init->fb_cpp; - dev_priv->front_offset = init->front_offset; - dev_priv->front_pitch = init->front_pitch; - dev_priv->back_offset = init->back_offset; - dev_priv->back_pitch = init->back_pitch; - - dev_priv->depth_cpp = init->depth_cpp; - dev_priv->depth_offset = init->depth_offset; - dev_priv->depth_pitch = init->depth_pitch; - - /* FIXME: Need to support AGP textures... - */ - dev_priv->texture_offset = init->texture_offset[0]; - dev_priv->texture_size = init->texture_size[0]; - - DRM_GETSAREA(); - - if(!dev_priv->sarea) { - DRM_ERROR( "failed to find sarea!\n" ); - /* Assign dev_private so we can do cleanup. */ - dev->dev_private = (void *)dev_priv; - mga_do_cleanup_dma( dev ); - return DRM_ERR(EINVAL); - } - - dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset); - if(!dev_priv->mmio) { - DRM_ERROR( "failed to find mmio region!\n" ); - /* Assign dev_private so we can do cleanup. */ - dev->dev_private = (void *)dev_priv; - mga_do_cleanup_dma( dev ); - return DRM_ERR(EINVAL); - } - dev_priv->status = drm_core_findmap(dev, init->status_offset); - if(!dev_priv->status) { - DRM_ERROR( "failed to find status page!\n" ); - /* Assign dev_private so we can do cleanup. */ - dev->dev_private = (void *)dev_priv; - mga_do_cleanup_dma( dev ); - return DRM_ERR(EINVAL); - } - dev_priv->warp = drm_core_findmap(dev, init->warp_offset); - if(!dev_priv->warp) { - DRM_ERROR( "failed to find warp microcode region!\n" ); - /* Assign dev_private so we can do cleanup. */ - dev->dev_private = (void *)dev_priv; - mga_do_cleanup_dma( dev ); - return DRM_ERR(EINVAL); - } - dev_priv->primary = drm_core_findmap(dev, init->primary_offset); - if(!dev_priv->primary) { - DRM_ERROR( "failed to find primary dma region!\n" ); - /* Assign dev_private so we can do cleanup. */ - dev->dev_private = (void *)dev_priv; - mga_do_cleanup_dma( dev ); - return DRM_ERR(EINVAL); - } - dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); - if(!dev->agp_buffer_map) { - DRM_ERROR( "failed to find dma buffer region!\n" ); - /* Assign dev_private so we can do cleanup. */ - dev->dev_private = (void *)dev_priv; - mga_do_cleanup_dma( dev ); - return DRM_ERR(EINVAL); - } - - dev_priv->sarea_priv = - (drm_mga_sarea_t *)((u8 *)dev_priv->sarea->handle + - init->sarea_priv_offset); - - drm_core_ioremap( dev_priv->warp, dev ); - drm_core_ioremap( dev_priv->primary, dev ); - drm_core_ioremap( dev->agp_buffer_map, dev ); - - if(!dev_priv->warp->handle || - !dev_priv->primary->handle || - !dev->agp_buffer_map->handle ) { - DRM_ERROR( "failed to ioremap agp regions!\n" ); - /* Assign dev_private so we can do cleanup. */ - dev->dev_private = (void *)dev_priv; - mga_do_cleanup_dma( dev ); - return DRM_ERR(ENOMEM); - } - - ret = mga_warp_install_microcode( dev_priv ); - if ( ret < 0 ) { - DRM_ERROR( "failed to install WARP ucode!\n" ); - /* Assign dev_private so we can do cleanup. */ - dev->dev_private = (void *)dev_priv; - mga_do_cleanup_dma( dev ); - return ret; - } - - ret = mga_warp_init( dev_priv ); - if ( ret < 0 ) { - DRM_ERROR( "failed to init WARP engine!\n" ); - /* Assign dev_private so we can do cleanup. */ - dev->dev_private = (void *)dev_priv; - mga_do_cleanup_dma( dev ); - return ret; - } - - dev_priv->prim.status = (u32 *)dev_priv->status->handle; - - mga_do_wait_for_idle( dev_priv ); - - /* Init the primary DMA registers. - */ - MGA_WRITE( MGA_PRIMADDRESS, - dev_priv->primary->offset | MGA_DMA_GENERAL ); -#if 0 - MGA_WRITE( MGA_PRIMPTR, - virt_to_bus((void *)dev_priv->prim.status) | - MGA_PRIMPTREN0 | /* Soft trap, SECEND, SETUPEND */ - MGA_PRIMPTREN1 ); /* DWGSYNC */ -#endif - - dev_priv->prim.start = (u8 *)dev_priv->primary->handle; - dev_priv->prim.end = ((u8 *)dev_priv->primary->handle - + dev_priv->primary->size); - dev_priv->prim.size = dev_priv->primary->size; - - dev_priv->prim.tail = 0; - dev_priv->prim.space = dev_priv->prim.size; - dev_priv->prim.wrapped = 0; - - dev_priv->prim.last_flush = 0; - dev_priv->prim.last_wrap = 0; - - dev_priv->prim.high_mark = 256 * DMA_BLOCK_SIZE; - - dev_priv->prim.status[0] = dev_priv->primary->offset; - dev_priv->prim.status[1] = 0; - - dev_priv->sarea_priv->last_wrap = 0; - dev_priv->sarea_priv->last_frame.head = 0; - dev_priv->sarea_priv->last_frame.wrap = 0; - - if ( mga_freelist_init( dev, dev_priv ) < 0 ) { - DRM_ERROR( "could not initialize freelist\n" ); - /* Assign dev_private so we can do cleanup. */ - dev->dev_private = (void *)dev_priv; - mga_do_cleanup_dma( dev ); - return DRM_ERR(ENOMEM); - } - - /* Make dev_private visable to others. */ - dev->dev_private = (void *)dev_priv; - return 0; -} - -int mga_do_cleanup_dma( drm_device_t *dev ) -{ - DRM_DEBUG( "\n" ); - - /* Make sure interrupts are disabled here because the uninstall ioctl - * may not have been called from userspace and after dev_private - * is freed, it's too late. - */ - if ( dev->irq_enabled ) DRM(irq_uninstall)(dev); - - if ( dev->dev_private ) { - drm_mga_private_t *dev_priv = dev->dev_private; - - if ( dev_priv->warp != NULL ) - drm_core_ioremapfree( dev_priv->warp, dev ); - if ( dev_priv->primary != NULL ) - drm_core_ioremapfree( dev_priv->primary, dev ); - if ( dev->agp_buffer_map != NULL ) { - drm_core_ioremapfree( dev->agp_buffer_map, dev ); - dev->agp_buffer_map = NULL; - } - - if ( dev_priv->head != NULL ) { - mga_freelist_cleanup( dev ); - } - - DRM(free)( dev->dev_private, sizeof(drm_mga_private_t), - DRM_MEM_DRIVER ); - dev->dev_private = NULL; - } - - return 0; -} - -int mga_dma_init( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_mga_init_t init; - - LOCK_TEST_WITH_RETURN( dev, filp ); - - DRM_COPY_FROM_USER_IOCTL( init, (drm_mga_init_t __user *)data, sizeof(init) ); - - switch ( init.func ) { - case MGA_INIT_DMA: - return mga_do_init_dma( dev, &init ); - case MGA_CLEANUP_DMA: - return mga_do_cleanup_dma( dev ); - } - - return DRM_ERR(EINVAL); -} - - -/* ================================================================ - * Primary DMA stream management - */ - -int mga_dma_flush( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; - drm_lock_t lock; - - LOCK_TEST_WITH_RETURN( dev, filp ); - - DRM_COPY_FROM_USER_IOCTL( lock, (drm_lock_t __user *)data, sizeof(lock) ); - - DRM_DEBUG( "%s%s%s\n", - (lock.flags & _DRM_LOCK_FLUSH) ? "flush, " : "", - (lock.flags & _DRM_LOCK_FLUSH_ALL) ? "flush all, " : "", - (lock.flags & _DRM_LOCK_QUIESCENT) ? "idle, " : "" ); - - WRAP_WAIT_WITH_RETURN( dev_priv ); - - if ( lock.flags & (_DRM_LOCK_FLUSH | _DRM_LOCK_FLUSH_ALL) ) { - mga_do_dma_flush( dev_priv ); - } - - if ( lock.flags & _DRM_LOCK_QUIESCENT ) { -#if MGA_DMA_DEBUG - int ret = mga_do_wait_for_idle( dev_priv ); - if ( ret < 0 ) - DRM_INFO( "%s: -EBUSY\n", __FUNCTION__ ); - return ret; -#else - return mga_do_wait_for_idle( dev_priv ); -#endif - } else { - return 0; - } -} - -int mga_dma_reset( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; - - LOCK_TEST_WITH_RETURN( dev, filp ); - - return mga_do_dma_reset( dev_priv ); -} - - -/* ================================================================ - * DMA buffer management - */ - -static int mga_dma_get_buffers( DRMFILE filp, - drm_device_t *dev, drm_dma_t *d ) -{ - drm_buf_t *buf; - int i; - - for ( i = d->granted_count ; i < d->request_count ; i++ ) { - buf = mga_freelist_get( dev ); - if ( !buf ) return DRM_ERR(EAGAIN); - - buf->filp = filp; - - if ( DRM_COPY_TO_USER( &d->request_indices[i], - &buf->idx, sizeof(buf->idx) ) ) - return DRM_ERR(EFAULT); - if ( DRM_COPY_TO_USER( &d->request_sizes[i], - &buf->total, sizeof(buf->total) ) ) - return DRM_ERR(EFAULT); - - d->granted_count++; - } - return 0; -} - -int mga_dma_buffers( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_device_dma_t *dma = dev->dma; - drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; - drm_dma_t __user *argp = (void __user *)data; - drm_dma_t d; - int ret = 0; - - LOCK_TEST_WITH_RETURN( dev, filp ); - - DRM_COPY_FROM_USER_IOCTL( d, argp, sizeof(d) ); - - /* Please don't send us buffers. - */ - if ( d.send_count != 0 ) { - DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n", - DRM_CURRENTPID, d.send_count ); - return DRM_ERR(EINVAL); - } - - /* We'll send you buffers. - */ - if ( d.request_count < 0 || d.request_count > dma->buf_count ) { - DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n", - DRM_CURRENTPID, d.request_count, dma->buf_count ); - return DRM_ERR(EINVAL); - } - - WRAP_TEST_WITH_RETURN( dev_priv ); - - d.granted_count = 0; - - if ( d.request_count ) { - ret = mga_dma_get_buffers( filp, dev, &d ); - } - - DRM_COPY_TO_USER_IOCTL( argp, d, sizeof(d) ); - - return ret; -} - -static void mga_driver_pretakedown(drm_device_t *dev) -{ - mga_do_cleanup_dma( dev ); -} - -static int mga_driver_dma_quiescent(drm_device_t *dev) -{ - drm_mga_private_t *dev_priv = dev->dev_private; - return mga_do_wait_for_idle( dev_priv ); -} - -void mga_driver_register_fns(drm_device_t *dev) -{ - dev->driver_features = DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | DRIVER_USE_MTRR | DRIVER_HAVE_DMA | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_IRQ_VBL; - dev->fn_tbl.pretakedown = mga_driver_pretakedown; - dev->fn_tbl.dma_quiescent = mga_driver_dma_quiescent; - dev->fn_tbl.vblank_wait = mga_driver_vblank_wait; - dev->fn_tbl.irq_preinstall = mga_driver_irq_preinstall; - dev->fn_tbl.irq_postinstall = mga_driver_irq_postinstall; - dev->fn_tbl.irq_uninstall = mga_driver_irq_uninstall; - dev->fn_tbl.irq_handler = mga_driver_irq_handler; - - dev->counters += 3; - dev->types[6] = _DRM_STAT_IRQ; - dev->types[7] = _DRM_STAT_PRIMARY; - dev->types[8] = _DRM_STAT_SECONDARY; -} diff --git a/nx-X11/extras/drm/shared/mga_drm.h b/nx-X11/extras/drm/shared/mga_drm.h deleted file mode 100644 index 5b8f1564e..000000000 --- a/nx-X11/extras/drm/shared/mga_drm.h +++ /dev/null @@ -1,425 +0,0 @@ -/* mga_drm.h -- Public header for the Matrox g200/g400 driver -*- linux-c -*- - * Created: Tue Jan 25 01:50:01 1999 by jhartmann@precisioninsight.com - * - * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. - * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. - * All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Jeff Hartmann - * Keith Whitwell - * - * Rewritten by: - * Gareth Hughes - */ - -#ifndef __MGA_DRM_H__ -#define __MGA_DRM_H__ - -/* WARNING: If you change any of these defines, make sure to change the - * defines in the Xserver file (mga_sarea.h) - */ - -#ifndef __MGA_SAREA_DEFINES__ -#define __MGA_SAREA_DEFINES__ - -/* WARP pipe flags - */ -#define MGA_F 0x1 /* fog */ -#define MGA_A 0x2 /* alpha */ -#define MGA_S 0x4 /* specular */ -#define MGA_T2 0x8 /* multitexture */ - -#define MGA_WARP_TGZ 0 -#define MGA_WARP_TGZF (MGA_F) -#define MGA_WARP_TGZA (MGA_A) -#define MGA_WARP_TGZAF (MGA_F|MGA_A) -#define MGA_WARP_TGZS (MGA_S) -#define MGA_WARP_TGZSF (MGA_S|MGA_F) -#define MGA_WARP_TGZSA (MGA_S|MGA_A) -#define MGA_WARP_TGZSAF (MGA_S|MGA_F|MGA_A) -#define MGA_WARP_T2GZ (MGA_T2) -#define MGA_WARP_T2GZF (MGA_T2|MGA_F) -#define MGA_WARP_T2GZA (MGA_T2|MGA_A) -#define MGA_WARP_T2GZAF (MGA_T2|MGA_A|MGA_F) -#define MGA_WARP_T2GZS (MGA_T2|MGA_S) -#define MGA_WARP_T2GZSF (MGA_T2|MGA_S|MGA_F) -#define MGA_WARP_T2GZSA (MGA_T2|MGA_S|MGA_A) -#define MGA_WARP_T2GZSAF (MGA_T2|MGA_S|MGA_F|MGA_A) - -#define MGA_MAX_G200_PIPES 8 /* no multitex */ -#define MGA_MAX_G400_PIPES 16 -#define MGA_MAX_WARP_PIPES MGA_MAX_G400_PIPES -#define MGA_WARP_UCODE_SIZE 32768 /* in bytes */ - -#define MGA_CARD_TYPE_G200 1 -#define MGA_CARD_TYPE_G400 2 -#define MGA_CARD_TYPE_G450 3 /* not currently used */ -#define MGA_CARD_TYPE_G550 4 - -#define MGA_FRONT 0x1 -#define MGA_BACK 0x2 -#define MGA_DEPTH 0x4 - -/* What needs to be changed for the current vertex dma buffer? - */ -#define MGA_UPLOAD_CONTEXT 0x1 -#define MGA_UPLOAD_TEX0 0x2 -#define MGA_UPLOAD_TEX1 0x4 -#define MGA_UPLOAD_PIPE 0x8 -#define MGA_UPLOAD_TEX0IMAGE 0x10 /* handled client-side */ -#define MGA_UPLOAD_TEX1IMAGE 0x20 /* handled client-side */ -#define MGA_UPLOAD_2D 0x40 -#define MGA_WAIT_AGE 0x80 /* handled client-side */ -#define MGA_UPLOAD_CLIPRECTS 0x100 /* handled client-side */ -#if 0 -#define MGA_DMA_FLUSH 0x200 /* set when someone gets the lock - quiescent */ -#endif - -/* 32 buffers of 64k each, total 2 meg. - */ -#define MGA_BUFFER_SIZE (1 << 16) -#define MGA_NUM_BUFFERS 128 - -/* Keep these small for testing. - */ -#define MGA_NR_SAREA_CLIPRECTS 8 - -/* 2 heaps (1 for card, 1 for agp), each divided into upto 128 - * regions, subject to a minimum region size of (1<<16) == 64k. - * - * Clients may subdivide regions internally, but when sharing between - * clients, the region size is the minimum granularity. - */ - -#define MGA_CARD_HEAP 0 -#define MGA_AGP_HEAP 1 -#define MGA_NR_TEX_HEAPS 2 -#define MGA_NR_TEX_REGIONS 16 -#define MGA_LOG_MIN_TEX_REGION_SIZE 16 - -#define DRM_MGA_IDLE_RETRY 2048 - -#endif /* __MGA_SAREA_DEFINES__ */ - -/* Setup registers for 3D context - */ -typedef struct { - unsigned int dstorg; - unsigned int maccess; - unsigned int plnwt; - unsigned int dwgctl; - unsigned int alphactrl; - unsigned int fogcolor; - unsigned int wflag; - unsigned int tdualstage0; - unsigned int tdualstage1; - unsigned int fcol; - unsigned int stencil; - unsigned int stencilctl; -} drm_mga_context_regs_t; - -/* Setup registers for 2D, X server - */ -typedef struct { - unsigned int pitch; -} drm_mga_server_regs_t; - -/* Setup registers for each texture unit - */ -typedef struct { - unsigned int texctl; - unsigned int texctl2; - unsigned int texfilter; - unsigned int texbordercol; - unsigned int texorg; - unsigned int texwidth; - unsigned int texheight; - unsigned int texorg1; - unsigned int texorg2; - unsigned int texorg3; - unsigned int texorg4; -} drm_mga_texture_regs_t; - -/* General aging mechanism - */ -typedef struct { - unsigned int head; /* Position of head pointer */ - unsigned int wrap; /* Primary DMA wrap count */ -} drm_mga_age_t; - -typedef struct _drm_mga_sarea { - /* The channel for communication of state information to the kernel - * on firing a vertex dma buffer. - */ - drm_mga_context_regs_t context_state; - drm_mga_server_regs_t server_state; - drm_mga_texture_regs_t tex_state[2]; - unsigned int warp_pipe; - unsigned int dirty; - unsigned int vertsize; - - /* The current cliprects, or a subset thereof. - */ - drm_clip_rect_t boxes[MGA_NR_SAREA_CLIPRECTS]; - unsigned int nbox; - - /* Information about the most recently used 3d drawable. The - * client fills in the req_* fields, the server fills in the - * exported_ fields and puts the cliprects into boxes, above. - * - * The client clears the exported_drawable field before - * clobbering the boxes data. - */ - unsigned int req_drawable; /* the X drawable id */ - unsigned int req_draw_buffer; /* MGA_FRONT or MGA_BACK */ - - unsigned int exported_drawable; - unsigned int exported_index; - unsigned int exported_stamp; - unsigned int exported_buffers; - unsigned int exported_nfront; - unsigned int exported_nback; - int exported_back_x, exported_front_x, exported_w; - int exported_back_y, exported_front_y, exported_h; - drm_clip_rect_t exported_boxes[MGA_NR_SAREA_CLIPRECTS]; - - /* Counters for aging textures and for client-side throttling. - */ - unsigned int status[4]; - unsigned int last_wrap; - - drm_mga_age_t last_frame; - unsigned int last_enqueue; /* last time a buffer was enqueued */ - unsigned int last_dispatch; /* age of the most recently dispatched buffer */ - unsigned int last_quiescent; /* */ - - /* LRU lists for texture memory in agp space and on the card. - */ - drm_tex_region_t texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS + 1]; - unsigned int texAge[MGA_NR_TEX_HEAPS]; - - /* Mechanism to validate card state. - */ - int ctxOwner; -} drm_mga_sarea_t; - - -/* MGA specific ioctls - * The device specific ioctl range is 0x40 to 0x79. - */ -#define DRM_MGA_INIT 0x00 -#define DRM_MGA_FLUSH 0x01 -#define DRM_MGA_RESET 0x02 -#define DRM_MGA_SWAP 0x03 -#define DRM_MGA_CLEAR 0x04 -#define DRM_MGA_VERTEX 0x05 -#define DRM_MGA_INDICES 0x06 -#define DRM_MGA_ILOAD 0x07 -#define DRM_MGA_BLIT 0x08 -#define DRM_MGA_GETPARAM 0x09 - -/* 3.2: - * ioctls for operating on fences. - */ -#define DRM_MGA_SET_FENCE 0x0a -#define DRM_MGA_WAIT_FENCE 0x0b -#define DRM_MGA_DMA_BOOTSTRAP 0x0c - - -#define DRM_IOCTL_MGA_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t) -#define DRM_IOCTL_MGA_FLUSH DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_FLUSH, drm_lock_t) -#define DRM_IOCTL_MGA_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MGA_RESET) -#define DRM_IOCTL_MGA_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_MGA_SWAP) -#define DRM_IOCTL_MGA_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_CLEAR, drm_mga_clear_t) -#define DRM_IOCTL_MGA_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_VERTEX, drm_mga_vertex_t) -#define DRM_IOCTL_MGA_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INDICES, drm_mga_indices_t) -#define DRM_IOCTL_MGA_ILOAD DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t) -#define DRM_IOCTL_MGA_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t) -#define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t) -#define DRM_IOCTL_MGA_SET_FENCE DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_SET_FENCE, uint32_t) -#define DRM_IOCTL_MGA_WAIT_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_WAIT_FENCE, uint32_t) -#define DRM_IOCTL_MGA_DMA_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_DMA_BOOTSTRAP, drm_mga_dma_bootstrap_t) - -typedef struct _drm_mga_warp_index { - int installed; - unsigned long phys_addr; - int size; -} drm_mga_warp_index_t; - -typedef struct drm_mga_init { - enum { - MGA_INIT_DMA = 0x01, - MGA_CLEANUP_DMA = 0x02 - } func; - - unsigned long sarea_priv_offset; - - int chipset; - int sgram; - - unsigned int maccess; - - unsigned int fb_cpp; - unsigned int front_offset, front_pitch; - unsigned int back_offset, back_pitch; - - unsigned int depth_cpp; - unsigned int depth_offset, depth_pitch; - - unsigned int texture_offset[MGA_NR_TEX_HEAPS]; - unsigned int texture_size[MGA_NR_TEX_HEAPS]; - - unsigned long fb_offset; - unsigned long mmio_offset; - unsigned long status_offset; - unsigned long warp_offset; - unsigned long primary_offset; - unsigned long buffers_offset; -} drm_mga_init_t; - - -typedef struct drm_mga_dma_bootstrap { - /** - * \name AGP texture region - * - * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, these fields will - * be filled in with the actual AGP texture settings. - * - * \warning - * If these fields are non-zero, but dma_mga_dma_bootstrap::agp_mode - * is zero, it means that PCI memory (most likely through the use of - * an IOMMU) is being used for "AGP" textures. - */ - /*@{*/ - drm_handle_t texture_handle; /**< Handle used to map AGP textures. */ - uint32_t texture_size; /**< Size of the AGP texture region. */ - /*@}*/ - - - /** - * Requested size of the primary DMA region. - * - * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be - * filled in with the actual AGP mode. If AGP was not available - */ - uint32_t primary_size; - - - /** - * Requested number of secondary DMA buffers. - * - * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be - * filled in with the actual number of secondary DMA buffers - * allocated. Particularly when PCI DMA is used, this may be - * (subtantially) less than the number requested. - */ - uint32_t secondary_bin_count; - - - /** - * Requested size of each secondary DMA buffer. - * - * While the kernel \b is free to reduce - * dma_mga_dma_bootstrap::secondary_bin_count, it is \b not allowed - * to reduce dma_mga_dma_bootstrap::secondary_bin_size. - */ - uint32_t secondary_bin_size; - - - /** - * Bit-wise mask of AGPSTAT2_* values. Currently only \c AGPSTAT2_1X, - * \c AGPSTAT2_2X, and \c AGPSTAT2_4X are supported. If this value is - * zero, it means that PCI DMA should be used, even if AGP is - * possible. - * - * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be - * filled in with the actual AGP mode. If AGP was not available - * (i.e., PCI DMA was used), this value will be zero. - */ - uint32_t agp_mode; - - - /** - * Desired AGP GART size, measured in megabytes. - */ - uint8_t agp_size; -} drm_mga_dma_bootstrap_t; - -typedef struct drm_mga_clear { - unsigned int flags; - unsigned int clear_color; - unsigned int clear_depth; - unsigned int color_mask; - unsigned int depth_mask; -} drm_mga_clear_t; - -typedef struct drm_mga_vertex { - int idx; /* buffer to queue */ - int used; /* bytes in use */ - int discard; /* client finished with buffer? */ -} drm_mga_vertex_t; - -typedef struct drm_mga_indices { - int idx; /* buffer to queue */ - unsigned int start; - unsigned int end; - int discard; /* client finished with buffer? */ -} drm_mga_indices_t; - -typedef struct drm_mga_iload { - int idx; - unsigned int dstorg; - unsigned int length; -} drm_mga_iload_t; - -typedef struct _drm_mga_blit { - unsigned int planemask; - unsigned int srcorg; - unsigned int dstorg; - int src_pitch, dst_pitch; - int delta_sx, delta_sy; - int delta_dx, delta_dy; - int height, ydir; /* flip image vertically */ - int source_pitch, dest_pitch; -} drm_mga_blit_t; - -/* 3.1: An ioctl to get parameters that aren't available to the 3d - * client any other way. - */ -#define MGA_PARAM_IRQ_NR 1 - -/* 3.2: Query the actual card type. The DDX only distinguishes between - * G200 chips and non-G200 chips, which it calls G400. It turns out that - * there are some very sublte differences between the G4x0 chips and the G550 - * chips. Using this parameter query, a client-side driver can detect the - * difference between a G4x0 and a G550. - */ -#define MGA_PARAM_CARD_TYPE 2 - -typedef struct drm_mga_getparam { - int param; - void __user *value; -} drm_mga_getparam_t; - -#endif diff --git a/nx-X11/extras/drm/shared/mga_drv.h b/nx-X11/extras/drm/shared/mga_drv.h deleted file mode 100644 index 75dcb0e93..000000000 --- a/nx-X11/extras/drm/shared/mga_drv.h +++ /dev/null @@ -1,636 +0,0 @@ -/* mga_drv.h -- Private header for the Matrox G200/G400 driver -*- linux-c -*- - * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com - * - * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. - * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. - * All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Gareth Hughes - */ - -#ifndef __MGA_DRV_H__ -#define __MGA_DRV_H__ - -typedef struct drm_mga_primary_buffer { - u8 *start; - u8 *end; - int size; - - u32 tail; - int space; - volatile long wrapped; - - volatile u32 *status; - - u32 last_flush; - u32 last_wrap; - - u32 high_mark; -} drm_mga_primary_buffer_t; - -typedef struct drm_mga_freelist { - struct drm_mga_freelist *next; - struct drm_mga_freelist *prev; - drm_mga_age_t age; - drm_buf_t *buf; -} drm_mga_freelist_t; - -typedef struct { - drm_mga_freelist_t *list_entry; - int discard; - int dispatched; -} drm_mga_buf_priv_t; - -typedef struct drm_mga_private { - drm_mga_primary_buffer_t prim; - drm_mga_sarea_t *sarea_priv; - - drm_mga_freelist_t *head; - drm_mga_freelist_t *tail; - - unsigned int warp_pipe; - unsigned long warp_pipe_phys[MGA_MAX_WARP_PIPES]; - - int chipset; - int usec_timeout; - - u32 clear_cmd; - u32 maccess; - - unsigned int fb_cpp; - unsigned int front_offset; - unsigned int front_pitch; - unsigned int back_offset; - unsigned int back_pitch; - - unsigned int depth_cpp; - unsigned int depth_offset; - unsigned int depth_pitch; - - unsigned int texture_offset; - unsigned int texture_size; - - drm_local_map_t *sarea; - drm_local_map_t *mmio; - drm_local_map_t *status; - drm_local_map_t *warp; - drm_local_map_t *primary; - drm_local_map_t *buffers; - drm_local_map_t *agp_textures; -} drm_mga_private_t; - - /* mga_dma.c */ -extern int mga_dma_init( DRM_IOCTL_ARGS ); -extern int mga_dma_flush( DRM_IOCTL_ARGS ); -extern int mga_dma_reset( DRM_IOCTL_ARGS ); -extern int mga_dma_buffers( DRM_IOCTL_ARGS ); - -extern int mga_do_wait_for_idle( drm_mga_private_t *dev_priv ); -extern int mga_do_dma_idle( drm_mga_private_t *dev_priv ); -extern int mga_do_dma_reset( drm_mga_private_t *dev_priv ); -extern int mga_do_engine_reset( drm_mga_private_t *dev_priv ); -extern int mga_do_cleanup_dma( drm_device_t *dev ); - -extern void mga_do_dma_flush( drm_mga_private_t *dev_priv ); -extern void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv ); -extern void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv ); - -extern int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf ); - - /* mga_state.c */ -extern int mga_dma_clear( DRM_IOCTL_ARGS ); -extern int mga_dma_swap( DRM_IOCTL_ARGS ); -extern int mga_dma_vertex( DRM_IOCTL_ARGS ); -extern int mga_dma_indices( DRM_IOCTL_ARGS ); -extern int mga_dma_iload( DRM_IOCTL_ARGS ); -extern int mga_dma_blit( DRM_IOCTL_ARGS ); -extern int mga_getparam( DRM_IOCTL_ARGS ); - - /* mga_warp.c */ -extern int mga_warp_install_microcode( drm_mga_private_t *dev_priv ); -extern int mga_warp_init( drm_mga_private_t *dev_priv ); - -extern int mga_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence); -extern irqreturn_t mga_driver_irq_handler( DRM_IRQ_ARGS ); -extern void mga_driver_irq_preinstall( drm_device_t *dev ); -extern void mga_driver_irq_postinstall( drm_device_t *dev ); -extern void mga_driver_irq_uninstall( drm_device_t *dev ); - -#define mga_flush_write_combine() DRM_WRITEMEMORYBARRIER() - -#if defined(__linux__) && defined(__alpha__) -#define MGA_BASE( reg ) ((unsigned long)(dev_priv->mmio->handle)) -#define MGA_ADDR( reg ) (MGA_BASE(reg) + reg) - -#define MGA_DEREF( reg ) *(volatile u32 *)MGA_ADDR( reg ) -#define MGA_DEREF8( reg ) *(volatile u8 *)MGA_ADDR( reg ) - -#define MGA_READ( reg ) (_MGA_READ((u32 *)MGA_ADDR(reg))) -#define MGA_READ8( reg ) (_MGA_READ((u8 *)MGA_ADDR(reg))) -#define MGA_WRITE( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF( reg ) = val; } while (0) -#define MGA_WRITE8( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF8( reg ) = val; } while (0) - -static inline u32 _MGA_READ(u32 *addr) -{ - DRM_MEMORYBARRIER(); - return *(volatile u32 *)addr; -} -#else -#define MGA_READ8( reg ) DRM_READ8(dev_priv->mmio, (reg)) -#define MGA_READ( reg ) DRM_READ32(dev_priv->mmio, (reg)) -#define MGA_WRITE8( reg, val ) DRM_WRITE8(dev_priv->mmio, (reg), (val)) -#define MGA_WRITE( reg, val ) DRM_WRITE32(dev_priv->mmio, (reg), (val)) -#endif - -#define DWGREG0 0x1c00 -#define DWGREG0_END 0x1dff -#define DWGREG1 0x2c00 -#define DWGREG1_END 0x2dff - -#define ISREG0(r) (r >= DWGREG0 && r <= DWGREG0_END) -#define DMAREG0(r) (u8)((r - DWGREG0) >> 2) -#define DMAREG1(r) (u8)(((r - DWGREG1) >> 2) | 0x80) -#define DMAREG(r) (ISREG0(r) ? DMAREG0(r) : DMAREG1(r)) - - - -/* ================================================================ - * Helper macross... - */ - -#define MGA_EMIT_STATE( dev_priv, dirty ) \ -do { \ - if ( (dirty) & ~MGA_UPLOAD_CLIPRECTS ) { \ - if ( dev_priv->chipset == MGA_CARD_TYPE_G400 ) { \ - mga_g400_emit_state( dev_priv ); \ - } else { \ - mga_g200_emit_state( dev_priv ); \ - } \ - } \ -} while (0) - -#define WRAP_TEST_WITH_RETURN( dev_priv ) \ -do { \ - if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \ - if ( mga_is_idle( dev_priv ) ) { \ - mga_do_dma_wrap_end( dev_priv ); \ - } else if ( dev_priv->prim.space < \ - dev_priv->prim.high_mark ) { \ - if ( MGA_DMA_DEBUG ) \ - DRM_INFO( "%s: wrap...\n", __FUNCTION__ ); \ - return DRM_ERR(EBUSY); \ - } \ - } \ -} while (0) - -#define WRAP_WAIT_WITH_RETURN( dev_priv ) \ -do { \ - if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \ - if ( mga_do_wait_for_idle( dev_priv ) < 0 ) { \ - if ( MGA_DMA_DEBUG ) \ - DRM_INFO( "%s: wrap...\n", __FUNCTION__ ); \ - return DRM_ERR(EBUSY); \ - } \ - mga_do_dma_wrap_end( dev_priv ); \ - } \ -} while (0) - - -/* ================================================================ - * Primary DMA command stream - */ - -#define MGA_VERBOSE 0 - -#define DMA_LOCALS unsigned int write; volatile u8 *prim; - -#define DMA_BLOCK_SIZE (5 * sizeof(u32)) - -#define BEGIN_DMA( n ) \ -do { \ - if ( MGA_VERBOSE ) { \ - DRM_INFO( "BEGIN_DMA( %d ) in %s\n", \ - (n), __FUNCTION__ ); \ - DRM_INFO( " space=0x%x req=0x%Zx\n", \ - dev_priv->prim.space, (n) * DMA_BLOCK_SIZE ); \ - } \ - prim = dev_priv->prim.start; \ - write = dev_priv->prim.tail; \ -} while (0) - -#define BEGIN_DMA_WRAP() \ -do { \ - if ( MGA_VERBOSE ) { \ - DRM_INFO( "BEGIN_DMA() in %s\n", __FUNCTION__ ); \ - DRM_INFO( " space=0x%x\n", dev_priv->prim.space ); \ - } \ - prim = dev_priv->prim.start; \ - write = dev_priv->prim.tail; \ -} while (0) - -#define ADVANCE_DMA() \ -do { \ - dev_priv->prim.tail = write; \ - if ( MGA_VERBOSE ) { \ - DRM_INFO( "ADVANCE_DMA() tail=0x%05x sp=0x%x\n", \ - write, dev_priv->prim.space ); \ - } \ -} while (0) - -#define FLUSH_DMA() \ -do { \ - if ( 0 ) { \ - DRM_INFO( "%s:\n", __FUNCTION__ ); \ - DRM_INFO( " tail=0x%06x head=0x%06lx\n", \ - dev_priv->prim.tail, \ - MGA_READ( MGA_PRIMADDRESS ) - \ - dev_priv->primary->offset ); \ - } \ - if ( !test_bit( 0, &dev_priv->prim.wrapped ) ) { \ - if ( dev_priv->prim.space < \ - dev_priv->prim.high_mark ) { \ - mga_do_dma_wrap_start( dev_priv ); \ - } else { \ - mga_do_dma_flush( dev_priv ); \ - } \ - } \ -} while (0) - -/* Never use this, always use DMA_BLOCK(...) for primary DMA output. - */ -#define DMA_WRITE( offset, val ) \ -do { \ - if ( MGA_VERBOSE ) { \ - DRM_INFO( " DMA_WRITE( 0x%08x ) at 0x%04Zx\n", \ - (u32)(val), write + (offset) * sizeof(u32) ); \ - } \ - *(volatile u32 *)(prim + write + (offset) * sizeof(u32)) = val; \ -} while (0) - -#define DMA_BLOCK( reg0, val0, reg1, val1, reg2, val2, reg3, val3 ) \ -do { \ - DMA_WRITE( 0, ((DMAREG( reg0 ) << 0) | \ - (DMAREG( reg1 ) << 8) | \ - (DMAREG( reg2 ) << 16) | \ - (DMAREG( reg3 ) << 24)) ); \ - DMA_WRITE( 1, val0 ); \ - DMA_WRITE( 2, val1 ); \ - DMA_WRITE( 3, val2 ); \ - DMA_WRITE( 4, val3 ); \ - write += DMA_BLOCK_SIZE; \ -} while (0) - - -/* Buffer aging via primary DMA stream head pointer. - */ - -#define SET_AGE( age, h, w ) \ -do { \ - (age)->head = h; \ - (age)->wrap = w; \ -} while (0) - -#define TEST_AGE( age, h, w ) ( (age)->wrap < w || \ - ( (age)->wrap == w && \ - (age)->head < h ) ) - -#define AGE_BUFFER( buf_priv ) \ -do { \ - drm_mga_freelist_t *entry = (buf_priv)->list_entry; \ - if ( (buf_priv)->dispatched ) { \ - entry->age.head = (dev_priv->prim.tail + \ - dev_priv->primary->offset); \ - entry->age.wrap = dev_priv->sarea_priv->last_wrap; \ - } else { \ - entry->age.head = 0; \ - entry->age.wrap = 0; \ - } \ -} while (0) - - -#define MGA_ENGINE_IDLE_MASK (MGA_SOFTRAPEN | \ - MGA_DWGENGSTS | \ - MGA_ENDPRDMASTS) -#define MGA_DMA_IDLE_MASK (MGA_SOFTRAPEN | \ - MGA_ENDPRDMASTS) - -#define MGA_DMA_DEBUG 0 - - - -/* A reduced set of the mga registers. - */ -#define MGA_CRTC_INDEX 0x1fd4 -#define MGA_CRTC_DATA 0x1fd5 - -/* CRTC11 */ -#define MGA_VINTCLR (1 << 4) -#define MGA_VINTEN (1 << 5) - -#define MGA_ALPHACTRL 0x2c7c -#define MGA_AR0 0x1c60 -#define MGA_AR1 0x1c64 -#define MGA_AR2 0x1c68 -#define MGA_AR3 0x1c6c -#define MGA_AR4 0x1c70 -#define MGA_AR5 0x1c74 -#define MGA_AR6 0x1c78 - -#define MGA_CXBNDRY 0x1c80 -#define MGA_CXLEFT 0x1ca0 -#define MGA_CXRIGHT 0x1ca4 - -#define MGA_DMAPAD 0x1c54 -#define MGA_DSTORG 0x2cb8 -#define MGA_DWGCTL 0x1c00 -# define MGA_OPCOD_MASK (15 << 0) -# define MGA_OPCOD_TRAP (4 << 0) -# define MGA_OPCOD_TEXTURE_TRAP (6 << 0) -# define MGA_OPCOD_BITBLT (8 << 0) -# define MGA_OPCOD_ILOAD (9 << 0) -# define MGA_ATYPE_MASK (7 << 4) -# define MGA_ATYPE_RPL (0 << 4) -# define MGA_ATYPE_RSTR (1 << 4) -# define MGA_ATYPE_ZI (3 << 4) -# define MGA_ATYPE_BLK (4 << 4) -# define MGA_ATYPE_I (7 << 4) -# define MGA_LINEAR (1 << 7) -# define MGA_ZMODE_MASK (7 << 8) -# define MGA_ZMODE_NOZCMP (0 << 8) -# define MGA_ZMODE_ZE (2 << 8) -# define MGA_ZMODE_ZNE (3 << 8) -# define MGA_ZMODE_ZLT (4 << 8) -# define MGA_ZMODE_ZLTE (5 << 8) -# define MGA_ZMODE_ZGT (6 << 8) -# define MGA_ZMODE_ZGTE (7 << 8) -# define MGA_SOLID (1 << 11) -# define MGA_ARZERO (1 << 12) -# define MGA_SGNZERO (1 << 13) -# define MGA_SHIFTZERO (1 << 14) -# define MGA_BOP_MASK (15 << 16) -# define MGA_BOP_ZERO (0 << 16) -# define MGA_BOP_DST (10 << 16) -# define MGA_BOP_SRC (12 << 16) -# define MGA_BOP_ONE (15 << 16) -# define MGA_TRANS_SHIFT 20 -# define MGA_TRANS_MASK (15 << 20) -# define MGA_BLTMOD_MASK (15 << 25) -# define MGA_BLTMOD_BMONOLEF (0 << 25) -# define MGA_BLTMOD_BMONOWF (4 << 25) -# define MGA_BLTMOD_PLAN (1 << 25) -# define MGA_BLTMOD_BFCOL (2 << 25) -# define MGA_BLTMOD_BU32BGR (3 << 25) -# define MGA_BLTMOD_BU32RGB (7 << 25) -# define MGA_BLTMOD_BU24BGR (11 << 25) -# define MGA_BLTMOD_BU24RGB (15 << 25) -# define MGA_PATTERN (1 << 29) -# define MGA_TRANSC (1 << 30) -# define MGA_CLIPDIS (1 << 31) -#define MGA_DWGSYNC 0x2c4c - -#define MGA_FCOL 0x1c24 -#define MGA_FIFOSTATUS 0x1e10 -#define MGA_FOGCOL 0x1cf4 -#define MGA_FXBNDRY 0x1c84 -#define MGA_FXLEFT 0x1ca8 -#define MGA_FXRIGHT 0x1cac - -#define MGA_ICLEAR 0x1e18 -# define MGA_SOFTRAPICLR (1 << 0) -# define MGA_VLINEICLR (1 << 5) -#define MGA_IEN 0x1e1c -# define MGA_SOFTRAPIEN (1 << 0) -# define MGA_VLINEIEN (1 << 5) - -#define MGA_LEN 0x1c5c - -#define MGA_MACCESS 0x1c04 - -#define MGA_PITCH 0x1c8c -#define MGA_PLNWT 0x1c1c -#define MGA_PRIMADDRESS 0x1e58 -# define MGA_DMA_GENERAL (0 << 0) -# define MGA_DMA_BLIT (1 << 0) -# define MGA_DMA_VECTOR (2 << 0) -# define MGA_DMA_VERTEX (3 << 0) -#define MGA_PRIMEND 0x1e5c -# define MGA_PRIMNOSTART (1 << 0) -# define MGA_PAGPXFER (1 << 1) -#define MGA_PRIMPTR 0x1e50 -# define MGA_PRIMPTREN0 (1 << 0) -# define MGA_PRIMPTREN1 (1 << 1) - -#define MGA_RST 0x1e40 -# define MGA_SOFTRESET (1 << 0) -# define MGA_SOFTEXTRST (1 << 1) - -#define MGA_SECADDRESS 0x2c40 -#define MGA_SECEND 0x2c44 -#define MGA_SETUPADDRESS 0x2cd0 -#define MGA_SETUPEND 0x2cd4 -#define MGA_SGN 0x1c58 -#define MGA_SOFTRAP 0x2c48 -#define MGA_SRCORG 0x2cb4 -# define MGA_SRMMAP_MASK (1 << 0) -# define MGA_SRCMAP_FB (0 << 0) -# define MGA_SRCMAP_SYSMEM (1 << 0) -# define MGA_SRCACC_MASK (1 << 1) -# define MGA_SRCACC_PCI (0 << 1) -# define MGA_SRCACC_AGP (1 << 1) -#define MGA_STATUS 0x1e14 -# define MGA_SOFTRAPEN (1 << 0) -# define MGA_VSYNCPEN (1 << 4) -# define MGA_VLINEPEN (1 << 5) -# define MGA_DWGENGSTS (1 << 16) -# define MGA_ENDPRDMASTS (1 << 17) -#define MGA_STENCIL 0x2cc8 -#define MGA_STENCILCTL 0x2ccc - -#define MGA_TDUALSTAGE0 0x2cf8 -#define MGA_TDUALSTAGE1 0x2cfc -#define MGA_TEXBORDERCOL 0x2c5c -#define MGA_TEXCTL 0x2c30 -#define MGA_TEXCTL2 0x2c3c -# define MGA_DUALTEX (1 << 7) -# define MGA_G400_TC2_MAGIC (1 << 15) -# define MGA_MAP1_ENABLE (1 << 31) -#define MGA_TEXFILTER 0x2c58 -#define MGA_TEXHEIGHT 0x2c2c -#define MGA_TEXORG 0x2c24 -# define MGA_TEXORGMAP_MASK (1 << 0) -# define MGA_TEXORGMAP_FB (0 << 0) -# define MGA_TEXORGMAP_SYSMEM (1 << 0) -# define MGA_TEXORGACC_MASK (1 << 1) -# define MGA_TEXORGACC_PCI (0 << 1) -# define MGA_TEXORGACC_AGP (1 << 1) -#define MGA_TEXORG1 0x2ca4 -#define MGA_TEXORG2 0x2ca8 -#define MGA_TEXORG3 0x2cac -#define MGA_TEXORG4 0x2cb0 -#define MGA_TEXTRANS 0x2c34 -#define MGA_TEXTRANSHIGH 0x2c38 -#define MGA_TEXWIDTH 0x2c28 - -#define MGA_WACCEPTSEQ 0x1dd4 -#define MGA_WCODEADDR 0x1e6c -#define MGA_WFLAG 0x1dc4 -#define MGA_WFLAG1 0x1de0 -#define MGA_WFLAGNB 0x1e64 -#define MGA_WFLAGNB1 0x1e08 -#define MGA_WGETMSB 0x1dc8 -#define MGA_WIADDR 0x1dc0 -#define MGA_WIADDR2 0x1dd8 -# define MGA_WMODE_SUSPEND (0 << 0) -# define MGA_WMODE_RESUME (1 << 0) -# define MGA_WMODE_JUMP (2 << 0) -# define MGA_WMODE_START (3 << 0) -# define MGA_WAGP_ENABLE (1 << 2) -#define MGA_WMISC 0x1e70 -# define MGA_WUCODECACHE_ENABLE (1 << 0) -# define MGA_WMASTER_ENABLE (1 << 1) -# define MGA_WCACHEFLUSH_ENABLE (1 << 3) -#define MGA_WVRTXSZ 0x1dcc - -#define MGA_YBOT 0x1c9c -#define MGA_YDST 0x1c90 -#define MGA_YDSTLEN 0x1c88 -#define MGA_YDSTORG 0x1c94 -#define MGA_YTOP 0x1c98 - -#define MGA_ZORG 0x1c0c - -/* This finishes the current batch of commands - */ -#define MGA_EXEC 0x0100 - -/* Warp registers - */ -#define MGA_WR0 0x2d00 -#define MGA_WR1 0x2d04 -#define MGA_WR2 0x2d08 -#define MGA_WR3 0x2d0c -#define MGA_WR4 0x2d10 -#define MGA_WR5 0x2d14 -#define MGA_WR6 0x2d18 -#define MGA_WR7 0x2d1c -#define MGA_WR8 0x2d20 -#define MGA_WR9 0x2d24 -#define MGA_WR10 0x2d28 -#define MGA_WR11 0x2d2c -#define MGA_WR12 0x2d30 -#define MGA_WR13 0x2d34 -#define MGA_WR14 0x2d38 -#define MGA_WR15 0x2d3c -#define MGA_WR16 0x2d40 -#define MGA_WR17 0x2d44 -#define MGA_WR18 0x2d48 -#define MGA_WR19 0x2d4c -#define MGA_WR20 0x2d50 -#define MGA_WR21 0x2d54 -#define MGA_WR22 0x2d58 -#define MGA_WR23 0x2d5c -#define MGA_WR24 0x2d60 -#define MGA_WR25 0x2d64 -#define MGA_WR26 0x2d68 -#define MGA_WR27 0x2d6c -#define MGA_WR28 0x2d70 -#define MGA_WR29 0x2d74 -#define MGA_WR30 0x2d78 -#define MGA_WR31 0x2d7c -#define MGA_WR32 0x2d80 -#define MGA_WR33 0x2d84 -#define MGA_WR34 0x2d88 -#define MGA_WR35 0x2d8c -#define MGA_WR36 0x2d90 -#define MGA_WR37 0x2d94 -#define MGA_WR38 0x2d98 -#define MGA_WR39 0x2d9c -#define MGA_WR40 0x2da0 -#define MGA_WR41 0x2da4 -#define MGA_WR42 0x2da8 -#define MGA_WR43 0x2dac -#define MGA_WR44 0x2db0 -#define MGA_WR45 0x2db4 -#define MGA_WR46 0x2db8 -#define MGA_WR47 0x2dbc -#define MGA_WR48 0x2dc0 -#define MGA_WR49 0x2dc4 -#define MGA_WR50 0x2dc8 -#define MGA_WR51 0x2dcc -#define MGA_WR52 0x2dd0 -#define MGA_WR53 0x2dd4 -#define MGA_WR54 0x2dd8 -#define MGA_WR55 0x2ddc -#define MGA_WR56 0x2de0 -#define MGA_WR57 0x2de4 -#define MGA_WR58 0x2de8 -#define MGA_WR59 0x2dec -#define MGA_WR60 0x2df0 -#define MGA_WR61 0x2df4 -#define MGA_WR62 0x2df8 -#define MGA_WR63 0x2dfc -# define MGA_G400_WR_MAGIC (1 << 6) -# define MGA_G400_WR56_MAGIC 0x46480000 /* 12800.0f */ - - -#define MGA_ILOAD_ALIGN 64 -#define MGA_ILOAD_MASK (MGA_ILOAD_ALIGN - 1) - -#define MGA_DWGCTL_FLUSH (MGA_OPCOD_TEXTURE_TRAP | \ - MGA_ATYPE_I | \ - MGA_ZMODE_NOZCMP | \ - MGA_ARZERO | \ - MGA_SGNZERO | \ - MGA_BOP_SRC | \ - (15 << MGA_TRANS_SHIFT)) - -#define MGA_DWGCTL_CLEAR (MGA_OPCOD_TRAP | \ - MGA_ZMODE_NOZCMP | \ - MGA_SOLID | \ - MGA_ARZERO | \ - MGA_SGNZERO | \ - MGA_SHIFTZERO | \ - MGA_BOP_SRC | \ - (0 << MGA_TRANS_SHIFT) | \ - MGA_BLTMOD_BMONOLEF | \ - MGA_TRANSC | \ - MGA_CLIPDIS) - -#define MGA_DWGCTL_COPY (MGA_OPCOD_BITBLT | \ - MGA_ATYPE_RPL | \ - MGA_SGNZERO | \ - MGA_SHIFTZERO | \ - MGA_BOP_SRC | \ - (0 << MGA_TRANS_SHIFT) | \ - MGA_BLTMOD_BFCOL | \ - MGA_CLIPDIS) - -/* Simple idle test. - */ -static __inline__ int mga_is_idle( drm_mga_private_t *dev_priv ) -{ - u32 status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK; - return ( status == MGA_ENDPRDMASTS ); -} - -#endif diff --git a/nx-X11/extras/drm/shared/mga_irq.c b/nx-X11/extras/drm/shared/mga_irq.c deleted file mode 100644 index c3185b0b8..000000000 --- a/nx-X11/extras/drm/shared/mga_irq.c +++ /dev/null @@ -1,103 +0,0 @@ -/* mga_irq.c -- IRQ handling for radeon -*- linux-c -*- - * - * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - * - * The Weather Channel (TM) funded Tungsten Graphics to develop the - * initial release of the Radeon 8500 driver under the XFree86 license. - * This notice must be preserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Keith Whitwell - * Eric Anholt - */ - -#include "mga.h" -#include "drmP.h" -#include "drm.h" -#include "mga_drm.h" -#include "mga_drv.h" - -irqreturn_t mga_driver_irq_handler( DRM_IRQ_ARGS ) -{ - drm_device_t *dev = (drm_device_t *) arg; - drm_mga_private_t *dev_priv = - (drm_mga_private_t *)dev->dev_private; - int status; - - status = MGA_READ( MGA_STATUS ); - - /* VBLANK interrupt */ - if ( status & MGA_VLINEPEN ) { - MGA_WRITE( MGA_ICLEAR, MGA_VLINEICLR ); - atomic_inc(&dev->vbl_received); - DRM_WAKEUP(&dev->vbl_queue); - DRM(vbl_send_signals)( dev ); - return IRQ_HANDLED; - } - return IRQ_NONE; -} - -int mga_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence) -{ - unsigned int cur_vblank; - int ret = 0; - - /* Assume that the user has missed the current sequence number - * by about a day rather than she wants to wait for years - * using vertical blanks... - */ - DRM_WAIT_ON( ret, dev->vbl_queue, 3*DRM_HZ, - ( ( ( cur_vblank = atomic_read(&dev->vbl_received ) ) - - *sequence ) <= (1<<23) ) ); - - *sequence = cur_vblank; - - return ret; -} - -void mga_driver_irq_preinstall( drm_device_t *dev ) { - drm_mga_private_t *dev_priv = - (drm_mga_private_t *)dev->dev_private; - - /* Disable *all* interrupts */ - MGA_WRITE( MGA_IEN, 0 ); - /* Clear bits if they're already high */ - MGA_WRITE( MGA_ICLEAR, ~0 ); -} - -void mga_driver_irq_postinstall( drm_device_t *dev ) { - drm_mga_private_t *dev_priv = - (drm_mga_private_t *)dev->dev_private; - - /* Turn on VBL interrupt */ - MGA_WRITE( MGA_IEN, MGA_VLINEIEN ); -} - -void mga_driver_irq_uninstall( drm_device_t *dev ) { - drm_mga_private_t *dev_priv = - (drm_mga_private_t *)dev->dev_private; - if (!dev_priv) - return; - - /* Disable *all* interrupts */ - MGA_WRITE( MGA_IEN, 0 ); -} diff --git a/nx-X11/extras/drm/shared/mga_state.c b/nx-X11/extras/drm/shared/mga_state.c deleted file mode 100644 index 3dc1999a3..000000000 --- a/nx-X11/extras/drm/shared/mga_state.c +++ /dev/null @@ -1,1110 +0,0 @@ -/* mga_state.c -- State support for MGA G200/G400 -*- linux-c -*- - * Created: Thu Jan 27 02:53:43 2000 by jhartmann@precisioninsight.com - * - * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. - * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Jeff Hartmann - * Keith Whitwell - * - * Rewritten by: - * Gareth Hughes - */ - -#include "mga.h" -#include "drmP.h" -#include "drm.h" -#include "mga_drm.h" -#include "mga_drv.h" - - -/* ================================================================ - * DMA hardware state programming functions - */ - -static void mga_emit_clip_rect( drm_mga_private_t *dev_priv, - drm_clip_rect_t *box ) -{ - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mga_context_regs_t *ctx = &sarea_priv->context_state; - unsigned int pitch = dev_priv->front_pitch; - DMA_LOCALS; - - BEGIN_DMA( 2 ); - - /* Force reset of DWGCTL on G400 (eliminates clip disable bit). - */ - if ( dev_priv->chipset == MGA_CARD_TYPE_G400 ) { - DMA_BLOCK( MGA_DWGCTL, ctx->dwgctl, - MGA_LEN + MGA_EXEC, 0x80000000, - MGA_DWGCTL, ctx->dwgctl, - MGA_LEN + MGA_EXEC, 0x80000000 ); - } - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_CXBNDRY, ((box->x2 - 1) << 16) | box->x1, - MGA_YTOP, box->y1 * pitch, - MGA_YBOT, (box->y2 - 1) * pitch ); - - ADVANCE_DMA(); -} - -static __inline__ void mga_g200_emit_context( drm_mga_private_t *dev_priv ) -{ - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mga_context_regs_t *ctx = &sarea_priv->context_state; - DMA_LOCALS; - - BEGIN_DMA( 3 ); - - DMA_BLOCK( MGA_DSTORG, ctx->dstorg, - MGA_MACCESS, ctx->maccess, - MGA_PLNWT, ctx->plnwt, - MGA_DWGCTL, ctx->dwgctl ); - - DMA_BLOCK( MGA_ALPHACTRL, ctx->alphactrl, - MGA_FOGCOL, ctx->fogcolor, - MGA_WFLAG, ctx->wflag, - MGA_ZORG, dev_priv->depth_offset ); - - DMA_BLOCK( MGA_FCOL, ctx->fcol, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000 ); - - ADVANCE_DMA(); -} - -static __inline__ void mga_g400_emit_context( drm_mga_private_t *dev_priv ) -{ - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mga_context_regs_t *ctx = &sarea_priv->context_state; - DMA_LOCALS; - - BEGIN_DMA( 4 ); - - DMA_BLOCK( MGA_DSTORG, ctx->dstorg, - MGA_MACCESS, ctx->maccess, - MGA_PLNWT, ctx->plnwt, - MGA_DWGCTL, ctx->dwgctl ); - - DMA_BLOCK( MGA_ALPHACTRL, ctx->alphactrl, - MGA_FOGCOL, ctx->fogcolor, - MGA_WFLAG, ctx->wflag, - MGA_ZORG, dev_priv->depth_offset ); - - DMA_BLOCK( MGA_WFLAG1, ctx->wflag, - MGA_TDUALSTAGE0, ctx->tdualstage0, - MGA_TDUALSTAGE1, ctx->tdualstage1, - MGA_FCOL, ctx->fcol ); - - DMA_BLOCK( MGA_STENCIL, ctx->stencil, - MGA_STENCILCTL, ctx->stencilctl, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000 ); - - ADVANCE_DMA(); -} - -static __inline__ void mga_g200_emit_tex0( drm_mga_private_t *dev_priv ) -{ - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0]; - DMA_LOCALS; - - BEGIN_DMA( 4 ); - - DMA_BLOCK( MGA_TEXCTL2, tex->texctl2, - MGA_TEXCTL, tex->texctl, - MGA_TEXFILTER, tex->texfilter, - MGA_TEXBORDERCOL, tex->texbordercol ); - - DMA_BLOCK( MGA_TEXORG, tex->texorg, - MGA_TEXORG1, tex->texorg1, - MGA_TEXORG2, tex->texorg2, - MGA_TEXORG3, tex->texorg3 ); - - DMA_BLOCK( MGA_TEXORG4, tex->texorg4, - MGA_TEXWIDTH, tex->texwidth, - MGA_TEXHEIGHT, tex->texheight, - MGA_WR24, tex->texwidth ); - - DMA_BLOCK( MGA_WR34, tex->texheight, - MGA_TEXTRANS, 0x0000ffff, - MGA_TEXTRANSHIGH, 0x0000ffff, - MGA_DMAPAD, 0x00000000 ); - - ADVANCE_DMA(); -} - -static __inline__ void mga_g400_emit_tex0( drm_mga_private_t *dev_priv ) -{ - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0]; - DMA_LOCALS; - -/* printk("mga_g400_emit_tex0 %x %x %x\n", tex->texorg, */ -/* tex->texctl, tex->texctl2); */ - - BEGIN_DMA( 6 ); - - DMA_BLOCK( MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC, - MGA_TEXCTL, tex->texctl, - MGA_TEXFILTER, tex->texfilter, - MGA_TEXBORDERCOL, tex->texbordercol ); - - DMA_BLOCK( MGA_TEXORG, tex->texorg, - MGA_TEXORG1, tex->texorg1, - MGA_TEXORG2, tex->texorg2, - MGA_TEXORG3, tex->texorg3 ); - - DMA_BLOCK( MGA_TEXORG4, tex->texorg4, - MGA_TEXWIDTH, tex->texwidth, - MGA_TEXHEIGHT, tex->texheight, - MGA_WR49, 0x00000000 ); - - DMA_BLOCK( MGA_WR57, 0x00000000, - MGA_WR53, 0x00000000, - MGA_WR61, 0x00000000, - MGA_WR52, MGA_G400_WR_MAGIC ); - - DMA_BLOCK( MGA_WR60, MGA_G400_WR_MAGIC, - MGA_WR54, tex->texwidth | MGA_G400_WR_MAGIC, - MGA_WR62, tex->texheight | MGA_G400_WR_MAGIC, - MGA_DMAPAD, 0x00000000 ); - - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_TEXTRANS, 0x0000ffff, - MGA_TEXTRANSHIGH, 0x0000ffff ); - - ADVANCE_DMA(); -} - -static __inline__ void mga_g400_emit_tex1( drm_mga_private_t *dev_priv ) -{ - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[1]; - DMA_LOCALS; - -/* printk("mga_g400_emit_tex1 %x %x %x\n", tex->texorg, */ -/* tex->texctl, tex->texctl2); */ - - BEGIN_DMA( 5 ); - - DMA_BLOCK( MGA_TEXCTL2, (tex->texctl2 | - MGA_MAP1_ENABLE | - MGA_G400_TC2_MAGIC), - MGA_TEXCTL, tex->texctl, - MGA_TEXFILTER, tex->texfilter, - MGA_TEXBORDERCOL, tex->texbordercol ); - - DMA_BLOCK( MGA_TEXORG, tex->texorg, - MGA_TEXORG1, tex->texorg1, - MGA_TEXORG2, tex->texorg2, - MGA_TEXORG3, tex->texorg3 ); - - DMA_BLOCK( MGA_TEXORG4, tex->texorg4, - MGA_TEXWIDTH, tex->texwidth, - MGA_TEXHEIGHT, tex->texheight, - MGA_WR49, 0x00000000 ); - - DMA_BLOCK( MGA_WR57, 0x00000000, - MGA_WR53, 0x00000000, - MGA_WR61, 0x00000000, - MGA_WR52, tex->texwidth | MGA_G400_WR_MAGIC ); - - DMA_BLOCK( MGA_WR60, tex->texheight | MGA_G400_WR_MAGIC, - MGA_TEXTRANS, 0x0000ffff, - MGA_TEXTRANSHIGH, 0x0000ffff, - MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC ); - - ADVANCE_DMA(); -} - -static __inline__ void mga_g200_emit_pipe( drm_mga_private_t *dev_priv ) -{ - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - unsigned int pipe = sarea_priv->warp_pipe; - DMA_LOCALS; - - BEGIN_DMA( 3 ); - - DMA_BLOCK( MGA_WIADDR, MGA_WMODE_SUSPEND, - MGA_WVRTXSZ, 0x00000007, - MGA_WFLAG, 0x00000000, - MGA_WR24, 0x00000000 ); - - DMA_BLOCK( MGA_WR25, 0x00000100, - MGA_WR34, 0x00000000, - MGA_WR42, 0x0000ffff, - MGA_WR60, 0x0000ffff ); - - /* Padding required to to hardware bug. - */ - DMA_BLOCK( MGA_DMAPAD, 0xffffffff, - MGA_DMAPAD, 0xffffffff, - MGA_DMAPAD, 0xffffffff, - MGA_WIADDR, (dev_priv->warp_pipe_phys[pipe] | - MGA_WMODE_START | - MGA_WAGP_ENABLE) ); - - ADVANCE_DMA(); -} - -static __inline__ void mga_g400_emit_pipe( drm_mga_private_t *dev_priv ) -{ - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - unsigned int pipe = sarea_priv->warp_pipe; - DMA_LOCALS; - -/* printk("mga_g400_emit_pipe %x\n", pipe); */ - - BEGIN_DMA( 10 ); - - DMA_BLOCK( MGA_WIADDR2, MGA_WMODE_SUSPEND, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000 ); - - if ( pipe & MGA_T2 ) { - DMA_BLOCK( MGA_WVRTXSZ, 0x00001e09, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000 ); - - DMA_BLOCK( MGA_WACCEPTSEQ, 0x00000000, - MGA_WACCEPTSEQ, 0x00000000, - MGA_WACCEPTSEQ, 0x00000000, - MGA_WACCEPTSEQ, 0x1e000000 ); - } else { - if ( dev_priv->warp_pipe & MGA_T2 ) { - /* Flush the WARP pipe */ - DMA_BLOCK( MGA_YDST, 0x00000000, - MGA_FXLEFT, 0x00000000, - MGA_FXRIGHT, 0x00000001, - MGA_DWGCTL, MGA_DWGCTL_FLUSH ); - - DMA_BLOCK( MGA_LEN + MGA_EXEC, 0x00000001, - MGA_DWGSYNC, 0x00007000, - MGA_TEXCTL2, MGA_G400_TC2_MAGIC, - MGA_LEN + MGA_EXEC, 0x00000000 ); - - DMA_BLOCK( MGA_TEXCTL2, (MGA_DUALTEX | - MGA_G400_TC2_MAGIC), - MGA_LEN + MGA_EXEC, 0x00000000, - MGA_TEXCTL2, MGA_G400_TC2_MAGIC, - MGA_DMAPAD, 0x00000000 ); - } - - DMA_BLOCK( MGA_WVRTXSZ, 0x00001807, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000 ); - - DMA_BLOCK( MGA_WACCEPTSEQ, 0x00000000, - MGA_WACCEPTSEQ, 0x00000000, - MGA_WACCEPTSEQ, 0x00000000, - MGA_WACCEPTSEQ, 0x18000000 ); - } - - DMA_BLOCK( MGA_WFLAG, 0x00000000, - MGA_WFLAG1, 0x00000000, - MGA_WR56, MGA_G400_WR56_MAGIC, - MGA_DMAPAD, 0x00000000 ); - - DMA_BLOCK( MGA_WR49, 0x00000000, /* tex0 */ - MGA_WR57, 0x00000000, /* tex0 */ - MGA_WR53, 0x00000000, /* tex1 */ - MGA_WR61, 0x00000000 ); /* tex1 */ - - DMA_BLOCK( MGA_WR54, MGA_G400_WR_MAGIC, /* tex0 width */ - MGA_WR62, MGA_G400_WR_MAGIC, /* tex0 height */ - MGA_WR52, MGA_G400_WR_MAGIC, /* tex1 width */ - MGA_WR60, MGA_G400_WR_MAGIC ); /* tex1 height */ - - /* Padding required to to hardware bug */ - DMA_BLOCK( MGA_DMAPAD, 0xffffffff, - MGA_DMAPAD, 0xffffffff, - MGA_DMAPAD, 0xffffffff, - MGA_WIADDR2, (dev_priv->warp_pipe_phys[pipe] | - MGA_WMODE_START | - MGA_WAGP_ENABLE) ); - - ADVANCE_DMA(); -} - -static void mga_g200_emit_state( drm_mga_private_t *dev_priv ) -{ - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - unsigned int dirty = sarea_priv->dirty; - - if ( sarea_priv->warp_pipe != dev_priv->warp_pipe ) { - mga_g200_emit_pipe( dev_priv ); - dev_priv->warp_pipe = sarea_priv->warp_pipe; - } - - if ( dirty & MGA_UPLOAD_CONTEXT ) { - mga_g200_emit_context( dev_priv ); - sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT; - } - - if ( dirty & MGA_UPLOAD_TEX0 ) { - mga_g200_emit_tex0( dev_priv ); - sarea_priv->dirty &= ~MGA_UPLOAD_TEX0; - } -} - -static void mga_g400_emit_state( drm_mga_private_t *dev_priv ) -{ - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - unsigned int dirty = sarea_priv->dirty; - int multitex = sarea_priv->warp_pipe & MGA_T2; - - if ( sarea_priv->warp_pipe != dev_priv->warp_pipe ) { - mga_g400_emit_pipe( dev_priv ); - dev_priv->warp_pipe = sarea_priv->warp_pipe; - } - - if ( dirty & MGA_UPLOAD_CONTEXT ) { - mga_g400_emit_context( dev_priv ); - sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT; - } - - if ( dirty & MGA_UPLOAD_TEX0 ) { - mga_g400_emit_tex0( dev_priv ); - sarea_priv->dirty &= ~MGA_UPLOAD_TEX0; - } - - if ( (dirty & MGA_UPLOAD_TEX1) && multitex ) { - mga_g400_emit_tex1( dev_priv ); - sarea_priv->dirty &= ~MGA_UPLOAD_TEX1; - } -} - - -/* ================================================================ - * SAREA state verification - */ - -/* Disallow all write destinations except the front and backbuffer. - */ -static int mga_verify_context( drm_mga_private_t *dev_priv ) -{ - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mga_context_regs_t *ctx = &sarea_priv->context_state; - - if ( ctx->dstorg != dev_priv->front_offset && - ctx->dstorg != dev_priv->back_offset ) { - DRM_ERROR( "*** bad DSTORG: %x (front %x, back %x)\n\n", - ctx->dstorg, dev_priv->front_offset, - dev_priv->back_offset ); - ctx->dstorg = 0; - return DRM_ERR(EINVAL); - } - - return 0; -} - -/* Disallow texture reads from PCI space. - */ -static int mga_verify_tex( drm_mga_private_t *dev_priv, int unit ) -{ - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[unit]; - unsigned int org; - - org = tex->texorg & (MGA_TEXORGMAP_MASK | MGA_TEXORGACC_MASK); - - if ( org == (MGA_TEXORGMAP_SYSMEM | MGA_TEXORGACC_PCI) ) { - DRM_ERROR( "*** bad TEXORG: 0x%x, unit %d\n", - tex->texorg, unit ); - tex->texorg = 0; - return DRM_ERR(EINVAL); - } - - return 0; -} - -static int mga_verify_state( drm_mga_private_t *dev_priv ) -{ - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - unsigned int dirty = sarea_priv->dirty; - int ret = 0; - - if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS ) - sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; - - if ( dirty & MGA_UPLOAD_CONTEXT ) - ret |= mga_verify_context( dev_priv ); - - if ( dirty & MGA_UPLOAD_TEX0 ) - ret |= mga_verify_tex( dev_priv, 0 ); - - if ( dev_priv->chipset == MGA_CARD_TYPE_G400 ) { - if ( dirty & MGA_UPLOAD_TEX1 ) - ret |= mga_verify_tex( dev_priv, 1 ); - - if ( dirty & MGA_UPLOAD_PIPE ) - ret |= ( sarea_priv->warp_pipe > MGA_MAX_G400_PIPES ); - } else { - if ( dirty & MGA_UPLOAD_PIPE ) - ret |= ( sarea_priv->warp_pipe > MGA_MAX_G200_PIPES ); - } - - return ( ret == 0 ); -} - -static int mga_verify_iload( drm_mga_private_t *dev_priv, - unsigned int dstorg, unsigned int length ) -{ - if ( dstorg < dev_priv->texture_offset || - dstorg + length > (dev_priv->texture_offset + - dev_priv->texture_size) ) { - DRM_ERROR( "*** bad iload DSTORG: 0x%x\n", dstorg ); - return DRM_ERR(EINVAL); - } - - if ( length & MGA_ILOAD_MASK ) { - DRM_ERROR( "*** bad iload length: 0x%x\n", - length & MGA_ILOAD_MASK ); - return DRM_ERR(EINVAL); - } - - return 0; -} - -static int mga_verify_blit( drm_mga_private_t *dev_priv, - unsigned int srcorg, unsigned int dstorg ) -{ - if ( (srcorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) || - (dstorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) ) { - DRM_ERROR( "*** bad blit: src=0x%x dst=0x%x\n", - srcorg, dstorg ); - return DRM_ERR(EINVAL); - } - return 0; -} - - -/* ================================================================ - * - */ - -static void mga_dma_dispatch_clear( drm_device_t *dev, - drm_mga_clear_t *clear ) -{ - drm_mga_private_t *dev_priv = dev->dev_private; - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mga_context_regs_t *ctx = &sarea_priv->context_state; - drm_clip_rect_t *pbox = sarea_priv->boxes; - int nbox = sarea_priv->nbox; - int i; - DMA_LOCALS; - DRM_DEBUG( "\n" ); - - BEGIN_DMA( 1 ); - - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DWGSYNC, 0x00007100, - MGA_DWGSYNC, 0x00007000 ); - - ADVANCE_DMA(); - - for ( i = 0 ; i < nbox ; i++ ) { - drm_clip_rect_t *box = &pbox[i]; - u32 height = box->y2 - box->y1; - - DRM_DEBUG( " from=%d,%d to=%d,%d\n", - box->x1, box->y1, box->x2, box->y2 ); - - if ( clear->flags & MGA_FRONT ) { - BEGIN_DMA( 2 ); - - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_PLNWT, clear->color_mask, - MGA_YDSTLEN, (box->y1 << 16) | height, - MGA_FXBNDRY, (box->x2 << 16) | box->x1 ); - - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_FCOL, clear->clear_color, - MGA_DSTORG, dev_priv->front_offset, - MGA_DWGCTL + MGA_EXEC, - dev_priv->clear_cmd ); - - ADVANCE_DMA(); - } - - - if ( clear->flags & MGA_BACK ) { - BEGIN_DMA( 2 ); - - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_PLNWT, clear->color_mask, - MGA_YDSTLEN, (box->y1 << 16) | height, - MGA_FXBNDRY, (box->x2 << 16) | box->x1 ); - - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_FCOL, clear->clear_color, - MGA_DSTORG, dev_priv->back_offset, - MGA_DWGCTL + MGA_EXEC, - dev_priv->clear_cmd ); - - ADVANCE_DMA(); - } - - if ( clear->flags & MGA_DEPTH ) { - BEGIN_DMA( 2 ); - - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_PLNWT, clear->depth_mask, - MGA_YDSTLEN, (box->y1 << 16) | height, - MGA_FXBNDRY, (box->x2 << 16) | box->x1 ); - - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_FCOL, clear->clear_depth, - MGA_DSTORG, dev_priv->depth_offset, - MGA_DWGCTL + MGA_EXEC, - dev_priv->clear_cmd ); - - ADVANCE_DMA(); - } - - } - - BEGIN_DMA( 1 ); - - /* Force reset of DWGCTL */ - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_PLNWT, ctx->plnwt, - MGA_DWGCTL, ctx->dwgctl ); - - ADVANCE_DMA(); - - FLUSH_DMA(); -} - -static void mga_dma_dispatch_swap( drm_device_t *dev ) -{ - drm_mga_private_t *dev_priv = dev->dev_private; - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mga_context_regs_t *ctx = &sarea_priv->context_state; - drm_clip_rect_t *pbox = sarea_priv->boxes; - int nbox = sarea_priv->nbox; - int i; - DMA_LOCALS; - DRM_DEBUG( "\n" ); - - sarea_priv->last_frame.head = dev_priv->prim.tail; - sarea_priv->last_frame.wrap = dev_priv->prim.last_wrap; - - BEGIN_DMA( 4 + nbox ); - - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DWGSYNC, 0x00007100, - MGA_DWGSYNC, 0x00007000 ); - - DMA_BLOCK( MGA_DSTORG, dev_priv->front_offset, - MGA_MACCESS, dev_priv->maccess, - MGA_SRCORG, dev_priv->back_offset, - MGA_AR5, dev_priv->front_pitch ); - - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_PLNWT, 0xffffffff, - MGA_DWGCTL, MGA_DWGCTL_COPY ); - - for ( i = 0 ; i < nbox ; i++ ) { - drm_clip_rect_t *box = &pbox[i]; - u32 height = box->y2 - box->y1; - u32 start = box->y1 * dev_priv->front_pitch; - - DRM_DEBUG( " from=%d,%d to=%d,%d\n", - box->x1, box->y1, box->x2, box->y2 ); - - DMA_BLOCK( MGA_AR0, start + box->x2 - 1, - MGA_AR3, start + box->x1, - MGA_FXBNDRY, ((box->x2 - 1) << 16) | box->x1, - MGA_YDSTLEN + MGA_EXEC, - (box->y1 << 16) | height ); - } - - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_PLNWT, ctx->plnwt, - MGA_SRCORG, dev_priv->front_offset, - MGA_DWGCTL, ctx->dwgctl ); - - ADVANCE_DMA(); - - FLUSH_DMA(); - - DRM_DEBUG( "%s... done.\n", __FUNCTION__ ); -} - -static void mga_dma_dispatch_vertex( drm_device_t *dev, drm_buf_t *buf ) -{ - drm_mga_private_t *dev_priv = dev->dev_private; - drm_mga_buf_priv_t *buf_priv = buf->dev_private; - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - u32 address = (u32) buf->bus_address; - u32 length = (u32) buf->used; - int i = 0; - DMA_LOCALS; - DRM_DEBUG( "vertex: buf=%d used=%d\n", buf->idx, buf->used ); - - if ( buf->used ) { - buf_priv->dispatched = 1; - - MGA_EMIT_STATE( dev_priv, sarea_priv->dirty ); - - do { - if ( i < sarea_priv->nbox ) { - mga_emit_clip_rect( dev_priv, - &sarea_priv->boxes[i] ); - } - - BEGIN_DMA( 1 ); - - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_SECADDRESS, (address | - MGA_DMA_VERTEX), - MGA_SECEND, ((address + length) | - MGA_PAGPXFER) ); - - ADVANCE_DMA(); - } while ( ++i < sarea_priv->nbox ); - } - - if ( buf_priv->discard ) { - AGE_BUFFER( buf_priv ); - buf->pending = 0; - buf->used = 0; - buf_priv->dispatched = 0; - - mga_freelist_put( dev, buf ); - } - - FLUSH_DMA(); -} - -static void mga_dma_dispatch_indices( drm_device_t *dev, drm_buf_t *buf, - unsigned int start, unsigned int end ) -{ - drm_mga_private_t *dev_priv = dev->dev_private; - drm_mga_buf_priv_t *buf_priv = buf->dev_private; - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - u32 address = (u32) buf->bus_address; - int i = 0; - DMA_LOCALS; - DRM_DEBUG( "indices: buf=%d start=%d end=%d\n", buf->idx, start, end ); - - if ( start != end ) { - buf_priv->dispatched = 1; - - MGA_EMIT_STATE( dev_priv, sarea_priv->dirty ); - - do { - if ( i < sarea_priv->nbox ) { - mga_emit_clip_rect( dev_priv, - &sarea_priv->boxes[i] ); - } - - BEGIN_DMA( 1 ); - - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_SETUPADDRESS, address + start, - MGA_SETUPEND, ((address + end) | - MGA_PAGPXFER) ); - - ADVANCE_DMA(); - } while ( ++i < sarea_priv->nbox ); - } - - if ( buf_priv->discard ) { - AGE_BUFFER( buf_priv ); - buf->pending = 0; - buf->used = 0; - buf_priv->dispatched = 0; - - mga_freelist_put( dev, buf ); - } - - FLUSH_DMA(); -} - -/* This copies a 64 byte aligned agp region to the frambuffer with a - * standard blit, the ioctl needs to do checking. - */ -static void mga_dma_dispatch_iload( drm_device_t *dev, drm_buf_t *buf, - unsigned int dstorg, unsigned int length ) -{ - drm_mga_private_t *dev_priv = dev->dev_private; - drm_mga_buf_priv_t *buf_priv = buf->dev_private; - drm_mga_context_regs_t *ctx = &dev_priv->sarea_priv->context_state; - u32 srcorg = buf->bus_address | MGA_SRCACC_AGP | MGA_SRCMAP_SYSMEM; - u32 y2; - DMA_LOCALS; - DRM_DEBUG( "buf=%d used=%d\n", buf->idx, buf->used ); - - y2 = length / 64; - - BEGIN_DMA( 5 ); - - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DWGSYNC, 0x00007100, - MGA_DWGSYNC, 0x00007000 ); - - DMA_BLOCK( MGA_DSTORG, dstorg, - MGA_MACCESS, 0x00000000, - MGA_SRCORG, srcorg, - MGA_AR5, 64 ); - - DMA_BLOCK( MGA_PITCH, 64, - MGA_PLNWT, 0xffffffff, - MGA_DMAPAD, 0x00000000, - MGA_DWGCTL, MGA_DWGCTL_COPY ); - - DMA_BLOCK( MGA_AR0, 63, - MGA_AR3, 0, - MGA_FXBNDRY, (63 << 16) | 0, - MGA_YDSTLEN + MGA_EXEC, y2 ); - - DMA_BLOCK( MGA_PLNWT, ctx->plnwt, - MGA_SRCORG, dev_priv->front_offset, - MGA_PITCH, dev_priv->front_pitch, - MGA_DWGSYNC, 0x00007000 ); - - ADVANCE_DMA(); - - AGE_BUFFER( buf_priv ); - - buf->pending = 0; - buf->used = 0; - buf_priv->dispatched = 0; - - mga_freelist_put( dev, buf ); - - FLUSH_DMA(); -} - -static void mga_dma_dispatch_blit( drm_device_t *dev, - drm_mga_blit_t *blit ) -{ - drm_mga_private_t *dev_priv = dev->dev_private; - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mga_context_regs_t *ctx = &sarea_priv->context_state; - drm_clip_rect_t *pbox = sarea_priv->boxes; - int nbox = sarea_priv->nbox; - u32 scandir = 0, i; - DMA_LOCALS; - DRM_DEBUG( "\n" ); - - BEGIN_DMA( 4 + nbox ); - - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DWGSYNC, 0x00007100, - MGA_DWGSYNC, 0x00007000 ); - - DMA_BLOCK( MGA_DWGCTL, MGA_DWGCTL_COPY, - MGA_PLNWT, blit->planemask, - MGA_SRCORG, blit->srcorg, - MGA_DSTORG, blit->dstorg ); - - DMA_BLOCK( MGA_SGN, scandir, - MGA_MACCESS, dev_priv->maccess, - MGA_AR5, blit->ydir * blit->src_pitch, - MGA_PITCH, blit->dst_pitch ); - - for ( i = 0 ; i < nbox ; i++ ) { - int srcx = pbox[i].x1 + blit->delta_sx; - int srcy = pbox[i].y1 + blit->delta_sy; - int dstx = pbox[i].x1 + blit->delta_dx; - int dsty = pbox[i].y1 + blit->delta_dy; - int h = pbox[i].y2 - pbox[i].y1; - int w = pbox[i].x2 - pbox[i].x1 - 1; - int start; - - if ( blit->ydir == -1 ) { - srcy = blit->height - srcy - 1; - } - - start = srcy * blit->src_pitch + srcx; - - DMA_BLOCK( MGA_AR0, start + w, - MGA_AR3, start, - MGA_FXBNDRY, ((dstx + w) << 16) | (dstx & 0xffff), - MGA_YDSTLEN + MGA_EXEC, (dsty << 16) | h ); - } - - /* Do something to flush AGP? - */ - - /* Force reset of DWGCTL */ - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_PLNWT, ctx->plnwt, - MGA_PITCH, dev_priv->front_pitch, - MGA_DWGCTL, ctx->dwgctl ); - - ADVANCE_DMA(); -} - - -/* ================================================================ - * - */ - -int mga_dma_clear( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_mga_private_t *dev_priv = dev->dev_private; - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mga_clear_t clear; - - LOCK_TEST_WITH_RETURN( dev, filp ); - - DRM_COPY_FROM_USER_IOCTL( clear, (drm_mga_clear_t __user *)data, sizeof(clear) ); - - if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS ) - sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; - - WRAP_TEST_WITH_RETURN( dev_priv ); - - mga_dma_dispatch_clear( dev, &clear ); - - /* Make sure we restore the 3D state next time. - */ - dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT; - - return 0; -} - -int mga_dma_swap( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_mga_private_t *dev_priv = dev->dev_private; - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - - LOCK_TEST_WITH_RETURN( dev, filp ); - - if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS ) - sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; - - WRAP_TEST_WITH_RETURN( dev_priv ); - - mga_dma_dispatch_swap( dev ); - - /* Make sure we restore the 3D state next time. - */ - dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT; - - return 0; -} - -int mga_dma_vertex( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_mga_private_t *dev_priv = dev->dev_private; - drm_device_dma_t *dma = dev->dma; - drm_buf_t *buf; - drm_mga_buf_priv_t *buf_priv; - drm_mga_vertex_t vertex; - - LOCK_TEST_WITH_RETURN( dev, filp ); - - DRM_COPY_FROM_USER_IOCTL( vertex, - (drm_mga_vertex_t __user *)data, - sizeof(vertex) ); - - if(vertex.idx < 0 || vertex.idx > dma->buf_count) return DRM_ERR(EINVAL); - buf = dma->buflist[vertex.idx]; - buf_priv = buf->dev_private; - - buf->used = vertex.used; - buf_priv->discard = vertex.discard; - - if ( !mga_verify_state( dev_priv ) ) { - if ( vertex.discard ) { - if ( buf_priv->dispatched == 1 ) - AGE_BUFFER( buf_priv ); - buf_priv->dispatched = 0; - mga_freelist_put( dev, buf ); - } - return DRM_ERR(EINVAL); - } - - WRAP_TEST_WITH_RETURN( dev_priv ); - - mga_dma_dispatch_vertex( dev, buf ); - - return 0; -} - -int mga_dma_indices( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_mga_private_t *dev_priv = dev->dev_private; - drm_device_dma_t *dma = dev->dma; - drm_buf_t *buf; - drm_mga_buf_priv_t *buf_priv; - drm_mga_indices_t indices; - - LOCK_TEST_WITH_RETURN( dev, filp ); - - DRM_COPY_FROM_USER_IOCTL( indices, - (drm_mga_indices_t __user *)data, - sizeof(indices) ); - - if(indices.idx < 0 || indices.idx > dma->buf_count) return DRM_ERR(EINVAL); - - buf = dma->buflist[indices.idx]; - buf_priv = buf->dev_private; - - buf_priv->discard = indices.discard; - - if ( !mga_verify_state( dev_priv ) ) { - if ( indices.discard ) { - if ( buf_priv->dispatched == 1 ) - AGE_BUFFER( buf_priv ); - buf_priv->dispatched = 0; - mga_freelist_put( dev, buf ); - } - return DRM_ERR(EINVAL); - } - - WRAP_TEST_WITH_RETURN( dev_priv ); - - mga_dma_dispatch_indices( dev, buf, indices.start, indices.end ); - - return 0; -} - -int mga_dma_iload( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_device_dma_t *dma = dev->dma; - drm_mga_private_t *dev_priv = dev->dev_private; - drm_buf_t *buf; - drm_mga_buf_priv_t *buf_priv; - drm_mga_iload_t iload; - DRM_DEBUG( "\n" ); - - LOCK_TEST_WITH_RETURN( dev, filp ); - - DRM_COPY_FROM_USER_IOCTL( iload, (drm_mga_iload_t __user *)data, sizeof(iload) ); - -#if 0 - if ( mga_do_wait_for_idle( dev_priv ) < 0 ) { - if ( MGA_DMA_DEBUG ) - DRM_INFO( "%s: -EBUSY\n", __FUNCTION__ ); - return DRM_ERR(EBUSY); - } -#endif - if(iload.idx < 0 || iload.idx > dma->buf_count) return DRM_ERR(EINVAL); - - buf = dma->buflist[iload.idx]; - buf_priv = buf->dev_private; - - if ( mga_verify_iload( dev_priv, iload.dstorg, iload.length ) ) { - mga_freelist_put( dev, buf ); - return DRM_ERR(EINVAL); - } - - WRAP_TEST_WITH_RETURN( dev_priv ); - - mga_dma_dispatch_iload( dev, buf, iload.dstorg, iload.length ); - - /* Make sure we restore the 3D state next time. - */ - dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT; - - return 0; -} - -int mga_dma_blit( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_mga_private_t *dev_priv = dev->dev_private; - drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_mga_blit_t blit; - DRM_DEBUG( "\n" ); - - LOCK_TEST_WITH_RETURN( dev, filp ); - - DRM_COPY_FROM_USER_IOCTL( blit, (drm_mga_blit_t __user *)data, sizeof(blit) ); - - if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS ) - sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; - - if ( mga_verify_blit( dev_priv, blit.srcorg, blit.dstorg ) ) - return DRM_ERR(EINVAL); - - WRAP_TEST_WITH_RETURN( dev_priv ); - - mga_dma_dispatch_blit( dev, &blit ); - - /* Make sure we restore the 3D state next time. - */ - dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT; - - return 0; -} - -int mga_getparam( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_mga_private_t *dev_priv = dev->dev_private; - drm_mga_getparam_t param; - int value; - - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); - return DRM_ERR(EINVAL); - } - - DRM_COPY_FROM_USER_IOCTL( param, (drm_mga_getparam_t __user *)data, - sizeof(param) ); - - DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID ); - - switch( param.param ) { - case MGA_PARAM_IRQ_NR: - value = dev->irq; - break; - default: - return DRM_ERR(EINVAL); - } - - if ( DRM_COPY_TO_USER( param.value, &value, sizeof(int) ) ) { - DRM_ERROR( "copy_to_user\n" ); - return DRM_ERR(EFAULT); - } - - return 0; -} diff --git a/nx-X11/extras/drm/shared/mga_ucode.h b/nx-X11/extras/drm/shared/mga_ucode.h deleted file mode 100644 index fa0f82ec9..000000000 --- a/nx-X11/extras/drm/shared/mga_ucode.h +++ /dev/null @@ -1,11645 +0,0 @@ -/* mga_ucode.h -- Matrox G200/G400 WARP engine microcode -*- linux-c -*- - * Created: Thu Jan 11 21:20:43 2001 by gareth@valinux.com - * - * Copyright 1999 Matrox Graphics Inc. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * MATROX GRAPHICS INC., OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE - * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * Kernel-based WARP engine management: - * Gareth Hughes - */ - -/* - * WARP pipes are named according to the functions they perform, where: - * - * - T stands for computation of texture stage 0 - * - T2 stands for computation of both texture stage 0 and texture stage 1 - * - G stands for computation of triangle intensity (Gouraud interpolation) - * - Z stands for computation of Z buffer interpolation - * - S stands for computation of specular highlight - * - A stands for computation of the alpha channel - * - F stands for computation of vertex fog interpolation - */ - -static unsigned char warp_g200_tgz[] = { - -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, - -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, - 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-0x8B, 0xFF, 0x20, 0xEA, -0x57, 0xC0, 0xBF, 0xEA, - -0x00, 0x80, 0xA0, 0xE9, -0x00, 0x00, 0xD8, 0xEC, - -}; diff --git a/nx-X11/extras/drm/shared/mga_warp.c b/nx-X11/extras/drm/shared/mga_warp.c deleted file mode 100644 index de1b911f8..000000000 --- a/nx-X11/extras/drm/shared/mga_warp.c +++ /dev/null @@ -1,211 +0,0 @@ -/* mga_warp.c -- Matrox G200/G400 WARP engine management -*- linux-c -*- - * Created: Thu Jan 11 21:29:32 2001 by gareth@valinux.com - * - * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Gareth Hughes - */ - -#include "mga.h" -#include "drmP.h" -#include "drm.h" -#include "mga_drm.h" -#include "mga_drv.h" -#include "mga_ucode.h" - - -#define MGA_WARP_CODE_ALIGN 256 /* in bytes */ - -#define WARP_UCODE_SIZE( which ) \ - ((sizeof(which) / MGA_WARP_CODE_ALIGN + 1) * MGA_WARP_CODE_ALIGN) - -#define WARP_UCODE_INSTALL( which, where ) \ -do { \ - DRM_DEBUG( " pcbase = 0x%08lx vcbase = %p\n", pcbase, vcbase );\ - dev_priv->warp_pipe_phys[where] = pcbase; \ - memcpy( vcbase, which, sizeof(which) ); \ - pcbase += WARP_UCODE_SIZE( which ); \ - vcbase += WARP_UCODE_SIZE( which ); \ -} while (0) - - -static unsigned int mga_warp_g400_microcode_size( drm_mga_private_t *dev_priv ) -{ - unsigned int size; - - size = ( WARP_UCODE_SIZE( warp_g400_tgz ) + - WARP_UCODE_SIZE( warp_g400_tgza ) + - WARP_UCODE_SIZE( warp_g400_tgzaf ) + - WARP_UCODE_SIZE( warp_g400_tgzf ) + - WARP_UCODE_SIZE( warp_g400_tgzs ) + - WARP_UCODE_SIZE( warp_g400_tgzsa ) + - WARP_UCODE_SIZE( warp_g400_tgzsaf ) + - WARP_UCODE_SIZE( warp_g400_tgzsf ) + - WARP_UCODE_SIZE( warp_g400_t2gz ) + - WARP_UCODE_SIZE( warp_g400_t2gza ) + - WARP_UCODE_SIZE( warp_g400_t2gzaf ) + - WARP_UCODE_SIZE( warp_g400_t2gzf ) + - WARP_UCODE_SIZE( warp_g400_t2gzs ) + - WARP_UCODE_SIZE( warp_g400_t2gzsa ) + - WARP_UCODE_SIZE( warp_g400_t2gzsaf ) + - WARP_UCODE_SIZE( warp_g400_t2gzsf ) ); - - size = PAGE_ALIGN( size ); - - DRM_DEBUG( "G400 ucode size = %d bytes\n", size ); - return size; -} - -static unsigned int mga_warp_g200_microcode_size( drm_mga_private_t *dev_priv ) -{ - unsigned int size; - - size = ( WARP_UCODE_SIZE( warp_g200_tgz ) + - WARP_UCODE_SIZE( warp_g200_tgza ) + - WARP_UCODE_SIZE( warp_g200_tgzaf ) + - WARP_UCODE_SIZE( warp_g200_tgzf ) + - WARP_UCODE_SIZE( warp_g200_tgzs ) + - WARP_UCODE_SIZE( warp_g200_tgzsa ) + - WARP_UCODE_SIZE( warp_g200_tgzsaf ) + - WARP_UCODE_SIZE( warp_g200_tgzsf ) ); - - size = PAGE_ALIGN( size ); - - DRM_DEBUG( "G200 ucode size = %d bytes\n", size ); - return size; -} - -static int mga_warp_install_g400_microcode( drm_mga_private_t *dev_priv ) -{ - unsigned char *vcbase = dev_priv->warp->handle; - unsigned long pcbase = dev_priv->warp->offset; - unsigned int size; - - size = mga_warp_g400_microcode_size( dev_priv ); - if ( size > dev_priv->warp->size ) { - DRM_ERROR( "microcode too large! (%u > %lu)\n", - size, dev_priv->warp->size ); - return DRM_ERR(ENOMEM); - } - - memset( dev_priv->warp_pipe_phys, 0, - sizeof(dev_priv->warp_pipe_phys) ); - - WARP_UCODE_INSTALL( warp_g400_tgz, MGA_WARP_TGZ ); - WARP_UCODE_INSTALL( warp_g400_tgzf, MGA_WARP_TGZF ); - WARP_UCODE_INSTALL( warp_g400_tgza, MGA_WARP_TGZA ); - WARP_UCODE_INSTALL( warp_g400_tgzaf, MGA_WARP_TGZAF ); - WARP_UCODE_INSTALL( warp_g400_tgzs, MGA_WARP_TGZS ); - WARP_UCODE_INSTALL( warp_g400_tgzsf, MGA_WARP_TGZSF ); - WARP_UCODE_INSTALL( warp_g400_tgzsa, MGA_WARP_TGZSA ); - WARP_UCODE_INSTALL( warp_g400_tgzsaf, MGA_WARP_TGZSAF ); - - WARP_UCODE_INSTALL( warp_g400_t2gz, MGA_WARP_T2GZ ); - WARP_UCODE_INSTALL( warp_g400_t2gzf, MGA_WARP_T2GZF ); - WARP_UCODE_INSTALL( warp_g400_t2gza, MGA_WARP_T2GZA ); - WARP_UCODE_INSTALL( warp_g400_t2gzaf, MGA_WARP_T2GZAF ); - WARP_UCODE_INSTALL( warp_g400_t2gzs, MGA_WARP_T2GZS ); - WARP_UCODE_INSTALL( warp_g400_t2gzsf, MGA_WARP_T2GZSF ); - WARP_UCODE_INSTALL( warp_g400_t2gzsa, MGA_WARP_T2GZSA ); - WARP_UCODE_INSTALL( warp_g400_t2gzsaf, MGA_WARP_T2GZSAF ); - - return 0; -} - -static int mga_warp_install_g200_microcode( drm_mga_private_t *dev_priv ) -{ - unsigned char *vcbase = dev_priv->warp->handle; - unsigned long pcbase = dev_priv->warp->offset; - unsigned int size; - - size = mga_warp_g200_microcode_size( dev_priv ); - if ( size > dev_priv->warp->size ) { - DRM_ERROR( "microcode too large! (%u > %lu)\n", - size, dev_priv->warp->size ); - return DRM_ERR(ENOMEM); - } - - memset( dev_priv->warp_pipe_phys, 0, - sizeof(dev_priv->warp_pipe_phys) ); - - WARP_UCODE_INSTALL( warp_g200_tgz, MGA_WARP_TGZ ); - WARP_UCODE_INSTALL( warp_g200_tgzf, MGA_WARP_TGZF ); - WARP_UCODE_INSTALL( warp_g200_tgza, MGA_WARP_TGZA ); - WARP_UCODE_INSTALL( warp_g200_tgzaf, MGA_WARP_TGZAF ); - WARP_UCODE_INSTALL( warp_g200_tgzs, MGA_WARP_TGZS ); - WARP_UCODE_INSTALL( warp_g200_tgzsf, MGA_WARP_TGZSF ); - WARP_UCODE_INSTALL( warp_g200_tgzsa, MGA_WARP_TGZSA ); - WARP_UCODE_INSTALL( warp_g200_tgzsaf, MGA_WARP_TGZSAF ); - - return 0; -} - -int mga_warp_install_microcode( drm_mga_private_t *dev_priv ) -{ - switch ( dev_priv->chipset ) { - case MGA_CARD_TYPE_G400: - return mga_warp_install_g400_microcode( dev_priv ); - case MGA_CARD_TYPE_G200: - return mga_warp_install_g200_microcode( dev_priv ); - default: - return DRM_ERR(EINVAL); - } -} - -#define WMISC_EXPECTED (MGA_WUCODECACHE_ENABLE | MGA_WMASTER_ENABLE) - -int mga_warp_init( drm_mga_private_t *dev_priv ) -{ - u32 wmisc; - - /* FIXME: Get rid of these damned magic numbers... - */ - switch ( dev_priv->chipset ) { - case MGA_CARD_TYPE_G400: - MGA_WRITE( MGA_WIADDR2, MGA_WMODE_SUSPEND ); - MGA_WRITE( MGA_WGETMSB, 0x00000E00 ); - MGA_WRITE( MGA_WVRTXSZ, 0x00001807 ); - MGA_WRITE( MGA_WACCEPTSEQ, 0x18000000 ); - break; - case MGA_CARD_TYPE_G200: - MGA_WRITE( MGA_WIADDR, MGA_WMODE_SUSPEND ); - MGA_WRITE( MGA_WGETMSB, 0x1606 ); - MGA_WRITE( MGA_WVRTXSZ, 7 ); - break; - default: - return DRM_ERR(EINVAL); - } - - MGA_WRITE( MGA_WMISC, (MGA_WUCODECACHE_ENABLE | - MGA_WMASTER_ENABLE | - MGA_WCACHEFLUSH_ENABLE) ); - wmisc = MGA_READ( MGA_WMISC ); - if ( wmisc != WMISC_EXPECTED ) { - DRM_ERROR( "WARP engine config failed! 0x%x != 0x%x\n", - wmisc, WMISC_EXPECTED ); - return DRM_ERR(EINVAL); - } - - return 0; -} diff --git a/nx-X11/extras/drm/shared/r128.h b/nx-X11/extras/drm/shared/r128.h deleted file mode 100644 index 1df7042a2..000000000 --- a/nx-X11/extras/drm/shared/r128.h +++ /dev/null @@ -1,75 +0,0 @@ -/* r128.h -- ATI Rage 128 DRM template customization -*- linux-c -*- - * Created: Wed Feb 14 16:07:10 2001 by gareth@valinux.com - * - * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Gareth Hughes - */ - -#ifndef __R128_H__ -#define __R128_H__ - -/* This remains constant for all DRM template files. - */ -#define DRM(x) r128_##x - -/* General customization: - */ -#define DRIVER_AUTHOR "Gareth Hughes, VA Linux Systems Inc." - -#define DRIVER_NAME "r128" -#define DRIVER_DESC "ATI Rage 128" -#define DRIVER_DATE "20030725" - -#define DRIVER_MAJOR 2 -#define DRIVER_MINOR 5 -#define DRIVER_PATCHLEVEL 0 - -/* Interface history: - * - * ?? - ?? - * 2.4 - Add support for ycbcr textures (no new ioctls) - * 2.5 - Add FLIP ioctl, disable FULLSCREEN. - */ -#define DRIVER_IOCTLS \ - [DRM_IOCTL_NR(DRM_IOCTL_DMA)] = { r128_cce_buffers, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_R128_INIT)] = { r128_cce_init, 1, 1 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_R128_CCE_START)] = { r128_cce_start, 1, 1 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_R128_CCE_STOP)] = { r128_cce_stop, 1, 1 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_R128_CCE_RESET)] = { r128_cce_reset, 1, 1 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_R128_CCE_IDLE)] = { r128_cce_idle, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_R128_RESET)] = { r128_engine_reset, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_R128_FULLSCREEN)] = { r128_fullscreen, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_R128_SWAP)] = { r128_cce_swap, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_R128_FLIP)] = { r128_cce_flip, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_R128_CLEAR)] = { r128_cce_clear, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_R128_VERTEX)] = { r128_cce_vertex, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_R128_INDICES)] = { r128_cce_indices, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_R128_BLIT)] = { r128_cce_blit, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_R128_DEPTH)] = { r128_cce_depth, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_R128_STIPPLE)] = { r128_cce_stipple, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_R128_INDIRECT)] = { r128_cce_indirect, 1, 1 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_R128_GETPARAM)] = { r128_getparam, 1, 0 }, - -#endif diff --git a/nx-X11/extras/drm/shared/r128_cce.c b/nx-X11/extras/drm/shared/r128_cce.c deleted file mode 100644 index 64c9b8be7..000000000 --- a/nx-X11/extras/drm/shared/r128_cce.c +++ /dev/null @@ -1,946 +0,0 @@ -/* r128_cce.c -- ATI Rage 128 driver -*- linux-c -*- - * Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com - * - * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. - * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Gareth Hughes - */ - -#include "r128.h" -#include "drmP.h" -#include "drm.h" -#include "r128_drm.h" -#include "r128_drv.h" - -#define R128_FIFO_DEBUG 0 - -/* CCE microcode (from ATI) */ -static u32 r128_cce_microcode[] = { - 0, 276838400, 0, 268449792, 2, 142, 2, 145, 0, 1076765731, 0, - 1617039951, 0, 774592877, 0, 1987540286, 0, 2307490946U, 0, - 599558925, 0, 589505315, 0, 596487092, 0, 589505315, 1, - 11544576, 1, 206848, 1, 311296, 1, 198656, 2, 912273422, 11, - 262144, 0, 0, 1, 33559837, 1, 7438, 1, 14809, 1, 6615, 12, 28, - 1, 6614, 12, 28, 2, 23, 11, 18874368, 0, 16790922, 1, 409600, 9, - 30, 1, 147854772, 16, 420483072, 3, 8192, 0, 10240, 1, 198656, - 1, 15630, 1, 51200, 10, 34858, 9, 42, 1, 33559823, 2, 10276, 1, - 15717, 1, 15718, 2, 43, 1, 15936948, 1, 570480831, 1, 14715071, - 12, 322123831, 1, 33953125, 12, 55, 1, 33559908, 1, 15718, 2, - 46, 4, 2099258, 1, 526336, 1, 442623, 4, 4194365, 1, 509952, 1, - 459007, 3, 0, 12, 92, 2, 46, 12, 176, 1, 15734, 1, 206848, 1, - 18432, 1, 133120, 1, 100670734, 1, 149504, 1, 165888, 1, - 15975928, 1, 1048576, 6, 3145806, 1, 15715, 16, 2150645232U, 2, - 268449859, 2, 10307, 12, 176, 1, 15734, 1, 15735, 1, 15630, 1, - 15631, 1, 5253120, 6, 3145810, 16, 2150645232U, 1, 15864, 2, 82, - 1, 343310, 1, 1064207, 2, 3145813, 1, 15728, 1, 7817, 1, 15729, - 3, 15730, 12, 92, 2, 98, 1, 16168, 1, 16167, 1, 16002, 1, 16008, - 1, 15974, 1, 15975, 1, 15990, 1, 15976, 1, 15977, 1, 15980, 0, - 15981, 1, 10240, 1, 5253120, 1, 15720, 1, 198656, 6, 110, 1, - 180224, 1, 103824738, 2, 112, 2, 3145839, 0, 536885440, 1, - 114880, 14, 125, 12, 206975, 1, 33559995, 12, 198784, 0, - 33570236, 1, 15803, 0, 15804, 3, 294912, 1, 294912, 3, 442370, - 1, 11544576, 0, 811612160, 1, 12593152, 1, 11536384, 1, - 14024704, 7, 310382726, 0, 10240, 1, 14796, 1, 14797, 1, 14793, - 1, 14794, 0, 14795, 1, 268679168, 1, 9437184, 1, 268449792, 1, - 198656, 1, 9452827, 1, 1075854602, 1, 1075854603, 1, 557056, 1, - 114880, 14, 159, 12, 198784, 1, 1109409213, 12, 198783, 1, - 1107312059, 12, 198784, 1, 1109409212, 2, 162, 1, 1075854781, 1, - 1073757627, 1, 1075854780, 1, 540672, 1, 10485760, 6, 3145894, - 16, 274741248, 9, 168, 3, 4194304, 3, 4209949, 0, 0, 0, 256, 14, - 174, 1, 114857, 1, 33560007, 12, 176, 0, 10240, 1, 114858, 1, - 33560018, 1, 114857, 3, 33560007, 1, 16008, 1, 114874, 1, - 33560360, 1, 114875, 1, 33560154, 0, 15963, 0, 256, 0, 4096, 1, - 409611, 9, 188, 0, 10240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -}; - -int R128_READ_PLL(drm_device_t *dev, int addr) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - - R128_WRITE8(R128_CLOCK_CNTL_INDEX, addr & 0x1f); - return R128_READ(R128_CLOCK_CNTL_DATA); -} - -#if R128_FIFO_DEBUG -static void r128_status( drm_r128_private_t *dev_priv ) -{ - printk( "GUI_STAT = 0x%08x\n", - (unsigned int)R128_READ( R128_GUI_STAT ) ); - printk( "PM4_STAT = 0x%08x\n", - (unsigned int)R128_READ( R128_PM4_STAT ) ); - printk( "PM4_BUFFER_DL_WPTR = 0x%08x\n", - (unsigned int)R128_READ( R128_PM4_BUFFER_DL_WPTR ) ); - printk( "PM4_BUFFER_DL_RPTR = 0x%08x\n", - (unsigned int)R128_READ( R128_PM4_BUFFER_DL_RPTR ) ); - printk( "PM4_MICRO_CNTL = 0x%08x\n", - (unsigned int)R128_READ( R128_PM4_MICRO_CNTL ) ); - printk( "PM4_BUFFER_CNTL = 0x%08x\n", - (unsigned int)R128_READ( R128_PM4_BUFFER_CNTL ) ); -} -#endif - - -/* ================================================================ - * Engine, FIFO control - */ - -static int r128_do_pixcache_flush( drm_r128_private_t *dev_priv ) -{ - u32 tmp; - int i; - - tmp = R128_READ( R128_PC_NGUI_CTLSTAT ) | R128_PC_FLUSH_ALL; - R128_WRITE( R128_PC_NGUI_CTLSTAT, tmp ); - - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - if ( !(R128_READ( R128_PC_NGUI_CTLSTAT ) & R128_PC_BUSY) ) { - return 0; - } - DRM_UDELAY( 1 ); - } - -#if R128_FIFO_DEBUG - DRM_ERROR( "failed!\n" ); -#endif - return DRM_ERR(EBUSY); -} - -static int r128_do_wait_for_fifo( drm_r128_private_t *dev_priv, int entries ) -{ - int i; - - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - int slots = R128_READ( R128_GUI_STAT ) & R128_GUI_FIFOCNT_MASK; - if ( slots >= entries ) return 0; - DRM_UDELAY( 1 ); - } - -#if R128_FIFO_DEBUG - DRM_ERROR( "failed!\n" ); -#endif - return DRM_ERR(EBUSY); -} - -static int r128_do_wait_for_idle( drm_r128_private_t *dev_priv ) -{ - int i, ret; - - ret = r128_do_wait_for_fifo( dev_priv, 64 ); - if ( ret ) return ret; - - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - if ( !(R128_READ( R128_GUI_STAT ) & R128_GUI_ACTIVE) ) { - r128_do_pixcache_flush( dev_priv ); - return 0; - } - DRM_UDELAY( 1 ); - } - -#if R128_FIFO_DEBUG - DRM_ERROR( "failed!\n" ); -#endif - return DRM_ERR(EBUSY); -} - - -/* ================================================================ - * CCE control, initialization - */ - -/* Load the microcode for the CCE */ -static void r128_cce_load_microcode( drm_r128_private_t *dev_priv ) -{ - int i; - - DRM_DEBUG( "\n" ); - - r128_do_wait_for_idle( dev_priv ); - - R128_WRITE( R128_PM4_MICROCODE_ADDR, 0 ); - for ( i = 0 ; i < 256 ; i++ ) { - R128_WRITE( R128_PM4_MICROCODE_DATAH, - r128_cce_microcode[i * 2] ); - R128_WRITE( R128_PM4_MICROCODE_DATAL, - r128_cce_microcode[i * 2 + 1] ); - } -} - -/* Flush any pending commands to the CCE. This should only be used just - * prior to a wait for idle, as it informs the engine that the command - * stream is ending. - */ -static void r128_do_cce_flush( drm_r128_private_t *dev_priv ) -{ - u32 tmp; - - tmp = R128_READ( R128_PM4_BUFFER_DL_WPTR ) | R128_PM4_BUFFER_DL_DONE; - R128_WRITE( R128_PM4_BUFFER_DL_WPTR, tmp ); -} - -/* Wait for the CCE to go idle. - */ -int r128_do_cce_idle( drm_r128_private_t *dev_priv ) -{ - int i; - - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - if ( GET_RING_HEAD( dev_priv ) == dev_priv->ring.tail ) { - int pm4stat = R128_READ( R128_PM4_STAT ); - if ( ( (pm4stat & R128_PM4_FIFOCNT_MASK) >= - dev_priv->cce_fifo_size ) && - !(pm4stat & (R128_PM4_BUSY | - R128_PM4_GUI_ACTIVE)) ) { - return r128_do_pixcache_flush( dev_priv ); - } - } - DRM_UDELAY( 1 ); - } - -#if R128_FIFO_DEBUG - DRM_ERROR( "failed!\n" ); - r128_status( dev_priv ); -#endif - return DRM_ERR(EBUSY); -} - -/* Start the Concurrent Command Engine. - */ -static void r128_do_cce_start( drm_r128_private_t *dev_priv ) -{ - r128_do_wait_for_idle( dev_priv ); - - R128_WRITE( R128_PM4_BUFFER_CNTL, - dev_priv->cce_mode | dev_priv->ring.size_l2qw - | R128_PM4_BUFFER_CNTL_NOUPDATE ); - R128_READ( R128_PM4_BUFFER_ADDR ); /* as per the sample code */ - R128_WRITE( R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN ); - - dev_priv->cce_running = 1; -} - -/* Reset the Concurrent Command Engine. This will not flush any pending - * commands, so you must wait for the CCE command stream to complete - * before calling this routine. - */ -static void r128_do_cce_reset( drm_r128_private_t *dev_priv ) -{ - R128_WRITE( R128_PM4_BUFFER_DL_WPTR, 0 ); - R128_WRITE( R128_PM4_BUFFER_DL_RPTR, 0 ); - dev_priv->ring.tail = 0; -} - -/* Stop the Concurrent Command Engine. This will not flush any pending - * commands, so you must flush the command stream and wait for the CCE - * to go idle before calling this routine. - */ -static void r128_do_cce_stop( drm_r128_private_t *dev_priv ) -{ - R128_WRITE( R128_PM4_MICRO_CNTL, 0 ); - R128_WRITE( R128_PM4_BUFFER_CNTL, - R128_PM4_NONPM4 | R128_PM4_BUFFER_CNTL_NOUPDATE ); - - dev_priv->cce_running = 0; -} - -/* Reset the engine. This will stop the CCE if it is running. - */ -static int r128_do_engine_reset( drm_device_t *dev ) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - u32 clock_cntl_index, mclk_cntl, gen_reset_cntl; - - r128_do_pixcache_flush( dev_priv ); - - clock_cntl_index = R128_READ( R128_CLOCK_CNTL_INDEX ); - mclk_cntl = R128_READ_PLL( dev, R128_MCLK_CNTL ); - - R128_WRITE_PLL( R128_MCLK_CNTL, - mclk_cntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CP ); - - gen_reset_cntl = R128_READ( R128_GEN_RESET_CNTL ); - - /* Taken from the sample code - do not change */ - R128_WRITE( R128_GEN_RESET_CNTL, - gen_reset_cntl | R128_SOFT_RESET_GUI ); - R128_READ( R128_GEN_RESET_CNTL ); - R128_WRITE( R128_GEN_RESET_CNTL, - gen_reset_cntl & ~R128_SOFT_RESET_GUI ); - R128_READ( R128_GEN_RESET_CNTL ); - - R128_WRITE_PLL( R128_MCLK_CNTL, mclk_cntl ); - R128_WRITE( R128_CLOCK_CNTL_INDEX, clock_cntl_index ); - R128_WRITE( R128_GEN_RESET_CNTL, gen_reset_cntl ); - - /* Reset the CCE ring */ - r128_do_cce_reset( dev_priv ); - - /* The CCE is no longer running after an engine reset */ - dev_priv->cce_running = 0; - - /* Reset any pending vertex, indirect buffers */ - r128_freelist_reset( dev ); - - return 0; -} - -static void r128_cce_init_ring_buffer( drm_device_t *dev, - drm_r128_private_t *dev_priv ) -{ - u32 ring_start; - u32 tmp; - - DRM_DEBUG( "\n" ); - - /* The manual (p. 2) says this address is in "VM space". This - * means it's an offset from the start of AGP space. - */ -#if __OS_HAS_AGP - if ( !dev_priv->is_pci ) - ring_start = dev_priv->cce_ring->offset - dev->agp->base; - else -#endif - ring_start = dev_priv->cce_ring->offset - dev->sg->handle; - - R128_WRITE( R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET ); - - R128_WRITE( R128_PM4_BUFFER_DL_WPTR, 0 ); - R128_WRITE( R128_PM4_BUFFER_DL_RPTR, 0 ); - - /* Set watermark control */ - R128_WRITE( R128_PM4_BUFFER_WM_CNTL, - ((R128_WATERMARK_L/4) << R128_WMA_SHIFT) - | ((R128_WATERMARK_M/4) << R128_WMB_SHIFT) - | ((R128_WATERMARK_N/4) << R128_WMC_SHIFT) - | ((R128_WATERMARK_K/64) << R128_WB_WM_SHIFT) ); - - /* Force read. Why? Because it's in the examples... */ - R128_READ( R128_PM4_BUFFER_ADDR ); - - /* Turn on bus mastering */ - tmp = R128_READ( R128_BUS_CNTL ) & ~R128_BUS_MASTER_DIS; - R128_WRITE( R128_BUS_CNTL, tmp ); -} - -static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init ) -{ - drm_r128_private_t *dev_priv; - - DRM_DEBUG( "\n" ); - - dev_priv = DRM(alloc)( sizeof(drm_r128_private_t), DRM_MEM_DRIVER ); - if ( dev_priv == NULL ) - return DRM_ERR(ENOMEM); - - memset( dev_priv, 0, sizeof(drm_r128_private_t) ); - - dev_priv->is_pci = init->is_pci; - - if ( dev_priv->is_pci && !dev->sg ) { - DRM_ERROR( "PCI GART memory not allocated!\n" ); - dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); - return DRM_ERR(EINVAL); - } - - dev_priv->usec_timeout = init->usec_timeout; - if ( dev_priv->usec_timeout < 1 || - dev_priv->usec_timeout > R128_MAX_USEC_TIMEOUT ) { - DRM_DEBUG( "TIMEOUT problem!\n" ); - dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); - return DRM_ERR(EINVAL); - } - - dev_priv->cce_mode = init->cce_mode; - - /* GH: Simple idle check. - */ - atomic_set( &dev_priv->idle_count, 0 ); - - /* We don't support anything other than bus-mastering ring mode, - * but the ring can be in either AGP or PCI space for the ring - * read pointer. - */ - if ( ( init->cce_mode != R128_PM4_192BM ) && - ( init->cce_mode != R128_PM4_128BM_64INDBM ) && - ( init->cce_mode != R128_PM4_64BM_128INDBM ) && - ( init->cce_mode != R128_PM4_64BM_64VCBM_64INDBM ) ) { - DRM_DEBUG( "Bad cce_mode!\n" ); - dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); - return DRM_ERR(EINVAL); - } - - switch ( init->cce_mode ) { - case R128_PM4_NONPM4: - dev_priv->cce_fifo_size = 0; - break; - case R128_PM4_192PIO: - case R128_PM4_192BM: - dev_priv->cce_fifo_size = 192; - break; - case R128_PM4_128PIO_64INDBM: - case R128_PM4_128BM_64INDBM: - dev_priv->cce_fifo_size = 128; - break; - case R128_PM4_64PIO_128INDBM: - case R128_PM4_64BM_128INDBM: - case R128_PM4_64PIO_64VCBM_64INDBM: - case R128_PM4_64BM_64VCBM_64INDBM: - case R128_PM4_64PIO_64VCPIO_64INDPIO: - dev_priv->cce_fifo_size = 64; - break; - } - - switch ( init->fb_bpp ) { - case 16: - dev_priv->color_fmt = R128_DATATYPE_RGB565; - break; - case 32: - default: - dev_priv->color_fmt = R128_DATATYPE_ARGB8888; - break; - } - dev_priv->front_offset = init->front_offset; - dev_priv->front_pitch = init->front_pitch; - dev_priv->back_offset = init->back_offset; - dev_priv->back_pitch = init->back_pitch; - - switch ( init->depth_bpp ) { - case 16: - dev_priv->depth_fmt = R128_DATATYPE_RGB565; - break; - case 24: - case 32: - default: - dev_priv->depth_fmt = R128_DATATYPE_ARGB8888; - break; - } - dev_priv->depth_offset = init->depth_offset; - dev_priv->depth_pitch = init->depth_pitch; - dev_priv->span_offset = init->span_offset; - - dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch/8) << 21) | - (dev_priv->front_offset >> 5)); - dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch/8) << 21) | - (dev_priv->back_offset >> 5)); - dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch/8) << 21) | - (dev_priv->depth_offset >> 5) | - R128_DST_TILE); - dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch/8) << 21) | - (dev_priv->span_offset >> 5)); - - DRM_GETSAREA(); - - if(!dev_priv->sarea) { - DRM_ERROR("could not find sarea!\n"); - dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); - return DRM_ERR(EINVAL); - } - - dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset); - if(!dev_priv->mmio) { - DRM_ERROR("could not find mmio region!\n"); - dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); - return DRM_ERR(EINVAL); - } - dev_priv->cce_ring = drm_core_findmap(dev, init->ring_offset); - if(!dev_priv->cce_ring) { - DRM_ERROR("could not find cce ring region!\n"); - dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); - return DRM_ERR(EINVAL); - } - dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); - if(!dev_priv->ring_rptr) { - DRM_ERROR("could not find ring read pointer!\n"); - dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); - return DRM_ERR(EINVAL); - } - dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); - if(!dev->agp_buffer_map) { - DRM_ERROR("could not find dma buffer region!\n"); - dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); - return DRM_ERR(EINVAL); - } - - if ( !dev_priv->is_pci ) { - dev_priv->agp_textures = drm_core_findmap(dev, init->agp_textures_offset); - if(!dev_priv->agp_textures) { - DRM_ERROR("could not find agp texture region!\n"); - dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); - return DRM_ERR(EINVAL); - } - } - - dev_priv->sarea_priv = - (drm_r128_sarea_t *)((u8 *)dev_priv->sarea->handle + - init->sarea_priv_offset); - -#if __OS_HAS_AGP - if ( !dev_priv->is_pci ) { - drm_core_ioremap( dev_priv->cce_ring, dev ); - drm_core_ioremap( dev_priv->ring_rptr, dev ); - drm_core_ioremap( dev->agp_buffer_map, dev ); - if(!dev_priv->cce_ring->handle || - !dev_priv->ring_rptr->handle || - !dev->agp_buffer_map->handle) { - DRM_ERROR("Could not ioremap agp regions!\n"); - dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); - return DRM_ERR(ENOMEM); - } - } else -#endif - { - dev_priv->cce_ring->handle = - (void *)dev_priv->cce_ring->offset; - dev_priv->ring_rptr->handle = - (void *)dev_priv->ring_rptr->offset; - dev->agp_buffer_map->handle = (void *)dev->agp_buffer_map->offset; - } - -#if __OS_HAS_AGP - if ( !dev_priv->is_pci ) - dev_priv->cce_buffers_offset = dev->agp->base; - else -#endif - dev_priv->cce_buffers_offset = dev->sg->handle; - - dev_priv->ring.start = (u32 *)dev_priv->cce_ring->handle; - dev_priv->ring.end = ((u32 *)dev_priv->cce_ring->handle - + init->ring_size / sizeof(u32)); - dev_priv->ring.size = init->ring_size; - dev_priv->ring.size_l2qw = DRM(order)( init->ring_size / 8 ); - - dev_priv->ring.tail_mask = - (dev_priv->ring.size / sizeof(u32)) - 1; - - dev_priv->ring.high_mark = 128; - - dev_priv->sarea_priv->last_frame = 0; - R128_WRITE( R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame ); - - dev_priv->sarea_priv->last_dispatch = 0; - R128_WRITE( R128_LAST_DISPATCH_REG, - dev_priv->sarea_priv->last_dispatch ); - -#if __OS_HAS_AGP - if ( dev_priv->is_pci ) { -#endif - if (!DRM(ati_pcigart_init)( dev, &dev_priv->phys_pci_gart, - &dev_priv->bus_pci_gart) ) { - DRM_ERROR( "failed to init PCI GART!\n" ); - dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); - return DRM_ERR(ENOMEM); - } - R128_WRITE( R128_PCI_GART_PAGE, dev_priv->bus_pci_gart ); -#if __OS_HAS_AGP - } -#endif - - r128_cce_init_ring_buffer( dev, dev_priv ); - r128_cce_load_microcode( dev_priv ); - - dev->dev_private = (void *)dev_priv; - - r128_do_engine_reset( dev ); - - return 0; -} - -int r128_do_cleanup_cce( drm_device_t *dev ) -{ - - /* Make sure interrupts are disabled here because the uninstall ioctl - * may not have been called from userspace and after dev_private - * is freed, it's too late. - */ - if ( dev->irq_enabled ) DRM(irq_uninstall)(dev); - - if ( dev->dev_private ) { - drm_r128_private_t *dev_priv = dev->dev_private; - -#if __OS_HAS_AGP - if ( !dev_priv->is_pci ) { - if ( dev_priv->cce_ring != NULL ) - drm_core_ioremapfree( dev_priv->cce_ring, dev ); - if ( dev_priv->ring_rptr != NULL ) - drm_core_ioremapfree( dev_priv->ring_rptr, dev ); - if ( dev->agp_buffer_map != NULL ) { - drm_core_ioremapfree( dev->agp_buffer_map, dev ); - dev->agp_buffer_map = NULL; - } - } else -#endif - { - if (!DRM(ati_pcigart_cleanup)( dev, - dev_priv->phys_pci_gart, - dev_priv->bus_pci_gart )) - DRM_ERROR( "failed to cleanup PCI GART!\n" ); - } - - DRM(free)( dev->dev_private, sizeof(drm_r128_private_t), - DRM_MEM_DRIVER ); - dev->dev_private = NULL; - } - - return 0; -} - -int r128_cce_init( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_r128_init_t init; - - DRM_DEBUG( "\n" ); - - LOCK_TEST_WITH_RETURN( dev, filp ); - - DRM_COPY_FROM_USER_IOCTL( init, (drm_r128_init_t __user *)data, sizeof(init) ); - - switch ( init.func ) { - case R128_INIT_CCE: - return r128_do_init_cce( dev, &init ); - case R128_CLEANUP_CCE: - return r128_do_cleanup_cce( dev ); - } - - return DRM_ERR(EINVAL); -} - -int r128_cce_start( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_r128_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "\n" ); - - LOCK_TEST_WITH_RETURN( dev, filp ); - - if ( dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4 ) { - DRM_DEBUG( "%s while CCE running\n", __FUNCTION__ ); - return 0; - } - - r128_do_cce_start( dev_priv ); - - return 0; -} - -/* Stop the CCE. The engine must have been idled before calling this - * routine. - */ -int r128_cce_stop( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_cce_stop_t stop; - int ret; - DRM_DEBUG( "\n" ); - - LOCK_TEST_WITH_RETURN( dev, filp ); - - DRM_COPY_FROM_USER_IOCTL(stop, (drm_r128_cce_stop_t __user *)data, sizeof(stop) ); - - /* Flush any pending CCE commands. This ensures any outstanding - * commands are exectuted by the engine before we turn it off. - */ - if ( stop.flush ) { - r128_do_cce_flush( dev_priv ); - } - - /* If we fail to make the engine go idle, we return an error - * code so that the DRM ioctl wrapper can try again. - */ - if ( stop.idle ) { - ret = r128_do_cce_idle( dev_priv ); - if ( ret ) return ret; - } - - /* Finally, we can turn off the CCE. If the engine isn't idle, - * we will get some dropped triangles as they won't be fully - * rendered before the CCE is shut down. - */ - r128_do_cce_stop( dev_priv ); - - /* Reset the engine */ - r128_do_engine_reset( dev ); - - return 0; -} - -/* Just reset the CCE ring. Called as part of an X Server engine reset. - */ -int r128_cce_reset( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_r128_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "\n" ); - - LOCK_TEST_WITH_RETURN( dev, filp ); - - if ( !dev_priv ) { - DRM_DEBUG( "%s called before init done\n", __FUNCTION__ ); - return DRM_ERR(EINVAL); - } - - r128_do_cce_reset( dev_priv ); - - /* The CCE is no longer running after an engine reset */ - dev_priv->cce_running = 0; - - return 0; -} - -int r128_cce_idle( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_r128_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "\n" ); - - LOCK_TEST_WITH_RETURN( dev, filp ); - - if ( dev_priv->cce_running ) { - r128_do_cce_flush( dev_priv ); - } - - return r128_do_cce_idle( dev_priv ); -} - -int r128_engine_reset( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - DRM_DEBUG( "\n" ); - - LOCK_TEST_WITH_RETURN( dev, filp ); - - return r128_do_engine_reset( dev ); -} - -int r128_fullscreen( DRM_IOCTL_ARGS ) -{ - return DRM_ERR(EINVAL); -} - - -/* ================================================================ - * Freelist management - */ -#define R128_BUFFER_USED 0xffffffff -#define R128_BUFFER_FREE 0 - -#if 0 -static int r128_freelist_init( drm_device_t *dev ) -{ - drm_device_dma_t *dma = dev->dma; - drm_r128_private_t *dev_priv = dev->dev_private; - drm_buf_t *buf; - drm_r128_buf_priv_t *buf_priv; - drm_r128_freelist_t *entry; - int i; - - dev_priv->head = DRM(alloc)( sizeof(drm_r128_freelist_t), - DRM_MEM_DRIVER ); - if ( dev_priv->head == NULL ) - return DRM_ERR(ENOMEM); - - memset( dev_priv->head, 0, sizeof(drm_r128_freelist_t) ); - dev_priv->head->age = R128_BUFFER_USED; - - for ( i = 0 ; i < dma->buf_count ; i++ ) { - buf = dma->buflist[i]; - buf_priv = buf->dev_private; - - entry = DRM(alloc)( sizeof(drm_r128_freelist_t), - DRM_MEM_DRIVER ); - if ( !entry ) return DRM_ERR(ENOMEM); - - entry->age = R128_BUFFER_FREE; - entry->buf = buf; - entry->prev = dev_priv->head; - entry->next = dev_priv->head->next; - if ( !entry->next ) - dev_priv->tail = entry; - - buf_priv->discard = 0; - buf_priv->dispatched = 0; - buf_priv->list_entry = entry; - - dev_priv->head->next = entry; - - if ( dev_priv->head->next ) - dev_priv->head->next->prev = entry; - } - - return 0; - -} -#endif - -drm_buf_t *r128_freelist_get( drm_device_t *dev ) -{ - drm_device_dma_t *dma = dev->dma; - drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_buf_priv_t *buf_priv; - drm_buf_t *buf; - int i, t; - - /* FIXME: Optimize -- use freelist code */ - - for ( i = 0 ; i < dma->buf_count ; i++ ) { - buf = dma->buflist[i]; - buf_priv = buf->dev_private; - if ( buf->filp == 0 ) - return buf; - } - - for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) { - u32 done_age = R128_READ( R128_LAST_DISPATCH_REG ); - - for ( i = 0 ; i < dma->buf_count ; i++ ) { - buf = dma->buflist[i]; - buf_priv = buf->dev_private; - if ( buf->pending && buf_priv->age <= done_age ) { - /* The buffer has been processed, so it - * can now be used. - */ - buf->pending = 0; - return buf; - } - } - DRM_UDELAY( 1 ); - } - - DRM_DEBUG( "returning NULL!\n" ); - return NULL; -} - -void r128_freelist_reset( drm_device_t *dev ) -{ - drm_device_dma_t *dma = dev->dma; - int i; - - for ( i = 0 ; i < dma->buf_count ; i++ ) { - drm_buf_t *buf = dma->buflist[i]; - drm_r128_buf_priv_t *buf_priv = buf->dev_private; - buf_priv->age = 0; - } -} - - -/* ================================================================ - * CCE command submission - */ - -int r128_wait_ring( drm_r128_private_t *dev_priv, int n ) -{ - drm_r128_ring_buffer_t *ring = &dev_priv->ring; - int i; - - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - r128_update_ring_snapshot( dev_priv ); - if ( ring->space >= n ) - return 0; - DRM_UDELAY( 1 ); - } - - /* FIXME: This is being ignored... */ - DRM_ERROR( "failed!\n" ); - return DRM_ERR(EBUSY); -} - -static int r128_cce_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d ) -{ - int i; - drm_buf_t *buf; - - for ( i = d->granted_count ; i < d->request_count ; i++ ) { - buf = r128_freelist_get( dev ); - if ( !buf ) return DRM_ERR(EAGAIN); - - buf->filp = filp; - - if ( DRM_COPY_TO_USER( &d->request_indices[i], &buf->idx, - sizeof(buf->idx) ) ) - return DRM_ERR(EFAULT); - if ( DRM_COPY_TO_USER( &d->request_sizes[i], &buf->total, - sizeof(buf->total) ) ) - return DRM_ERR(EFAULT); - - d->granted_count++; - } - return 0; -} - -int r128_cce_buffers( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_device_dma_t *dma = dev->dma; - int ret = 0; - drm_dma_t __user *argp = (void __user *)data; - drm_dma_t d; - - LOCK_TEST_WITH_RETURN( dev, filp ); - - DRM_COPY_FROM_USER_IOCTL( d, argp, sizeof(d) ); - - /* Please don't send us buffers. - */ - if ( d.send_count != 0 ) { - DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n", - DRM_CURRENTPID, d.send_count ); - return DRM_ERR(EINVAL); - } - - /* We'll send you buffers. - */ - if ( d.request_count < 0 || d.request_count > dma->buf_count ) { - DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n", - DRM_CURRENTPID, d.request_count, dma->buf_count ); - return DRM_ERR(EINVAL); - } - - d.granted_count = 0; - - if ( d.request_count ) { - ret = r128_cce_get_buffers( filp, dev, &d ); - } - - DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d) ); - - return ret; -} diff --git a/nx-X11/extras/drm/shared/r128_drm.h b/nx-X11/extras/drm/shared/r128_drm.h deleted file mode 100644 index 0cba17d1e..000000000 --- a/nx-X11/extras/drm/shared/r128_drm.h +++ /dev/null @@ -1,345 +0,0 @@ -/* r128_drm.h -- Public header for the r128 driver -*- linux-c -*- - * Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com - * - * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. - * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. - * All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Gareth Hughes - * Kevin E. Martin - */ - -#ifndef __R128_DRM_H__ -#define __R128_DRM_H__ - -/* WARNING: If you change any of these defines, make sure to change the - * defines in the X server file (r128_sarea.h) - */ -#ifndef __R128_SAREA_DEFINES__ -#define __R128_SAREA_DEFINES__ - -/* What needs to be changed for the current vertex buffer? - */ -#define R128_UPLOAD_CONTEXT 0x001 -#define R128_UPLOAD_SETUP 0x002 -#define R128_UPLOAD_TEX0 0x004 -#define R128_UPLOAD_TEX1 0x008 -#define R128_UPLOAD_TEX0IMAGES 0x010 -#define R128_UPLOAD_TEX1IMAGES 0x020 -#define R128_UPLOAD_CORE 0x040 -#define R128_UPLOAD_MASKS 0x080 -#define R128_UPLOAD_WINDOW 0x100 -#define R128_UPLOAD_CLIPRECTS 0x200 /* handled client-side */ -#define R128_REQUIRE_QUIESCENCE 0x400 -#define R128_UPLOAD_ALL 0x7ff - -#define R128_FRONT 0x1 -#define R128_BACK 0x2 -#define R128_DEPTH 0x4 - -/* Primitive types - */ -#define R128_POINTS 0x1 -#define R128_LINES 0x2 -#define R128_LINE_STRIP 0x3 -#define R128_TRIANGLES 0x4 -#define R128_TRIANGLE_FAN 0x5 -#define R128_TRIANGLE_STRIP 0x6 - -/* Vertex/indirect buffer size - */ -#define R128_BUFFER_SIZE 16384 - -/* Byte offsets for indirect buffer data - */ -#define R128_INDEX_PRIM_OFFSET 20 -#define R128_HOSTDATA_BLIT_OFFSET 32 - -/* Keep these small for testing. - */ -#define R128_NR_SAREA_CLIPRECTS 12 - -/* There are 2 heaps (local/AGP). Each region within a heap is a - * minimum of 64k, and there are at most 64 of them per heap. - */ -#define R128_LOCAL_TEX_HEAP 0 -#define R128_AGP_TEX_HEAP 1 -#define R128_NR_TEX_HEAPS 2 -#define R128_NR_TEX_REGIONS 64 -#define R128_LOG_TEX_GRANULARITY 16 - -#define R128_NR_CONTEXT_REGS 12 - -#define R128_MAX_TEXTURE_LEVELS 11 -#define R128_MAX_TEXTURE_UNITS 2 - -#endif /* __R128_SAREA_DEFINES__ */ - -typedef struct { - /* Context state - can be written in one large chunk */ - unsigned int dst_pitch_offset_c; - unsigned int dp_gui_master_cntl_c; - unsigned int sc_top_left_c; - unsigned int sc_bottom_right_c; - unsigned int z_offset_c; - unsigned int z_pitch_c; - unsigned int z_sten_cntl_c; - unsigned int tex_cntl_c; - unsigned int misc_3d_state_cntl_reg; - unsigned int texture_clr_cmp_clr_c; - unsigned int texture_clr_cmp_msk_c; - unsigned int fog_color_c; - - /* Texture state */ - unsigned int tex_size_pitch_c; - unsigned int constant_color_c; - - /* Setup state */ - unsigned int pm4_vc_fpu_setup; - unsigned int setup_cntl; - - /* Mask state */ - unsigned int dp_write_mask; - unsigned int sten_ref_mask_c; - unsigned int plane_3d_mask_c; - - /* Window state */ - unsigned int window_xy_offset; - - /* Core state */ - unsigned int scale_3d_cntl; -} drm_r128_context_regs_t; - -/* Setup registers for each texture unit - */ -typedef struct { - unsigned int tex_cntl; - unsigned int tex_combine_cntl; - unsigned int tex_size_pitch; - unsigned int tex_offset[R128_MAX_TEXTURE_LEVELS]; - unsigned int tex_border_color; -} drm_r128_texture_regs_t; - - -typedef struct drm_r128_sarea { - /* The channel for communication of state information to the kernel - * on firing a vertex buffer. - */ - drm_r128_context_regs_t context_state; - drm_r128_texture_regs_t tex_state[R128_MAX_TEXTURE_UNITS]; - unsigned int dirty; - unsigned int vertsize; - unsigned int vc_format; - - /* The current cliprects, or a subset thereof. - */ - drm_clip_rect_t boxes[R128_NR_SAREA_CLIPRECTS]; - unsigned int nbox; - - /* Counters for client-side throttling of rendering clients. - */ - unsigned int last_frame; - unsigned int last_dispatch; - - drm_tex_region_t tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS+1]; - unsigned int tex_age[R128_NR_TEX_HEAPS]; - int ctx_owner; - int pfAllowPageFlip; /* number of 3d windows (0,1,2 or more) */ - int pfCurrentPage; /* which buffer is being displayed? */ -} drm_r128_sarea_t; - - -/* WARNING: If you change any of these defines, make sure to change the - * defines in the Xserver file (xf86drmR128.h) - */ - -/* Rage 128 specific ioctls - * The device specific ioctl range is 0x40 to 0x79. - */ -#define DRM_R128_INIT 0x00 -#define DRM_R128_CCE_START 0x01 -#define DRM_R128_CCE_STOP 0x02 -#define DRM_R128_CCE_RESET 0x03 -#define DRM_R128_CCE_IDLE 0x04 -/* 0x05 not used */ -#define DRM_R128_RESET 0x06 -#define DRM_R128_SWAP 0x07 -#define DRM_R128_CLEAR 0x08 -#define DRM_R128_VERTEX 0x09 -#define DRM_R128_INDICES 0x0a -#define DRM_R128_BLIT 0x0b -#define DRM_R128_DEPTH 0x0c -#define DRM_R128_STIPPLE 0x0d -/* 0x0e not used */ -#define DRM_R128_INDIRECT 0x0f -#define DRM_R128_FULLSCREEN 0x10 -#define DRM_R128_CLEAR2 0x11 -#define DRM_R128_GETPARAM 0x12 -#define DRM_R128_FLIP 0x13 - -#define DRM_IOCTL_R128_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INIT, drm_r128_init_t) -#define DRM_IOCTL_R128_CCE_START DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_START) -#define DRM_IOCTL_R128_CCE_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CCE_STOP, drm_r128_cce_stop_t) -#define DRM_IOCTL_R128_CCE_RESET DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_RESET) -#define DRM_IOCTL_R128_CCE_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_IDLE) -/* 0x05 not used */ -#define DRM_IOCTL_R128_RESET DRM_IO( DRM_COMMAND_BASE + DRM_R128_RESET) -#define DRM_IOCTL_R128_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_R128_SWAP) -#define DRM_IOCTL_R128_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR, drm_r128_clear_t) -#define DRM_IOCTL_R128_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_R128_VERTEX, drm_r128_vertex_t) -#define DRM_IOCTL_R128_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INDICES, drm_r128_indices_t) -#define DRM_IOCTL_R128_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_R128_BLIT, drm_r128_blit_t) -#define DRM_IOCTL_R128_DEPTH DRM_IOW( DRM_COMMAND_BASE + DRM_R128_DEPTH, drm_r128_depth_t) -#define DRM_IOCTL_R128_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_R128_STIPPLE, drm_r128_stipple_t) -/* 0x0e not used */ -#define DRM_IOCTL_R128_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_R128_INDIRECT, drm_r128_indirect_t) -#define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_R128_FULLSCREEN, drm_r128_fullscreen_t) -#define DRM_IOCTL_R128_CLEAR2 DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR2, drm_r128_clear2_t) -#define DRM_IOCTL_R128_GETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_R128_GETPARAM, drm_r128_getparam_t) -#define DRM_IOCTL_R128_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_R128_FLIP) - -typedef struct drm_r128_init { - enum { - R128_INIT_CCE = 0x01, - R128_CLEANUP_CCE = 0x02 - } func; -#if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0) - int sarea_priv_offset; -#else - unsigned long sarea_priv_offset; -#endif - int is_pci; - int cce_mode; - int cce_secure; - int ring_size; - int usec_timeout; - - unsigned int fb_bpp; - unsigned int front_offset, front_pitch; - unsigned int back_offset, back_pitch; - unsigned int depth_bpp; - unsigned int depth_offset, depth_pitch; - unsigned int span_offset; - -#if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0) - unsigned int fb_offset; - unsigned int mmio_offset; - unsigned int ring_offset; - unsigned int ring_rptr_offset; - unsigned int buffers_offset; - unsigned int agp_textures_offset; -#else - unsigned long fb_offset; - unsigned long mmio_offset; - unsigned long ring_offset; - unsigned long ring_rptr_offset; - unsigned long buffers_offset; - unsigned long agp_textures_offset; -#endif -} drm_r128_init_t; - -typedef struct drm_r128_cce_stop { - int flush; - int idle; -} drm_r128_cce_stop_t; - -typedef struct drm_r128_clear { - unsigned int flags; -#if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0) - int x, y, w, h; -#endif - unsigned int clear_color; - unsigned int clear_depth; -#if CONFIG_XFREE86_VERSION >= XFREE86_VERSION(4,1,0,0) - unsigned int color_mask; - unsigned int depth_mask; -#endif -} drm_r128_clear_t; - -typedef struct drm_r128_vertex { - int prim; - int idx; /* Index of vertex buffer */ - int count; /* Number of vertices in buffer */ - int discard; /* Client finished with buffer? */ -} drm_r128_vertex_t; - -typedef struct drm_r128_indices { - int prim; - int idx; - int start; - int end; - int discard; /* Client finished with buffer? */ -} drm_r128_indices_t; - -typedef struct drm_r128_blit { - int idx; - int pitch; - int offset; - int format; - unsigned short x, y; - unsigned short width, height; -} drm_r128_blit_t; - -typedef struct drm_r128_depth { - enum { - R128_WRITE_SPAN = 0x01, - R128_WRITE_PIXELS = 0x02, - R128_READ_SPAN = 0x03, - R128_READ_PIXELS = 0x04 - } func; - int n; - int __user *x; - int __user *y; - unsigned int __user *buffer; - unsigned char __user *mask; -} drm_r128_depth_t; - -typedef struct drm_r128_stipple { - unsigned int __user *mask; -} drm_r128_stipple_t; - -typedef struct drm_r128_indirect { - int idx; - int start; - int end; - int discard; -} drm_r128_indirect_t; - -typedef struct drm_r128_fullscreen { - enum { - R128_INIT_FULLSCREEN = 0x01, - R128_CLEANUP_FULLSCREEN = 0x02 - } func; -} drm_r128_fullscreen_t; - -/* 2.3: An ioctl to get parameters that aren't available to the 3d - * client any other way. - */ -#define R128_PARAM_IRQ_NR 1 - -typedef struct drm_r128_getparam { - int param; - void __user *value; -} drm_r128_getparam_t; - -#endif diff --git a/nx-X11/extras/drm/shared/r128_drv.h b/nx-X11/extras/drm/shared/r128_drv.h deleted file mode 100644 index 5b91256c1..000000000 --- a/nx-X11/extras/drm/shared/r128_drv.h +++ /dev/null @@ -1,516 +0,0 @@ -/* r128_drv.h -- Private header for r128 driver -*- linux-c -*- - * Created: Mon Dec 13 09:51:11 1999 by faith@precisioninsight.com - * - * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. - * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. - * All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Rickard E. (Rik) Faith - * Kevin E. Martin - * Gareth Hughes - * Michel Dänzer - */ - -#ifndef __R128_DRV_H__ -#define __R128_DRV_H__ - -#define GET_RING_HEAD(dev_priv) R128_READ( R128_PM4_BUFFER_DL_RPTR ) - -typedef struct drm_r128_freelist { - unsigned int age; - drm_buf_t *buf; - struct drm_r128_freelist *next; - struct drm_r128_freelist *prev; -} drm_r128_freelist_t; - -typedef struct drm_r128_ring_buffer { - u32 *start; - u32 *end; - int size; - int size_l2qw; - - u32 tail; - u32 tail_mask; - int space; - - int high_mark; -} drm_r128_ring_buffer_t; - -typedef struct drm_r128_private { - drm_r128_ring_buffer_t ring; - drm_r128_sarea_t *sarea_priv; - - int cce_mode; - int cce_fifo_size; - int cce_running; - - drm_r128_freelist_t *head; - drm_r128_freelist_t *tail; - - int usec_timeout; - int is_pci; - unsigned long phys_pci_gart; - dma_addr_t bus_pci_gart; - unsigned long cce_buffers_offset; - - atomic_t idle_count; - - int page_flipping; - int current_page; - u32 crtc_offset; - u32 crtc_offset_cntl; - - u32 color_fmt; - unsigned int front_offset; - unsigned int front_pitch; - unsigned int back_offset; - unsigned int back_pitch; - - u32 depth_fmt; - unsigned int depth_offset; - unsigned int depth_pitch; - unsigned int span_offset; - - u32 front_pitch_offset_c; - u32 back_pitch_offset_c; - u32 depth_pitch_offset_c; - u32 span_pitch_offset_c; - - drm_local_map_t *sarea; - drm_local_map_t *mmio; - drm_local_map_t *cce_ring; - drm_local_map_t *ring_rptr; - drm_local_map_t *agp_textures; -} drm_r128_private_t; - -typedef struct drm_r128_buf_priv { - u32 age; - int prim; - int discard; - int dispatched; - drm_r128_freelist_t *list_entry; -} drm_r128_buf_priv_t; - - /* r128_cce.c */ -extern int r128_cce_init( DRM_IOCTL_ARGS ); -extern int r128_cce_start( DRM_IOCTL_ARGS ); -extern int r128_cce_stop( DRM_IOCTL_ARGS ); -extern int r128_cce_reset( DRM_IOCTL_ARGS ); -extern int r128_cce_idle( DRM_IOCTL_ARGS ); -extern int r128_engine_reset( DRM_IOCTL_ARGS ); -extern int r128_fullscreen( DRM_IOCTL_ARGS ); -extern int r128_cce_buffers( DRM_IOCTL_ARGS ); -extern int r128_getparam( DRM_IOCTL_ARGS ); - -extern void r128_freelist_reset( drm_device_t *dev ); -extern drm_buf_t *r128_freelist_get( drm_device_t *dev ); - -extern int r128_wait_ring( drm_r128_private_t *dev_priv, int n ); - -extern int r128_do_cce_idle( drm_r128_private_t *dev_priv ); -extern int r128_do_cleanup_cce( drm_device_t *dev ); -extern int r128_do_cleanup_pageflip( drm_device_t *dev ); - - /* r128_state.c */ -extern int r128_cce_clear( DRM_IOCTL_ARGS ); -extern int r128_cce_swap( DRM_IOCTL_ARGS ); -extern int r128_cce_flip( DRM_IOCTL_ARGS ); -extern int r128_cce_vertex( DRM_IOCTL_ARGS ); -extern int r128_cce_indices( DRM_IOCTL_ARGS ); -extern int r128_cce_blit( DRM_IOCTL_ARGS ); -extern int r128_cce_depth( DRM_IOCTL_ARGS ); -extern int r128_cce_stipple( DRM_IOCTL_ARGS ); -extern int r128_cce_indirect( DRM_IOCTL_ARGS ); - -extern int r128_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence); - -extern irqreturn_t r128_driver_irq_handler( DRM_IRQ_ARGS ); -extern void r128_driver_irq_preinstall( drm_device_t *dev ); -extern void r128_driver_irq_postinstall( drm_device_t *dev ); -extern void r128_driver_irq_uninstall( drm_device_t *dev ); - -/* Register definitions, register access macros and drmAddMap constants - * for Rage 128 kernel driver. - */ - -#define R128_AUX_SC_CNTL 0x1660 -# define R128_AUX1_SC_EN (1 << 0) -# define R128_AUX1_SC_MODE_OR (0 << 1) -# define R128_AUX1_SC_MODE_NAND (1 << 1) -# define R128_AUX2_SC_EN (1 << 2) -# define R128_AUX2_SC_MODE_OR (0 << 3) -# define R128_AUX2_SC_MODE_NAND (1 << 3) -# define R128_AUX3_SC_EN (1 << 4) -# define R128_AUX3_SC_MODE_OR (0 << 5) -# define R128_AUX3_SC_MODE_NAND (1 << 5) -#define R128_AUX1_SC_LEFT 0x1664 -#define R128_AUX1_SC_RIGHT 0x1668 -#define R128_AUX1_SC_TOP 0x166c -#define R128_AUX1_SC_BOTTOM 0x1670 -#define R128_AUX2_SC_LEFT 0x1674 -#define R128_AUX2_SC_RIGHT 0x1678 -#define R128_AUX2_SC_TOP 0x167c -#define R128_AUX2_SC_BOTTOM 0x1680 -#define R128_AUX3_SC_LEFT 0x1684 -#define R128_AUX3_SC_RIGHT 0x1688 -#define R128_AUX3_SC_TOP 0x168c -#define R128_AUX3_SC_BOTTOM 0x1690 - -#define R128_BRUSH_DATA0 0x1480 -#define R128_BUS_CNTL 0x0030 -# define R128_BUS_MASTER_DIS (1 << 6) - -#define R128_CLOCK_CNTL_INDEX 0x0008 -#define R128_CLOCK_CNTL_DATA 0x000c -# define R128_PLL_WR_EN (1 << 7) -#define R128_CONSTANT_COLOR_C 0x1d34 -#define R128_CRTC_OFFSET 0x0224 -#define R128_CRTC_OFFSET_CNTL 0x0228 -# define R128_CRTC_OFFSET_FLIP_CNTL (1 << 16) - -#define R128_DP_GUI_MASTER_CNTL 0x146c -# define R128_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) -# define R128_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) -# define R128_GMC_BRUSH_SOLID_COLOR (13 << 4) -# define R128_GMC_BRUSH_NONE (15 << 4) -# define R128_GMC_DST_16BPP (4 << 8) -# define R128_GMC_DST_24BPP (5 << 8) -# define R128_GMC_DST_32BPP (6 << 8) -# define R128_GMC_DST_DATATYPE_SHIFT 8 -# define R128_GMC_SRC_DATATYPE_COLOR (3 << 12) -# define R128_DP_SRC_SOURCE_MEMORY (2 << 24) -# define R128_DP_SRC_SOURCE_HOST_DATA (3 << 24) -# define R128_GMC_CLR_CMP_CNTL_DIS (1 << 28) -# define R128_GMC_AUX_CLIP_DIS (1 << 29) -# define R128_GMC_WR_MSK_DIS (1 << 30) -# define R128_ROP3_S 0x00cc0000 -# define R128_ROP3_P 0x00f00000 -#define R128_DP_WRITE_MASK 0x16cc -#define R128_DST_PITCH_OFFSET_C 0x1c80 -# define R128_DST_TILE (1 << 31) - -#define R128_GEN_INT_CNTL 0x0040 -# define R128_CRTC_VBLANK_INT_EN (1 << 0) -#define R128_GEN_INT_STATUS 0x0044 -# define R128_CRTC_VBLANK_INT (1 << 0) -# define R128_CRTC_VBLANK_INT_AK (1 << 0) -#define R128_GEN_RESET_CNTL 0x00f0 -# define R128_SOFT_RESET_GUI (1 << 0) - -#define R128_GUI_SCRATCH_REG0 0x15e0 -#define R128_GUI_SCRATCH_REG1 0x15e4 -#define R128_GUI_SCRATCH_REG2 0x15e8 -#define R128_GUI_SCRATCH_REG3 0x15ec -#define R128_GUI_SCRATCH_REG4 0x15f0 -#define R128_GUI_SCRATCH_REG5 0x15f4 - -#define R128_GUI_STAT 0x1740 -# define R128_GUI_FIFOCNT_MASK 0x0fff -# define R128_GUI_ACTIVE (1 << 31) - -#define R128_MCLK_CNTL 0x000f -# define R128_FORCE_GCP (1 << 16) -# define R128_FORCE_PIPE3D_CP (1 << 17) -# define R128_FORCE_RCP (1 << 18) - -#define R128_PC_GUI_CTLSTAT 0x1748 -#define R128_PC_NGUI_CTLSTAT 0x0184 -# define R128_PC_FLUSH_GUI (3 << 0) -# define R128_PC_RI_GUI (1 << 2) -# define R128_PC_FLUSH_ALL 0x00ff -# define R128_PC_BUSY (1 << 31) - -#define R128_PCI_GART_PAGE 0x017c -#define R128_PRIM_TEX_CNTL_C 0x1cb0 - -#define R128_SCALE_3D_CNTL 0x1a00 -#define R128_SEC_TEX_CNTL_C 0x1d00 -#define R128_SEC_TEXTURE_BORDER_COLOR_C 0x1d3c -#define R128_SETUP_CNTL 0x1bc4 -#define R128_STEN_REF_MASK_C 0x1d40 - -#define R128_TEX_CNTL_C 0x1c9c -# define R128_TEX_CACHE_FLUSH (1 << 23) - -#define R128_WAIT_UNTIL 0x1720 -# define R128_EVENT_CRTC_OFFSET (1 << 0) -#define R128_WINDOW_XY_OFFSET 0x1bcc - - -/* CCE registers - */ -#define R128_PM4_BUFFER_OFFSET 0x0700 -#define R128_PM4_BUFFER_CNTL 0x0704 -# define R128_PM4_MASK (15 << 28) -# define R128_PM4_NONPM4 (0 << 28) -# define R128_PM4_192PIO (1 << 28) -# define R128_PM4_192BM (2 << 28) -# define R128_PM4_128PIO_64INDBM (3 << 28) -# define R128_PM4_128BM_64INDBM (4 << 28) -# define R128_PM4_64PIO_128INDBM (5 << 28) -# define R128_PM4_64BM_128INDBM (6 << 28) -# define R128_PM4_64PIO_64VCBM_64INDBM (7 << 28) -# define R128_PM4_64BM_64VCBM_64INDBM (8 << 28) -# define R128_PM4_64PIO_64VCPIO_64INDPIO (15 << 28) -# define R128_PM4_BUFFER_CNTL_NOUPDATE (1 << 27) - -#define R128_PM4_BUFFER_WM_CNTL 0x0708 -# define R128_WMA_SHIFT 0 -# define R128_WMB_SHIFT 8 -# define R128_WMC_SHIFT 16 -# define R128_WB_WM_SHIFT 24 - -#define R128_PM4_BUFFER_DL_RPTR_ADDR 0x070c -#define R128_PM4_BUFFER_DL_RPTR 0x0710 -#define R128_PM4_BUFFER_DL_WPTR 0x0714 -# define R128_PM4_BUFFER_DL_DONE (1 << 31) - -#define R128_PM4_VC_FPU_SETUP 0x071c - -#define R128_PM4_IW_INDOFF 0x0738 -#define R128_PM4_IW_INDSIZE 0x073c - -#define R128_PM4_STAT 0x07b8 -# define R128_PM4_FIFOCNT_MASK 0x0fff -# define R128_PM4_BUSY (1 << 16) -# define R128_PM4_GUI_ACTIVE (1 << 31) - -#define R128_PM4_MICROCODE_ADDR 0x07d4 -#define R128_PM4_MICROCODE_RADDR 0x07d8 -#define R128_PM4_MICROCODE_DATAH 0x07dc -#define R128_PM4_MICROCODE_DATAL 0x07e0 - -#define R128_PM4_BUFFER_ADDR 0x07f0 -#define R128_PM4_MICRO_CNTL 0x07fc -# define R128_PM4_MICRO_FREERUN (1 << 30) - -#define R128_PM4_FIFO_DATA_EVEN 0x1000 -#define R128_PM4_FIFO_DATA_ODD 0x1004 - - -/* CCE command packets - */ -#define R128_CCE_PACKET0 0x00000000 -#define R128_CCE_PACKET1 0x40000000 -#define R128_CCE_PACKET2 0x80000000 -#define R128_CCE_PACKET3 0xC0000000 -# define R128_CNTL_HOSTDATA_BLT 0x00009400 -# define R128_CNTL_PAINT_MULTI 0x00009A00 -# define R128_CNTL_BITBLT_MULTI 0x00009B00 -# define R128_3D_RNDR_GEN_INDX_PRIM 0x00002300 - -#define R128_CCE_PACKET_MASK 0xC0000000 -#define R128_CCE_PACKET_COUNT_MASK 0x3fff0000 -#define R128_CCE_PACKET0_REG_MASK 0x000007ff -#define R128_CCE_PACKET1_REG0_MASK 0x000007ff -#define R128_CCE_PACKET1_REG1_MASK 0x003ff800 - -#define R128_CCE_VC_CNTL_PRIM_TYPE_NONE 0x00000000 -#define R128_CCE_VC_CNTL_PRIM_TYPE_POINT 0x00000001 -#define R128_CCE_VC_CNTL_PRIM_TYPE_LINE 0x00000002 -#define R128_CCE_VC_CNTL_PRIM_TYPE_POLY_LINE 0x00000003 -#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004 -#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005 -#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006 -#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 0x00000007 -#define R128_CCE_VC_CNTL_PRIM_WALK_IND 0x00000010 -#define R128_CCE_VC_CNTL_PRIM_WALK_LIST 0x00000020 -#define R128_CCE_VC_CNTL_PRIM_WALK_RING 0x00000030 -#define R128_CCE_VC_CNTL_NUM_SHIFT 16 - -#define R128_DATATYPE_VQ 0 -#define R128_DATATYPE_CI4 1 -#define R128_DATATYPE_CI8 2 -#define R128_DATATYPE_ARGB1555 3 -#define R128_DATATYPE_RGB565 4 -#define R128_DATATYPE_RGB888 5 -#define R128_DATATYPE_ARGB8888 6 -#define R128_DATATYPE_RGB332 7 -#define R128_DATATYPE_Y8 8 -#define R128_DATATYPE_RGB8 9 -#define R128_DATATYPE_CI16 10 -#define R128_DATATYPE_YVYU422 11 -#define R128_DATATYPE_VYUY422 12 -#define R128_DATATYPE_AYUV444 14 -#define R128_DATATYPE_ARGB4444 15 - -/* Constants */ -#define R128_AGP_OFFSET 0x02000000 - -#define R128_WATERMARK_L 16 -#define R128_WATERMARK_M 8 -#define R128_WATERMARK_N 8 -#define R128_WATERMARK_K 128 - -#define R128_MAX_USEC_TIMEOUT 100000 /* 100 ms */ - -#define R128_LAST_FRAME_REG R128_GUI_SCRATCH_REG0 -#define R128_LAST_DISPATCH_REG R128_GUI_SCRATCH_REG1 -#define R128_MAX_VB_AGE 0x7fffffff -#define R128_MAX_VB_VERTS (0xffff) - -#define R128_RING_HIGH_MARK 128 - -#define R128_PERFORMANCE_BOXES 0 - -#define R128_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) -#define R128_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) -#define R128_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) -#define R128_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) - -#define R128_WRITE_PLL(addr,val) \ -do { \ - R128_WRITE8(R128_CLOCK_CNTL_INDEX, \ - ((addr) & 0x1f) | R128_PLL_WR_EN); \ - R128_WRITE(R128_CLOCK_CNTL_DATA, (val)); \ -} while (0) - -extern int R128_READ_PLL(drm_device_t *dev, int addr); - - -#define CCE_PACKET0( reg, n ) (R128_CCE_PACKET0 | \ - ((n) << 16) | ((reg) >> 2)) -#define CCE_PACKET1( reg0, reg1 ) (R128_CCE_PACKET1 | \ - (((reg1) >> 2) << 11) | ((reg0) >> 2)) -#define CCE_PACKET2() (R128_CCE_PACKET2) -#define CCE_PACKET3( pkt, n ) (R128_CCE_PACKET3 | \ - (pkt) | ((n) << 16)) - - -static __inline__ void -r128_update_ring_snapshot( drm_r128_private_t *dev_priv ) -{ - drm_r128_ring_buffer_t *ring = &dev_priv->ring; - ring->space = (GET_RING_HEAD( dev_priv ) - ring->tail) * sizeof(u32); - if ( ring->space <= 0 ) - ring->space += ring->size; -} - -/* ================================================================ - * Misc helper macros - */ - -#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \ -do { \ - drm_r128_ring_buffer_t *ring = &dev_priv->ring; int i; \ - if ( ring->space < ring->high_mark ) { \ - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { \ - r128_update_ring_snapshot( dev_priv ); \ - if ( ring->space >= ring->high_mark ) \ - goto __ring_space_done; \ - DRM_UDELAY(1); \ - } \ - DRM_ERROR( "ring space check failed!\n" ); \ - return DRM_ERR(EBUSY); \ - } \ - __ring_space_done: \ - ; \ -} while (0) - -#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \ -do { \ - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; \ - if ( sarea_priv->last_dispatch >= R128_MAX_VB_AGE ) { \ - int __ret = r128_do_cce_idle( dev_priv ); \ - if ( __ret ) return __ret; \ - sarea_priv->last_dispatch = 0; \ - r128_freelist_reset( dev ); \ - } \ -} while (0) - -#define R128_WAIT_UNTIL_PAGE_FLIPPED() do { \ - OUT_RING( CCE_PACKET0( R128_WAIT_UNTIL, 0 ) ); \ - OUT_RING( R128_EVENT_CRTC_OFFSET ); \ -} while (0) - - -/* ================================================================ - * Ring control - */ - -#define R128_VERBOSE 0 - -#define RING_LOCALS \ - int write, _nr; unsigned int tail_mask; volatile u32 *ring; - -#define BEGIN_RING( n ) do { \ - if ( R128_VERBOSE ) { \ - DRM_INFO( "BEGIN_RING( %d ) in %s\n", \ - (n), __FUNCTION__ ); \ - } \ - if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \ - COMMIT_RING(); \ - r128_wait_ring( dev_priv, (n) * sizeof(u32) ); \ - } \ - _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \ - ring = dev_priv->ring.start; \ - write = dev_priv->ring.tail; \ - tail_mask = dev_priv->ring.tail_mask; \ -} while (0) - -/* You can set this to zero if you want. If the card locks up, you'll - * need to keep this set. It works around a bug in early revs of the - * Rage 128 chipset, where the CCE would read 32 dwords past the end of - * the ring buffer before wrapping around. - */ -#define R128_BROKEN_CCE 1 - -#define ADVANCE_RING() do { \ - if ( R128_VERBOSE ) { \ - DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \ - write, dev_priv->ring.tail ); \ - } \ - if ( R128_BROKEN_CCE && write < 32 ) { \ - memcpy( dev_priv->ring.end, \ - dev_priv->ring.start, \ - write * sizeof(u32) ); \ - } \ - if (((dev_priv->ring.tail + _nr) & tail_mask) != write) { \ - DRM_ERROR( \ - "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \ - ((dev_priv->ring.tail + _nr) & tail_mask), \ - write, __LINE__); \ - } else \ - dev_priv->ring.tail = write; \ -} while (0) - -#define COMMIT_RING() do { \ - if ( R128_VERBOSE ) { \ - DRM_INFO( "COMMIT_RING() tail=0x%06x\n", \ - dev_priv->ring.tail ); \ - } \ - DRM_MEMORYBARRIER(); \ - R128_WRITE( R128_PM4_BUFFER_DL_WPTR, dev_priv->ring.tail ); \ - R128_READ( R128_PM4_BUFFER_DL_WPTR ); \ -} while (0) - -#define OUT_RING( x ) do { \ - if ( R128_VERBOSE ) { \ - DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ - (unsigned int)(x), write ); \ - } \ - ring[write++] = cpu_to_le32( x ); \ - write &= tail_mask; \ -} while (0) - -#endif /* __R128_DRV_H__ */ diff --git a/nx-X11/extras/drm/shared/r128_irq.c b/nx-X11/extras/drm/shared/r128_irq.c deleted file mode 100644 index be1b9dac6..000000000 --- a/nx-X11/extras/drm/shared/r128_irq.c +++ /dev/null @@ -1,103 +0,0 @@ -/* r128_irq.c -- IRQ handling for radeon -*- linux-c -*- - * - * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - * - * The Weather Channel (TM) funded Tungsten Graphics to develop the - * initial release of the Radeon 8500 driver under the XFree86 license. - * This notice must be preserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Keith Whitwell - * Eric Anholt - */ - -#include "r128.h" -#include "drmP.h" -#include "drm.h" -#include "r128_drm.h" -#include "r128_drv.h" - -irqreturn_t r128_driver_irq_handler( DRM_IRQ_ARGS ) -{ - drm_device_t *dev = (drm_device_t *) arg; - drm_r128_private_t *dev_priv = - (drm_r128_private_t *)dev->dev_private; - int status; - - status = R128_READ( R128_GEN_INT_STATUS ); - - /* VBLANK interrupt */ - if ( status & R128_CRTC_VBLANK_INT ) { - R128_WRITE( R128_GEN_INT_STATUS, R128_CRTC_VBLANK_INT_AK ); - atomic_inc(&dev->vbl_received); - DRM_WAKEUP(&dev->vbl_queue); - DRM(vbl_send_signals)( dev ); - return IRQ_HANDLED; - } - return IRQ_NONE; -} - -int r128_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence) -{ - unsigned int cur_vblank; - int ret = 0; - - /* Assume that the user has missed the current sequence number - * by about a day rather than she wants to wait for years - * using vertical blanks... - */ - DRM_WAIT_ON( ret, dev->vbl_queue, 3*DRM_HZ, - ( ( ( cur_vblank = atomic_read(&dev->vbl_received ) ) - - *sequence ) <= (1<<23) ) ); - - *sequence = cur_vblank; - - return ret; -} - -void r128_driver_irq_preinstall( drm_device_t *dev ) { - drm_r128_private_t *dev_priv = - (drm_r128_private_t *)dev->dev_private; - - /* Disable *all* interrupts */ - R128_WRITE( R128_GEN_INT_CNTL, 0 ); - /* Clear vblank bit if it's already high */ - R128_WRITE( R128_GEN_INT_STATUS, R128_CRTC_VBLANK_INT_AK ); -} - -void r128_driver_irq_postinstall( drm_device_t *dev ) { - drm_r128_private_t *dev_priv = - (drm_r128_private_t *)dev->dev_private; - - /* Turn on VBL interrupt */ - R128_WRITE( R128_GEN_INT_CNTL, R128_CRTC_VBLANK_INT_EN ); -} - -void r128_driver_irq_uninstall( drm_device_t *dev ) { - drm_r128_private_t *dev_priv = - (drm_r128_private_t *)dev->dev_private; - if (!dev_priv) - return; - - /* Disable *all* interrupts */ - R128_WRITE( R128_GEN_INT_CNTL, 0 ); -} diff --git a/nx-X11/extras/drm/shared/r128_state.c b/nx-X11/extras/drm/shared/r128_state.c deleted file mode 100644 index 5b8af9f99..000000000 --- a/nx-X11/extras/drm/shared/r128_state.c +++ /dev/null @@ -1,1724 +0,0 @@ -/* r128_state.c -- State support for r128 -*- linux-c -*- - * Created: Thu Jan 27 02:53:43 2000 by gareth@valinux.com - * - * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Gareth Hughes - */ - -#include "r128.h" -#include "drmP.h" -#include "drm.h" -#include "r128_drm.h" -#include "r128_drv.h" - - -/* ================================================================ - * CCE hardware state programming functions - */ - -static void r128_emit_clip_rects( drm_r128_private_t *dev_priv, - drm_clip_rect_t *boxes, int count ) -{ - u32 aux_sc_cntl = 0x00000000; - RING_LOCALS; - DRM_DEBUG( " %s\n", __FUNCTION__ ); - - BEGIN_RING( (count < 3? count: 3) * 5 + 2 ); - - if ( count >= 1 ) { - OUT_RING( CCE_PACKET0( R128_AUX1_SC_LEFT, 3 ) ); - OUT_RING( boxes[0].x1 ); - OUT_RING( boxes[0].x2 - 1 ); - OUT_RING( boxes[0].y1 ); - OUT_RING( boxes[0].y2 - 1 ); - - aux_sc_cntl |= (R128_AUX1_SC_EN | R128_AUX1_SC_MODE_OR); - } - if ( count >= 2 ) { - OUT_RING( CCE_PACKET0( R128_AUX2_SC_LEFT, 3 ) ); - OUT_RING( boxes[1].x1 ); - OUT_RING( boxes[1].x2 - 1 ); - OUT_RING( boxes[1].y1 ); - OUT_RING( boxes[1].y2 - 1 ); - - aux_sc_cntl |= (R128_AUX2_SC_EN | R128_AUX2_SC_MODE_OR); - } - if ( count >= 3 ) { - OUT_RING( CCE_PACKET0( R128_AUX3_SC_LEFT, 3 ) ); - OUT_RING( boxes[2].x1 ); - OUT_RING( boxes[2].x2 - 1 ); - OUT_RING( boxes[2].y1 ); - OUT_RING( boxes[2].y2 - 1 ); - - aux_sc_cntl |= (R128_AUX3_SC_EN | R128_AUX3_SC_MODE_OR); - } - - OUT_RING( CCE_PACKET0( R128_AUX_SC_CNTL, 0 ) ); - OUT_RING( aux_sc_cntl ); - - ADVANCE_RING(); -} - -static __inline__ void r128_emit_core( drm_r128_private_t *dev_priv ) -{ - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_r128_context_regs_t *ctx = &sarea_priv->context_state; - RING_LOCALS; - DRM_DEBUG( " %s\n", __FUNCTION__ ); - - BEGIN_RING( 2 ); - - OUT_RING( CCE_PACKET0( R128_SCALE_3D_CNTL, 0 ) ); - OUT_RING( ctx->scale_3d_cntl ); - - ADVANCE_RING(); -} - -static __inline__ void r128_emit_context( drm_r128_private_t *dev_priv ) -{ - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_r128_context_regs_t *ctx = &sarea_priv->context_state; - RING_LOCALS; - DRM_DEBUG( " %s\n", __FUNCTION__ ); - - BEGIN_RING( 13 ); - - OUT_RING( CCE_PACKET0( R128_DST_PITCH_OFFSET_C, 11 ) ); - OUT_RING( ctx->dst_pitch_offset_c ); - OUT_RING( ctx->dp_gui_master_cntl_c ); - OUT_RING( ctx->sc_top_left_c ); - OUT_RING( ctx->sc_bottom_right_c ); - OUT_RING( ctx->z_offset_c ); - OUT_RING( ctx->z_pitch_c ); - OUT_RING( ctx->z_sten_cntl_c ); - OUT_RING( ctx->tex_cntl_c ); - OUT_RING( ctx->misc_3d_state_cntl_reg ); - OUT_RING( ctx->texture_clr_cmp_clr_c ); - OUT_RING( ctx->texture_clr_cmp_msk_c ); - OUT_RING( ctx->fog_color_c ); - - ADVANCE_RING(); -} - -static __inline__ void r128_emit_setup( drm_r128_private_t *dev_priv ) -{ - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_r128_context_regs_t *ctx = &sarea_priv->context_state; - RING_LOCALS; - DRM_DEBUG( " %s\n", __FUNCTION__ ); - - BEGIN_RING( 3 ); - - OUT_RING( CCE_PACKET1( R128_SETUP_CNTL, R128_PM4_VC_FPU_SETUP ) ); - OUT_RING( ctx->setup_cntl ); - OUT_RING( ctx->pm4_vc_fpu_setup ); - - ADVANCE_RING(); -} - -static __inline__ void r128_emit_masks( drm_r128_private_t *dev_priv ) -{ - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_r128_context_regs_t *ctx = &sarea_priv->context_state; - RING_LOCALS; - DRM_DEBUG( " %s\n", __FUNCTION__ ); - - BEGIN_RING( 5 ); - - OUT_RING( CCE_PACKET0( R128_DP_WRITE_MASK, 0 ) ); - OUT_RING( ctx->dp_write_mask ); - - OUT_RING( CCE_PACKET0( R128_STEN_REF_MASK_C, 1 ) ); - OUT_RING( ctx->sten_ref_mask_c ); - OUT_RING( ctx->plane_3d_mask_c ); - - ADVANCE_RING(); -} - -static __inline__ void r128_emit_window( drm_r128_private_t *dev_priv ) -{ - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_r128_context_regs_t *ctx = &sarea_priv->context_state; - RING_LOCALS; - DRM_DEBUG( " %s\n", __FUNCTION__ ); - - BEGIN_RING( 2 ); - - OUT_RING( CCE_PACKET0( R128_WINDOW_XY_OFFSET, 0 ) ); - OUT_RING( ctx->window_xy_offset ); - - ADVANCE_RING(); -} - -static __inline__ void r128_emit_tex0( drm_r128_private_t *dev_priv ) -{ - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_r128_context_regs_t *ctx = &sarea_priv->context_state; - drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[0]; - int i; - RING_LOCALS; - DRM_DEBUG( " %s\n", __FUNCTION__ ); - - BEGIN_RING( 7 + R128_MAX_TEXTURE_LEVELS ); - - OUT_RING( CCE_PACKET0( R128_PRIM_TEX_CNTL_C, - 2 + R128_MAX_TEXTURE_LEVELS ) ); - OUT_RING( tex->tex_cntl ); - OUT_RING( tex->tex_combine_cntl ); - OUT_RING( ctx->tex_size_pitch_c ); - for ( i = 0 ; i < R128_MAX_TEXTURE_LEVELS ; i++ ) { - OUT_RING( tex->tex_offset[i] ); - } - - OUT_RING( CCE_PACKET0( R128_CONSTANT_COLOR_C, 1 ) ); - OUT_RING( ctx->constant_color_c ); - OUT_RING( tex->tex_border_color ); - - ADVANCE_RING(); -} - -static __inline__ void r128_emit_tex1( drm_r128_private_t *dev_priv ) -{ - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[1]; - int i; - RING_LOCALS; - DRM_DEBUG( " %s\n", __FUNCTION__ ); - - BEGIN_RING( 5 + R128_MAX_TEXTURE_LEVELS ); - - OUT_RING( CCE_PACKET0( R128_SEC_TEX_CNTL_C, - 1 + R128_MAX_TEXTURE_LEVELS ) ); - OUT_RING( tex->tex_cntl ); - OUT_RING( tex->tex_combine_cntl ); - for ( i = 0 ; i < R128_MAX_TEXTURE_LEVELS ; i++ ) { - OUT_RING( tex->tex_offset[i] ); - } - - OUT_RING( CCE_PACKET0( R128_SEC_TEXTURE_BORDER_COLOR_C, 0 ) ); - OUT_RING( tex->tex_border_color ); - - ADVANCE_RING(); -} - -static __inline__ void r128_emit_state( drm_r128_private_t *dev_priv ) -{ - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - unsigned int dirty = sarea_priv->dirty; - - DRM_DEBUG( "%s: dirty=0x%08x\n", __FUNCTION__, dirty ); - - if ( dirty & R128_UPLOAD_CORE ) { - r128_emit_core( dev_priv ); - sarea_priv->dirty &= ~R128_UPLOAD_CORE; - } - - if ( dirty & R128_UPLOAD_CONTEXT ) { - r128_emit_context( dev_priv ); - sarea_priv->dirty &= ~R128_UPLOAD_CONTEXT; - } - - if ( dirty & R128_UPLOAD_SETUP ) { - r128_emit_setup( dev_priv ); - sarea_priv->dirty &= ~R128_UPLOAD_SETUP; - } - - if ( dirty & R128_UPLOAD_MASKS ) { - r128_emit_masks( dev_priv ); - sarea_priv->dirty &= ~R128_UPLOAD_MASKS; - } - - if ( dirty & R128_UPLOAD_WINDOW ) { - r128_emit_window( dev_priv ); - sarea_priv->dirty &= ~R128_UPLOAD_WINDOW; - } - - if ( dirty & R128_UPLOAD_TEX0 ) { - r128_emit_tex0( dev_priv ); - sarea_priv->dirty &= ~R128_UPLOAD_TEX0; - } - - if ( dirty & R128_UPLOAD_TEX1 ) { - r128_emit_tex1( dev_priv ); - sarea_priv->dirty &= ~R128_UPLOAD_TEX1; - } - - /* Turn off the texture cache flushing */ - sarea_priv->context_state.tex_cntl_c &= ~R128_TEX_CACHE_FLUSH; - - sarea_priv->dirty &= ~R128_REQUIRE_QUIESCENCE; -} - - -#if R128_PERFORMANCE_BOXES -/* ================================================================ - * Performance monitoring functions - */ - -static void r128_clear_box( drm_r128_private_t *dev_priv, - int x, int y, int w, int h, - int r, int g, int b ) -{ - u32 pitch, offset; - u32 fb_bpp, color; - RING_LOCALS; - - switch ( dev_priv->fb_bpp ) { - case 16: - fb_bpp = R128_GMC_DST_16BPP; - color = (((r & 0xf8) << 8) | - ((g & 0xfc) << 3) | - ((b & 0xf8) >> 3)); - break; - case 24: - fb_bpp = R128_GMC_DST_24BPP; - color = ((r << 16) | (g << 8) | b); - break; - case 32: - fb_bpp = R128_GMC_DST_32BPP; - color = (((0xff) << 24) | (r << 16) | (g << 8) | b); - break; - default: - return; - } - - offset = dev_priv->back_offset; - pitch = dev_priv->back_pitch >> 3; - - BEGIN_RING( 6 ); - - OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); - OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_SOLID_COLOR | - fb_bpp | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_P | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_AUX_CLIP_DIS ); - - OUT_RING( (pitch << 21) | (offset >> 5) ); - OUT_RING( color ); - - OUT_RING( (x << 16) | y ); - OUT_RING( (w << 16) | h ); - - ADVANCE_RING(); -} - -static void r128_cce_performance_boxes( drm_r128_private_t *dev_priv ) -{ - if ( atomic_read( &dev_priv->idle_count ) == 0 ) { - r128_clear_box( dev_priv, 64, 4, 8, 8, 0, 255, 0 ); - } else { - atomic_set( &dev_priv->idle_count, 0 ); - } -} - -#endif - - -/* ================================================================ - * CCE command dispatch functions - */ - -static void r128_print_dirty( const char *msg, unsigned int flags ) -{ - DRM_INFO( "%s: (0x%x) %s%s%s%s%s%s%s%s%s\n", - msg, - flags, - (flags & R128_UPLOAD_CORE) ? "core, " : "", - (flags & R128_UPLOAD_CONTEXT) ? "context, " : "", - (flags & R128_UPLOAD_SETUP) ? "setup, " : "", - (flags & R128_UPLOAD_TEX0) ? "tex0, " : "", - (flags & R128_UPLOAD_TEX1) ? "tex1, " : "", - (flags & R128_UPLOAD_MASKS) ? "masks, " : "", - (flags & R128_UPLOAD_WINDOW) ? "window, " : "", - (flags & R128_UPLOAD_CLIPRECTS) ? "cliprects, " : "", - (flags & R128_REQUIRE_QUIESCENCE) ? "quiescence, " : "" ); -} - -static void r128_cce_dispatch_clear( drm_device_t *dev, - drm_r128_clear_t *clear ) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - int nbox = sarea_priv->nbox; - drm_clip_rect_t *pbox = sarea_priv->boxes; - unsigned int flags = clear->flags; - int i; - RING_LOCALS; - DRM_DEBUG( "%s\n", __FUNCTION__ ); - - if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) { - unsigned int tmp = flags; - - flags &= ~(R128_FRONT | R128_BACK); - if ( tmp & R128_FRONT ) flags |= R128_BACK; - if ( tmp & R128_BACK ) flags |= R128_FRONT; - } - - for ( i = 0 ; i < nbox ; i++ ) { - int x = pbox[i].x1; - int y = pbox[i].y1; - int w = pbox[i].x2 - x; - int h = pbox[i].y2 - y; - - DRM_DEBUG( "dispatch clear %d,%d-%d,%d flags 0x%x\n", - pbox[i].x1, pbox[i].y1, pbox[i].x2, - pbox[i].y2, flags ); - - if ( flags & (R128_FRONT | R128_BACK) ) { - BEGIN_RING( 2 ); - - OUT_RING( CCE_PACKET0( R128_DP_WRITE_MASK, 0 ) ); - OUT_RING( clear->color_mask ); - - ADVANCE_RING(); - } - - if ( flags & R128_FRONT ) { - BEGIN_RING( 6 ); - - OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); - OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_SOLID_COLOR | - (dev_priv->color_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_P | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_AUX_CLIP_DIS ); - - OUT_RING( dev_priv->front_pitch_offset_c ); - OUT_RING( clear->clear_color ); - - OUT_RING( (x << 16) | y ); - OUT_RING( (w << 16) | h ); - - ADVANCE_RING(); - } - - if ( flags & R128_BACK ) { - BEGIN_RING( 6 ); - - OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); - OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_SOLID_COLOR | - (dev_priv->color_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_P | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_AUX_CLIP_DIS ); - - OUT_RING( dev_priv->back_pitch_offset_c ); - OUT_RING( clear->clear_color ); - - OUT_RING( (x << 16) | y ); - OUT_RING( (w << 16) | h ); - - ADVANCE_RING(); - } - - if ( flags & R128_DEPTH ) { - BEGIN_RING( 6 ); - - OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); - OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_SOLID_COLOR | - (dev_priv->depth_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_P | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_AUX_CLIP_DIS | - R128_GMC_WR_MSK_DIS ); - - OUT_RING( dev_priv->depth_pitch_offset_c ); - OUT_RING( clear->clear_depth ); - - OUT_RING( (x << 16) | y ); - OUT_RING( (w << 16) | h ); - - ADVANCE_RING(); - } - } -} - -static void r128_cce_dispatch_swap( drm_device_t *dev ) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - int nbox = sarea_priv->nbox; - drm_clip_rect_t *pbox = sarea_priv->boxes; - int i; - RING_LOCALS; - DRM_DEBUG( "%s\n", __FUNCTION__ ); - -#if R128_PERFORMANCE_BOXES - /* Do some trivial performance monitoring... - */ - r128_cce_performance_boxes( dev_priv ); -#endif - - for ( i = 0 ; i < nbox ; i++ ) { - int x = pbox[i].x1; - int y = pbox[i].y1; - int w = pbox[i].x2 - x; - int h = pbox[i].y2 - y; - - BEGIN_RING( 7 ); - - OUT_RING( CCE_PACKET3( R128_CNTL_BITBLT_MULTI, 5 ) ); - OUT_RING( R128_GMC_SRC_PITCH_OFFSET_CNTL | - R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_NONE | - (dev_priv->color_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_S | - R128_DP_SRC_SOURCE_MEMORY | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_AUX_CLIP_DIS | - R128_GMC_WR_MSK_DIS ); - - /* Make this work even if front & back are flipped: - */ - if (dev_priv->current_page == 0) { - OUT_RING( dev_priv->back_pitch_offset_c ); - OUT_RING( dev_priv->front_pitch_offset_c ); - } - else { - OUT_RING( dev_priv->front_pitch_offset_c ); - OUT_RING( dev_priv->back_pitch_offset_c ); - } - - OUT_RING( (x << 16) | y ); - OUT_RING( (x << 16) | y ); - OUT_RING( (w << 16) | h ); - - ADVANCE_RING(); - } - - /* Increment the frame counter. The client-side 3D driver must - * throttle the framerate by waiting for this value before - * performing the swapbuffer ioctl. - */ - dev_priv->sarea_priv->last_frame++; - - BEGIN_RING( 2 ); - - OUT_RING( CCE_PACKET0( R128_LAST_FRAME_REG, 0 ) ); - OUT_RING( dev_priv->sarea_priv->last_frame ); - - ADVANCE_RING(); -} - -static void r128_cce_dispatch_flip( drm_device_t *dev ) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - RING_LOCALS; - DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n", - __FUNCTION__, - dev_priv->current_page, - dev_priv->sarea_priv->pfCurrentPage); - -#if R128_PERFORMANCE_BOXES - /* Do some trivial performance monitoring... - */ - r128_cce_performance_boxes( dev_priv ); -#endif - - BEGIN_RING( 4 ); - - R128_WAIT_UNTIL_PAGE_FLIPPED(); - OUT_RING( CCE_PACKET0( R128_CRTC_OFFSET, 0 ) ); - - if ( dev_priv->current_page == 0 ) { - OUT_RING( dev_priv->back_offset ); - } else { - OUT_RING( dev_priv->front_offset ); - } - - ADVANCE_RING(); - - /* Increment the frame counter. The client-side 3D driver must - * throttle the framerate by waiting for this value before - * performing the swapbuffer ioctl. - */ - dev_priv->sarea_priv->last_frame++; - dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page = - 1 - dev_priv->current_page; - - BEGIN_RING( 2 ); - - OUT_RING( CCE_PACKET0( R128_LAST_FRAME_REG, 0 ) ); - OUT_RING( dev_priv->sarea_priv->last_frame ); - - ADVANCE_RING(); -} - -static void r128_cce_dispatch_vertex( drm_device_t *dev, - drm_buf_t *buf ) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_buf_priv_t *buf_priv = buf->dev_private; - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - int format = sarea_priv->vc_format; - int offset = buf->bus_address; - int size = buf->used; - int prim = buf_priv->prim; - int i = 0; - RING_LOCALS; - DRM_DEBUG( "buf=%d nbox=%d\n", buf->idx, sarea_priv->nbox ); - - if ( 0 ) - r128_print_dirty( "dispatch_vertex", sarea_priv->dirty ); - - if ( buf->used ) { - buf_priv->dispatched = 1; - - if ( sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS ) { - r128_emit_state( dev_priv ); - } - - do { - /* Emit the next set of up to three cliprects */ - if ( i < sarea_priv->nbox ) { - r128_emit_clip_rects( dev_priv, - &sarea_priv->boxes[i], - sarea_priv->nbox - i ); - } - - /* Emit the vertex buffer rendering commands */ - BEGIN_RING( 5 ); - - OUT_RING( CCE_PACKET3( R128_3D_RNDR_GEN_INDX_PRIM, 3 ) ); - OUT_RING( offset ); - OUT_RING( size ); - OUT_RING( format ); - OUT_RING( prim | R128_CCE_VC_CNTL_PRIM_WALK_LIST | - (size << R128_CCE_VC_CNTL_NUM_SHIFT) ); - - ADVANCE_RING(); - - i += 3; - } while ( i < sarea_priv->nbox ); - } - - if ( buf_priv->discard ) { - buf_priv->age = dev_priv->sarea_priv->last_dispatch; - - /* Emit the vertex buffer age */ - BEGIN_RING( 2 ); - - OUT_RING( CCE_PACKET0( R128_LAST_DISPATCH_REG, 0 ) ); - OUT_RING( buf_priv->age ); - - ADVANCE_RING(); - - buf->pending = 1; - buf->used = 0; - /* FIXME: Check dispatched field */ - buf_priv->dispatched = 0; - } - - dev_priv->sarea_priv->last_dispatch++; - - sarea_priv->dirty &= ~R128_UPLOAD_CLIPRECTS; - sarea_priv->nbox = 0; -} - -static void r128_cce_dispatch_indirect( drm_device_t *dev, - drm_buf_t *buf, - int start, int end ) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_buf_priv_t *buf_priv = buf->dev_private; - RING_LOCALS; - DRM_DEBUG( "indirect: buf=%d s=0x%x e=0x%x\n", - buf->idx, start, end ); - - if ( start != end ) { - int offset = buf->bus_address + start; - int dwords = (end - start + 3) / sizeof(u32); - - /* Indirect buffer data must be an even number of - * dwords, so if we've been given an odd number we must - * pad the data with a Type-2 CCE packet. - */ - if ( dwords & 1 ) { - u32 *data = (u32 *) - ((char *)dev->agp_buffer_map->handle - + buf->offset + start); - data[dwords++] = cpu_to_le32( R128_CCE_PACKET2 ); - } - - buf_priv->dispatched = 1; - - /* Fire off the indirect buffer */ - BEGIN_RING( 3 ); - - OUT_RING( CCE_PACKET0( R128_PM4_IW_INDOFF, 1 ) ); - OUT_RING( offset ); - OUT_RING( dwords ); - - ADVANCE_RING(); - } - - if ( buf_priv->discard ) { - buf_priv->age = dev_priv->sarea_priv->last_dispatch; - - /* Emit the indirect buffer age */ - BEGIN_RING( 2 ); - - OUT_RING( CCE_PACKET0( R128_LAST_DISPATCH_REG, 0 ) ); - OUT_RING( buf_priv->age ); - - ADVANCE_RING(); - - buf->pending = 1; - buf->used = 0; - /* FIXME: Check dispatched field */ - buf_priv->dispatched = 0; - } - - dev_priv->sarea_priv->last_dispatch++; -} - -static void r128_cce_dispatch_indices( drm_device_t *dev, - drm_buf_t *buf, - int start, int end, - int count ) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_buf_priv_t *buf_priv = buf->dev_private; - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - int format = sarea_priv->vc_format; - int offset = dev->agp_buffer_map->offset - dev_priv->cce_buffers_offset; - int prim = buf_priv->prim; - u32 *data; - int dwords; - int i = 0; - RING_LOCALS; - DRM_DEBUG( "indices: s=%d e=%d c=%d\n", start, end, count ); - - if ( 0 ) - r128_print_dirty( "dispatch_indices", sarea_priv->dirty ); - - if ( start != end ) { - buf_priv->dispatched = 1; - - if ( sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS ) { - r128_emit_state( dev_priv ); - } - - dwords = (end - start + 3) / sizeof(u32); - - data = (u32 *)((char *)dev->agp_buffer_map->handle - + buf->offset + start); - - data[0] = cpu_to_le32( CCE_PACKET3( R128_3D_RNDR_GEN_INDX_PRIM, - dwords-2 ) ); - - data[1] = cpu_to_le32( offset ); - data[2] = cpu_to_le32( R128_MAX_VB_VERTS ); - data[3] = cpu_to_le32( format ); - data[4] = cpu_to_le32( (prim | R128_CCE_VC_CNTL_PRIM_WALK_IND | - (count << 16)) ); - - if ( count & 0x1 ) { -#ifdef __LITTLE_ENDIAN - data[dwords-1] &= 0x0000ffff; -#else - data[dwords-1] &= 0xffff0000; -#endif - } - - do { - /* Emit the next set of up to three cliprects */ - if ( i < sarea_priv->nbox ) { - r128_emit_clip_rects( dev_priv, - &sarea_priv->boxes[i], - sarea_priv->nbox - i ); - } - - r128_cce_dispatch_indirect( dev, buf, start, end ); - - i += 3; - } while ( i < sarea_priv->nbox ); - } - - if ( buf_priv->discard ) { - buf_priv->age = dev_priv->sarea_priv->last_dispatch; - - /* Emit the vertex buffer age */ - BEGIN_RING( 2 ); - - OUT_RING( CCE_PACKET0( R128_LAST_DISPATCH_REG, 0 ) ); - OUT_RING( buf_priv->age ); - - ADVANCE_RING(); - - buf->pending = 1; - /* FIXME: Check dispatched field */ - buf_priv->dispatched = 0; - } - - dev_priv->sarea_priv->last_dispatch++; - - sarea_priv->dirty &= ~R128_UPLOAD_CLIPRECTS; - sarea_priv->nbox = 0; -} - -static int r128_cce_dispatch_blit( DRMFILE filp, - drm_device_t *dev, - drm_r128_blit_t *blit ) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - drm_device_dma_t *dma = dev->dma; - drm_buf_t *buf; - drm_r128_buf_priv_t *buf_priv; - u32 *data; - int dword_shift, dwords; - RING_LOCALS; - DRM_DEBUG( "\n" ); - - /* The compiler won't optimize away a division by a variable, - * even if the only legal values are powers of two. Thus, we'll - * use a shift instead. - */ - switch ( blit->format ) { - case R128_DATATYPE_ARGB8888: - dword_shift = 0; - break; - case R128_DATATYPE_ARGB1555: - case R128_DATATYPE_RGB565: - case R128_DATATYPE_ARGB4444: - case R128_DATATYPE_YVYU422: - case R128_DATATYPE_VYUY422: - dword_shift = 1; - break; - case R128_DATATYPE_CI8: - case R128_DATATYPE_RGB8: - dword_shift = 2; - break; - default: - DRM_ERROR( "invalid blit format %d\n", blit->format ); - return DRM_ERR(EINVAL); - } - - /* Flush the pixel cache, and mark the contents as Read Invalid. - * This ensures no pixel data gets mixed up with the texture - * data from the host data blit, otherwise part of the texture - * image may be corrupted. - */ - BEGIN_RING( 2 ); - - OUT_RING( CCE_PACKET0( R128_PC_GUI_CTLSTAT, 0 ) ); - OUT_RING( R128_PC_RI_GUI | R128_PC_FLUSH_GUI ); - - ADVANCE_RING(); - - /* Dispatch the indirect buffer. - */ - buf = dma->buflist[blit->idx]; - buf_priv = buf->dev_private; - - if ( buf->filp != filp ) { - DRM_ERROR( "process %d using buffer owned by %p\n", - DRM_CURRENTPID, buf->filp ); - return DRM_ERR(EINVAL); - } - if ( buf->pending ) { - DRM_ERROR( "sending pending buffer %d\n", blit->idx ); - return DRM_ERR(EINVAL); - } - - buf_priv->discard = 1; - - dwords = (blit->width * blit->height) >> dword_shift; - - data = (u32 *)((char *)dev->agp_buffer_map->handle + buf->offset); - - data[0] = cpu_to_le32( CCE_PACKET3( R128_CNTL_HOSTDATA_BLT, dwords + 6 ) ); - data[1] = cpu_to_le32( (R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_NONE | - (blit->format << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_S | - R128_DP_SRC_SOURCE_HOST_DATA | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_AUX_CLIP_DIS | - R128_GMC_WR_MSK_DIS) ); - - data[2] = cpu_to_le32( (blit->pitch << 21) | (blit->offset >> 5) ); - data[3] = cpu_to_le32( 0xffffffff ); - data[4] = cpu_to_le32( 0xffffffff ); - data[5] = cpu_to_le32( (blit->y << 16) | blit->x ); - data[6] = cpu_to_le32( (blit->height << 16) | blit->width ); - data[7] = cpu_to_le32( dwords ); - - buf->used = (dwords + 8) * sizeof(u32); - - r128_cce_dispatch_indirect( dev, buf, 0, buf->used ); - - /* Flush the pixel cache after the blit completes. This ensures - * the texture data is written out to memory before rendering - * continues. - */ - BEGIN_RING( 2 ); - - OUT_RING( CCE_PACKET0( R128_PC_GUI_CTLSTAT, 0 ) ); - OUT_RING( R128_PC_FLUSH_GUI ); - - ADVANCE_RING(); - - return 0; -} - - -/* ================================================================ - * Tiled depth buffer management - * - * FIXME: These should all set the destination write mask for when we - * have hardware stencil support. - */ - -static int r128_cce_dispatch_write_span( drm_device_t *dev, - drm_r128_depth_t *depth ) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - int count, x, y; - u32 *buffer; - u8 *mask; - int i, buffer_size, mask_size; - RING_LOCALS; - DRM_DEBUG( "\n" ); - - count = depth->n; - if (count > 4096 || count <= 0) - return DRM_ERR(EMSGSIZE); - - if ( DRM_COPY_FROM_USER( &x, depth->x, sizeof(x) ) ) { - return DRM_ERR(EFAULT); - } - if ( DRM_COPY_FROM_USER( &y, depth->y, sizeof(y) ) ) { - return DRM_ERR(EFAULT); - } - - buffer_size = depth->n * sizeof(u32); - buffer = DRM(alloc)( buffer_size, DRM_MEM_BUFS ); - if ( buffer == NULL ) - return DRM_ERR(ENOMEM); - if ( DRM_COPY_FROM_USER( buffer, depth->buffer, buffer_size ) ) { - DRM(free)( buffer, buffer_size, DRM_MEM_BUFS); - return DRM_ERR(EFAULT); - } - - mask_size = depth->n * sizeof(u8); - if ( depth->mask ) { - mask = DRM(alloc)( mask_size, DRM_MEM_BUFS ); - if ( mask == NULL ) { - DRM(free)( buffer, buffer_size, DRM_MEM_BUFS ); - return DRM_ERR(ENOMEM); - } - if ( DRM_COPY_FROM_USER( mask, depth->mask, mask_size ) ) { - DRM(free)( buffer, buffer_size, DRM_MEM_BUFS ); - DRM(free)( mask, mask_size, DRM_MEM_BUFS ); - return DRM_ERR(EFAULT); - } - - for ( i = 0 ; i < count ; i++, x++ ) { - if ( mask[i] ) { - BEGIN_RING( 6 ); - - OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); - OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_SOLID_COLOR | - (dev_priv->depth_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_P | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_WR_MSK_DIS ); - - OUT_RING( dev_priv->depth_pitch_offset_c ); - OUT_RING( buffer[i] ); - - OUT_RING( (x << 16) | y ); - OUT_RING( (1 << 16) | 1 ); - - ADVANCE_RING(); - } - } - - DRM(free)( mask, mask_size, DRM_MEM_BUFS ); - } else { - for ( i = 0 ; i < count ; i++, x++ ) { - BEGIN_RING( 6 ); - - OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); - OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_SOLID_COLOR | - (dev_priv->depth_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_P | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_WR_MSK_DIS ); - - OUT_RING( dev_priv->depth_pitch_offset_c ); - OUT_RING( buffer[i] ); - - OUT_RING( (x << 16) | y ); - OUT_RING( (1 << 16) | 1 ); - - ADVANCE_RING(); - } - } - - DRM(free)( buffer, buffer_size, DRM_MEM_BUFS ); - - return 0; -} - -static int r128_cce_dispatch_write_pixels( drm_device_t *dev, - drm_r128_depth_t *depth ) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - int count, *x, *y; - u32 *buffer; - u8 *mask; - int i, xbuf_size, ybuf_size, buffer_size, mask_size; - RING_LOCALS; - DRM_DEBUG( "\n" ); - - count = depth->n; - if (count > 4096 || count <= 0) - return DRM_ERR(EMSGSIZE); - - xbuf_size = count * sizeof(*x); - ybuf_size = count * sizeof(*y); - x = DRM(alloc)( xbuf_size, DRM_MEM_BUFS ); - if ( x == NULL ) { - return DRM_ERR(ENOMEM); - } - y = DRM(alloc)( ybuf_size, DRM_MEM_BUFS ); - if ( y == NULL ) { - DRM(free)( x, xbuf_size, DRM_MEM_BUFS ); - return DRM_ERR(ENOMEM); - } - if ( DRM_COPY_FROM_USER( x, depth->x, xbuf_size ) ) { - DRM(free)( x, xbuf_size, DRM_MEM_BUFS ); - DRM(free)( y, ybuf_size, DRM_MEM_BUFS ); - return DRM_ERR(EFAULT); - } - if ( DRM_COPY_FROM_USER( y, depth->y, xbuf_size ) ) { - DRM(free)( x, xbuf_size, DRM_MEM_BUFS ); - DRM(free)( y, ybuf_size, DRM_MEM_BUFS ); - return DRM_ERR(EFAULT); - } - - buffer_size = depth->n * sizeof(u32); - buffer = DRM(alloc)( buffer_size, DRM_MEM_BUFS ); - if ( buffer == NULL ) { - DRM(free)( x, xbuf_size, DRM_MEM_BUFS ); - DRM(free)( y, ybuf_size, DRM_MEM_BUFS ); - return DRM_ERR(ENOMEM); - } - if ( DRM_COPY_FROM_USER( buffer, depth->buffer, buffer_size ) ) { - DRM(free)( x, xbuf_size, DRM_MEM_BUFS ); - DRM(free)( y, ybuf_size, DRM_MEM_BUFS ); - DRM(free)( buffer, buffer_size, DRM_MEM_BUFS ); - return DRM_ERR(EFAULT); - } - - if ( depth->mask ) { - mask_size = depth->n * sizeof(u8); - mask = DRM(alloc)( mask_size, DRM_MEM_BUFS ); - if ( mask == NULL ) { - DRM(free)( x, xbuf_size, DRM_MEM_BUFS ); - DRM(free)( y, ybuf_size, DRM_MEM_BUFS ); - DRM(free)( buffer, buffer_size, DRM_MEM_BUFS ); - return DRM_ERR(ENOMEM); - } - if ( DRM_COPY_FROM_USER( mask, depth->mask, mask_size ) ) { - DRM(free)( x, xbuf_size, DRM_MEM_BUFS ); - DRM(free)( y, ybuf_size, DRM_MEM_BUFS ); - DRM(free)( buffer, buffer_size, DRM_MEM_BUFS ); - DRM(free)( mask, mask_size, DRM_MEM_BUFS ); - return DRM_ERR(EFAULT); - } - - for ( i = 0 ; i < count ; i++ ) { - if ( mask[i] ) { - BEGIN_RING( 6 ); - - OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); - OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_SOLID_COLOR | - (dev_priv->depth_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_P | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_WR_MSK_DIS ); - - OUT_RING( dev_priv->depth_pitch_offset_c ); - OUT_RING( buffer[i] ); - - OUT_RING( (x[i] << 16) | y[i] ); - OUT_RING( (1 << 16) | 1 ); - - ADVANCE_RING(); - } - } - - DRM(free)( mask, mask_size, DRM_MEM_BUFS ); - } else { - for ( i = 0 ; i < count ; i++ ) { - BEGIN_RING( 6 ); - - OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); - OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_SOLID_COLOR | - (dev_priv->depth_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_P | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_WR_MSK_DIS ); - - OUT_RING( dev_priv->depth_pitch_offset_c ); - OUT_RING( buffer[i] ); - - OUT_RING( (x[i] << 16) | y[i] ); - OUT_RING( (1 << 16) | 1 ); - - ADVANCE_RING(); - } - } - - DRM(free)( x, xbuf_size, DRM_MEM_BUFS ); - DRM(free)( y, ybuf_size, DRM_MEM_BUFS ); - DRM(free)( buffer, buffer_size, DRM_MEM_BUFS ); - - return 0; -} - -static int r128_cce_dispatch_read_span( drm_device_t *dev, - drm_r128_depth_t *depth ) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - int count, x, y; - RING_LOCALS; - DRM_DEBUG( "\n" ); - - count = depth->n; - if (count > 4096 || count <= 0) - return DRM_ERR(EMSGSIZE); - - if ( DRM_COPY_FROM_USER( &x, depth->x, sizeof(x) ) ) { - return DRM_ERR(EFAULT); - } - if ( DRM_COPY_FROM_USER( &y, depth->y, sizeof(y) ) ) { - return DRM_ERR(EFAULT); - } - - BEGIN_RING( 7 ); - - OUT_RING( CCE_PACKET3( R128_CNTL_BITBLT_MULTI, 5 ) ); - OUT_RING( R128_GMC_SRC_PITCH_OFFSET_CNTL | - R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_NONE | - (dev_priv->depth_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_S | - R128_DP_SRC_SOURCE_MEMORY | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_WR_MSK_DIS ); - - OUT_RING( dev_priv->depth_pitch_offset_c ); - OUT_RING( dev_priv->span_pitch_offset_c ); - - OUT_RING( (x << 16) | y ); - OUT_RING( (0 << 16) | 0 ); - OUT_RING( (count << 16) | 1 ); - - ADVANCE_RING(); - - return 0; -} - -static int r128_cce_dispatch_read_pixels( drm_device_t *dev, - drm_r128_depth_t *depth ) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - int count, *x, *y; - int i, xbuf_size, ybuf_size; - RING_LOCALS; - DRM_DEBUG( "%s\n", __FUNCTION__ ); - - count = depth->n; - if (count > 4096 || count <= 0) - return DRM_ERR(EMSGSIZE); - - if ( count > dev_priv->depth_pitch ) { - count = dev_priv->depth_pitch; - } - - xbuf_size = count * sizeof(*x); - ybuf_size = count * sizeof(*y); - x = DRM(alloc)( xbuf_size, DRM_MEM_BUFS ); - if ( x == NULL ) { - return DRM_ERR(ENOMEM); - } - y = DRM(alloc)( ybuf_size, DRM_MEM_BUFS ); - if ( y == NULL ) { - DRM(free)( x, xbuf_size, DRM_MEM_BUFS ); - return DRM_ERR(ENOMEM); - } - if ( DRM_COPY_FROM_USER( x, depth->x, xbuf_size ) ) { - DRM(free)( x, xbuf_size, DRM_MEM_BUFS ); - DRM(free)( y, ybuf_size, DRM_MEM_BUFS ); - return DRM_ERR(EFAULT); - } - if ( DRM_COPY_FROM_USER( y, depth->y, ybuf_size ) ) { - DRM(free)( x, xbuf_size, DRM_MEM_BUFS ); - DRM(free)( y, ybuf_size, DRM_MEM_BUFS ); - return DRM_ERR(EFAULT); - } - - for ( i = 0 ; i < count ; i++ ) { - BEGIN_RING( 7 ); - - OUT_RING( CCE_PACKET3( R128_CNTL_BITBLT_MULTI, 5 ) ); - OUT_RING( R128_GMC_SRC_PITCH_OFFSET_CNTL | - R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_NONE | - (dev_priv->depth_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_S | - R128_DP_SRC_SOURCE_MEMORY | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_WR_MSK_DIS ); - - OUT_RING( dev_priv->depth_pitch_offset_c ); - OUT_RING( dev_priv->span_pitch_offset_c ); - - OUT_RING( (x[i] << 16) | y[i] ); - OUT_RING( (i << 16) | 0 ); - OUT_RING( (1 << 16) | 1 ); - - ADVANCE_RING(); - } - - DRM(free)( x, xbuf_size, DRM_MEM_BUFS ); - DRM(free)( y, ybuf_size, DRM_MEM_BUFS ); - - return 0; -} - - -/* ================================================================ - * Polygon stipple - */ - -static void r128_cce_dispatch_stipple( drm_device_t *dev, u32 *stipple ) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - int i; - RING_LOCALS; - DRM_DEBUG( "%s\n", __FUNCTION__ ); - - BEGIN_RING( 33 ); - - OUT_RING( CCE_PACKET0( R128_BRUSH_DATA0, 31 ) ); - for ( i = 0 ; i < 32 ; i++ ) { - OUT_RING( stipple[i] ); - } - - ADVANCE_RING(); -} - - -/* ================================================================ - * IOCTL functions - */ - -int r128_cce_clear( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_r128_clear_t clear; - DRM_DEBUG( "\n" ); - - LOCK_TEST_WITH_RETURN( dev, filp ); - - DRM_COPY_FROM_USER_IOCTL( clear, (drm_r128_clear_t __user *) data, - sizeof(clear) ); - - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - - if ( sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS ) - sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS; - - r128_cce_dispatch_clear( dev, &clear ); - COMMIT_RING(); - - /* Make sure we restore the 3D state next time. - */ - dev_priv->sarea_priv->dirty |= R128_UPLOAD_CONTEXT | R128_UPLOAD_MASKS; - - return 0; -} - -static int r128_do_init_pageflip( drm_device_t *dev ) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "\n" ); - - dev_priv->crtc_offset = R128_READ( R128_CRTC_OFFSET ); - dev_priv->crtc_offset_cntl = R128_READ( R128_CRTC_OFFSET_CNTL ); - - R128_WRITE( R128_CRTC_OFFSET, dev_priv->front_offset ); - R128_WRITE( R128_CRTC_OFFSET_CNTL, - dev_priv->crtc_offset_cntl | R128_CRTC_OFFSET_FLIP_CNTL ); - - dev_priv->page_flipping = 1; - dev_priv->current_page = 0; - dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page; - - return 0; -} - -int r128_do_cleanup_pageflip( drm_device_t *dev ) -{ - drm_r128_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "\n" ); - - R128_WRITE( R128_CRTC_OFFSET, dev_priv->crtc_offset ); - R128_WRITE( R128_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl ); - - if (dev_priv->current_page != 0) { - r128_cce_dispatch_flip( dev ); - COMMIT_RING(); - } - - dev_priv->page_flipping = 0; - return 0; -} - -/* Swapping and flipping are different operations, need different ioctls. - * They can & should be intermixed to support multiple 3d windows. - */ - -int r128_cce_flip( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_r128_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "%s\n", __FUNCTION__ ); - - LOCK_TEST_WITH_RETURN( dev, filp ); - - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - - if (!dev_priv->page_flipping) - r128_do_init_pageflip( dev ); - - r128_cce_dispatch_flip( dev ); - - COMMIT_RING(); - return 0; -} - -int r128_cce_swap( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - DRM_DEBUG( "%s\n", __FUNCTION__ ); - - LOCK_TEST_WITH_RETURN( dev, filp ); - - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - - if ( sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS ) - sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS; - - r128_cce_dispatch_swap( dev ); - dev_priv->sarea_priv->dirty |= (R128_UPLOAD_CONTEXT | - R128_UPLOAD_MASKS); - - COMMIT_RING(); - return 0; -} - -int r128_cce_vertex( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_r128_private_t *dev_priv = dev->dev_private; - drm_device_dma_t *dma = dev->dma; - drm_buf_t *buf; - drm_r128_buf_priv_t *buf_priv; - drm_r128_vertex_t vertex; - - LOCK_TEST_WITH_RETURN( dev, filp ); - - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); - return DRM_ERR(EINVAL); - } - - DRM_COPY_FROM_USER_IOCTL( vertex, (drm_r128_vertex_t __user *) data, - sizeof(vertex) ); - - DRM_DEBUG( "pid=%d index=%d count=%d discard=%d\n", - DRM_CURRENTPID, - vertex.idx, vertex.count, vertex.discard ); - - if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) { - DRM_ERROR( "buffer index %d (of %d max)\n", - vertex.idx, dma->buf_count - 1 ); - return DRM_ERR(EINVAL); - } - if ( vertex.prim < 0 || - vertex.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 ) { - DRM_ERROR( "buffer prim %d\n", vertex.prim ); - return DRM_ERR(EINVAL); - } - - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - VB_AGE_TEST_WITH_RETURN( dev_priv ); - - buf = dma->buflist[vertex.idx]; - buf_priv = buf->dev_private; - - if ( buf->filp != filp ) { - DRM_ERROR( "process %d using buffer owned by %p\n", - DRM_CURRENTPID, buf->filp ); - return DRM_ERR(EINVAL); - } - if ( buf->pending ) { - DRM_ERROR( "sending pending buffer %d\n", vertex.idx ); - return DRM_ERR(EINVAL); - } - - buf->used = vertex.count; - buf_priv->prim = vertex.prim; - buf_priv->discard = vertex.discard; - - r128_cce_dispatch_vertex( dev, buf ); - - COMMIT_RING(); - return 0; -} - -int r128_cce_indices( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_r128_private_t *dev_priv = dev->dev_private; - drm_device_dma_t *dma = dev->dma; - drm_buf_t *buf; - drm_r128_buf_priv_t *buf_priv; - drm_r128_indices_t elts; - int count; - - LOCK_TEST_WITH_RETURN( dev, filp ); - - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); - return DRM_ERR(EINVAL); - } - - DRM_COPY_FROM_USER_IOCTL( elts, (drm_r128_indices_t __user *) data, - sizeof(elts) ); - - DRM_DEBUG( "pid=%d buf=%d s=%d e=%d d=%d\n", DRM_CURRENTPID, - elts.idx, elts.start, elts.end, elts.discard ); - - if ( elts.idx < 0 || elts.idx >= dma->buf_count ) { - DRM_ERROR( "buffer index %d (of %d max)\n", - elts.idx, dma->buf_count - 1 ); - return DRM_ERR(EINVAL); - } - if ( elts.prim < 0 || - elts.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 ) { - DRM_ERROR( "buffer prim %d\n", elts.prim ); - return DRM_ERR(EINVAL); - } - - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - VB_AGE_TEST_WITH_RETURN( dev_priv ); - - buf = dma->buflist[elts.idx]; - buf_priv = buf->dev_private; - - if ( buf->filp != filp ) { - DRM_ERROR( "process %d using buffer owned by %p\n", - DRM_CURRENTPID, buf->filp ); - return DRM_ERR(EINVAL); - } - if ( buf->pending ) { - DRM_ERROR( "sending pending buffer %d\n", elts.idx ); - return DRM_ERR(EINVAL); - } - - count = (elts.end - elts.start) / sizeof(u16); - elts.start -= R128_INDEX_PRIM_OFFSET; - - if ( elts.start & 0x7 ) { - DRM_ERROR( "misaligned buffer 0x%x\n", elts.start ); - return DRM_ERR(EINVAL); - } - if ( elts.start < buf->used ) { - DRM_ERROR( "no header 0x%x - 0x%x\n", elts.start, buf->used ); - return DRM_ERR(EINVAL); - } - - buf->used = elts.end; - buf_priv->prim = elts.prim; - buf_priv->discard = elts.discard; - - r128_cce_dispatch_indices( dev, buf, elts.start, elts.end, count ); - - COMMIT_RING(); - return 0; -} - -int r128_cce_blit( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_device_dma_t *dma = dev->dma; - drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_blit_t blit; - int ret; - - LOCK_TEST_WITH_RETURN( dev, filp ); - - DRM_COPY_FROM_USER_IOCTL( blit, (drm_r128_blit_t __user *) data, - sizeof(blit) ); - - DRM_DEBUG( "pid=%d index=%d\n", DRM_CURRENTPID, blit.idx ); - - if ( blit.idx < 0 || blit.idx >= dma->buf_count ) { - DRM_ERROR( "buffer index %d (of %d max)\n", - blit.idx, dma->buf_count - 1 ); - return DRM_ERR(EINVAL); - } - - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - VB_AGE_TEST_WITH_RETURN( dev_priv ); - - ret = r128_cce_dispatch_blit( filp, dev, &blit ); - - COMMIT_RING(); - return ret; -} - -int r128_cce_depth( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_depth_t depth; - int ret; - - LOCK_TEST_WITH_RETURN( dev, filp ); - - DRM_COPY_FROM_USER_IOCTL( depth, (drm_r128_depth_t __user *) data, - sizeof(depth) ); - - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - - ret = DRM_ERR(EINVAL); - switch ( depth.func ) { - case R128_WRITE_SPAN: - ret = r128_cce_dispatch_write_span( dev, &depth ); - case R128_WRITE_PIXELS: - ret = r128_cce_dispatch_write_pixels( dev, &depth ); - case R128_READ_SPAN: - ret = r128_cce_dispatch_read_span( dev, &depth ); - case R128_READ_PIXELS: - ret = r128_cce_dispatch_read_pixels( dev, &depth ); - } - - COMMIT_RING(); - return ret; -} - -int r128_cce_stipple( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_stipple_t stipple; - u32 mask[32]; - - LOCK_TEST_WITH_RETURN( dev, filp ); - - DRM_COPY_FROM_USER_IOCTL( stipple, (drm_r128_stipple_t __user *) data, - sizeof(stipple) ); - - if ( DRM_COPY_FROM_USER( &mask, stipple.mask, - 32 * sizeof(u32) ) ) - return DRM_ERR( EFAULT ); - - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - - r128_cce_dispatch_stipple( dev, mask ); - - COMMIT_RING(); - return 0; -} - -int r128_cce_indirect( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_r128_private_t *dev_priv = dev->dev_private; - drm_device_dma_t *dma = dev->dma; - drm_buf_t *buf; - drm_r128_buf_priv_t *buf_priv; - drm_r128_indirect_t indirect; -#if 0 - RING_LOCALS; -#endif - - LOCK_TEST_WITH_RETURN( dev, filp ); - - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); - return DRM_ERR(EINVAL); - } - - DRM_COPY_FROM_USER_IOCTL( indirect, (drm_r128_indirect_t __user *) data, - sizeof(indirect) ); - - DRM_DEBUG( "indirect: idx=%d s=%d e=%d d=%d\n", - indirect.idx, indirect.start, - indirect.end, indirect.discard ); - - if ( indirect.idx < 0 || indirect.idx >= dma->buf_count ) { - DRM_ERROR( "buffer index %d (of %d max)\n", - indirect.idx, dma->buf_count - 1 ); - return DRM_ERR(EINVAL); - } - - buf = dma->buflist[indirect.idx]; - buf_priv = buf->dev_private; - - if ( buf->filp != filp ) { - DRM_ERROR( "process %d using buffer owned by %p\n", - DRM_CURRENTPID, buf->filp ); - return DRM_ERR(EINVAL); - } - if ( buf->pending ) { - DRM_ERROR( "sending pending buffer %d\n", indirect.idx ); - return DRM_ERR(EINVAL); - } - - if ( indirect.start < buf->used ) { - DRM_ERROR( "reusing indirect: start=0x%x actual=0x%x\n", - indirect.start, buf->used ); - return DRM_ERR(EINVAL); - } - - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - VB_AGE_TEST_WITH_RETURN( dev_priv ); - - buf->used = indirect.end; - buf_priv->discard = indirect.discard; - -#if 0 - /* Wait for the 3D stream to idle before the indirect buffer - * containing 2D acceleration commands is processed. - */ - BEGIN_RING( 2 ); - RADEON_WAIT_UNTIL_3D_IDLE(); - ADVANCE_RING(); -#endif - - /* Dispatch the indirect buffer full of commands from the - * X server. This is insecure and is thus only available to - * privileged clients. - */ - r128_cce_dispatch_indirect( dev, buf, indirect.start, indirect.end ); - - COMMIT_RING(); - return 0; -} - -int r128_getparam( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_r128_private_t *dev_priv = dev->dev_private; - drm_r128_getparam_t param; - int value; - - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); - return DRM_ERR(EINVAL); - } - - DRM_COPY_FROM_USER_IOCTL( param, (drm_r128_getparam_t __user *)data, - sizeof(param) ); - - DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID ); - - switch( param.param ) { - case R128_PARAM_IRQ_NR: - value = dev->irq; - break; - default: - return DRM_ERR(EINVAL); - } - - if ( DRM_COPY_TO_USER( param.value, &value, sizeof(int) ) ) { - DRM_ERROR( "copy_to_user\n" ); - return DRM_ERR(EFAULT); - } - - return 0; -} - -static void r128_driver_prerelease(drm_device_t *dev, DRMFILE filp) -{ - if ( dev->dev_private ) { - drm_r128_private_t *dev_priv = dev->dev_private; - if ( dev_priv->page_flipping ) { - r128_do_cleanup_pageflip( dev ); - } - } -} - -static void r128_driver_pretakedown(drm_device_t *dev) -{ - r128_do_cleanup_cce( dev ); -} - -void r128_driver_register_fns(drm_device_t *dev) -{ - dev->driver_features = DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG | DRIVER_HAVE_DMA | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_IRQ_VBL; - dev->dev_priv_size = sizeof(drm_r128_buf_priv_t); - dev->fn_tbl.prerelease = r128_driver_prerelease; - dev->fn_tbl.pretakedown = r128_driver_pretakedown; - dev->fn_tbl.vblank_wait = r128_driver_vblank_wait; - dev->fn_tbl.irq_preinstall = r128_driver_irq_preinstall; - dev->fn_tbl.irq_postinstall = r128_driver_irq_postinstall; - dev->fn_tbl.irq_uninstall = r128_driver_irq_uninstall; - dev->fn_tbl.irq_handler = r128_driver_irq_handler; -} diff --git a/nx-X11/extras/drm/shared/radeon.h b/nx-X11/extras/drm/shared/radeon.h deleted file mode 100644 index 23946a8ad..000000000 --- a/nx-X11/extras/drm/shared/radeon.h +++ /dev/null @@ -1,124 +0,0 @@ -/* radeon.h -- ATI Radeon DRM template customization -*- linux-c -*- - * Created: Wed Feb 14 17:07:34 2001 by gareth@valinux.com - * - * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Gareth Hughes - * Keith Whitwell - */ - -#ifndef __RADEON_H__ -#define __RADEON_H__ - -/* This remains constant for all DRM template files. - */ -#define DRM(x) radeon_##x - -/* General customization: - */ - -#define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others." - -#define DRIVER_NAME "radeon" -#define DRIVER_DESC "ATI Radeon" -#define DRIVER_DATE "20050311" - -#define DRIVER_MAJOR 1 -#define DRIVER_MINOR 16 -#define DRIVER_PATCHLEVEL 0 - -/* Interface history: - * - * 1.1 - ?? - * 1.2 - Add vertex2 ioctl (keith) - * - Add stencil capability to clear ioctl (gareth, keith) - * - Increase MAX_TEXTURE_LEVELS (brian) - * 1.3 - Add cmdbuf ioctl (keith) - * - Add support for new radeon packets (keith) - * - Add getparam ioctl (keith) - * - Add flip-buffers ioctl, deprecate fullscreen foo (keith). - * 1.4 - Add scratch registers to get_param ioctl. - * 1.5 - Add r200 packets to cmdbuf ioctl - * - Add r200 function to init ioctl - * - Add 'scalar2' instruction to cmdbuf - * 1.6 - Add static GART memory manager - * Add irq handler (won't be turned on unless X server knows to) - * Add irq ioctls and irq_active getparam. - * Add wait command for cmdbuf ioctl - * Add GART offset query for getparam - * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5] - * and R200_PP_CUBIC_OFFSET_F1_[0..5]. - * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and - * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian) - * 1.8 - Remove need to call cleanup ioctls on last client exit (keith) - * Add 'GET' queries for starting additional clients on different VT's. - * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl. - * Add texture rectangle support for r100. - * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which - * clients use to tell the DRM where they think the framebuffer is - * located in the card's address space - * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color - * and GL_EXT_blend_[func|equation]_separate on r200 - * 1.12- Add R300 CP microcode support - this just loads the CP on r300 - * (No 3D support yet - just microcode loading). - * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters - * - Add hyperz support, add hyperz flags to clear ioctl. - * 1.14- Add support for color tiling - * - Add R100/R200 surface allocation/free support - * 1.15- Add support for texture micro tiling - * - Add support for r100 cube maps - * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear - * texture filtering on r200 - */ -#define DRIVER_IOCTLS \ - [DRM_IOCTL_NR(DRM_IOCTL_DMA)] = { radeon_cp_buffers, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_INIT)] = { radeon_cp_init, 1, 1 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_START)] = { radeon_cp_start, 1, 1 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_STOP)] = { radeon_cp_stop, 1, 1 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_RESET)] = { radeon_cp_reset, 1, 1 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_IDLE)] = { radeon_cp_idle, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_RESUME)] = { radeon_cp_resume, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_RADEON_RESET)] = { radeon_engine_reset, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_RADEON_FULLSCREEN)] = { radeon_fullscreen, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_RADEON_SWAP)] = { radeon_cp_swap, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CLEAR)] = { radeon_cp_clear, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_RADEON_VERTEX)] = { radeon_cp_vertex, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_RADEON_INDICES)] = { radeon_cp_indices, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_RADEON_TEXTURE)] = { radeon_cp_texture, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_RADEON_STIPPLE)] = { radeon_cp_stipple, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_RADEON_INDIRECT)] = { radeon_cp_indirect, 1, 1 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_RADEON_VERTEX2)] = { radeon_cp_vertex2, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CMDBUF)] = { radeon_cp_cmdbuf, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_RADEON_GETPARAM)] = { radeon_cp_getparam, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_RADEON_FLIP)] = { radeon_cp_flip, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_RADEON_ALLOC)] = { radeon_mem_alloc, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_RADEON_FREE)] = { radeon_mem_free, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_RADEON_INIT_HEAP)] = { radeon_mem_init_heap, 1, 1 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_RADEON_IRQ_EMIT)] = { radeon_irq_emit, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_RADEON_IRQ_WAIT)] = { radeon_irq_wait, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_RADEON_SETPARAM)] = { radeon_cp_setparam, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_RADEON_SURF_ALLOC)] = { radeon_surface_alloc, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_RADEON_SURF_FREE)] = { radeon_surface_free, 1, 0 }, \ - -#endif diff --git a/nx-X11/extras/drm/shared/radeon_cp.c b/nx-X11/extras/drm/shared/radeon_cp.c deleted file mode 100644 index dfb8b734a..000000000 --- a/nx-X11/extras/drm/shared/radeon_cp.c +++ /dev/null @@ -1,2092 +0,0 @@ -/* radeon_cp.c -- CP support for Radeon -*- linux-c -*- - * - * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. - * Copyright 2000 VA Linux Systems, Inc., Fremont, California. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Kevin E. Martin - * Gareth Hughes - */ - -#include "radeon.h" -#include "drmP.h" -#include "drm.h" -#include "radeon_drm.h" -#include "radeon_drv.h" - -#define RADEON_FIFO_DEBUG 0 - -/* CP microcode (from ATI) */ -static u32 R200_cp_microcode[][2] = { - { 0x21007000, 0000000000 }, - { 0x20007000, 0000000000 }, - { 0x000000ab, 0x00000004 }, - { 0x000000af, 0x00000004 }, - { 0x66544a49, 0000000000 }, - { 0x49494174, 0000000000 }, - { 0x54517d83, 0000000000 }, - { 0x498d8b64, 0000000000 }, - { 0x49494949, 0000000000 }, - { 0x49da493c, 0000000000 }, - { 0x49989898, 0000000000 }, - { 0xd34949d5, 0000000000 }, - { 0x9dc90e11, 0000000000 }, - { 0xce9b9b9b, 0000000000 }, - { 0x000f0000, 0x00000016 }, - { 0x352e232c, 0000000000 }, - { 0x00000013, 0x00000004 }, - { 0x000f0000, 0x00000016 }, - { 0x352e272c, 0000000000 }, - { 0x000f0001, 0x00000016 }, - { 0x3239362f, 0000000000 }, - { 0x000077ef, 0x00000002 }, - { 0x00061000, 0x00000002 }, - { 0x00000020, 0x0000001a }, - { 0x00004000, 0x0000001e }, - { 0x00061000, 0x00000002 }, - { 0x00000020, 0x0000001a }, - { 0x00004000, 0x0000001e }, - { 0x00061000, 0x00000002 }, - { 0x00000020, 0x0000001a }, - { 0x00004000, 0x0000001e }, - { 0x00000016, 0x00000004 }, - { 0x0003802a, 0x00000002 }, - { 0x040067e0, 0x00000002 }, - { 0x00000016, 0x00000004 }, - { 0x000077e0, 0x00000002 }, - { 0x00065000, 0x00000002 }, - { 0x000037e1, 0x00000002 }, - { 0x040067e1, 0x00000006 }, - { 0x000077e0, 0x00000002 }, - { 0x000077e1, 0x00000002 }, - { 0x000077e1, 0x00000006 }, - { 0xffffffff, 0000000000 }, - { 0x10000000, 0000000000 }, - { 0x0003802a, 0x00000002 }, - { 0x040067e0, 0x00000006 }, - { 0x00007675, 0x00000002 }, - { 0x00007676, 0x00000002 }, - { 0x00007677, 0x00000002 }, - { 0x00007678, 0x00000006 }, - { 0x0003802b, 0x00000002 }, - { 0x04002676, 0x00000002 }, - { 0x00007677, 0x00000002 }, - { 0x00007678, 0x00000006 }, - { 0x0000002e, 0x00000018 }, - { 0x0000002e, 0x00000018 }, - { 0000000000, 0x00000006 }, - { 0x0000002f, 0x00000018 }, - { 0x0000002f, 0x00000018 }, - { 0000000000, 0x00000006 }, - { 0x01605000, 0x00000002 }, - { 0x00065000, 0x00000002 }, - { 0x00098000, 0x00000002 }, - { 0x00061000, 0x00000002 }, - { 0x64c0603d, 0x00000004 }, - { 0x00080000, 0x00000016 }, - { 0000000000, 0000000000 }, - { 0x0400251d, 0x00000002 }, - { 0x00007580, 0x00000002 }, - { 0x00067581, 0x00000002 }, - { 0x04002580, 0x00000002 }, - { 0x00067581, 0x00000002 }, - { 0x00000046, 0x00000004 }, - { 0x00005000, 0000000000 }, - { 0x00061000, 0x00000002 }, - { 0x0000750e, 0x00000002 }, - { 0x00019000, 0x00000002 }, - { 0x00011055, 0x00000014 }, - { 0x00000055, 0x00000012 }, - { 0x0400250f, 0x00000002 }, - { 0x0000504a, 0x00000004 }, - { 0x00007565, 0x00000002 }, - { 0x00007566, 0x00000002 }, - { 0x00000051, 0x00000004 }, - { 0x01e655b4, 0x00000002 }, - { 0x4401b0dc, 0x00000002 }, - { 0x01c110dc, 0x00000002 }, - { 0x2666705d, 0x00000018 }, - { 0x040c2565, 0x00000002 }, - { 0x0000005d, 0x00000018 }, - { 0x04002564, 0x00000002 }, - { 0x00007566, 0x00000002 }, - { 0x00000054, 0x00000004 }, - { 0x00401060, 0x00000008 }, - { 0x00101000, 0x00000002 }, - { 0x000d80ff, 0x00000002 }, - { 0x00800063, 0x00000008 }, - { 0x000f9000, 0x00000002 }, - { 0x000e00ff, 0x00000002 }, - { 0000000000, 0x00000006 }, - { 0x00000080, 0x00000018 }, - { 0x00000054, 0x00000004 }, - { 0x00007576, 0x00000002 }, - { 0x00065000, 0x00000002 }, - { 0x00009000, 0x00000002 }, - { 0x00041000, 0x00000002 }, - { 0x0c00350e, 0x00000002 }, - { 0x00049000, 0x00000002 }, - { 0x00051000, 0x00000002 }, - { 0x01e785f8, 0x00000002 }, - { 0x00200000, 0x00000002 }, - { 0x00600073, 0x0000000c }, - { 0x00007563, 0x00000002 }, - { 0x006075f0, 0x00000021 }, - { 0x20007068, 0x00000004 }, - { 0x00005068, 0x00000004 }, - { 0x00007576, 0x00000002 }, - { 0x00007577, 0x00000002 }, - { 0x0000750e, 0x00000002 }, - { 0x0000750f, 0x00000002 }, - { 0x00a05000, 0x00000002 }, - { 0x00600076, 0x0000000c }, - { 0x006075f0, 0x00000021 }, - { 0x000075f8, 0x00000002 }, - { 0x00000076, 0x00000004 }, - { 0x000a750e, 0x00000002 }, - { 0x0020750f, 0x00000002 }, - { 0x00600079, 0x00000004 }, - { 0x00007570, 0x00000002 }, - { 0x00007571, 0x00000002 }, - { 0x00007572, 0x00000006 }, - { 0x00005000, 0x00000002 }, - { 0x00a05000, 0x00000002 }, - { 0x00007568, 0x00000002 }, - { 0x00061000, 0x00000002 }, - { 0x00000084, 0x0000000c }, - { 0x00058000, 0x00000002 }, - { 0x0c607562, 0x00000002 }, - { 0x00000086, 0x00000004 }, - { 0x00600085, 0x00000004 }, - { 0x400070dd, 0000000000 }, - { 0x000380dd, 0x00000002 }, - { 0x00000093, 0x0000001c }, - { 0x00065095, 0x00000018 }, - { 0x040025bb, 0x00000002 }, - { 0x00061096, 0x00000018 }, - { 0x040075bc, 0000000000 }, - { 0x000075bb, 0x00000002 }, - { 0x000075bc, 0000000000 }, - { 0x00090000, 0x00000006 }, - { 0x00090000, 0x00000002 }, - { 0x000d8002, 0x00000006 }, - { 0x00005000, 0x00000002 }, - { 0x00007821, 0x00000002 }, - { 0x00007800, 0000000000 }, - { 0x00007821, 0x00000002 }, - { 0x00007800, 0000000000 }, - { 0x01665000, 0x00000002 }, - { 0x000a0000, 0x00000002 }, - { 0x000671cc, 0x00000002 }, - { 0x0286f1cd, 0x00000002 }, - { 0x000000a3, 0x00000010 }, - { 0x21007000, 0000000000 }, - { 0x000000aa, 0x0000001c }, - { 0x00065000, 0x00000002 }, - { 0x000a0000, 0x00000002 }, - { 0x00061000, 0x00000002 }, - { 0x000b0000, 0x00000002 }, - { 0x38067000, 0x00000002 }, - { 0x000a00a6, 0x00000004 }, - { 0x20007000, 0000000000 }, - { 0x01200000, 0x00000002 }, - { 0x20077000, 0x00000002 }, - { 0x01200000, 0x00000002 }, - { 0x20007000, 0000000000 }, - { 0x00061000, 0x00000002 }, - { 0x0120751b, 0x00000002 }, - { 0x8040750a, 0x00000002 }, - { 0x8040750b, 0x00000002 }, - { 0x00110000, 0x00000002 }, - { 0x000380dd, 0x00000002 }, - { 0x000000bd, 0x0000001c }, - { 0x00061096, 0x00000018 }, - { 0x844075bd, 0x00000002 }, - { 0x00061095, 0x00000018 }, - { 0x840075bb, 0x00000002 }, - { 0x00061096, 0x00000018 }, - { 0x844075bc, 0x00000002 }, - { 0x000000c0, 0x00000004 }, - { 0x804075bd, 0x00000002 }, - { 0x800075bb, 0x00000002 }, - { 0x804075bc, 0x00000002 }, - { 0x00108000, 0x00000002 }, - { 0x01400000, 0x00000002 }, - { 0x006000c4, 0x0000000c }, - { 0x20c07000, 0x00000020 }, - { 0x000000c6, 0x00000012 }, - { 0x00800000, 0x00000006 }, - { 0x0080751d, 0x00000006 }, - { 0x000025bb, 0x00000002 }, - { 0x000040c0, 0x00000004 }, - { 0x0000775c, 0x00000002 }, - { 0x00a05000, 0x00000002 }, - { 0x00661000, 0x00000002 }, - { 0x0460275d, 0x00000020 }, - { 0x00004000, 0000000000 }, - { 0x00007999, 0x00000002 }, - { 0x00a05000, 0x00000002 }, - { 0x00661000, 0x00000002 }, - { 0x0460299b, 0x00000020 }, - { 0x00004000, 0000000000 }, - { 0x01e00830, 0x00000002 }, - { 0x21007000, 0000000000 }, - { 0x00005000, 0x00000002 }, - { 0x00038042, 0x00000002 }, - { 0x040025e0, 0x00000002 }, - { 0x000075e1, 0000000000 }, - { 0x00000001, 0000000000 }, - { 0x000380d9, 0x00000002 }, - { 0x04007394, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, -}; - - -static u32 radeon_cp_microcode[][2] = { - { 0x21007000, 0000000000 }, - { 0x20007000, 0000000000 }, - { 0x000000b4, 0x00000004 }, - { 0x000000b8, 0x00000004 }, - { 0x6f5b4d4c, 0000000000 }, - { 0x4c4c427f, 0000000000 }, - { 0x5b568a92, 0000000000 }, - { 0x4ca09c6d, 0000000000 }, - { 0xad4c4c4c, 0000000000 }, - { 0x4ce1af3d, 0000000000 }, - { 0xd8afafaf, 0000000000 }, - { 0xd64c4cdc, 0000000000 }, - { 0x4cd10d10, 0000000000 }, - { 0x000f0000, 0x00000016 }, - { 0x362f242d, 0000000000 }, - { 0x00000012, 0x00000004 }, - { 0x000f0000, 0x00000016 }, - { 0x362f282d, 0000000000 }, - { 0x000380e7, 0x00000002 }, - { 0x04002c97, 0x00000002 }, - { 0x000f0001, 0x00000016 }, - { 0x333a3730, 0000000000 }, - { 0x000077ef, 0x00000002 }, - { 0x00061000, 0x00000002 }, - { 0x00000021, 0x0000001a }, - { 0x00004000, 0x0000001e }, - { 0x00061000, 0x00000002 }, - { 0x00000021, 0x0000001a }, - { 0x00004000, 0x0000001e }, - { 0x00061000, 0x00000002 }, - { 0x00000021, 0x0000001a }, - { 0x00004000, 0x0000001e }, - { 0x00000017, 0x00000004 }, - { 0x0003802b, 0x00000002 }, - { 0x040067e0, 0x00000002 }, - { 0x00000017, 0x00000004 }, - { 0x000077e0, 0x00000002 }, - { 0x00065000, 0x00000002 }, - { 0x000037e1, 0x00000002 }, - { 0x040067e1, 0x00000006 }, - { 0x000077e0, 0x00000002 }, - { 0x000077e1, 0x00000002 }, - { 0x000077e1, 0x00000006 }, - { 0xffffffff, 0000000000 }, - { 0x10000000, 0000000000 }, - { 0x0003802b, 0x00000002 }, - { 0x040067e0, 0x00000006 }, - { 0x00007675, 0x00000002 }, - { 0x00007676, 0x00000002 }, - { 0x00007677, 0x00000002 }, - { 0x00007678, 0x00000006 }, - { 0x0003802c, 0x00000002 }, - { 0x04002676, 0x00000002 }, - { 0x00007677, 0x00000002 }, - { 0x00007678, 0x00000006 }, - { 0x0000002f, 0x00000018 }, - { 0x0000002f, 0x00000018 }, - { 0000000000, 0x00000006 }, - { 0x00000030, 0x00000018 }, - { 0x00000030, 0x00000018 }, - { 0000000000, 0x00000006 }, - { 0x01605000, 0x00000002 }, - { 0x00065000, 0x00000002 }, - { 0x00098000, 0x00000002 }, - { 0x00061000, 0x00000002 }, - { 0x64c0603e, 0x00000004 }, - { 0x000380e6, 0x00000002 }, - { 0x040025c5, 0x00000002 }, - { 0x00080000, 0x00000016 }, - { 0000000000, 0000000000 }, - { 0x0400251d, 0x00000002 }, - { 0x00007580, 0x00000002 }, - { 0x00067581, 0x00000002 }, - { 0x04002580, 0x00000002 }, - { 0x00067581, 0x00000002 }, - { 0x00000049, 0x00000004 }, - { 0x00005000, 0000000000 }, - { 0x000380e6, 0x00000002 }, - { 0x040025c5, 0x00000002 }, - { 0x00061000, 0x00000002 }, - { 0x0000750e, 0x00000002 }, - { 0x00019000, 0x00000002 }, - { 0x00011055, 0x00000014 }, - { 0x00000055, 0x00000012 }, - { 0x0400250f, 0x00000002 }, - { 0x0000504f, 0x00000004 }, - { 0x000380e6, 0x00000002 }, - { 0x040025c5, 0x00000002 }, - { 0x00007565, 0x00000002 }, - { 0x00007566, 0x00000002 }, - { 0x00000058, 0x00000004 }, - { 0x000380e6, 0x00000002 }, - { 0x040025c5, 0x00000002 }, - { 0x01e655b4, 0x00000002 }, - { 0x4401b0e4, 0x00000002 }, - { 0x01c110e4, 0x00000002 }, - { 0x26667066, 0x00000018 }, - { 0x040c2565, 0x00000002 }, - { 0x00000066, 0x00000018 }, - { 0x04002564, 0x00000002 }, - { 0x00007566, 0x00000002 }, - { 0x0000005d, 0x00000004 }, - { 0x00401069, 0x00000008 }, - { 0x00101000, 0x00000002 }, - { 0x000d80ff, 0x00000002 }, - { 0x0080006c, 0x00000008 }, - { 0x000f9000, 0x00000002 }, - { 0x000e00ff, 0x00000002 }, - { 0000000000, 0x00000006 }, - { 0x0000008f, 0x00000018 }, - { 0x0000005b, 0x00000004 }, - { 0x000380e6, 0x00000002 }, - { 0x040025c5, 0x00000002 }, - { 0x00007576, 0x00000002 }, - { 0x00065000, 0x00000002 }, - { 0x00009000, 0x00000002 }, - { 0x00041000, 0x00000002 }, - { 0x0c00350e, 0x00000002 }, - { 0x00049000, 0x00000002 }, - { 0x00051000, 0x00000002 }, - { 0x01e785f8, 0x00000002 }, - { 0x00200000, 0x00000002 }, - { 0x0060007e, 0x0000000c }, - { 0x00007563, 0x00000002 }, - { 0x006075f0, 0x00000021 }, - { 0x20007073, 0x00000004 }, - { 0x00005073, 0x00000004 }, - { 0x000380e6, 0x00000002 }, - { 0x040025c5, 0x00000002 }, - { 0x00007576, 0x00000002 }, - { 0x00007577, 0x00000002 }, - { 0x0000750e, 0x00000002 }, - { 0x0000750f, 0x00000002 }, - { 0x00a05000, 0x00000002 }, - { 0x00600083, 0x0000000c }, - { 0x006075f0, 0x00000021 }, - { 0x000075f8, 0x00000002 }, - { 0x00000083, 0x00000004 }, - { 0x000a750e, 0x00000002 }, - { 0x000380e6, 0x00000002 }, - { 0x040025c5, 0x00000002 }, - { 0x0020750f, 0x00000002 }, - { 0x00600086, 0x00000004 }, - { 0x00007570, 0x00000002 }, - { 0x00007571, 0x00000002 }, - { 0x00007572, 0x00000006 }, - { 0x000380e6, 0x00000002 }, - { 0x040025c5, 0x00000002 }, - { 0x00005000, 0x00000002 }, - { 0x00a05000, 0x00000002 }, - { 0x00007568, 0x00000002 }, - { 0x00061000, 0x00000002 }, - { 0x00000095, 0x0000000c }, - { 0x00058000, 0x00000002 }, - { 0x0c607562, 0x00000002 }, - { 0x00000097, 0x00000004 }, - { 0x000380e6, 0x00000002 }, - { 0x040025c5, 0x00000002 }, - { 0x00600096, 0x00000004 }, - { 0x400070e5, 0000000000 }, - { 0x000380e6, 0x00000002 }, - { 0x040025c5, 0x00000002 }, - { 0x000380e5, 0x00000002 }, - { 0x000000a8, 0x0000001c }, - { 0x000650aa, 0x00000018 }, - { 0x040025bb, 0x00000002 }, - { 0x000610ab, 0x00000018 }, - { 0x040075bc, 0000000000 }, - { 0x000075bb, 0x00000002 }, - { 0x000075bc, 0000000000 }, - { 0x00090000, 0x00000006 }, - { 0x00090000, 0x00000002 }, - { 0x000d8002, 0x00000006 }, - { 0x00007832, 0x00000002 }, - { 0x00005000, 0x00000002 }, - { 0x000380e7, 0x00000002 }, - { 0x04002c97, 0x00000002 }, - { 0x00007820, 0x00000002 }, - { 0x00007821, 0x00000002 }, - { 0x00007800, 0000000000 }, - { 0x01200000, 0x00000002 }, - { 0x20077000, 0x00000002 }, - { 0x01200000, 0x00000002 }, - { 0x20007000, 0x00000002 }, - { 0x00061000, 0x00000002 }, - { 0x0120751b, 0x00000002 }, - { 0x8040750a, 0x00000002 }, - { 0x8040750b, 0x00000002 }, - { 0x00110000, 0x00000002 }, - { 0x000380e5, 0x00000002 }, - { 0x000000c6, 0x0000001c }, - { 0x000610ab, 0x00000018 }, - { 0x844075bd, 0x00000002 }, - { 0x000610aa, 0x00000018 }, - { 0x840075bb, 0x00000002 }, - { 0x000610ab, 0x00000018 }, - { 0x844075bc, 0x00000002 }, - { 0x000000c9, 0x00000004 }, - { 0x804075bd, 0x00000002 }, - { 0x800075bb, 0x00000002 }, - { 0x804075bc, 0x00000002 }, - { 0x00108000, 0x00000002 }, - { 0x01400000, 0x00000002 }, - { 0x006000cd, 0x0000000c }, - { 0x20c07000, 0x00000020 }, - { 0x000000cf, 0x00000012 }, - { 0x00800000, 0x00000006 }, - { 0x0080751d, 0x00000006 }, - { 0000000000, 0000000000 }, - { 0x0000775c, 0x00000002 }, - { 0x00a05000, 0x00000002 }, - { 0x00661000, 0x00000002 }, - { 0x0460275d, 0x00000020 }, - { 0x00004000, 0000000000 }, - { 0x01e00830, 0x00000002 }, - { 0x21007000, 0000000000 }, - { 0x6464614d, 0000000000 }, - { 0x69687420, 0000000000 }, - { 0x00000073, 0000000000 }, - { 0000000000, 0000000000 }, - { 0x00005000, 0x00000002 }, - { 0x000380d0, 0x00000002 }, - { 0x040025e0, 0x00000002 }, - { 0x000075e1, 0000000000 }, - { 0x00000001, 0000000000 }, - { 0x000380e0, 0x00000002 }, - { 0x04002394, 0x00000002 }, - { 0x00005000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0x00000008, 0000000000 }, - { 0x00000004, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, -}; - -static u32 R300_cp_microcode[][2] = { - { 0x4200e000, 0000000000 }, - { 0x4000e000, 0000000000 }, - { 0x000000af, 0x00000008 }, - { 0x000000b3, 0x00000008 }, - { 0x6c5a504f, 0000000000 }, - { 0x4f4f497a, 0000000000 }, - { 0x5a578288, 0000000000 }, - { 0x4f91906a, 0000000000 }, - { 0x4f4f4f4f, 0000000000 }, - { 0x4fe24f44, 0000000000 }, - { 0x4f9c9c9c, 0000000000 }, - { 0xdc4f4fde, 0000000000 }, - { 0xa1cd4f4f, 0000000000 }, - { 0xd29d9d9d, 0000000000 }, - { 0x4f0f9fd7, 0000000000 }, - { 0x000ca000, 0x00000004 }, - { 0x000d0012, 0x00000038 }, - { 0x0000e8b4, 0x00000004 }, - { 0x000d0014, 0x00000038 }, - { 0x0000e8b6, 0x00000004 }, - { 0x000d0016, 0x00000038 }, - { 0x0000e854, 0x00000004 }, - { 0x000d0018, 0x00000038 }, - { 0x0000e855, 0x00000004 }, - { 0x000d001a, 0x00000038 }, - { 0x0000e856, 0x00000004 }, - { 0x000d001c, 0x00000038 }, - { 0x0000e857, 0x00000004 }, - { 0x000d001e, 0x00000038 }, - { 0x0000e824, 0x00000004 }, - { 0x000d0020, 0x00000038 }, - { 0x0000e825, 0x00000004 }, - { 0x000d0022, 0x00000038 }, - { 0x0000e830, 0x00000004 }, - { 0x000d0024, 0x00000038 }, - { 0x0000f0c0, 0x00000004 }, - { 0x000d0026, 0x00000038 }, - { 0x0000f0c1, 0x00000004 }, - { 0x000d0028, 0x00000038 }, - { 0x0000f041, 0x00000004 }, - { 0x000d002a, 0x00000038 }, - { 0x0000f184, 0x00000004 }, - { 0x000d002c, 0x00000038 }, - { 0x0000f185, 0x00000004 }, - { 0x000d002e, 0x00000038 }, - { 0x0000f186, 0x00000004 }, - { 0x000d0030, 0x00000038 }, - { 0x0000f187, 0x00000004 }, - { 0x000d0032, 0x00000038 }, - { 0x0000f180, 0x00000004 }, - { 0x000d0034, 0x00000038 }, - { 0x0000f393, 0x00000004 }, - { 0x000d0036, 0x00000038 }, - { 0x0000f38a, 0x00000004 }, - { 0x000d0038, 0x00000038 }, - { 0x0000f38e, 0x00000004 }, - { 0x0000e821, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00000043, 0x00000018 }, - { 0x00cce800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x001b0001, 0x00000004 }, - { 0x08004800, 0x00000004 }, - { 0x0000003a, 0x00000008 }, - { 0x0000a000, 0000000000 }, - { 0x02c0a000, 0x00000004 }, - { 0x000ca000, 0x00000004 }, - { 0x00130000, 0x00000004 }, - { 0x000c2000, 0x00000004 }, - { 0xc980c045, 0x00000008 }, - { 0x2000451d, 0x00000004 }, - { 0x0000e580, 0x00000004 }, - { 0x000ce581, 0x00000004 }, - { 0x08004580, 0x00000004 }, - { 0x000ce581, 0x00000004 }, - { 0x0000004c, 0x00000008 }, - { 0x0000a000, 0000000000 }, - { 0x000c2000, 0x00000004 }, - { 0x0000e50e, 0x00000004 }, - { 0x00032000, 0x00000004 }, - { 0x00022056, 0x00000028 }, - { 0x00000056, 0x00000024 }, - { 0x0800450f, 0x00000004 }, - { 0x0000a050, 0x00000008 }, - { 0x0000e565, 0x00000004 }, - { 0x0000e566, 0x00000004 }, - { 0x00000057, 0x00000008 }, - { 0x03cca5b4, 0x00000004 }, - { 0x05432000, 0x00000004 }, - { 0x00022000, 0x00000004 }, - { 0x4ccce063, 0x00000030 }, - { 0x08274565, 0x00000004 }, - { 0x00000063, 0x00000030 }, - { 0x08004564, 0x00000004 }, - { 0x0000e566, 0x00000004 }, - { 0x0000005a, 0x00000008 }, - { 0x00802066, 0x00000010 }, - { 0x00202000, 0x00000004 }, - { 0x001b00ff, 0x00000004 }, - { 0x01000069, 0x00000010 }, - { 0x001f2000, 0x00000004 }, - { 0x001c00ff, 0x00000004 }, - { 0000000000, 0x0000000c }, - { 0x00000085, 0x00000030 }, - { 0x0000005a, 0x00000008 }, - { 0x0000e576, 0x00000004 }, - { 0x000ca000, 0x00000004 }, - { 0x00012000, 0x00000004 }, - { 0x00082000, 0x00000004 }, - { 0x1800650e, 0x00000004 }, - { 0x00092000, 0x00000004 }, - { 0x000a2000, 0x00000004 }, - { 0x000f0000, 0x00000004 }, - { 0x00400000, 0x00000004 }, - { 0x00000079, 0x00000018 }, - { 0x0000e563, 0x00000004 }, - { 0x00c0e5f9, 0x000000c2 }, - { 0x0000006e, 0x00000008 }, - { 0x0000a06e, 0x00000008 }, - { 0x0000e576, 0x00000004 }, - { 0x0000e577, 0x00000004 }, - { 0x0000e50e, 0x00000004 }, - { 0x0000e50f, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x0000007c, 0x00000018 }, - { 0x00c0e5f9, 0x000000c2 }, - { 0x0000007c, 0x00000008 }, - { 0x0014e50e, 0x00000004 }, - { 0x0040e50f, 0x00000004 }, - { 0x00c0007f, 0x00000008 }, - { 0x0000e570, 0x00000004 }, - { 0x0000e571, 0x00000004 }, - { 0x0000e572, 0x0000000c }, - { 0x0000a000, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x0000e568, 0x00000004 }, - { 0x000c2000, 0x00000004 }, - { 0x00000089, 0x00000018 }, - { 0x000b0000, 0x00000004 }, - { 0x18c0e562, 0x00000004 }, - { 0x0000008b, 0x00000008 }, - { 0x00c0008a, 0x00000008 }, - { 0x000700e4, 0x00000004 }, - { 0x00000097, 0x00000038 }, - { 0x000ca099, 0x00000030 }, - { 0x080045bb, 0x00000004 }, - { 0x000c209a, 0x00000030 }, - { 0x0800e5bc, 0000000000 }, - { 0x0000e5bb, 0x00000004 }, - { 0x0000e5bc, 0000000000 }, - { 0x00120000, 0x0000000c }, - { 0x00120000, 0x00000004 }, - { 0x001b0002, 0x0000000c }, - { 0x0000a000, 0x00000004 }, - { 0x0000e821, 0x00000004 }, - { 0x0000e800, 0000000000 }, - { 0x0000e821, 0x00000004 }, - { 0x0000e82e, 0000000000 }, - { 0x02cca000, 0x00000004 }, - { 0x00140000, 0x00000004 }, - { 0x000ce1cc, 0x00000004 }, - { 0x050de1cd, 0x00000004 }, - { 0x000000a7, 0x00000020 }, - { 0x4200e000, 0000000000 }, - { 0x000000ae, 0x00000038 }, - { 0x000ca000, 0x00000004 }, - { 0x00140000, 0x00000004 }, - { 0x000c2000, 0x00000004 }, - { 0x00160000, 0x00000004 }, - { 0x700ce000, 0x00000004 }, - { 0x001400aa, 0x00000008 }, - { 0x4000e000, 0000000000 }, - { 0x02400000, 0x00000004 }, - { 0x400ee000, 0x00000004 }, - { 0x02400000, 0x00000004 }, - { 0x4000e000, 0000000000 }, - { 0x000c2000, 0x00000004 }, - { 0x0240e51b, 0x00000004 }, - { 0x0080e50a, 0x00000005 }, - { 0x0080e50b, 0x00000005 }, - { 0x00220000, 0x00000004 }, - { 0x000700e4, 0x00000004 }, - { 0x000000c1, 0x00000038 }, - { 0x000c209a, 0x00000030 }, - { 0x0880e5bd, 0x00000005 }, - { 0x000c2099, 0x00000030 }, - { 0x0800e5bb, 0x00000005 }, - { 0x000c209a, 0x00000030 }, - { 0x0880e5bc, 0x00000005 }, - { 0x000000c4, 0x00000008 }, - { 0x0080e5bd, 0x00000005 }, - { 0x0000e5bb, 0x00000005 }, - { 0x0080e5bc, 0x00000005 }, - { 0x00210000, 0x00000004 }, - { 0x02800000, 0x00000004 }, - { 0x00c000c8, 0x00000018 }, - { 0x4180e000, 0x00000040 }, - { 0x000000ca, 0x00000024 }, - { 0x01000000, 0x0000000c }, - { 0x0100e51d, 0x0000000c }, - { 0x000045bb, 0x00000004 }, - { 0x000080c4, 0x00000008 }, - { 0x0000f3ce, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00cc2000, 0x00000004 }, - { 0x08c053cf, 0x00000040 }, - { 0x00008000, 0000000000 }, - { 0x0000f3d2, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00cc2000, 0x00000004 }, - { 0x08c053d3, 0x00000040 }, - { 0x00008000, 0000000000 }, - { 0x0000f39d, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00cc2000, 0x00000004 }, - { 0x08c0539e, 0x00000040 }, - { 0x00008000, 0000000000 }, - { 0x03c00830, 0x00000004 }, - { 0x4200e000, 0000000000 }, - { 0x0000a000, 0x00000004 }, - { 0x200045e0, 0x00000004 }, - { 0x0000e5e1, 0000000000 }, - { 0x00000001, 0000000000 }, - { 0x000700e1, 0x00000004 }, - { 0x0800e394, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, -}; - -int RADEON_READ_PLL(drm_device_t *dev, int addr) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - - RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f); - return RADEON_READ(RADEON_CLOCK_CNTL_DATA); -} - -#if RADEON_FIFO_DEBUG -static void radeon_status( drm_radeon_private_t *dev_priv ) -{ - printk( "%s:\n", __FUNCTION__ ); - printk( "RBBM_STATUS = 0x%08x\n", - (unsigned int)RADEON_READ( RADEON_RBBM_STATUS ) ); - printk( "CP_RB_RTPR = 0x%08x\n", - (unsigned int)RADEON_READ( RADEON_CP_RB_RPTR ) ); - printk( "CP_RB_WTPR = 0x%08x\n", - (unsigned int)RADEON_READ( RADEON_CP_RB_WPTR ) ); - printk( "AIC_CNTL = 0x%08x\n", - (unsigned int)RADEON_READ( RADEON_AIC_CNTL ) ); - printk( "AIC_STAT = 0x%08x\n", - (unsigned int)RADEON_READ( RADEON_AIC_STAT ) ); - printk( "AIC_PT_BASE = 0x%08x\n", - (unsigned int)RADEON_READ( RADEON_AIC_PT_BASE ) ); - printk( "TLB_ADDR = 0x%08x\n", - (unsigned int)RADEON_READ( RADEON_AIC_TLB_ADDR ) ); - printk( "TLB_DATA = 0x%08x\n", - (unsigned int)RADEON_READ( RADEON_AIC_TLB_DATA ) ); -} -#endif - - -/* ================================================================ - * Engine, FIFO control - */ - -static int radeon_do_pixcache_flush( drm_radeon_private_t *dev_priv ) -{ - u32 tmp; - int i; - - dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; - - tmp = RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT ); - tmp |= RADEON_RB2D_DC_FLUSH_ALL; - RADEON_WRITE( RADEON_RB2D_DSTCACHE_CTLSTAT, tmp ); - - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - if ( !(RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT ) - & RADEON_RB2D_DC_BUSY) ) { - return 0; - } - DRM_UDELAY( 1 ); - } - -#if RADEON_FIFO_DEBUG - DRM_ERROR( "failed!\n" ); - radeon_status( dev_priv ); -#endif - return DRM_ERR(EBUSY); -} - -static int radeon_do_wait_for_fifo( drm_radeon_private_t *dev_priv, - int entries ) -{ - int i; - - dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; - - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - int slots = ( RADEON_READ( RADEON_RBBM_STATUS ) - & RADEON_RBBM_FIFOCNT_MASK ); - if ( slots >= entries ) return 0; - DRM_UDELAY( 1 ); - } - -#if RADEON_FIFO_DEBUG - DRM_ERROR( "failed!\n" ); - radeon_status( dev_priv ); -#endif - return DRM_ERR(EBUSY); -} - -static int radeon_do_wait_for_idle( drm_radeon_private_t *dev_priv ) -{ - int i, ret; - - dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; - - ret = radeon_do_wait_for_fifo( dev_priv, 64 ); - if ( ret ) return ret; - - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - if ( !(RADEON_READ( RADEON_RBBM_STATUS ) - & RADEON_RBBM_ACTIVE) ) { - radeon_do_pixcache_flush( dev_priv ); - return 0; - } - DRM_UDELAY( 1 ); - } - -#if RADEON_FIFO_DEBUG - DRM_ERROR( "failed!\n" ); - radeon_status( dev_priv ); -#endif - return DRM_ERR(EBUSY); -} - - -/* ================================================================ - * CP control, initialization - */ - -/* Load the microcode for the CP */ -static void radeon_cp_load_microcode( drm_radeon_private_t *dev_priv ) -{ - int i; - DRM_DEBUG( "\n" ); - - radeon_do_wait_for_idle( dev_priv ); - - RADEON_WRITE( RADEON_CP_ME_RAM_ADDR, 0 ); - - if (dev_priv->microcode_version==UCODE_R200) { - DRM_INFO("Loading R200 Microcode\n"); - for ( i = 0 ; i < 256 ; i++ ) - { - RADEON_WRITE( RADEON_CP_ME_RAM_DATAH, - R200_cp_microcode[i][1] ); - RADEON_WRITE( RADEON_CP_ME_RAM_DATAL, - R200_cp_microcode[i][0] ); - } - } else if (dev_priv->microcode_version==UCODE_R300) { - DRM_INFO("Loading R300 Microcode\n"); - for ( i = 0 ; i < 256 ; i++ ) { - RADEON_WRITE( RADEON_CP_ME_RAM_DATAH, - R300_cp_microcode[i][1] ); - RADEON_WRITE( RADEON_CP_ME_RAM_DATAL, - R300_cp_microcode[i][0] ); - } - } else { - for ( i = 0 ; i < 256 ; i++ ) { - RADEON_WRITE( RADEON_CP_ME_RAM_DATAH, - radeon_cp_microcode[i][1] ); - RADEON_WRITE( RADEON_CP_ME_RAM_DATAL, - radeon_cp_microcode[i][0] ); - } - } -} - -/* Flush any pending commands to the CP. This should only be used just - * prior to a wait for idle, as it informs the engine that the command - * stream is ending. - */ -static void radeon_do_cp_flush( drm_radeon_private_t *dev_priv ) -{ - DRM_DEBUG( "\n" ); -#if 0 - u32 tmp; - - tmp = RADEON_READ( RADEON_CP_RB_WPTR ) | (1 << 31); - RADEON_WRITE( RADEON_CP_RB_WPTR, tmp ); -#endif -} - -/* Wait for the CP to go idle. - */ -int radeon_do_cp_idle( drm_radeon_private_t *dev_priv ) -{ - RING_LOCALS; - DRM_DEBUG( "\n" ); - - BEGIN_RING( 6 ); - - RADEON_PURGE_CACHE(); - RADEON_PURGE_ZCACHE(); - RADEON_WAIT_UNTIL_IDLE(); - - ADVANCE_RING(); - COMMIT_RING(); - - return radeon_do_wait_for_idle( dev_priv ); -} - -/* Start the Command Processor. - */ -static void radeon_do_cp_start( drm_radeon_private_t *dev_priv ) -{ - RING_LOCALS; - DRM_DEBUG( "\n" ); - - radeon_do_wait_for_idle( dev_priv ); - - RADEON_WRITE( RADEON_CP_CSQ_CNTL, dev_priv->cp_mode ); - - dev_priv->cp_running = 1; - - BEGIN_RING( 6 ); - - RADEON_PURGE_CACHE(); - RADEON_PURGE_ZCACHE(); - RADEON_WAIT_UNTIL_IDLE(); - - ADVANCE_RING(); - COMMIT_RING(); -} - -/* Reset the Command Processor. This will not flush any pending - * commands, so you must wait for the CP command stream to complete - * before calling this routine. - */ -static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv ) -{ - u32 cur_read_ptr; - DRM_DEBUG( "\n" ); - - cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR ); - RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr ); - SET_RING_HEAD( dev_priv, cur_read_ptr ); - dev_priv->ring.tail = cur_read_ptr; -} - -/* Stop the Command Processor. This will not flush any pending - * commands, so you must flush the command stream and wait for the CP - * to go idle before calling this routine. - */ -static void radeon_do_cp_stop( drm_radeon_private_t *dev_priv ) -{ - DRM_DEBUG( "\n" ); - - RADEON_WRITE( RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS ); - - dev_priv->cp_running = 0; -} - -/* Reset the engine. This will stop the CP if it is running. - */ -static int radeon_do_engine_reset( drm_device_t *dev ) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset; - DRM_DEBUG( "\n" ); - - radeon_do_pixcache_flush( dev_priv ); - - clock_cntl_index = RADEON_READ( RADEON_CLOCK_CNTL_INDEX ); - mclk_cntl = RADEON_READ_PLL( dev, RADEON_MCLK_CNTL ); - - RADEON_WRITE_PLL( RADEON_MCLK_CNTL, ( mclk_cntl | - RADEON_FORCEON_MCLKA | - RADEON_FORCEON_MCLKB | - RADEON_FORCEON_YCLKA | - RADEON_FORCEON_YCLKB | - RADEON_FORCEON_MC | - RADEON_FORCEON_AIC ) ); - - rbbm_soft_reset = RADEON_READ( RADEON_RBBM_SOFT_RESET ); - - RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset | - RADEON_SOFT_RESET_CP | - RADEON_SOFT_RESET_HI | - RADEON_SOFT_RESET_SE | - RADEON_SOFT_RESET_RE | - RADEON_SOFT_RESET_PP | - RADEON_SOFT_RESET_E2 | - RADEON_SOFT_RESET_RB ) ); - RADEON_READ( RADEON_RBBM_SOFT_RESET ); - RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset & - ~( RADEON_SOFT_RESET_CP | - RADEON_SOFT_RESET_HI | - RADEON_SOFT_RESET_SE | - RADEON_SOFT_RESET_RE | - RADEON_SOFT_RESET_PP | - RADEON_SOFT_RESET_E2 | - RADEON_SOFT_RESET_RB ) ) ); - RADEON_READ( RADEON_RBBM_SOFT_RESET ); - - - RADEON_WRITE_PLL( RADEON_MCLK_CNTL, mclk_cntl ); - RADEON_WRITE( RADEON_CLOCK_CNTL_INDEX, clock_cntl_index ); - RADEON_WRITE( RADEON_RBBM_SOFT_RESET, rbbm_soft_reset ); - - /* Reset the CP ring */ - radeon_do_cp_reset( dev_priv ); - - /* The CP is no longer running after an engine reset */ - dev_priv->cp_running = 0; - - /* Reset any pending vertex, indirect buffers */ - radeon_freelist_reset( dev ); - - return 0; -} - -static void radeon_cp_init_ring_buffer( drm_device_t *dev, - drm_radeon_private_t *dev_priv ) -{ - u32 ring_start, cur_read_ptr; - u32 tmp; - - /* Initialize the memory controller */ - RADEON_WRITE( RADEON_MC_FB_LOCATION, - ( ( dev_priv->gart_vm_start - 1 ) & 0xffff0000 ) - | ( dev_priv->fb_location >> 16 ) ); - -#if __OS_HAS_AGP - if (dev_priv->flags & CHIP_IS_AGP) { - RADEON_WRITE( RADEON_MC_AGP_LOCATION, - (((dev_priv->gart_vm_start - 1 + - dev_priv->gart_size) & 0xffff0000) | - (dev_priv->gart_vm_start >> 16)) ); - - ring_start = (dev_priv->cp_ring->offset - - dev->agp->base - + dev_priv->gart_vm_start); - } else -#endif - ring_start = (dev_priv->cp_ring->offset - - dev->sg->handle - + dev_priv->gart_vm_start); - - RADEON_WRITE( RADEON_CP_RB_BASE, ring_start ); - - /* Set the write pointer delay */ - RADEON_WRITE( RADEON_CP_RB_WPTR_DELAY, 0 ); - - /* Initialize the ring buffer's read and write pointers */ - cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR ); - RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr ); - SET_RING_HEAD( dev_priv, cur_read_ptr ); - dev_priv->ring.tail = cur_read_ptr; - -#if __OS_HAS_AGP - if (dev_priv->flags & CHIP_IS_AGP) { - /* set RADEON_AGP_BASE here instead of relying on X from user space */ - RADEON_WRITE( RADEON_AGP_BASE, (unsigned int)dev->agp->base ); - RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR, - dev_priv->ring_rptr->offset - - dev->agp->base - + dev_priv->gart_vm_start); - } else -#endif - { - drm_sg_mem_t *entry = dev->sg; - unsigned long tmp_ofs, page_ofs; - - tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle; - page_ofs = tmp_ofs >> PAGE_SHIFT; - - RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR, - entry->busaddr[page_ofs]); - DRM_DEBUG( "ring rptr: offset=0x%08lx handle=0x%08lx\n", - (unsigned long) entry->busaddr[page_ofs], - entry->handle + tmp_ofs ); - } - - /* Initialize the scratch register pointer. This will cause - * the scratch register values to be written out to memory - * whenever they are updated. - * - * We simply put this behind the ring read pointer, this works - * with PCI GART as well as (whatever kind of) AGP GART - */ - RADEON_WRITE( RADEON_SCRATCH_ADDR, RADEON_READ( RADEON_CP_RB_RPTR_ADDR ) - + RADEON_SCRATCH_REG_OFFSET ); - - dev_priv->scratch = ((__volatile__ u32 *) - dev_priv->ring_rptr->handle + - (RADEON_SCRATCH_REG_OFFSET / sizeof(u32))); - - RADEON_WRITE( RADEON_SCRATCH_UMSK, 0x7 ); - - /* Writeback doesn't seem to work everywhere, test it first */ - DRM_WRITE32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0 ); - RADEON_WRITE( RADEON_SCRATCH_REG1, 0xdeadbeef ); - - for ( tmp = 0 ; tmp < dev_priv->usec_timeout ; tmp++ ) { - if ( DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1) ) == 0xdeadbeef ) - break; - DRM_UDELAY( 1 ); - } - - if ( tmp < dev_priv->usec_timeout ) { - dev_priv->writeback_works = 1; - DRM_DEBUG( "writeback test succeeded, tmp=%d\n", tmp ); - } else { - dev_priv->writeback_works = 0; - DRM_DEBUG( "writeback test failed\n" ); - } - - dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0; - RADEON_WRITE( RADEON_LAST_FRAME_REG, - dev_priv->sarea_priv->last_frame ); - - dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0; - RADEON_WRITE( RADEON_LAST_DISPATCH_REG, - dev_priv->sarea_priv->last_dispatch ); - - dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0; - RADEON_WRITE( RADEON_LAST_CLEAR_REG, - dev_priv->sarea_priv->last_clear ); - - /* Set ring buffer size */ -#ifdef __BIG_ENDIAN - RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT ); -#else - RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw ); -#endif - - radeon_do_wait_for_idle( dev_priv ); - - /* Turn on bus mastering */ - tmp = RADEON_READ( RADEON_BUS_CNTL ) & ~RADEON_BUS_MASTER_DIS; - RADEON_WRITE( RADEON_BUS_CNTL, tmp ); - - /* Sync everything up */ - RADEON_WRITE( RADEON_ISYNC_CNTL, - (RADEON_ISYNC_ANY2D_IDLE3D | - RADEON_ISYNC_ANY3D_IDLE2D | - RADEON_ISYNC_WAIT_IDLEGUI | - RADEON_ISYNC_CPSCRATCH_IDLEGUI) ); -} - -/* Enable or disable PCI GART on the chip */ -static void radeon_set_pcigart( drm_radeon_private_t *dev_priv, int on ) -{ - u32 tmp = RADEON_READ( RADEON_AIC_CNTL ); - - if ( on ) { - RADEON_WRITE( RADEON_AIC_CNTL, tmp | RADEON_PCIGART_TRANSLATE_EN ); - - /* set PCI GART page-table base address - */ - RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart ); - - /* set address range for PCI address translate - */ - RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start ); - RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start - + dev_priv->gart_size - 1); - - /* Turn off AGP aperture -- is this required for PCI GART? - */ - RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */ - RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */ - } else { - RADEON_WRITE( RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN ); - } -} - -static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init ) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "\n" ); - - if ( (!(dev_priv->flags & CHIP_IS_AGP)) && !dev->sg ) { - DRM_ERROR( "PCI GART memory not allocated!\n" ); - radeon_do_cleanup_cp(dev); - return DRM_ERR(EINVAL); - } - - dev_priv->usec_timeout = init->usec_timeout; - if ( dev_priv->usec_timeout < 1 || - dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT ) { - DRM_DEBUG( "TIMEOUT problem!\n" ); - radeon_do_cleanup_cp(dev); - return DRM_ERR(EINVAL); - } - - switch(init->func) { - case RADEON_INIT_R200_CP: - dev_priv->microcode_version=UCODE_R200; - break; - case RADEON_INIT_R300_CP: - dev_priv->microcode_version=UCODE_R300; - break; - default: - dev_priv->microcode_version=UCODE_R100; - break; - } - - dev_priv->do_boxes = 0; - dev_priv->cp_mode = init->cp_mode; - - /* We don't support anything other than bus-mastering ring mode, - * but the ring can be in either AGP or PCI space for the ring - * read pointer. - */ - if ( ( init->cp_mode != RADEON_CSQ_PRIBM_INDDIS ) && - ( init->cp_mode != RADEON_CSQ_PRIBM_INDBM ) ) { - DRM_DEBUG( "BAD cp_mode (%x)!\n", init->cp_mode ); - radeon_do_cleanup_cp(dev); - return DRM_ERR(EINVAL); - } - - switch ( init->fb_bpp ) { - case 16: - dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565; - break; - case 32: - default: - dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888; - break; - } - dev_priv->front_offset = init->front_offset; - dev_priv->front_pitch = init->front_pitch; - dev_priv->back_offset = init->back_offset; - dev_priv->back_pitch = init->back_pitch; - - switch ( init->depth_bpp ) { - case 16: - dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; - break; - case 32: - default: - dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; - break; - } - dev_priv->depth_offset = init->depth_offset; - dev_priv->depth_pitch = init->depth_pitch; - - /* Hardware state for depth clears. Remove this if/when we no - * longer clear the depth buffer with a 3D rectangle. Hard-code - * all values to prevent unwanted 3D state from slipping through - * and screwing with the clear operation. - */ - dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE | - (dev_priv->color_fmt << 10) | - (dev_priv->microcode_version == UCODE_R100 ? - RADEON_ZBLOCK16 : 0)); - - dev_priv->depth_clear.rb3d_zstencilcntl = - (dev_priv->depth_fmt | - RADEON_Z_TEST_ALWAYS | - RADEON_STENCIL_TEST_ALWAYS | - RADEON_STENCIL_S_FAIL_REPLACE | - RADEON_STENCIL_ZPASS_REPLACE | - RADEON_STENCIL_ZFAIL_REPLACE | - RADEON_Z_WRITE_ENABLE); - - dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW | - RADEON_BFACE_SOLID | - RADEON_FFACE_SOLID | - RADEON_FLAT_SHADE_VTX_LAST | - RADEON_DIFFUSE_SHADE_FLAT | - RADEON_ALPHA_SHADE_FLAT | - RADEON_SPECULAR_SHADE_FLAT | - RADEON_FOG_SHADE_FLAT | - RADEON_VTX_PIX_CENTER_OGL | - RADEON_ROUND_MODE_TRUNC | - RADEON_ROUND_PREC_8TH_PIX); - - DRM_GETSAREA(); - - dev_priv->fb_offset = init->fb_offset; - dev_priv->mmio_offset = init->mmio_offset; - dev_priv->ring_offset = init->ring_offset; - dev_priv->ring_rptr_offset = init->ring_rptr_offset; - dev_priv->buffers_offset = init->buffers_offset; - dev_priv->gart_textures_offset = init->gart_textures_offset; - - if(!dev_priv->sarea) { - DRM_ERROR("could not find sarea!\n"); - radeon_do_cleanup_cp(dev); - return DRM_ERR(EINVAL); - } - - dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset); - if(!dev_priv->mmio) { - DRM_ERROR("could not find mmio region!\n"); - radeon_do_cleanup_cp(dev); - return DRM_ERR(EINVAL); - } - dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset); - if(!dev_priv->cp_ring) { - DRM_ERROR("could not find cp ring region!\n"); - radeon_do_cleanup_cp(dev); - return DRM_ERR(EINVAL); - } - dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); - if(!dev_priv->ring_rptr) { - DRM_ERROR("could not find ring read pointer!\n"); - radeon_do_cleanup_cp(dev); - return DRM_ERR(EINVAL); - } - dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); - if(!dev->agp_buffer_map) { - DRM_ERROR("could not find dma buffer region!\n"); - radeon_do_cleanup_cp(dev); - return DRM_ERR(EINVAL); - } - - if ( init->gart_textures_offset ) { - dev_priv->gart_textures = drm_core_findmap(dev, init->gart_textures_offset); - if ( !dev_priv->gart_textures ) { - DRM_ERROR("could not find GART texture region!\n"); - radeon_do_cleanup_cp(dev); - return DRM_ERR(EINVAL); - } - } - - dev_priv->sarea_priv = - (drm_radeon_sarea_t *)((u8 *)dev_priv->sarea->handle + - init->sarea_priv_offset); - -#if __OS_HAS_AGP - if ( dev_priv->flags & CHIP_IS_AGP ) { - drm_core_ioremap( dev_priv->cp_ring, dev ); - drm_core_ioremap( dev_priv->ring_rptr, dev ); - drm_core_ioremap( dev->agp_buffer_map, dev ); - if(!dev_priv->cp_ring->handle || - !dev_priv->ring_rptr->handle || - !dev->agp_buffer_map->handle) { - DRM_ERROR("could not find ioremap agp regions!\n"); - radeon_do_cleanup_cp(dev); - return DRM_ERR(EINVAL); - } - } else -#endif - { - dev_priv->cp_ring->handle = - (void *)dev_priv->cp_ring->offset; - dev_priv->ring_rptr->handle = - (void *)dev_priv->ring_rptr->offset; - dev->agp_buffer_map->handle = (void *)dev->agp_buffer_map->offset; - - DRM_DEBUG( "dev_priv->cp_ring->handle %p\n", - dev_priv->cp_ring->handle ); - DRM_DEBUG( "dev_priv->ring_rptr->handle %p\n", - dev_priv->ring_rptr->handle ); - DRM_DEBUG( "dev->agp_buffer_map->handle %p\n", - dev->agp_buffer_map->handle ); - } - - dev_priv->fb_location = ( RADEON_READ( RADEON_MC_FB_LOCATION ) - & 0xffff ) << 16; - - dev_priv->front_pitch_offset = (((dev_priv->front_pitch/64) << 22) | - ( ( dev_priv->front_offset - + dev_priv->fb_location ) >> 10 ) ); - - dev_priv->back_pitch_offset = (((dev_priv->back_pitch/64) << 22) | - ( ( dev_priv->back_offset - + dev_priv->fb_location ) >> 10 ) ); - - dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch/64) << 22) | - ( ( dev_priv->depth_offset - + dev_priv->fb_location ) >> 10 ) ); - - - dev_priv->gart_size = init->gart_size; - dev_priv->gart_vm_start = dev_priv->fb_location - + RADEON_READ( RADEON_CONFIG_APER_SIZE ); - -#if __OS_HAS_AGP - if (dev_priv->flags & CHIP_IS_AGP) - dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset - - dev->agp->base - + dev_priv->gart_vm_start); - else -#endif - dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset - - dev->sg->handle - + dev_priv->gart_vm_start); - - DRM_DEBUG( "dev_priv->gart_size %d\n", - dev_priv->gart_size ); - DRM_DEBUG( "dev_priv->gart_vm_start 0x%x\n", - dev_priv->gart_vm_start ); - DRM_DEBUG( "dev_priv->gart_buffers_offset 0x%lx\n", - dev_priv->gart_buffers_offset ); - - dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle; - dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle - + init->ring_size / sizeof(u32)); - dev_priv->ring.size = init->ring_size; - dev_priv->ring.size_l2qw = DRM(order)( init->ring_size / 8 ); - - dev_priv->ring.tail_mask = - (dev_priv->ring.size / sizeof(u32)) - 1; - - dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; - -#if __OS_HAS_AGP - if (dev_priv->flags & CHIP_IS_AGP) { - /* Turn off PCI GART */ - radeon_set_pcigart( dev_priv, 0 ); - } else -#endif - { - if (!DRM(ati_pcigart_init)( dev, &dev_priv->phys_pci_gart, - &dev_priv->bus_pci_gart)) { - DRM_ERROR( "failed to init PCI GART!\n" ); - radeon_do_cleanup_cp(dev); - return DRM_ERR(ENOMEM); - } - - /* Turn on PCI GART */ - radeon_set_pcigart( dev_priv, 1 ); - } - - radeon_cp_load_microcode( dev_priv ); - radeon_cp_init_ring_buffer( dev, dev_priv ); - - dev_priv->last_buf = 0; - - radeon_do_engine_reset( dev ); - - return 0; -} - -int radeon_do_cleanup_cp( drm_device_t *dev ) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "\n" ); - - /* Make sure interrupts are disabled here because the uninstall ioctl - * may not have been called from userspace and after dev_private - * is freed, it's too late. - */ - if ( dev->irq_enabled ) DRM(irq_uninstall)(dev); - -#if __OS_HAS_AGP - if (dev_priv->flags & CHIP_IS_AGP) { - if ( dev_priv->cp_ring != NULL ) { - drm_core_ioremapfree( dev_priv->cp_ring, dev ); - dev_priv->cp_ring = NULL; - } - if ( dev_priv->ring_rptr != NULL ) { - drm_core_ioremapfree( dev_priv->ring_rptr, dev ); - dev_priv->ring_rptr = NULL; - } - if ( dev->agp_buffer_map != NULL ) { - drm_core_ioremapfree( dev->agp_buffer_map, dev ); - dev->agp_buffer_map = NULL; - } - } else -#endif - { - if (!DRM(ati_pcigart_cleanup)( dev, - dev_priv->phys_pci_gart, - dev_priv->bus_pci_gart )) - DRM_ERROR( "failed to cleanup PCI GART!\n" ); - } - /* only clear to the start of flags */ - memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags)); - - return 0; -} - -/* This code will reinit the Radeon CP hardware after a resume from disc. - * AFAIK, it would be very difficult to pickle the state at suspend time, so - * here we make sure that all Radeon hardware initialisation is re-done without - * affecting running applications. - * - * Charl P. Botha - */ -static int radeon_do_resume_cp( drm_device_t *dev ) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - - if ( !dev_priv ) { - DRM_ERROR( "Called with no initialization\n" ); - return DRM_ERR( EINVAL ); - } - - DRM_DEBUG("Starting radeon_do_resume_cp()\n"); - -#if __OS_HAS_AGP - if (dev_priv->flags & CHIP_IS_AGP) { - /* Turn off PCI GART */ - radeon_set_pcigart( dev_priv, 0 ); - } else -#endif - { - /* Turn on PCI GART */ - radeon_set_pcigart( dev_priv, 1 ); - } - - radeon_cp_load_microcode( dev_priv ); - radeon_cp_init_ring_buffer( dev, dev_priv ); - - radeon_do_engine_reset( dev ); - - DRM_DEBUG("radeon_do_resume_cp() complete\n"); - - return 0; -} - - -int radeon_cp_init( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_radeon_init_t init; - - LOCK_TEST_WITH_RETURN( dev, filp ); - - DRM_COPY_FROM_USER_IOCTL( init, (drm_radeon_init_t __user *)data, sizeof(init) ); - - switch ( init.func ) { - case RADEON_INIT_CP: - case RADEON_INIT_R200_CP: - case RADEON_INIT_R300_CP: - return radeon_do_init_cp( dev, &init ); - case RADEON_CLEANUP_CP: - return radeon_do_cleanup_cp( dev ); - } - - return DRM_ERR(EINVAL); -} - -int radeon_cp_start( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_radeon_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "\n" ); - - LOCK_TEST_WITH_RETURN( dev, filp ); - - if ( dev_priv->cp_running ) { - DRM_DEBUG( "%s while CP running\n", __FUNCTION__ ); - return 0; - } - if ( dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS ) { - DRM_DEBUG( "%s called with bogus CP mode (%d)\n", - __FUNCTION__, dev_priv->cp_mode ); - return 0; - } - - radeon_do_cp_start( dev_priv ); - - return 0; -} - -/* Stop the CP. The engine must have been idled before calling this - * routine. - */ -int radeon_cp_stop( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_cp_stop_t stop; - int ret; - DRM_DEBUG( "\n" ); - - LOCK_TEST_WITH_RETURN( dev, filp ); - - DRM_COPY_FROM_USER_IOCTL( stop, (drm_radeon_cp_stop_t __user *)data, sizeof(stop) ); - - if (!dev_priv->cp_running) - return 0; - - /* Flush any pending CP commands. This ensures any outstanding - * commands are exectuted by the engine before we turn it off. - */ - if ( stop.flush ) { - radeon_do_cp_flush( dev_priv ); - } - - /* If we fail to make the engine go idle, we return an error - * code so that the DRM ioctl wrapper can try again. - */ - if ( stop.idle ) { - ret = radeon_do_cp_idle( dev_priv ); - if ( ret ) return ret; - } - - /* Finally, we can turn off the CP. If the engine isn't idle, - * we will get some dropped triangles as they won't be fully - * rendered before the CP is shut down. - */ - radeon_do_cp_stop( dev_priv ); - - /* Reset the engine */ - radeon_do_engine_reset( dev ); - - return 0; -} - - -void radeon_do_release( drm_device_t *dev ) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - int i, ret; - - if (dev_priv) { - - if (dev_priv->cp_running) { - /* Stop the cp */ - while ((ret = radeon_do_cp_idle( dev_priv )) != 0) { - DRM_DEBUG("radeon_do_cp_idle %d\n", ret); -#ifdef __linux__ - schedule(); -#else - tsleep(&ret, PZERO, "rdnrel", 1); -#endif - } - radeon_do_cp_stop( dev_priv ); - radeon_do_engine_reset( dev ); - } - - /* Disable *all* interrupts */ - if (dev_priv->mmio) /* remove this after permanent addmaps */ - RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 ); - - if (dev_priv->mmio) {/* remove all surfaces */ - for (i = 0; i < RADEON_MAX_SURFACES; i++) { - RADEON_WRITE(RADEON_SURFACE0_INFO + 16*i, 0); - RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16*i, 0); - RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16*i, 0); - } - } - - /* Free memory heap structures */ - radeon_mem_takedown( &(dev_priv->gart_heap) ); - radeon_mem_takedown( &(dev_priv->fb_heap) ); - - /* deallocate kernel resources */ - radeon_do_cleanup_cp( dev ); - } -} - -/* Just reset the CP ring. Called as part of an X Server engine reset. - */ -int radeon_cp_reset( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_radeon_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "\n" ); - - LOCK_TEST_WITH_RETURN( dev, filp ); - - if ( !dev_priv ) { - DRM_DEBUG( "%s called before init done\n", __FUNCTION__ ); - return DRM_ERR(EINVAL); - } - - radeon_do_cp_reset( dev_priv ); - - /* The CP is no longer running after an engine reset */ - dev_priv->cp_running = 0; - - return 0; -} - -int radeon_cp_idle( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_radeon_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "\n" ); - - LOCK_TEST_WITH_RETURN( dev, filp ); - - return radeon_do_cp_idle( dev_priv ); -} - -/* Added by Charl P. Botha to call radeon_do_resume_cp(). - */ -int radeon_cp_resume( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - - return radeon_do_resume_cp(dev); -} - - -int radeon_engine_reset( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - DRM_DEBUG( "\n" ); - - LOCK_TEST_WITH_RETURN( dev, filp ); - - return radeon_do_engine_reset( dev ); -} - - -/* ================================================================ - * Fullscreen mode - */ - -/* KW: Deprecated to say the least: - */ -int radeon_fullscreen( DRM_IOCTL_ARGS ) -{ - return 0; -} - - -/* ================================================================ - * Freelist management - */ - -/* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through - * bufs until freelist code is used. Note this hides a problem with - * the scratch register * (used to keep track of last buffer - * completed) being written to before * the last buffer has actually - * completed rendering. - * - * KW: It's also a good way to find free buffers quickly. - * - * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't - * sleep. However, bugs in older versions of radeon_accel.c mean that - * we essentially have to do this, else old clients will break. - * - * However, it does leave open a potential deadlock where all the - * buffers are held by other clients, which can't release them because - * they can't get the lock. - */ - -drm_buf_t *radeon_freelist_get( drm_device_t *dev ) -{ - drm_device_dma_t *dma = dev->dma; - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_buf_priv_t *buf_priv; - drm_buf_t *buf; - int i, t; - int start; - - if ( ++dev_priv->last_buf >= dma->buf_count ) - dev_priv->last_buf = 0; - - start = dev_priv->last_buf; - - for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) { - u32 done_age = GET_SCRATCH( 1 ); - DRM_DEBUG("done_age = %d\n",done_age); - for ( i = start ; i < dma->buf_count ; i++ ) { - buf = dma->buflist[i]; - buf_priv = buf->dev_private; - if ( buf->filp == 0 || (buf->pending && - buf_priv->age <= done_age) ) { - dev_priv->stats.requested_bufs++; - buf->pending = 0; - return buf; - } - start = 0; - } - - if (t) { - DRM_UDELAY( 1 ); - dev_priv->stats.freelist_loops++; - } - } - - DRM_DEBUG( "returning NULL!\n" ); - return NULL; -} -#if 0 -drm_buf_t *radeon_freelist_get( drm_device_t *dev ) -{ - drm_device_dma_t *dma = dev->dma; - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_buf_priv_t *buf_priv; - drm_buf_t *buf; - int i, t; - int start; - u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)); - - if ( ++dev_priv->last_buf >= dma->buf_count ) - dev_priv->last_buf = 0; - - start = dev_priv->last_buf; - dev_priv->stats.freelist_loops++; - - for ( t = 0 ; t < 2 ; t++ ) { - for ( i = start ; i < dma->buf_count ; i++ ) { - buf = dma->buflist[i]; - buf_priv = buf->dev_private; - if ( buf->filp == 0 || (buf->pending && - buf_priv->age <= done_age) ) { - dev_priv->stats.requested_bufs++; - buf->pending = 0; - return buf; - } - } - start = 0; - } - - return NULL; -} -#endif - -void radeon_freelist_reset( drm_device_t *dev ) -{ - drm_device_dma_t *dma = dev->dma; - drm_radeon_private_t *dev_priv = dev->dev_private; - int i; - - dev_priv->last_buf = 0; - for ( i = 0 ; i < dma->buf_count ; i++ ) { - drm_buf_t *buf = dma->buflist[i]; - drm_radeon_buf_priv_t *buf_priv = buf->dev_private; - buf_priv->age = 0; - } -} - - -/* ================================================================ - * CP command submission - */ - -int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n ) -{ - drm_radeon_ring_buffer_t *ring = &dev_priv->ring; - int i; - u32 last_head = GET_RING_HEAD( dev_priv ); - - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - u32 head = GET_RING_HEAD( dev_priv ); - - ring->space = (head - ring->tail) * sizeof(u32); - if ( ring->space <= 0 ) - ring->space += ring->size; - if ( ring->space > n ) - return 0; - - dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; - - if (head != last_head) - i = 0; - last_head = head; - - DRM_UDELAY( 1 ); - } - - /* FIXME: This return value is ignored in the BEGIN_RING macro! */ -#if RADEON_FIFO_DEBUG - radeon_status( dev_priv ); - DRM_ERROR( "failed!\n" ); -#endif - return DRM_ERR(EBUSY); -} - -static int radeon_cp_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d ) -{ - int i; - drm_buf_t *buf; - - for ( i = d->granted_count ; i < d->request_count ; i++ ) { - buf = radeon_freelist_get( dev ); - if ( !buf ) return DRM_ERR(EBUSY); /* NOTE: broken client */ - - buf->filp = filp; - - if ( DRM_COPY_TO_USER( &d->request_indices[i], &buf->idx, - sizeof(buf->idx) ) ) - return DRM_ERR(EFAULT); - if ( DRM_COPY_TO_USER( &d->request_sizes[i], &buf->total, - sizeof(buf->total) ) ) - return DRM_ERR(EFAULT); - - d->granted_count++; - } - return 0; -} - -int radeon_cp_buffers( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_device_dma_t *dma = dev->dma; - int ret = 0; - drm_dma_t __user *argp = (void __user *)data; - drm_dma_t d; - - LOCK_TEST_WITH_RETURN( dev, filp ); - - DRM_COPY_FROM_USER_IOCTL( d, argp, sizeof(d) ); - - /* Please don't send us buffers. - */ - if ( d.send_count != 0 ) { - DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n", - DRM_CURRENTPID, d.send_count ); - return DRM_ERR(EINVAL); - } - - /* We'll send you buffers. - */ - if ( d.request_count < 0 || d.request_count > dma->buf_count ) { - DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n", - DRM_CURRENTPID, d.request_count, dma->buf_count ); - return DRM_ERR(EINVAL); - } - - d.granted_count = 0; - - if ( d.request_count ) { - ret = radeon_cp_get_buffers( filp, dev, &d ); - } - - DRM_COPY_TO_USER_IOCTL( argp, d, sizeof(d) ); - - return ret; -} - -/* Always create a map record for MMIO and FB memory, done from DRIVER_POSTINIT */ -int radeon_preinit( struct drm_device *dev, unsigned long flags ) -{ - u32 save, temp; - drm_radeon_private_t *dev_priv; - int ret = 0; - - dev_priv = DRM(alloc)( sizeof(drm_radeon_private_t), DRM_MEM_DRIVER ); - if ( dev_priv == NULL ) - return DRM_ERR(ENOMEM); - - memset( dev_priv, 0, sizeof(drm_radeon_private_t) ); - dev->dev_private = (void *)dev_priv; - dev_priv->flags = flags; - - switch (flags & CHIP_FAMILY_MASK) { - case CHIP_R100: - case CHIP_RV200: - case CHIP_R200: - case CHIP_R300: - dev_priv->flags |= CHIP_HAS_HIERZ; - break; - default: - /* all other chips have no hierarchical z buffer */ - break; - } - - /* registers */ - if( (ret = DRM(initmap)( dev, pci_resource_start( dev->pdev, 2 ), - pci_resource_len( dev->pdev, 2 ), _DRM_REGISTERS, 0 ))) - return ret; - - /* framebuffer */ - if( (ret = DRM(initmap)( dev, pci_resource_start( dev->pdev, 0 ), - pci_resource_len( dev->pdev, 0 ), _DRM_FRAME_BUFFER, _DRM_WRITE_COMBINING ))) - return ret; - - /* There are signatures in BIOS and PCI-SSID for a PCI card, but they are not very reliable. - Following detection method works for all cards tested so far. - Note, checking AGP_ENABLE bit after drmAgpEnable call can also give the correct result. - However, calling drmAgpEnable on a PCI card can cause some strange lockup when the server - restarts next time. - */ - pci_read_config_dword(dev->pdev, RADEON_AGP_COMMAND_PCI_CONFIG, &save); - pci_write_config_dword(dev->pdev, RADEON_AGP_COMMAND_PCI_CONFIG, save | RADEON_AGP_ENABLE); - pci_read_config_dword(dev->pdev, RADEON_AGP_COMMAND_PCI_CONFIG, &temp); - if (temp & RADEON_AGP_ENABLE) - dev_priv->flags |= CHIP_IS_AGP; - DRM_DEBUG("%s card detected\n", ((dev_priv->flags & CHIP_IS_AGP) ? "AGP" : "PCI")); - pci_write_config_dword(dev->pdev, RADEON_AGP_COMMAND_PCI_CONFIG, save); - - /* Check if we need a reset */ - if (!(dev_priv->mmio = drm_core_findmap(dev , pci_resource_start( dev->pdev, 2 )))) - return DRM_ERR(ENOMEM); - -#if defined(__linux__) - ret = radeon_create_i2c_busses(dev); -#endif - return ret; -} - -int radeon_postinit( struct drm_device *dev, unsigned long flags ) -{ - return 0; -} - -int radeon_postcleanup( struct drm_device *dev ) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - - DRM_DEBUG("\n"); -#if defined(__linux__) - radeon_delete_i2c_busses(dev); -#endif - DRM(free)( dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER ); - - dev->dev_private = NULL; - return 0; -} diff --git a/nx-X11/extras/drm/shared/radeon_drm.h b/nx-X11/extras/drm/shared/radeon_drm.h deleted file mode 100644 index 0253a4ead..000000000 --- a/nx-X11/extras/drm/shared/radeon_drm.h +++ /dev/null @@ -1,661 +0,0 @@ -/* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*- - * - * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. - * Copyright 2000 VA Linux Systems, Inc., Fremont, California. - * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. - * All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Kevin E. Martin - * Gareth Hughes - * Keith Whitwell - */ - -#ifndef __RADEON_DRM_H__ -#define __RADEON_DRM_H__ - -/* WARNING: If you change any of these defines, make sure to change the - * defines in the X server file (radeon_sarea.h) - */ -#ifndef __RADEON_SAREA_DEFINES__ -#define __RADEON_SAREA_DEFINES__ - -/* Old style state flags, required for sarea interface (1.1 and 1.2 - * clears) and 1.2 drm_vertex2 ioctl. - */ -#define RADEON_UPLOAD_CONTEXT 0x00000001 -#define RADEON_UPLOAD_VERTFMT 0x00000002 -#define RADEON_UPLOAD_LINE 0x00000004 -#define RADEON_UPLOAD_BUMPMAP 0x00000008 -#define RADEON_UPLOAD_MASKS 0x00000010 -#define RADEON_UPLOAD_VIEWPORT 0x00000020 -#define RADEON_UPLOAD_SETUP 0x00000040 -#define RADEON_UPLOAD_TCL 0x00000080 -#define RADEON_UPLOAD_MISC 0x00000100 -#define RADEON_UPLOAD_TEX0 0x00000200 -#define RADEON_UPLOAD_TEX1 0x00000400 -#define RADEON_UPLOAD_TEX2 0x00000800 -#define RADEON_UPLOAD_TEX0IMAGES 0x00001000 -#define RADEON_UPLOAD_TEX1IMAGES 0x00002000 -#define RADEON_UPLOAD_TEX2IMAGES 0x00004000 -#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */ -#define RADEON_REQUIRE_QUIESCENCE 0x00010000 -#define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */ -#define RADEON_UPLOAD_ALL 0x003effff -#define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff - - -/* New style per-packet identifiers for use in cmd_buffer ioctl with - * the RADEON_EMIT_PACKET command. Comments relate new packets to old - * state bits and the packet size: - */ -#define RADEON_EMIT_PP_MISC 0 /* context/7 */ -#define RADEON_EMIT_PP_CNTL 1 /* context/3 */ -#define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */ -#define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */ -#define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */ -#define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */ -#define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */ -#define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */ -#define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */ -#define RADEON_EMIT_SE_CNTL 9 /* setup/2 */ -#define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */ -#define RADEON_EMIT_RE_MISC 11 /* misc/1 */ -#define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */ -#define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */ -#define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */ -#define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */ -#define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */ -#define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */ -#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */ -#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */ -#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */ -#define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */ -#define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */ -#define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */ -#define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */ -#define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */ -#define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */ -#define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */ -#define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */ -#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */ -#define R200_EMIT_TFACTOR_0 30 /* tf/7 */ -#define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */ -#define R200_EMIT_VAP_CTL 32 /* vap/1 */ -#define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */ -#define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */ -#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */ -#define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */ -#define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */ -#define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */ -#define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */ -#define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */ -#define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */ -#define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */ -#define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */ -#define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */ -#define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */ -#define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */ -#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */ -#define R200_EMIT_VTE_CNTL 48 /* vte/1 */ -#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */ -#define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */ -#define R200_EMIT_PP_CNTL_X 51 /* cst/1 */ -#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */ -#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */ -#define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */ -#define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */ -#define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */ -#define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */ -#define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */ -#define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */ -#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */ -#define R200_EMIT_PP_CUBIC_FACES_0 61 -#define R200_EMIT_PP_CUBIC_OFFSETS_0 62 -#define R200_EMIT_PP_CUBIC_FACES_1 63 -#define R200_EMIT_PP_CUBIC_OFFSETS_1 64 -#define R200_EMIT_PP_CUBIC_FACES_2 65 -#define R200_EMIT_PP_CUBIC_OFFSETS_2 66 -#define R200_EMIT_PP_CUBIC_FACES_3 67 -#define R200_EMIT_PP_CUBIC_OFFSETS_3 68 -#define R200_EMIT_PP_CUBIC_FACES_4 69 -#define R200_EMIT_PP_CUBIC_OFFSETS_4 70 -#define R200_EMIT_PP_CUBIC_FACES_5 71 -#define R200_EMIT_PP_CUBIC_OFFSETS_5 72 -#define RADEON_EMIT_PP_TEX_SIZE_0 73 -#define RADEON_EMIT_PP_TEX_SIZE_1 74 -#define RADEON_EMIT_PP_TEX_SIZE_2 75 -#define R200_EMIT_RB3D_BLENDCOLOR 76 -#define R200_EMIT_TCL_POINT_SPRITE_CNTL 77 -#define RADEON_EMIT_PP_CUBIC_FACES_0 78 -#define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79 -#define RADEON_EMIT_PP_CUBIC_FACES_1 80 -#define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81 -#define RADEON_EMIT_PP_CUBIC_FACES_2 82 -#define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83 -#define R200_EMIT_PP_TRI_PERF_CNTL 84 -#define RADEON_MAX_STATE_PACKETS 85 - - -/* Commands understood by cmd_buffer ioctl. More can be added but - * obviously these can't be removed or changed: - */ -#define RADEON_CMD_PACKET 1 /* emit one of the register packets above */ -#define RADEON_CMD_SCALARS 2 /* emit scalar data */ -#define RADEON_CMD_VECTORS 3 /* emit vector data */ -#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */ -#define RADEON_CMD_PACKET3 5 /* emit hw packet */ -#define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */ -#define RADEON_CMD_SCALARS2 7 /* r200 stopgap */ -#define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note: - * doesn't make the cpu wait, just - * the graphics hardware */ - - -typedef union { - int i; - struct { - unsigned char cmd_type, pad0, pad1, pad2; - } header; - struct { - unsigned char cmd_type, packet_id, pad0, pad1; - } packet; - struct { - unsigned char cmd_type, offset, stride, count; - } scalars; - struct { - unsigned char cmd_type, offset, stride, count; - } vectors; - struct { - unsigned char cmd_type, buf_idx, pad0, pad1; - } dma; - struct { - unsigned char cmd_type, flags, pad0, pad1; - } wait; -} drm_radeon_cmd_header_t; - -#define RADEON_WAIT_2D 0x1 -#define RADEON_WAIT_3D 0x2 - - -#define RADEON_FRONT 0x1 -#define RADEON_BACK 0x2 -#define RADEON_DEPTH 0x4 -#define RADEON_STENCIL 0x8 -#define RADEON_CLEAR_FASTZ 0x80000000 -#define RADEON_USE_HIERZ 0x40000000 -#define RADEON_USE_COMP_ZBUF 0x20000000 - -/* Primitive types - */ -#define RADEON_POINTS 0x1 -#define RADEON_LINES 0x2 -#define RADEON_LINE_STRIP 0x3 -#define RADEON_TRIANGLES 0x4 -#define RADEON_TRIANGLE_FAN 0x5 -#define RADEON_TRIANGLE_STRIP 0x6 - -/* Vertex/indirect buffer size - */ -#define RADEON_BUFFER_SIZE 65536 - -/* Byte offsets for indirect buffer data - */ -#define RADEON_INDEX_PRIM_OFFSET 20 - -#define RADEON_SCRATCH_REG_OFFSET 32 - -#define RADEON_NR_SAREA_CLIPRECTS 12 - -/* There are 2 heaps (local/GART). Each region within a heap is a - * minimum of 64k, and there are at most 64 of them per heap. - */ -#define RADEON_LOCAL_TEX_HEAP 0 -#define RADEON_GART_TEX_HEAP 1 -#define RADEON_NR_TEX_HEAPS 2 -#define RADEON_NR_TEX_REGIONS 64 -#define RADEON_LOG_TEX_GRANULARITY 16 - -#define RADEON_MAX_TEXTURE_LEVELS 12 -#define RADEON_MAX_TEXTURE_UNITS 3 - -#define RADEON_MAX_SURFACES 8 - -/* Blits have strict offset rules. All blit offset must be aligned on - * a 1K-byte boundary. - */ -#define RADEON_OFFSET_SHIFT 10 -#define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT) -#define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1) - -#endif /* __RADEON_SAREA_DEFINES__ */ - -typedef struct { - unsigned int red; - unsigned int green; - unsigned int blue; - unsigned int alpha; -} radeon_color_regs_t; - -typedef struct { - /* Context state */ - unsigned int pp_misc; /* 0x1c14 */ - unsigned int pp_fog_color; - unsigned int re_solid_color; - unsigned int rb3d_blendcntl; - unsigned int rb3d_depthoffset; - unsigned int rb3d_depthpitch; - unsigned int rb3d_zstencilcntl; - - unsigned int pp_cntl; /* 0x1c38 */ - unsigned int rb3d_cntl; - unsigned int rb3d_coloroffset; - unsigned int re_width_height; - unsigned int rb3d_colorpitch; - unsigned int se_cntl; - - /* Vertex format state */ - unsigned int se_coord_fmt; /* 0x1c50 */ - - /* Line state */ - unsigned int re_line_pattern; /* 0x1cd0 */ - unsigned int re_line_state; - - unsigned int se_line_width; /* 0x1db8 */ - - /* Bumpmap state */ - unsigned int pp_lum_matrix; /* 0x1d00 */ - - unsigned int pp_rot_matrix_0; /* 0x1d58 */ - unsigned int pp_rot_matrix_1; - - /* Mask state */ - unsigned int rb3d_stencilrefmask; /* 0x1d7c */ - unsigned int rb3d_ropcntl; - unsigned int rb3d_planemask; - - /* Viewport state */ - unsigned int se_vport_xscale; /* 0x1d98 */ - unsigned int se_vport_xoffset; - unsigned int se_vport_yscale; - unsigned int se_vport_yoffset; - unsigned int se_vport_zscale; - unsigned int se_vport_zoffset; - - /* Setup state */ - unsigned int se_cntl_status; /* 0x2140 */ - - /* Misc state */ - unsigned int re_top_left; /* 0x26c0 */ - unsigned int re_misc; -} drm_radeon_context_regs_t; - -typedef struct { - /* Zbias state */ - unsigned int se_zbias_factor; /* 0x1dac */ - unsigned int se_zbias_constant; -} drm_radeon_context2_regs_t; - - -/* Setup registers for each texture unit - */ -typedef struct { - unsigned int pp_txfilter; - unsigned int pp_txformat; - unsigned int pp_txoffset; - unsigned int pp_txcblend; - unsigned int pp_txablend; - unsigned int pp_tfactor; - unsigned int pp_border_color; -} drm_radeon_texture_regs_t; - -typedef struct { - unsigned int start; - unsigned int finish; - unsigned int prim:8; - unsigned int stateidx:8; - unsigned int numverts:16; /* overloaded as offset/64 for elt prims */ - unsigned int vc_format; /* vertex format */ -} drm_radeon_prim_t; - - -typedef struct { - drm_radeon_context_regs_t context; - drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS]; - drm_radeon_context2_regs_t context2; - unsigned int dirty; -} drm_radeon_state_t; - - -typedef struct { - /* The channel for communication of state information to the - * kernel on firing a vertex buffer with either of the - * obsoleted vertex/index ioctls. - */ - drm_radeon_context_regs_t context_state; - drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS]; - unsigned int dirty; - unsigned int vertsize; - unsigned int vc_format; - - /* The current cliprects, or a subset thereof. - */ - drm_clip_rect_t boxes[RADEON_NR_SAREA_CLIPRECTS]; - unsigned int nbox; - - /* Counters for client-side throttling of rendering clients. - */ - unsigned int last_frame; - unsigned int last_dispatch; - unsigned int last_clear; - - drm_tex_region_t tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS+1]; - unsigned int tex_age[RADEON_NR_TEX_HEAPS]; - int ctx_owner; - int pfState; /* number of 3d windows (0,1,2ormore) */ - int pfCurrentPage; /* which buffer is being displayed? */ - int crtc2_base; /* CRTC2 frame offset */ - int tiling_enabled; /* set by drm, read by 2d + 3d clients */ -} drm_radeon_sarea_t; - - -/* WARNING: If you change any of these defines, make sure to change the - * defines in the Xserver file (xf86drmRadeon.h) - * - * KW: actually it's illegal to change any of this (backwards compatibility). - */ - -/* Radeon specific ioctls - * The device specific ioctl range is 0x40 to 0x79. - */ -#define DRM_RADEON_CP_INIT 0x00 -#define DRM_RADEON_CP_START 0x01 -#define DRM_RADEON_CP_STOP 0x02 -#define DRM_RADEON_CP_RESET 0x03 -#define DRM_RADEON_CP_IDLE 0x04 -#define DRM_RADEON_RESET 0x05 -#define DRM_RADEON_FULLSCREEN 0x06 -#define DRM_RADEON_SWAP 0x07 -#define DRM_RADEON_CLEAR 0x08 -#define DRM_RADEON_VERTEX 0x09 -#define DRM_RADEON_INDICES 0x0A -#define DRM_RADEON_NOT_USED -#define DRM_RADEON_STIPPLE 0x0C -#define DRM_RADEON_INDIRECT 0x0D -#define DRM_RADEON_TEXTURE 0x0E -#define DRM_RADEON_VERTEX2 0x0F -#define DRM_RADEON_CMDBUF 0x10 -#define DRM_RADEON_GETPARAM 0x11 -#define DRM_RADEON_FLIP 0x12 -#define DRM_RADEON_ALLOC 0x13 -#define DRM_RADEON_FREE 0x14 -#define DRM_RADEON_INIT_HEAP 0x15 -#define DRM_RADEON_IRQ_EMIT 0x16 -#define DRM_RADEON_IRQ_WAIT 0x17 -#define DRM_RADEON_CP_RESUME 0x18 -#define DRM_RADEON_SETPARAM 0x19 -#define DRM_RADEON_SURF_ALLOC 0x1a -#define DRM_RADEON_SURF_FREE 0x1b - -#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t) -#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START) -#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t) -#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET) -#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE) -#define DRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET) -#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t) -#define DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP) -#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t) -#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t) -#define DRM_IOCTL_RADEON_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t) -#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t) -#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t) -#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t) -#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t) -#define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t) -#define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t) -#define DRM_IOCTL_RADEON_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP) -#define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t) -#define DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t) -#define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t) -#define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t) -#define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t) -#define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME) -#define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t) -#define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t) -#define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t) - -typedef struct drm_radeon_init { - enum { - RADEON_INIT_CP = 0x01, - RADEON_CLEANUP_CP = 0x02, - RADEON_INIT_R200_CP = 0x03, - RADEON_INIT_R300_CP = 0x04 - } func; - unsigned long sarea_priv_offset; - int is_pci; /* not used, driver asks hardware */ - int cp_mode; - int gart_size; - int ring_size; - int usec_timeout; - - unsigned int fb_bpp; - unsigned int front_offset, front_pitch; - unsigned int back_offset, back_pitch; - unsigned int depth_bpp; - unsigned int depth_offset, depth_pitch; - - unsigned long fb_offset; - unsigned long mmio_offset; - unsigned long ring_offset; - unsigned long ring_rptr_offset; - unsigned long buffers_offset; - unsigned long gart_textures_offset; -} drm_radeon_init_t; - -typedef struct drm_radeon_cp_stop { - int flush; - int idle; -} drm_radeon_cp_stop_t; - -typedef struct drm_radeon_fullscreen { - enum { - RADEON_INIT_FULLSCREEN = 0x01, - RADEON_CLEANUP_FULLSCREEN = 0x02 - } func; -} drm_radeon_fullscreen_t; - -#define CLEAR_X1 0 -#define CLEAR_Y1 1 -#define CLEAR_X2 2 -#define CLEAR_Y2 3 -#define CLEAR_DEPTH 4 - -typedef union drm_radeon_clear_rect { - float f[5]; - unsigned int ui[5]; -} drm_radeon_clear_rect_t; - -typedef struct drm_radeon_clear { - unsigned int flags; - unsigned int clear_color; - unsigned int clear_depth; - unsigned int color_mask; - unsigned int depth_mask; /* misnamed field: should be stencil */ - drm_radeon_clear_rect_t __user *depth_boxes; -} drm_radeon_clear_t; - -typedef struct drm_radeon_vertex { - int prim; - int idx; /* Index of vertex buffer */ - int count; /* Number of vertices in buffer */ - int discard; /* Client finished with buffer? */ -} drm_radeon_vertex_t; - -typedef struct drm_radeon_indices { - int prim; - int idx; - int start; - int end; - int discard; /* Client finished with buffer? */ -} drm_radeon_indices_t; - -/* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices - * - allows multiple primitives and state changes in a single ioctl - * - supports driver change to emit native primitives - */ -typedef struct drm_radeon_vertex2 { - int idx; /* Index of vertex buffer */ - int discard; /* Client finished with buffer? */ - int nr_states; - drm_radeon_state_t __user *state; - int nr_prims; - drm_radeon_prim_t __user *prim; -} drm_radeon_vertex2_t; - -/* v1.3 - obsoletes drm_radeon_vertex2 - * - allows arbitarily large cliprect list - * - allows updating of tcl packet, vector and scalar state - * - allows memory-efficient description of state updates - * - allows state to be emitted without a primitive - * (for clears, ctx switches) - * - allows more than one dma buffer to be referenced per ioctl - * - supports tcl driver - * - may be extended in future versions with new cmd types, packets - */ -typedef struct drm_radeon_cmd_buffer { - int bufsz; - char __user *buf; - int nbox; - drm_clip_rect_t __user *boxes; -} drm_radeon_cmd_buffer_t; - -typedef struct drm_radeon_tex_image { - unsigned int x, y; /* Blit coordinates */ - unsigned int width, height; - const void __user *data; -} drm_radeon_tex_image_t; - -typedef struct drm_radeon_texture { - unsigned int offset; - int pitch; - int format; - int width; /* Texture image coordinates */ - int height; - drm_radeon_tex_image_t __user *image; -} drm_radeon_texture_t; - -typedef struct drm_radeon_stipple { - unsigned int __user *mask; -} drm_radeon_stipple_t; - -typedef struct drm_radeon_indirect { - int idx; - int start; - int end; - int discard; -} drm_radeon_indirect_t; - - -/* 1.3: An ioctl to get parameters that aren't available to the 3d - * client any other way. - */ -#define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */ -#define RADEON_PARAM_LAST_FRAME 2 -#define RADEON_PARAM_LAST_DISPATCH 3 -#define RADEON_PARAM_LAST_CLEAR 4 -/* Added with DRM version 1.6. */ -#define RADEON_PARAM_IRQ_NR 5 -#define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */ -/* Added with DRM version 1.8. */ -#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */ -#define RADEON_PARAM_STATUS_HANDLE 8 -#define RADEON_PARAM_SAREA_HANDLE 9 -#define RADEON_PARAM_GART_TEX_HANDLE 10 -#define RADEON_PARAM_SCRATCH_OFFSET 11 - -typedef struct drm_radeon_getparam { - int param; - void __user *value; -} drm_radeon_getparam_t; - -/* 1.6: Set up a memory manager for regions of shared memory: - */ -#define RADEON_MEM_REGION_GART 1 -#define RADEON_MEM_REGION_FB 2 - -typedef struct drm_radeon_mem_alloc { - int region; - int alignment; - int size; - int __user *region_offset; /* offset from start of fb or GART */ -} drm_radeon_mem_alloc_t; - -typedef struct drm_radeon_mem_free { - int region; - int region_offset; -} drm_radeon_mem_free_t; - -typedef struct drm_radeon_mem_init_heap { - int region; - int size; - int start; -} drm_radeon_mem_init_heap_t; - - -/* 1.6: Userspace can request & wait on irq's: - */ -typedef struct drm_radeon_irq_emit { - int __user *irq_seq; -} drm_radeon_irq_emit_t; - -typedef struct drm_radeon_irq_wait { - int irq_seq; -} drm_radeon_irq_wait_t; - - -/* 1.10: Clients tell the DRM where they think the framebuffer is located in - * the card's address space, via a new generic ioctl to set parameters - */ - -typedef struct drm_radeon_setparam { - unsigned int param; - int64_t value; -} drm_radeon_setparam_t; - -#define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */ -#define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */ - -/* 1.14: Clients can allocate/free a surface - */ -typedef struct drm_radeon_surface_alloc { - unsigned int address; - unsigned int size; - unsigned int flags; -} drm_radeon_surface_alloc_t; - -typedef struct drm_radeon_surface_free { - unsigned int address; -} drm_radeon_surface_free_t; - - -#endif diff --git a/nx-X11/extras/drm/shared/radeon_drv.h b/nx-X11/extras/drm/shared/radeon_drv.h deleted file mode 100644 index 609be6595..000000000 --- a/nx-X11/extras/drm/shared/radeon_drv.h +++ /dev/null @@ -1,1011 +0,0 @@ -/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*- - * - * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. - * Copyright 2000 VA Linux Systems, Inc., Fremont, California. - * All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Kevin E. Martin - * Gareth Hughes - */ - -#ifndef __RADEON_DRV_H__ -#define __RADEON_DRV_H__ - -enum radeon_family { - CHIP_R100, - CHIP_RS100, - CHIP_RV100, - CHIP_R200, - CHIP_RV200, - CHIP_RS200, - CHIP_R250, - CHIP_RS250, - CHIP_RV250, - CHIP_RV280, - CHIP_R300, - CHIP_RS300, - CHIP_RV350, - CHIP_LAST, -}; - -enum radeon_cp_microcode_version { - UCODE_R100, - UCODE_R200, - UCODE_R300, -}; - -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) -#include "radeon_i2c.h" -#endif - -/* - * Chip flags - */ -enum radeon_chip_flags { - CHIP_FAMILY_MASK = 0x0000ffffUL, - CHIP_FLAGS_MASK = 0xffff0000UL, - CHIP_IS_MOBILITY = 0x00010000UL, - CHIP_IS_IGP = 0x00020000UL, - CHIP_SINGLE_CRTC = 0x00040000UL, - CHIP_IS_AGP = 0x00080000UL, - CHIP_HAS_HIERZ = 0x00100000UL, -}; - -#define GET_RING_HEAD(dev_priv) DRM_READ32( (dev_priv)->ring_rptr, 0 ) -#define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) ) - -typedef struct drm_radeon_freelist { - unsigned int age; - drm_buf_t *buf; - struct drm_radeon_freelist *next; - struct drm_radeon_freelist *prev; -} drm_radeon_freelist_t; - -typedef struct drm_radeon_ring_buffer { - u32 *start; - u32 *end; - int size; - int size_l2qw; - - u32 tail; - u32 tail_mask; - int space; - - int high_mark; -} drm_radeon_ring_buffer_t; - -typedef struct drm_radeon_depth_clear_t { - u32 rb3d_cntl; - u32 rb3d_zstencilcntl; - u32 se_cntl; -} drm_radeon_depth_clear_t; - -struct drm_radeon_driver_file_fields { - int64_t radeon_fb_delta; -}; - -struct mem_block { - struct mem_block *next; - struct mem_block *prev; - int start; - int size; - DRMFILE filp; /* 0: free, -1: heap, other: real files */ -}; - -struct radeon_surface { - int refcount; - u32 lower; - u32 upper; - u32 flags; -}; - -struct radeon_virt_surface { - int surface_index; - u32 lower; - u32 upper; - u32 flags; - DRMFILE filp; -}; - -typedef struct drm_radeon_private { - - drm_radeon_ring_buffer_t ring; - drm_radeon_sarea_t *sarea_priv; - - u32 fb_location; - - int gart_size; - u32 gart_vm_start; - unsigned long gart_buffers_offset; - - int cp_mode; - int cp_running; - - drm_radeon_freelist_t *head; - drm_radeon_freelist_t *tail; - int last_buf; - volatile u32 *scratch; - int writeback_works; - - int usec_timeout; - - int microcode_version; - - unsigned long phys_pci_gart; - dma_addr_t bus_pci_gart; - - struct { - u32 boxes; - int freelist_timeouts; - int freelist_loops; - int requested_bufs; - int last_frame_reads; - int last_clear_reads; - int clears; - int texture_uploads; - } stats; - - int do_boxes; - int page_flipping; - int current_page; - - u32 color_fmt; - unsigned int front_offset; - unsigned int front_pitch; - unsigned int back_offset; - unsigned int back_pitch; - - u32 depth_fmt; - unsigned int depth_offset; - unsigned int depth_pitch; - - u32 front_pitch_offset; - u32 back_pitch_offset; - u32 depth_pitch_offset; - - drm_radeon_depth_clear_t depth_clear; - - unsigned long fb_offset; - unsigned long mmio_offset; - unsigned long ring_offset; - unsigned long ring_rptr_offset; - unsigned long buffers_offset; - unsigned long gart_textures_offset; - - drm_local_map_t *sarea; - drm_local_map_t *mmio; - drm_local_map_t *cp_ring; - drm_local_map_t *ring_rptr; - drm_local_map_t *gart_textures; - - struct mem_block *gart_heap; - struct mem_block *fb_heap; - - /* SW interrupt */ - wait_queue_head_t swi_queue; - atomic_t swi_emitted; - - struct radeon_surface surfaces[RADEON_MAX_SURFACES]; - struct radeon_virt_surface virt_surfaces[2*RADEON_MAX_SURFACES]; - - /* starting from here on, data is preserved accross an open */ - uint32_t flags; /* see radeon_chip_flags */ - -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) - struct radeon_i2c_chan i2c[4]; -#endif -} drm_radeon_private_t; - -typedef struct drm_radeon_buf_priv { - u32 age; -} drm_radeon_buf_priv_t; - - /* radeon_cp.c */ -extern int radeon_cp_init( DRM_IOCTL_ARGS ); -extern int radeon_cp_start( DRM_IOCTL_ARGS ); -extern int radeon_cp_stop( DRM_IOCTL_ARGS ); -extern int radeon_cp_reset( DRM_IOCTL_ARGS ); -extern int radeon_cp_idle( DRM_IOCTL_ARGS ); -extern int radeon_cp_resume( DRM_IOCTL_ARGS ); -extern int radeon_engine_reset( DRM_IOCTL_ARGS ); -extern int radeon_fullscreen( DRM_IOCTL_ARGS ); -extern int radeon_cp_buffers( DRM_IOCTL_ARGS ); - -extern void radeon_freelist_reset( drm_device_t *dev ); -extern drm_buf_t *radeon_freelist_get( drm_device_t *dev ); - -extern int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n ); - -extern int radeon_do_cp_idle( drm_radeon_private_t *dev_priv ); -extern int radeon_do_cleanup_cp( drm_device_t *dev ); -extern int radeon_do_cleanup_pageflip( drm_device_t *dev ); - - /* radeon_state.c */ -extern int radeon_cp_clear( DRM_IOCTL_ARGS ); -extern int radeon_cp_swap( DRM_IOCTL_ARGS ); -extern int radeon_cp_vertex( DRM_IOCTL_ARGS ); -extern int radeon_cp_indices( DRM_IOCTL_ARGS ); -extern int radeon_cp_texture( DRM_IOCTL_ARGS ); -extern int radeon_cp_stipple( DRM_IOCTL_ARGS ); -extern int radeon_cp_indirect( DRM_IOCTL_ARGS ); -extern int radeon_cp_vertex2( DRM_IOCTL_ARGS ); -extern int radeon_cp_cmdbuf( DRM_IOCTL_ARGS ); -extern int radeon_cp_getparam( DRM_IOCTL_ARGS ); -extern int radeon_cp_setparam( DRM_IOCTL_ARGS ); -extern int radeon_cp_flip( DRM_IOCTL_ARGS ); - -extern int radeon_mem_alloc( DRM_IOCTL_ARGS ); -extern int radeon_mem_free( DRM_IOCTL_ARGS ); -extern int radeon_mem_init_heap( DRM_IOCTL_ARGS ); -extern void radeon_mem_takedown( struct mem_block **heap ); -extern void radeon_mem_release( DRMFILE filp, struct mem_block *heap ); -extern int radeon_surface_alloc( DRM_IOCTL_ARGS ); -extern int radeon_surface_free( DRM_IOCTL_ARGS ); - - /* radeon_irq.c */ -extern int radeon_irq_emit( DRM_IOCTL_ARGS ); -extern int radeon_irq_wait( DRM_IOCTL_ARGS ); - -extern int radeon_emit_and_wait_irq(drm_device_t *dev); -extern int radeon_wait_irq(drm_device_t *dev, int swi_nr); -extern int radeon_emit_irq(drm_device_t *dev); - -extern void radeon_do_release(drm_device_t *dev); -extern int radeon_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence); -extern irqreturn_t radeon_driver_irq_handler( DRM_IRQ_ARGS ); -extern void radeon_driver_irq_preinstall( drm_device_t *dev ); -extern void radeon_driver_irq_postinstall( drm_device_t *dev ); -extern void radeon_driver_irq_uninstall( drm_device_t *dev ); - -/* Flags for stats.boxes - */ -#define RADEON_BOX_DMA_IDLE 0x1 -#define RADEON_BOX_RING_FULL 0x2 -#define RADEON_BOX_FLIP 0x4 -#define RADEON_BOX_WAIT_IDLE 0x8 -#define RADEON_BOX_TEXTURE_LOAD 0x10 - -/* Register definitions, register access macros and drmAddMap constants - * for Radeon kernel driver. - */ -#define RADEON_AGP_COMMAND 0x0f60 -#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config*/ -# define RADEON_AGP_ENABLE (1<<8) - -#define RADEON_AUX_SCISSOR_CNTL 0x26f0 -# define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24) -# define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25) -# define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26) -# define RADEON_SCISSOR_0_ENABLE (1 << 28) -# define RADEON_SCISSOR_1_ENABLE (1 << 29) -# define RADEON_SCISSOR_2_ENABLE (1 << 30) - -#define RADEON_BUS_CNTL 0x0030 -# define RADEON_BUS_MASTER_DIS (1 << 6) - -#define RADEON_CLOCK_CNTL_DATA 0x000c -# define RADEON_PLL_WR_EN (1 << 7) -#define RADEON_CLOCK_CNTL_INDEX 0x0008 -#define RADEON_CONFIG_APER_SIZE 0x0108 -#define RADEON_CRTC_OFFSET 0x0224 -#define RADEON_CRTC_OFFSET_CNTL 0x0228 -# define RADEON_CRTC_TILE_EN (1 << 15) -# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16) -#define RADEON_CRTC2_OFFSET 0x0324 -#define RADEON_CRTC2_OFFSET_CNTL 0x0328 - -#define RADEON_MPP_TB_CONFIG 0x01c0 -#define RADEON_MEM_CNTL 0x0140 -#define RADEON_MEM_SDRAM_MODE_REG 0x0158 -#define RADEON_AGP_BASE 0x0170 - -#define RADEON_RB3D_COLOROFFSET 0x1c40 -#define RADEON_RB3D_COLORPITCH 0x1c48 - -#define RADEON_DP_GUI_MASTER_CNTL 0x146c -# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) -# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) -# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) -# define RADEON_GMC_BRUSH_NONE (15 << 4) -# define RADEON_GMC_DST_16BPP (4 << 8) -# define RADEON_GMC_DST_24BPP (5 << 8) -# define RADEON_GMC_DST_32BPP (6 << 8) -# define RADEON_GMC_DST_DATATYPE_SHIFT 8 -# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) -# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) -# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) -# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) -# define RADEON_GMC_WR_MSK_DIS (1 << 30) -# define RADEON_ROP3_S 0x00cc0000 -# define RADEON_ROP3_P 0x00f00000 -#define RADEON_DP_WRITE_MASK 0x16cc -#define RADEON_DST_PITCH_OFFSET 0x142c -#define RADEON_DST_PITCH_OFFSET_C 0x1c80 -# define RADEON_DST_TILE_LINEAR (0 << 30) -# define RADEON_DST_TILE_MACRO (1 << 30) -# define RADEON_DST_TILE_MICRO (2 << 30) -# define RADEON_DST_TILE_BOTH (3 << 30) - -#define RADEON_SCRATCH_REG0 0x15e0 -#define RADEON_SCRATCH_REG1 0x15e4 -#define RADEON_SCRATCH_REG2 0x15e8 -#define RADEON_SCRATCH_REG3 0x15ec -#define RADEON_SCRATCH_REG4 0x15f0 -#define RADEON_SCRATCH_REG5 0x15f4 -#define RADEON_SCRATCH_UMSK 0x0770 -#define RADEON_SCRATCH_ADDR 0x0774 - -#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x)) - -#define GET_SCRATCH( x ) (dev_priv->writeback_works \ - ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \ - : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) ) - - -#define RADEON_GEN_INT_CNTL 0x0040 -# define RADEON_CRTC_VBLANK_MASK (1 << 0) -# define RADEON_GUI_IDLE_INT_ENABLE (1 << 19) -# define RADEON_SW_INT_ENABLE (1 << 25) - -#define RADEON_GEN_INT_STATUS 0x0044 -# define RADEON_CRTC_VBLANK_STAT (1 << 0) -# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0) -# define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19) -# define RADEON_SW_INT_TEST (1 << 25) -# define RADEON_SW_INT_TEST_ACK (1 << 25) -# define RADEON_SW_INT_FIRE (1 << 26) - -#define RADEON_HOST_PATH_CNTL 0x0130 -# define RADEON_HDP_SOFT_RESET (1 << 26) -# define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28) -# define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28) - -#define RADEON_ISYNC_CNTL 0x1724 -# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0) -# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1) -# define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2) -# define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3) -# define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4) -# define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5) - -#define RADEON_RBBM_GUICNTL 0x172c -# define RADEON_HOST_DATA_SWAP_NONE (0 << 0) -# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0) -# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0) -# define RADEON_HOST_DATA_SWAP_HDW (3 << 0) - -#define RADEON_MC_AGP_LOCATION 0x014c -#define RADEON_MC_FB_LOCATION 0x0148 -#define RADEON_MCLK_CNTL 0x0012 -# define RADEON_FORCEON_MCLKA (1 << 16) -# define RADEON_FORCEON_MCLKB (1 << 17) -# define RADEON_FORCEON_YCLKA (1 << 18) -# define RADEON_FORCEON_YCLKB (1 << 19) -# define RADEON_FORCEON_MC (1 << 20) -# define RADEON_FORCEON_AIC (1 << 21) - -#define RADEON_PP_BORDER_COLOR_0 0x1d40 -#define RADEON_PP_BORDER_COLOR_1 0x1d44 -#define RADEON_PP_BORDER_COLOR_2 0x1d48 -#define RADEON_PP_CNTL 0x1c38 -# define RADEON_SCISSOR_ENABLE (1 << 1) -#define RADEON_PP_LUM_MATRIX 0x1d00 -#define RADEON_PP_MISC 0x1c14 -#define RADEON_PP_ROT_MATRIX_0 0x1d58 -#define RADEON_PP_TXFILTER_0 0x1c54 -#define RADEON_PP_TXOFFSET_0 0x1c5c -#define RADEON_PP_TXFILTER_1 0x1c6c -#define RADEON_PP_TXFILTER_2 0x1c84 - -#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c -# define RADEON_RB2D_DC_FLUSH (3 << 0) -# define RADEON_RB2D_DC_FREE (3 << 2) -# define RADEON_RB2D_DC_FLUSH_ALL 0xf -# define RADEON_RB2D_DC_BUSY (1 << 31) -#define RADEON_RB3D_CNTL 0x1c3c -# define RADEON_ALPHA_BLEND_ENABLE (1 << 0) -# define RADEON_PLANE_MASK_ENABLE (1 << 1) -# define RADEON_DITHER_ENABLE (1 << 2) -# define RADEON_ROUND_ENABLE (1 << 3) -# define RADEON_SCALE_DITHER_ENABLE (1 << 4) -# define RADEON_DITHER_INIT (1 << 5) -# define RADEON_ROP_ENABLE (1 << 6) -# define RADEON_STENCIL_ENABLE (1 << 7) -# define RADEON_Z_ENABLE (1 << 8) -# define RADEON_ZBLOCK16 (1 << 15) -#define RADEON_RB3D_DEPTHOFFSET 0x1c24 -#define RADEON_RB3D_DEPTHCLEARVALUE 0x3230 -#define RADEON_RB3D_DEPTHPITCH 0x1c28 -#define RADEON_RB3D_PLANEMASK 0x1d84 -#define RADEON_RB3D_STENCILREFMASK 0x1d7c -#define RADEON_RB3D_ZCACHE_MODE 0x3250 -#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254 -# define RADEON_RB3D_ZC_FLUSH (1 << 0) -# define RADEON_RB3D_ZC_FREE (1 << 2) -# define RADEON_RB3D_ZC_FLUSH_ALL 0x5 -# define RADEON_RB3D_ZC_BUSY (1 << 31) -#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c -# define RADEON_Z_TEST_MASK (7 << 4) -# define RADEON_Z_TEST_ALWAYS (7 << 4) -# define RADEON_Z_HIERARCHY_ENABLE (1 << 8) -# define RADEON_STENCIL_TEST_ALWAYS (7 << 12) -# define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16) -# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20) -# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24) -# define RADEON_Z_COMPRESSION_ENABLE (1 << 28) -# define RADEON_FORCE_Z_DIRTY (1 << 29) -# define RADEON_Z_WRITE_ENABLE (1 << 30) -# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31) -#define RADEON_RBBM_SOFT_RESET 0x00f0 -# define RADEON_SOFT_RESET_CP (1 << 0) -# define RADEON_SOFT_RESET_HI (1 << 1) -# define RADEON_SOFT_RESET_SE (1 << 2) -# define RADEON_SOFT_RESET_RE (1 << 3) -# define RADEON_SOFT_RESET_PP (1 << 4) -# define RADEON_SOFT_RESET_E2 (1 << 5) -# define RADEON_SOFT_RESET_RB (1 << 6) -# define RADEON_SOFT_RESET_HDP (1 << 7) -#define RADEON_RBBM_STATUS 0x0e40 -# define RADEON_RBBM_FIFOCNT_MASK 0x007f -# define RADEON_RBBM_ACTIVE (1 << 31) -#define RADEON_RE_LINE_PATTERN 0x1cd0 -#define RADEON_RE_MISC 0x26c4 -#define RADEON_RE_TOP_LEFT 0x26c0 -#define RADEON_RE_WIDTH_HEIGHT 0x1c44 -#define RADEON_RE_STIPPLE_ADDR 0x1cc8 -#define RADEON_RE_STIPPLE_DATA 0x1ccc - -#define RADEON_SCISSOR_TL_0 0x1cd8 -#define RADEON_SCISSOR_BR_0 0x1cdc -#define RADEON_SCISSOR_TL_1 0x1ce0 -#define RADEON_SCISSOR_BR_1 0x1ce4 -#define RADEON_SCISSOR_TL_2 0x1ce8 -#define RADEON_SCISSOR_BR_2 0x1cec -#define RADEON_SE_COORD_FMT 0x1c50 -#define RADEON_SE_CNTL 0x1c4c -# define RADEON_FFACE_CULL_CW (0 << 0) -# define RADEON_BFACE_SOLID (3 << 1) -# define RADEON_FFACE_SOLID (3 << 3) -# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6) -# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8) -# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8) -# define RADEON_ALPHA_SHADE_FLAT (1 << 10) -# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10) -# define RADEON_SPECULAR_SHADE_FLAT (1 << 12) -# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12) -# define RADEON_FOG_SHADE_FLAT (1 << 14) -# define RADEON_FOG_SHADE_GOURAUD (2 << 14) -# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24) -# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25) -# define RADEON_VTX_PIX_CENTER_OGL (1 << 27) -# define RADEON_ROUND_MODE_TRUNC (0 << 28) -# define RADEON_ROUND_PREC_8TH_PIX (1 << 30) -#define RADEON_SE_CNTL_STATUS 0x2140 -#define RADEON_SE_LINE_WIDTH 0x1db8 -#define RADEON_SE_VPORT_XSCALE 0x1d98 -#define RADEON_SE_ZBIAS_FACTOR 0x1db0 -#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210 -#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254 -#define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200 -# define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16 -# define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28 -#define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204 -#define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208 -# define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16 -#define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C -#define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8 -#define RADEON_SURFACE_ACCESS_CLR 0x0bfc -#define RADEON_SURFACE_CNTL 0x0b00 -# define RADEON_SURF_TRANSLATION_DIS (1 << 8) -# define RADEON_NONSURF_AP0_SWP_MASK (3 << 20) -# define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20) -# define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20) -# define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20) -# define RADEON_NONSURF_AP1_SWP_MASK (3 << 22) -# define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22) -# define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22) -# define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22) -#define RADEON_SURFACE0_INFO 0x0b0c -# define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0) -# define RADEON_SURF_TILE_MODE_MASK (3 << 16) -# define RADEON_SURF_TILE_MODE_MACRO (0 << 16) -# define RADEON_SURF_TILE_MODE_MICRO (1 << 16) -# define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16) -# define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16) -#define RADEON_SURFACE0_LOWER_BOUND 0x0b04 -#define RADEON_SURFACE0_UPPER_BOUND 0x0b08 -# define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0) -#define RADEON_SURFACE1_INFO 0x0b1c -#define RADEON_SURFACE1_LOWER_BOUND 0x0b14 -#define RADEON_SURFACE1_UPPER_BOUND 0x0b18 -#define RADEON_SURFACE2_INFO 0x0b2c -#define RADEON_SURFACE2_LOWER_BOUND 0x0b24 -#define RADEON_SURFACE2_UPPER_BOUND 0x0b28 -#define RADEON_SURFACE3_INFO 0x0b3c -#define RADEON_SURFACE3_LOWER_BOUND 0x0b34 -#define RADEON_SURFACE3_UPPER_BOUND 0x0b38 -#define RADEON_SURFACE4_INFO 0x0b4c -#define RADEON_SURFACE4_LOWER_BOUND 0x0b44 -#define RADEON_SURFACE4_UPPER_BOUND 0x0b48 -#define RADEON_SURFACE5_INFO 0x0b5c -#define RADEON_SURFACE5_LOWER_BOUND 0x0b54 -#define RADEON_SURFACE5_UPPER_BOUND 0x0b58 -#define RADEON_SURFACE6_INFO 0x0b6c -#define RADEON_SURFACE6_LOWER_BOUND 0x0b64 -#define RADEON_SURFACE6_UPPER_BOUND 0x0b68 -#define RADEON_SURFACE7_INFO 0x0b7c -#define RADEON_SURFACE7_LOWER_BOUND 0x0b74 -#define RADEON_SURFACE7_UPPER_BOUND 0x0b78 -#define RADEON_SW_SEMAPHORE 0x013c - -#define RADEON_WAIT_UNTIL 0x1720 -# define RADEON_WAIT_CRTC_PFLIP (1 << 0) -# define RADEON_WAIT_2D_IDLECLEAN (1 << 16) -# define RADEON_WAIT_3D_IDLECLEAN (1 << 17) -# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) - -#define RADEON_RB3D_ZMASKOFFSET 0x3234 -#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c -# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) -# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) - - -/* CP registers */ -#define RADEON_CP_ME_RAM_ADDR 0x07d4 -#define RADEON_CP_ME_RAM_RADDR 0x07d8 -#define RADEON_CP_ME_RAM_DATAH 0x07dc -#define RADEON_CP_ME_RAM_DATAL 0x07e0 - -#define RADEON_CP_RB_BASE 0x0700 -#define RADEON_CP_RB_CNTL 0x0704 -# define RADEON_BUF_SWAP_32BIT (2 << 16) -#define RADEON_CP_RB_RPTR_ADDR 0x070c -#define RADEON_CP_RB_RPTR 0x0710 -#define RADEON_CP_RB_WPTR 0x0714 - -#define RADEON_CP_RB_WPTR_DELAY 0x0718 -# define RADEON_PRE_WRITE_TIMER_SHIFT 0 -# define RADEON_PRE_WRITE_LIMIT_SHIFT 23 - -#define RADEON_CP_IB_BASE 0x0738 - -#define RADEON_CP_CSQ_CNTL 0x0740 -# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) -# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) -# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) -# define RADEON_CSQ_PRIBM_INDDIS (2 << 28) -# define RADEON_CSQ_PRIPIO_INDBM (3 << 28) -# define RADEON_CSQ_PRIBM_INDBM (4 << 28) -# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) - -#define RADEON_AIC_CNTL 0x01d0 -# define RADEON_PCIGART_TRANSLATE_EN (1 << 0) -#define RADEON_AIC_STAT 0x01d4 -#define RADEON_AIC_PT_BASE 0x01d8 -#define RADEON_AIC_LO_ADDR 0x01dc -#define RADEON_AIC_HI_ADDR 0x01e0 -#define RADEON_AIC_TLB_ADDR 0x01e4 -#define RADEON_AIC_TLB_DATA 0x01e8 - -/* CP command packets */ -#define RADEON_CP_PACKET0 0x00000000 -# define RADEON_ONE_REG_WR (1 << 15) -#define RADEON_CP_PACKET1 0x40000000 -#define RADEON_CP_PACKET2 0x80000000 -#define RADEON_CP_PACKET3 0xC0000000 -# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300 -# define RADEON_WAIT_FOR_IDLE 0x00002600 -# define RADEON_3D_DRAW_VBUF 0x00002800 -# define RADEON_3D_DRAW_IMMD 0x00002900 -# define RADEON_3D_DRAW_INDX 0x00002A00 -# define RADEON_3D_LOAD_VBPNTR 0x00002F00 -# define RADEON_3D_CLEAR_ZMASK 0x00003200 -# define RADEON_3D_CLEAR_HIZ 0x00003700 -# define RADEON_CNTL_HOSTDATA_BLT 0x00009400 -# define RADEON_CNTL_PAINT_MULTI 0x00009A00 -# define RADEON_CNTL_BITBLT_MULTI 0x00009B00 -# define RADEON_CNTL_SET_SCISSORS 0xC0001E00 - -#define RADEON_CP_PACKET_MASK 0xC0000000 -#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 -#define RADEON_CP_PACKET0_REG_MASK 0x000007ff -#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff -#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 - -#define RADEON_VTX_Z_PRESENT (1 << 31) -#define RADEON_VTX_PKCOLOR_PRESENT (1 << 3) - -#define RADEON_PRIM_TYPE_NONE (0 << 0) -#define RADEON_PRIM_TYPE_POINT (1 << 0) -#define RADEON_PRIM_TYPE_LINE (2 << 0) -#define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0) -#define RADEON_PRIM_TYPE_TRI_LIST (4 << 0) -#define RADEON_PRIM_TYPE_TRI_FAN (5 << 0) -#define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0) -#define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0) -#define RADEON_PRIM_TYPE_RECT_LIST (8 << 0) -#define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0) -#define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0) -#define RADEON_PRIM_TYPE_MASK 0xf -#define RADEON_PRIM_WALK_IND (1 << 4) -#define RADEON_PRIM_WALK_LIST (2 << 4) -#define RADEON_PRIM_WALK_RING (3 << 4) -#define RADEON_COLOR_ORDER_BGRA (0 << 6) -#define RADEON_COLOR_ORDER_RGBA (1 << 6) -#define RADEON_MAOS_ENABLE (1 << 7) -#define RADEON_VTX_FMT_R128_MODE (0 << 8) -#define RADEON_VTX_FMT_RADEON_MODE (1 << 8) -#define RADEON_NUM_VERTICES_SHIFT 16 - -#define RADEON_COLOR_FORMAT_CI8 2 -#define RADEON_COLOR_FORMAT_ARGB1555 3 -#define RADEON_COLOR_FORMAT_RGB565 4 -#define RADEON_COLOR_FORMAT_ARGB8888 6 -#define RADEON_COLOR_FORMAT_RGB332 7 -#define RADEON_COLOR_FORMAT_RGB8 9 -#define RADEON_COLOR_FORMAT_ARGB4444 15 - -#define RADEON_TXFORMAT_I8 0 -#define RADEON_TXFORMAT_AI88 1 -#define RADEON_TXFORMAT_RGB332 2 -#define RADEON_TXFORMAT_ARGB1555 3 -#define RADEON_TXFORMAT_RGB565 4 -#define RADEON_TXFORMAT_ARGB4444 5 -#define RADEON_TXFORMAT_ARGB8888 6 -#define RADEON_TXFORMAT_RGBA8888 7 -#define RADEON_TXFORMAT_Y8 8 -#define RADEON_TXFORMAT_VYUY422 10 -#define RADEON_TXFORMAT_YVYU422 11 -#define RADEON_TXFORMAT_DXT1 12 -#define RADEON_TXFORMAT_DXT23 14 -#define RADEON_TXFORMAT_DXT45 15 - -#define R200_PP_TXCBLEND_0 0x2f00 -#define R200_PP_TXCBLEND_1 0x2f10 -#define R200_PP_TXCBLEND_2 0x2f20 -#define R200_PP_TXCBLEND_3 0x2f30 -#define R200_PP_TXCBLEND_4 0x2f40 -#define R200_PP_TXCBLEND_5 0x2f50 -#define R200_PP_TXCBLEND_6 0x2f60 -#define R200_PP_TXCBLEND_7 0x2f70 -#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268 -#define R200_PP_TFACTOR_0 0x2ee0 -#define R200_SE_VTX_FMT_0 0x2088 -#define R200_SE_VAP_CNTL 0x2080 -#define R200_SE_TCL_MATRIX_SEL_0 0x2230 -#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8 -#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0 -#define R200_PP_TXFILTER_5 0x2ca0 -#define R200_PP_TXFILTER_4 0x2c80 -#define R200_PP_TXFILTER_3 0x2c60 -#define R200_PP_TXFILTER_2 0x2c40 -#define R200_PP_TXFILTER_1 0x2c20 -#define R200_PP_TXFILTER_0 0x2c00 -#define R200_PP_TXOFFSET_5 0x2d78 -#define R200_PP_TXOFFSET_4 0x2d60 -#define R200_PP_TXOFFSET_3 0x2d48 -#define R200_PP_TXOFFSET_2 0x2d30 -#define R200_PP_TXOFFSET_1 0x2d18 -#define R200_PP_TXOFFSET_0 0x2d00 - -#define R200_PP_CUBIC_FACES_0 0x2c18 -#define R200_PP_CUBIC_FACES_1 0x2c38 -#define R200_PP_CUBIC_FACES_2 0x2c58 -#define R200_PP_CUBIC_FACES_3 0x2c78 -#define R200_PP_CUBIC_FACES_4 0x2c98 -#define R200_PP_CUBIC_FACES_5 0x2cb8 -#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04 -#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08 -#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c -#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10 -#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14 -#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c -#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20 -#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24 -#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28 -#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c -#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34 -#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38 -#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c -#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40 -#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44 -#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c -#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50 -#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54 -#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58 -#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c -#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64 -#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68 -#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c -#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70 -#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74 -#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c -#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80 -#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84 -#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88 -#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c - -#define R200_RE_AUX_SCISSOR_CNTL 0x26f0 -#define R200_SE_VTE_CNTL 0x20b0 -#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250 -#define R200_PP_TAM_DEBUG3 0x2d9c -#define R200_PP_CNTL_X 0x2cc4 -#define R200_SE_VAP_CNTL_STATUS 0x2140 -#define R200_RE_SCISSOR_TL_0 0x1cd8 -#define R200_RE_SCISSOR_TL_1 0x1ce0 -#define R200_RE_SCISSOR_TL_2 0x1ce8 -#define R200_RB3D_DEPTHXY_OFFSET 0x1d60 -#define R200_RE_AUX_SCISSOR_CNTL 0x26f0 -#define R200_SE_VTX_STATE_CNTL 0x2180 -#define R200_RE_POINTSIZE 0x2648 -#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254 - -#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ -#define RADEON_PP_TEX_SIZE_1 0x1d0c -#define RADEON_PP_TEX_SIZE_2 0x1d14 - -#define RADEON_PP_CUBIC_FACES_0 0x1d24 -#define RADEON_PP_CUBIC_FACES_1 0x1d28 -#define RADEON_PP_CUBIC_FACES_2 0x1d2c -#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */ -#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00 -#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14 - -#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001 -#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000 -#define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012 -#define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100 -#define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200 -#define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001 -#define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002 -#define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b -#define R200_3D_DRAW_IMMD_2 0xC0003500 -#define R200_SE_VTX_FMT_1 0x208c -#define R200_RE_CNTL 0x1c50 - -#define R200_RB3D_BLENDCOLOR 0x3218 - -#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4 - -#define R200_PP_TRI_PERF 0x2cf8 - -/* Constants */ -#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ - -#define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0 -#define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1 -#define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2 -#define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3 -#define RADEON_LAST_DISPATCH 1 - -#define RADEON_MAX_VB_AGE 0x7fffffff -#define RADEON_MAX_VB_VERTS (0xffff) - -#define RADEON_RING_HIGH_MARK 128 - -#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) -#define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) -#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) -#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) - -#define RADEON_WRITE_PLL( addr, val ) \ -do { \ - RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \ - ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \ - RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \ -} while (0) - -extern int RADEON_READ_PLL( drm_device_t *dev, int addr ); -extern int radeon_preinit( struct drm_device *dev, unsigned long flags ); -extern int radeon_postinit( struct drm_device *dev, unsigned long flags ); -extern int radeon_postcleanup( struct drm_device *dev ); - -#define CP_PACKET0( reg, n ) \ - (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) -#define CP_PACKET0_TABLE( reg, n ) \ - (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2)) -#define CP_PACKET1( reg0, reg1 ) \ - (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2)) -#define CP_PACKET2() \ - (RADEON_CP_PACKET2) -#define CP_PACKET3( pkt, n ) \ - (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) - - -/* ================================================================ - * Engine control helper macros - */ - -#define RADEON_WAIT_UNTIL_2D_IDLE() do { \ - OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ - OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ - RADEON_WAIT_HOST_IDLECLEAN) ); \ -} while (0) - -#define RADEON_WAIT_UNTIL_3D_IDLE() do { \ - OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ - OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \ - RADEON_WAIT_HOST_IDLECLEAN) ); \ -} while (0) - -#define RADEON_WAIT_UNTIL_IDLE() do { \ - OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ - OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ - RADEON_WAIT_3D_IDLECLEAN | \ - RADEON_WAIT_HOST_IDLECLEAN) ); \ -} while (0) - -#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \ - OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ - OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \ -} while (0) - -#define RADEON_FLUSH_CACHE() do { \ - OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \ - OUT_RING( RADEON_RB2D_DC_FLUSH ); \ -} while (0) - -#define RADEON_PURGE_CACHE() do { \ - OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \ - OUT_RING( RADEON_RB2D_DC_FLUSH_ALL ); \ -} while (0) - -#define RADEON_FLUSH_ZCACHE() do { \ - OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \ - OUT_RING( RADEON_RB3D_ZC_FLUSH ); \ -} while (0) - -#define RADEON_PURGE_ZCACHE() do { \ - OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \ - OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \ -} while (0) - - -/* ================================================================ - * Misc helper macros - */ - -/* Perfbox functionality only. - */ -#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \ -do { \ - if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \ - u32 head = GET_RING_HEAD( dev_priv ); \ - if (head == dev_priv->ring.tail) \ - dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \ - } \ -} while (0) - -#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \ -do { \ - drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \ - if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \ - int __ret = radeon_do_cp_idle( dev_priv ); \ - if ( __ret ) return __ret; \ - sarea_priv->last_dispatch = 0; \ - radeon_freelist_reset( dev ); \ - } \ -} while (0) - -#define RADEON_DISPATCH_AGE( age ) do { \ - OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \ - OUT_RING( age ); \ -} while (0) - -#define RADEON_FRAME_AGE( age ) do { \ - OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \ - OUT_RING( age ); \ -} while (0) - -#define RADEON_CLEAR_AGE( age ) do { \ - OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \ - OUT_RING( age ); \ -} while (0) - - -/* ================================================================ - * Ring control - */ - -#define RADEON_VERBOSE 0 - -#define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring; - -#define BEGIN_RING( n ) do { \ - if ( RADEON_VERBOSE ) { \ - DRM_INFO( "BEGIN_RING( %d ) in %s\n", \ - n, __FUNCTION__ ); \ - } \ - if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \ - COMMIT_RING(); \ - radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \ - } \ - _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \ - ring = dev_priv->ring.start; \ - write = dev_priv->ring.tail; \ - mask = dev_priv->ring.tail_mask; \ -} while (0) - -#define ADVANCE_RING() do { \ - if ( RADEON_VERBOSE ) { \ - DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \ - write, dev_priv->ring.tail ); \ - } \ - if (((dev_priv->ring.tail + _nr) & mask) != write) { \ - DRM_ERROR( \ - "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \ - ((dev_priv->ring.tail + _nr) & mask), \ - write, __LINE__); \ - } else \ - dev_priv->ring.tail = write; \ -} while (0) - -#define COMMIT_RING() do { \ - /* Flush writes to ring */ \ - DRM_MEMORYBARRIER(); \ - GET_RING_HEAD( dev_priv ); \ - RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \ - /* read from PCI bus to ensure correct posting */ \ - RADEON_READ( RADEON_CP_RB_RPTR ); \ -} while (0) - -#define OUT_RING( x ) do { \ - if ( RADEON_VERBOSE ) { \ - DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ - (unsigned int)(x), write ); \ - } \ - ring[write++] = (x); \ - write &= mask; \ -} while (0) - -#define OUT_RING_REG( reg, val ) do { \ - OUT_RING( CP_PACKET0( reg, 0 ) ); \ - OUT_RING( val ); \ -} while (0) - - -#define OUT_RING_TABLE( tab, sz ) do { \ - int _size = (sz); \ - int *_tab = (int *)(tab); \ - \ - if (write + _size > mask) { \ - int _i = (mask+1) - write; \ - _size -= _i; \ - while (_i > 0) { \ - *(int *)(ring + write) = *_tab++; \ - write++; \ - _i--; \ - } \ - write = 0; \ - _tab += _i; \ - } \ - while (_size > 0) { \ - *(ring + write) = *_tab++; \ - write++; \ - _size--; \ - } \ - write &= mask; \ -} while (0) - - -#endif /* __RADEON_DRV_H__ */ diff --git a/nx-X11/extras/drm/shared/radeon_irq.c b/nx-X11/extras/drm/shared/radeon_irq.c deleted file mode 100644 index bdb3cc168..000000000 --- a/nx-X11/extras/drm/shared/radeon_irq.c +++ /dev/null @@ -1,258 +0,0 @@ -/* radeon_irq.c -- IRQ handling for radeon -*- linux-c -*- - * - * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - * - * The Weather Channel (TM) funded Tungsten Graphics to develop the - * initial release of the Radeon 8500 driver under the XFree86 license. - * This notice must be preserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Keith Whitwell - * Michel Dänzer - */ - -#include "radeon.h" -#include "drmP.h" -#include "drm.h" -#include "radeon_drm.h" -#include "radeon_drv.h" - -/* Interrupts - Used for device synchronization and flushing in the - * following circumstances: - * - * - Exclusive FB access with hw idle: - * - Wait for GUI Idle (?) interrupt, then do normal flush. - * - * - Frame throttling, NV_fence: - * - Drop marker irq's into command stream ahead of time. - * - Wait on irq's with lock *not held* - * - Check each for termination condition - * - * - Internally in cp_getbuffer, etc: - * - as above, but wait with lock held??? - * - * NOTE: These functions are misleadingly named -- the irq's aren't - * tied to dma at all, this is just a hangover from dri prehistory. - */ - -irqreturn_t radeon_driver_irq_handler( DRM_IRQ_ARGS ) -{ - drm_device_t *dev = (drm_device_t *) arg; - drm_radeon_private_t *dev_priv = - (drm_radeon_private_t *)dev->dev_private; - u32 stat; - - /* Only consider the bits we're interested in - others could be used - * outside the DRM - */ - stat = RADEON_READ(RADEON_GEN_INT_STATUS) - & (RADEON_SW_INT_TEST | RADEON_CRTC_VBLANK_STAT); - if (!stat) - return IRQ_NONE; - - /* SW interrupt */ - if (stat & RADEON_SW_INT_TEST) { - DRM_WAKEUP( &dev_priv->swi_queue ); - } - - /* VBLANK interrupt */ - if (stat & RADEON_CRTC_VBLANK_STAT) { - atomic_inc(&dev->vbl_received); - DRM_WAKEUP(&dev->vbl_queue); - DRM(vbl_send_signals)( dev ); - } - - /* Acknowledge interrupts we handle */ - RADEON_WRITE(RADEON_GEN_INT_STATUS, stat); - return IRQ_HANDLED; -} - -static __inline__ void radeon_acknowledge_irqs(drm_radeon_private_t *dev_priv) -{ - u32 tmp = RADEON_READ( RADEON_GEN_INT_STATUS ) - & (RADEON_SW_INT_TEST_ACK | RADEON_CRTC_VBLANK_STAT); - if (tmp) - RADEON_WRITE( RADEON_GEN_INT_STATUS, tmp ); -} - -int radeon_emit_irq(drm_device_t *dev) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - unsigned int ret; - RING_LOCALS; - - atomic_inc(&dev_priv->swi_emitted); - ret = atomic_read(&dev_priv->swi_emitted); - - BEGIN_RING( 4 ); - OUT_RING_REG( RADEON_LAST_SWI_REG, ret ); - OUT_RING_REG( RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE ); - ADVANCE_RING(); - COMMIT_RING(); - - return ret; -} - - -int radeon_wait_irq(drm_device_t *dev, int swi_nr) -{ - drm_radeon_private_t *dev_priv = - (drm_radeon_private_t *)dev->dev_private; - int ret = 0; - - if (RADEON_READ( RADEON_LAST_SWI_REG ) >= swi_nr) - return 0; - - dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; - - /* This is a hack to work around mysterious freezes on certain - * systems: - */ - radeon_acknowledge_irqs( dev_priv ); - - DRM_WAIT_ON( ret, dev_priv->swi_queue, 3 * DRM_HZ, - RADEON_READ( RADEON_LAST_SWI_REG ) >= swi_nr ); - - return ret; -} - -int radeon_emit_and_wait_irq(drm_device_t *dev) -{ - return radeon_wait_irq( dev, radeon_emit_irq(dev) ); -} - - -int radeon_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence) -{ - drm_radeon_private_t *dev_priv = - (drm_radeon_private_t *)dev->dev_private; - unsigned int cur_vblank; - int ret = 0; - - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); - return DRM_ERR(EINVAL); - } - - radeon_acknowledge_irqs( dev_priv ); - - dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; - - /* Assume that the user has missed the current sequence number - * by about a day rather than she wants to wait for years - * using vertical blanks... - */ - DRM_WAIT_ON( ret, dev->vbl_queue, 3*DRM_HZ, - ( ( ( cur_vblank = atomic_read(&dev->vbl_received ) ) - - *sequence ) <= (1<<23) ) ); - - *sequence = cur_vblank; - - return ret; -} - - -/* Needs the lock as it touches the ring. - */ -int radeon_irq_emit( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_irq_emit_t emit; - int result; - - LOCK_TEST_WITH_RETURN( dev, filp ); - - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); - return DRM_ERR(EINVAL); - } - - DRM_COPY_FROM_USER_IOCTL( emit, (drm_radeon_irq_emit_t __user *)data, - sizeof(emit) ); - - result = radeon_emit_irq( dev ); - - if ( DRM_COPY_TO_USER( emit.irq_seq, &result, sizeof(int) ) ) { - DRM_ERROR( "copy_to_user\n" ); - return DRM_ERR(EFAULT); - } - - return 0; -} - - -/* Doesn't need the hardware lock. - */ -int radeon_irq_wait( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_irq_wait_t irqwait; - - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); - return DRM_ERR(EINVAL); - } - - DRM_COPY_FROM_USER_IOCTL( irqwait, (drm_radeon_irq_wait_t __user*)data, - sizeof(irqwait) ); - - return radeon_wait_irq( dev, irqwait.irq_seq ); -} - - -/* drm_dma.h hooks -*/ -void DRM(driver_irq_preinstall)( drm_device_t *dev ) { - drm_radeon_private_t *dev_priv = - (drm_radeon_private_t *)dev->dev_private; - - /* Disable *all* interrupts */ - RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 ); - - /* Clear bits if they're already high */ - radeon_acknowledge_irqs( dev_priv ); -} - -void DRM(driver_irq_postinstall)( drm_device_t *dev ) { - drm_radeon_private_t *dev_priv = - (drm_radeon_private_t *)dev->dev_private; - - atomic_set(&dev_priv->swi_emitted, 0); - DRM_INIT_WAITQUEUE( &dev_priv->swi_queue ); - - /* Turn on SW and VBL ints */ - RADEON_WRITE( RADEON_GEN_INT_CNTL, - RADEON_CRTC_VBLANK_MASK | - RADEON_SW_INT_ENABLE ); -} - -void DRM(driver_irq_uninstall)( drm_device_t *dev ) { - drm_radeon_private_t *dev_priv = - (drm_radeon_private_t *)dev->dev_private; - if (!dev_priv) - return; - - /* Disable *all* interrupts */ - RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 ); -} diff --git a/nx-X11/extras/drm/shared/radeon_mem.c b/nx-X11/extras/drm/shared/radeon_mem.c deleted file mode 100644 index 9d7fded70..000000000 --- a/nx-X11/extras/drm/shared/radeon_mem.c +++ /dev/null @@ -1,323 +0,0 @@ -/* radeon_mem.c -- Simple GART/fb memory manager for radeon -*- linux-c -*- - * - * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - * - * The Weather Channel (TM) funded Tungsten Graphics to develop the - * initial release of the Radeon 8500 driver under the XFree86 license. - * This notice must be preserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Keith Whitwell - */ - -#include "radeon.h" -#include "drmP.h" -#include "drm.h" -#include "radeon_drm.h" -#include "radeon_drv.h" - -/* Very simple allocator for GART memory, working on a static range - * already mapped into each client's address space. - */ - -static struct mem_block *split_block(struct mem_block *p, int start, int size, - DRMFILE filp ) -{ - /* Maybe cut off the start of an existing block */ - if (start > p->start) { - struct mem_block *newblock = DRM(alloc)(sizeof(*newblock), DRM_MEM_BUFS ); - if (!newblock) - goto out; - newblock->start = start; - newblock->size = p->size - (start - p->start); - newblock->filp = NULL; - newblock->next = p->next; - newblock->prev = p; - p->next->prev = newblock; - p->next = newblock; - p->size -= newblock->size; - p = newblock; - } - - /* Maybe cut off the end of an existing block */ - if (size < p->size) { - struct mem_block *newblock = DRM(alloc)(sizeof(*newblock), DRM_MEM_BUFS ); - if (!newblock) - goto out; - newblock->start = start + size; - newblock->size = p->size - size; - newblock->filp = NULL; - newblock->next = p->next; - newblock->prev = p; - p->next->prev = newblock; - p->next = newblock; - p->size = size; - } - - out: - /* Our block is in the middle */ - p->filp = filp; - return p; -} - -static struct mem_block *alloc_block( struct mem_block *heap, int size, - int align2, DRMFILE filp ) -{ - struct mem_block *p; - int mask = (1 << align2)-1; - - for (p = heap->next ; p != heap ; p = p->next) { - int start = (p->start + mask) & ~mask; - if (p->filp == 0 && start + size <= p->start + p->size) - return split_block( p, start, size, filp ); - } - - return NULL; -} - -static struct mem_block *find_block( struct mem_block *heap, int start ) -{ - struct mem_block *p; - - for (p = heap->next ; p != heap ; p = p->next) - if (p->start == start) - return p; - - return NULL; -} - - -static void free_block( struct mem_block *p ) -{ - p->filp = NULL; - - /* Assumes a single contiguous range. Needs a special filp in - * 'heap' to stop it being subsumed. - */ - if (p->next->filp == 0) { - struct mem_block *q = p->next; - p->size += q->size; - p->next = q->next; - p->next->prev = p; - DRM(free)(q, sizeof(*q), DRM_MEM_BUFS ); - } - - if (p->prev->filp == 0) { - struct mem_block *q = p->prev; - q->size += p->size; - q->next = p->next; - q->next->prev = q; - DRM(free)(p, sizeof(*q), DRM_MEM_BUFS ); - } -} - -/* Initialize. How to check for an uninitialized heap? - */ -static int init_heap(struct mem_block **heap, int start, int size) -{ - struct mem_block *blocks = DRM(alloc)(sizeof(*blocks), DRM_MEM_BUFS ); - - if (!blocks) - return DRM_ERR(ENOMEM); - - *heap = DRM(alloc)(sizeof(**heap), DRM_MEM_BUFS ); - if (!*heap) { - DRM(free)( blocks, sizeof(*blocks), DRM_MEM_BUFS ); - return DRM_ERR(ENOMEM); - } - - blocks->start = start; - blocks->size = size; - blocks->filp = NULL; - blocks->next = blocks->prev = *heap; - - memset( *heap, 0, sizeof(**heap) ); - (*heap)->filp = (DRMFILE) -1; - (*heap)->next = (*heap)->prev = blocks; - return 0; -} - - -/* Free all blocks associated with the releasing file. - */ -void radeon_mem_release( DRMFILE filp, struct mem_block *heap ) -{ - struct mem_block *p; - - if (!heap || !heap->next) - return; - - for (p = heap->next ; p != heap ; p = p->next) { - if (p->filp == filp) - p->filp = NULL; - } - - /* Assumes a single contiguous range. Needs a special filp in - * 'heap' to stop it being subsumed. - */ - for (p = heap->next ; p != heap ; p = p->next) { - while (p->filp == 0 && p->next->filp == 0) { - struct mem_block *q = p->next; - p->size += q->size; - p->next = q->next; - p->next->prev = p; - DRM(free)(q, sizeof(*q),DRM_MEM_DRIVER); - } - } -} - -/* Shutdown. - */ -void radeon_mem_takedown( struct mem_block **heap ) -{ - struct mem_block *p; - - if (!*heap) - return; - - for (p = (*heap)->next ; p != *heap ; ) { - struct mem_block *q = p; - p = p->next; - DRM(free)(q, sizeof(*q),DRM_MEM_DRIVER); - } - - DRM(free)( *heap, sizeof(**heap),DRM_MEM_DRIVER ); - *heap = NULL; -} - - - -/* IOCTL HANDLERS */ - -static struct mem_block **get_heap( drm_radeon_private_t *dev_priv, - int region ) -{ - switch( region ) { - case RADEON_MEM_REGION_GART: - return &dev_priv->gart_heap; - case RADEON_MEM_REGION_FB: - return &dev_priv->fb_heap; - default: - return NULL; - } -} - -int radeon_mem_alloc( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_mem_alloc_t alloc; - struct mem_block *block, **heap; - - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); - return DRM_ERR(EINVAL); - } - - DRM_COPY_FROM_USER_IOCTL( alloc, (drm_radeon_mem_alloc_t __user *)data, - sizeof(alloc) ); - - heap = get_heap( dev_priv, alloc.region ); - if (!heap || !*heap) - return DRM_ERR(EFAULT); - - /* Make things easier on ourselves: all allocations at least - * 4k aligned. - */ - if (alloc.alignment < 12) - alloc.alignment = 12; - - block = alloc_block( *heap, alloc.size, alloc.alignment, - filp ); - - if (!block) - return DRM_ERR(ENOMEM); - - if ( DRM_COPY_TO_USER( alloc.region_offset, &block->start, - sizeof(int) ) ) { - DRM_ERROR( "copy_to_user\n" ); - return DRM_ERR(EFAULT); - } - - return 0; -} - - - -int radeon_mem_free( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_mem_free_t memfree; - struct mem_block *block, **heap; - - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); - return DRM_ERR(EINVAL); - } - - DRM_COPY_FROM_USER_IOCTL( memfree, (drm_radeon_mem_free_t __user *)data, - sizeof(memfree) ); - - heap = get_heap( dev_priv, memfree.region ); - if (!heap || !*heap) - return DRM_ERR(EFAULT); - - block = find_block( *heap, memfree.region_offset ); - if (!block) - return DRM_ERR(EFAULT); - - if (block->filp != filp) - return DRM_ERR(EPERM); - - free_block( block ); - return 0; -} - -int radeon_mem_init_heap( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_mem_init_heap_t initheap; - struct mem_block **heap; - - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); - return DRM_ERR(EINVAL); - } - - DRM_COPY_FROM_USER_IOCTL( initheap, (drm_radeon_mem_init_heap_t __user *)data, - sizeof(initheap) ); - - heap = get_heap( dev_priv, initheap.region ); - if (!heap) - return DRM_ERR(EFAULT); - - if (*heap) { - DRM_ERROR("heap already initialized?"); - return DRM_ERR(EFAULT); - } - - return init_heap( heap, initheap.start, initheap.size ); -} - - diff --git a/nx-X11/extras/drm/shared/radeon_state.c b/nx-X11/extras/drm/shared/radeon_state.c deleted file mode 100644 index 0f7550bdf..000000000 --- a/nx-X11/extras/drm/shared/radeon_state.c +++ /dev/null @@ -1,3093 +0,0 @@ -/* radeon_state.c -- State support for Radeon -*- linux-c -*- - * - * Copyright 2000 VA Linux Systems, Inc., Fremont, California. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Gareth Hughes - * Kevin E. Martin - */ - -#include "radeon.h" -#include "drmP.h" -#include "drm.h" -#include "drm_sarea.h" -#include "radeon_drm.h" -#include "radeon_drv.h" - - -/* ================================================================ - * Helper functions for client state checking and fixup - */ - -static __inline__ int radeon_check_and_fixup_offset( drm_radeon_private_t *dev_priv, - drm_file_t *filp_priv, - u32 *offset ) { - u32 off = *offset; - struct drm_radeon_driver_file_fields *radeon_priv; - - if ( off >= dev_priv->fb_location && - off < ( dev_priv->gart_vm_start + dev_priv->gart_size ) ) - return 0; - - radeon_priv = filp_priv->driver_priv; - - off += radeon_priv->radeon_fb_delta; - - DRM_DEBUG( "offset fixed up to 0x%x\n", off ); - - if ( off < dev_priv->fb_location || - off >= ( dev_priv->gart_vm_start + dev_priv->gart_size ) ) - return DRM_ERR( EINVAL ); - - *offset = off; - - return 0; -} - -static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_priv, - drm_file_t *filp_priv, - int id, - u32 __user *data ) { - switch ( id ) { - - case RADEON_EMIT_PP_MISC: - if (radeon_check_and_fixup_offset(dev_priv, filp_priv, - &data[(RADEON_RB3D_DEPTHOFFSET - RADEON_PP_MISC) / 4])) { - DRM_ERROR( "Invalid depth buffer offset\n" ); - return DRM_ERR( EINVAL ); - } - break; - - case RADEON_EMIT_PP_CNTL: - if (radeon_check_and_fixup_offset(dev_priv, filp_priv, - &data[(RADEON_RB3D_COLOROFFSET - RADEON_PP_CNTL) / 4])) { - DRM_ERROR( "Invalid colour buffer offset\n" ); - return DRM_ERR( EINVAL ); - } - break; - - case R200_EMIT_PP_TXOFFSET_0: - case R200_EMIT_PP_TXOFFSET_1: - case R200_EMIT_PP_TXOFFSET_2: - case R200_EMIT_PP_TXOFFSET_3: - case R200_EMIT_PP_TXOFFSET_4: - case R200_EMIT_PP_TXOFFSET_5: - if (radeon_check_and_fixup_offset(dev_priv, filp_priv, - &data[0])) { - DRM_ERROR( "Invalid R200 texture offset\n" ); - return DRM_ERR( EINVAL ); - } - break; - - case RADEON_EMIT_PP_TXFILTER_0: - case RADEON_EMIT_PP_TXFILTER_1: - case RADEON_EMIT_PP_TXFILTER_2: - if (radeon_check_and_fixup_offset(dev_priv, filp_priv, - &data[(RADEON_PP_TXOFFSET_0 - RADEON_PP_TXFILTER_0) / 4])) { - DRM_ERROR( "Invalid R100 texture offset\n" ); - return DRM_ERR( EINVAL ); - } - break; - - case R200_EMIT_PP_CUBIC_OFFSETS_0: - case R200_EMIT_PP_CUBIC_OFFSETS_1: - case R200_EMIT_PP_CUBIC_OFFSETS_2: - case R200_EMIT_PP_CUBIC_OFFSETS_3: - case R200_EMIT_PP_CUBIC_OFFSETS_4: - case R200_EMIT_PP_CUBIC_OFFSETS_5: { - int i; - for ( i = 0; i < 5; i++ ) { - if (radeon_check_and_fixup_offset(dev_priv, - filp_priv, - &data[i])) { - DRM_ERROR( "Invalid R200 cubic texture offset\n" ); - return DRM_ERR( EINVAL ); - } - } - break; - } - - case RADEON_EMIT_PP_CUBIC_OFFSETS_T0: - case RADEON_EMIT_PP_CUBIC_OFFSETS_T1: - case RADEON_EMIT_PP_CUBIC_OFFSETS_T2:{ - int i; - for (i = 0; i < 5; i++) { - if (radeon_check_and_fixup_offset(dev_priv, - filp_priv, - &data[i])) { - DRM_ERROR - ("Invalid R100 cubic texture offset\n"); - return DRM_ERR(EINVAL); - } - } - } - break; - - case RADEON_EMIT_RB3D_COLORPITCH: - case RADEON_EMIT_RE_LINE_PATTERN: - case RADEON_EMIT_SE_LINE_WIDTH: - case RADEON_EMIT_PP_LUM_MATRIX: - case RADEON_EMIT_PP_ROT_MATRIX_0: - case RADEON_EMIT_RB3D_STENCILREFMASK: - case RADEON_EMIT_SE_VPORT_XSCALE: - case RADEON_EMIT_SE_CNTL: - case RADEON_EMIT_SE_CNTL_STATUS: - case RADEON_EMIT_RE_MISC: - case RADEON_EMIT_PP_BORDER_COLOR_0: - case RADEON_EMIT_PP_BORDER_COLOR_1: - case RADEON_EMIT_PP_BORDER_COLOR_2: - case RADEON_EMIT_SE_ZBIAS_FACTOR: - case RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT: - case RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED: - case R200_EMIT_PP_TXCBLEND_0: - case R200_EMIT_PP_TXCBLEND_1: - case R200_EMIT_PP_TXCBLEND_2: - case R200_EMIT_PP_TXCBLEND_3: - case R200_EMIT_PP_TXCBLEND_4: - case R200_EMIT_PP_TXCBLEND_5: - case R200_EMIT_PP_TXCBLEND_6: - case R200_EMIT_PP_TXCBLEND_7: - case R200_EMIT_TCL_LIGHT_MODEL_CTL_0: - case R200_EMIT_TFACTOR_0: - case R200_EMIT_VTX_FMT_0: - case R200_EMIT_VAP_CTL: - case R200_EMIT_MATRIX_SELECT_0: - case R200_EMIT_TEX_PROC_CTL_2: - case R200_EMIT_TCL_UCP_VERT_BLEND_CTL: - case R200_EMIT_PP_TXFILTER_0: - case R200_EMIT_PP_TXFILTER_1: - case R200_EMIT_PP_TXFILTER_2: - case R200_EMIT_PP_TXFILTER_3: - case R200_EMIT_PP_TXFILTER_4: - case R200_EMIT_PP_TXFILTER_5: - case R200_EMIT_VTE_CNTL: - case R200_EMIT_OUTPUT_VTX_COMP_SEL: - case R200_EMIT_PP_TAM_DEBUG3: - case R200_EMIT_PP_CNTL_X: - case R200_EMIT_RB3D_DEPTHXY_OFFSET: - case R200_EMIT_RE_AUX_SCISSOR_CNTL: - case R200_EMIT_RE_SCISSOR_TL_0: - case R200_EMIT_RE_SCISSOR_TL_1: - case R200_EMIT_RE_SCISSOR_TL_2: - case R200_EMIT_SE_VAP_CNTL_STATUS: - case R200_EMIT_SE_VTX_STATE_CNTL: - case R200_EMIT_RE_POINTSIZE: - case R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0: - case R200_EMIT_PP_CUBIC_FACES_0: - case R200_EMIT_PP_CUBIC_FACES_1: - case R200_EMIT_PP_CUBIC_FACES_2: - case R200_EMIT_PP_CUBIC_FACES_3: - case R200_EMIT_PP_CUBIC_FACES_4: - case R200_EMIT_PP_CUBIC_FACES_5: - case RADEON_EMIT_PP_TEX_SIZE_0: - case RADEON_EMIT_PP_TEX_SIZE_1: - case RADEON_EMIT_PP_TEX_SIZE_2: - case R200_EMIT_RB3D_BLENDCOLOR: - case R200_EMIT_TCL_POINT_SPRITE_CNTL: - case RADEON_EMIT_PP_CUBIC_FACES_0: - case RADEON_EMIT_PP_CUBIC_FACES_1: - case RADEON_EMIT_PP_CUBIC_FACES_2: - case R200_EMIT_PP_TRI_PERF_CNTL: - /* These packets don't contain memory offsets */ - break; - - default: - DRM_ERROR( "Unknown state packet ID %d\n", id ); - return DRM_ERR( EINVAL ); - } - - return 0; -} - -static __inline__ int radeon_check_and_fixup_packet3( drm_radeon_private_t *dev_priv, - drm_file_t *filp_priv, - drm_radeon_cmd_buffer_t *cmdbuf, - unsigned int *cmdsz ) { - u32 *cmd = (u32 *) cmdbuf->buf; - - *cmdsz = 2 + ((cmd[0] & RADEON_CP_PACKET_COUNT_MASK) >> 16); - - if ((cmd[0] & 0xc0000000) != RADEON_CP_PACKET3) { - DRM_ERROR( "Not a type 3 packet\n" ); - return DRM_ERR( EINVAL ); - } - - if ( 4 * *cmdsz > cmdbuf->bufsz ) { - DRM_ERROR( "Packet size larger than size of data provided\n" ); - return DRM_ERR( EINVAL ); - } - - /* Check client state and fix it up if necessary */ - if (cmd[0] & 0x8000) { /* MSB of opcode: next DWORD GUI_CNTL */ - u32 offset; - - if (cmd[1] & (RADEON_GMC_SRC_PITCH_OFFSET_CNTL - | RADEON_GMC_DST_PITCH_OFFSET_CNTL ) ) { - offset = cmd[2] << 10; - if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, &offset ) ) { - DRM_ERROR( "Invalid first packet offset\n" ); - return DRM_ERR( EINVAL ); - } - cmd[2] = (cmd[2] & 0xffc00000) | offset >> 10; - } - - if ((cmd[1] & RADEON_GMC_SRC_PITCH_OFFSET_CNTL) && - (cmd[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL)) { - offset = cmd[3] << 10; - if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, &offset ) ) { - DRM_ERROR( "Invalid second packet offset\n" ); - return DRM_ERR( EINVAL ); - } - cmd[3] = (cmd[3] & 0xffc00000) | offset >> 10; - } - } - - return 0; -} - - -/* ================================================================ - * CP hardware state programming functions - */ - -static __inline__ void radeon_emit_clip_rect( drm_radeon_private_t *dev_priv, - drm_clip_rect_t *box ) -{ - RING_LOCALS; - - DRM_DEBUG( " box: x1=%d y1=%d x2=%d y2=%d\n", - box->x1, box->y1, box->x2, box->y2 ); - - BEGIN_RING( 4 ); - OUT_RING( CP_PACKET0( RADEON_RE_TOP_LEFT, 0 ) ); - OUT_RING( (box->y1 << 16) | box->x1 ); - OUT_RING( CP_PACKET0( RADEON_RE_WIDTH_HEIGHT, 0 ) ); - OUT_RING( ((box->y2 - 1) << 16) | (box->x2 - 1) ); - ADVANCE_RING(); -} - -/* Emit 1.1 state - */ -static int radeon_emit_state( drm_radeon_private_t *dev_priv, - drm_file_t *filp_priv, - drm_radeon_context_regs_t *ctx, - drm_radeon_texture_regs_t *tex, - unsigned int dirty ) -{ - RING_LOCALS; - DRM_DEBUG( "dirty=0x%08x\n", dirty ); - - if ( dirty & RADEON_UPLOAD_CONTEXT ) { - if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, - &ctx->rb3d_depthoffset ) ) { - DRM_ERROR( "Invalid depth buffer offset\n" ); - return DRM_ERR( EINVAL ); - } - - if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, - &ctx->rb3d_coloroffset ) ) { - DRM_ERROR( "Invalid depth buffer offset\n" ); - return DRM_ERR( EINVAL ); - } - - BEGIN_RING( 14 ); - OUT_RING( CP_PACKET0( RADEON_PP_MISC, 6 ) ); - OUT_RING( ctx->pp_misc ); - OUT_RING( ctx->pp_fog_color ); - OUT_RING( ctx->re_solid_color ); - OUT_RING( ctx->rb3d_blendcntl ); - OUT_RING( ctx->rb3d_depthoffset ); - OUT_RING( ctx->rb3d_depthpitch ); - OUT_RING( ctx->rb3d_zstencilcntl ); - OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 2 ) ); - OUT_RING( ctx->pp_cntl ); - OUT_RING( ctx->rb3d_cntl ); - OUT_RING( ctx->rb3d_coloroffset ); - OUT_RING( CP_PACKET0( RADEON_RB3D_COLORPITCH, 0 ) ); - OUT_RING( ctx->rb3d_colorpitch ); - ADVANCE_RING(); - } - - if ( dirty & RADEON_UPLOAD_VERTFMT ) { - BEGIN_RING( 2 ); - OUT_RING( CP_PACKET0( RADEON_SE_COORD_FMT, 0 ) ); - OUT_RING( ctx->se_coord_fmt ); - ADVANCE_RING(); - } - - if ( dirty & RADEON_UPLOAD_LINE ) { - BEGIN_RING( 5 ); - OUT_RING( CP_PACKET0( RADEON_RE_LINE_PATTERN, 1 ) ); - OUT_RING( ctx->re_line_pattern ); - OUT_RING( ctx->re_line_state ); - OUT_RING( CP_PACKET0( RADEON_SE_LINE_WIDTH, 0 ) ); - OUT_RING( ctx->se_line_width ); - ADVANCE_RING(); - } - - if ( dirty & RADEON_UPLOAD_BUMPMAP ) { - BEGIN_RING( 5 ); - OUT_RING( CP_PACKET0( RADEON_PP_LUM_MATRIX, 0 ) ); - OUT_RING( ctx->pp_lum_matrix ); - OUT_RING( CP_PACKET0( RADEON_PP_ROT_MATRIX_0, 1 ) ); - OUT_RING( ctx->pp_rot_matrix_0 ); - OUT_RING( ctx->pp_rot_matrix_1 ); - ADVANCE_RING(); - } - - if ( dirty & RADEON_UPLOAD_MASKS ) { - BEGIN_RING( 4 ); - OUT_RING( CP_PACKET0( RADEON_RB3D_STENCILREFMASK, 2 ) ); - OUT_RING( ctx->rb3d_stencilrefmask ); - OUT_RING( ctx->rb3d_ropcntl ); - OUT_RING( ctx->rb3d_planemask ); - ADVANCE_RING(); - } - - if ( dirty & RADEON_UPLOAD_VIEWPORT ) { - BEGIN_RING( 7 ); - OUT_RING( CP_PACKET0( RADEON_SE_VPORT_XSCALE, 5 ) ); - OUT_RING( ctx->se_vport_xscale ); - OUT_RING( ctx->se_vport_xoffset ); - OUT_RING( ctx->se_vport_yscale ); - OUT_RING( ctx->se_vport_yoffset ); - OUT_RING( ctx->se_vport_zscale ); - OUT_RING( ctx->se_vport_zoffset ); - ADVANCE_RING(); - } - - if ( dirty & RADEON_UPLOAD_SETUP ) { - BEGIN_RING( 4 ); - OUT_RING( CP_PACKET0( RADEON_SE_CNTL, 0 ) ); - OUT_RING( ctx->se_cntl ); - OUT_RING( CP_PACKET0( RADEON_SE_CNTL_STATUS, 0 ) ); - OUT_RING( ctx->se_cntl_status ); - ADVANCE_RING(); - } - - if ( dirty & RADEON_UPLOAD_MISC ) { - BEGIN_RING( 2 ); - OUT_RING( CP_PACKET0( RADEON_RE_MISC, 0 ) ); - OUT_RING( ctx->re_misc ); - ADVANCE_RING(); - } - - if ( dirty & RADEON_UPLOAD_TEX0 ) { - if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, - &tex[0].pp_txoffset ) ) { - DRM_ERROR( "Invalid texture offset for unit 0\n" ); - return DRM_ERR( EINVAL ); - } - - BEGIN_RING( 9 ); - OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_0, 5 ) ); - OUT_RING( tex[0].pp_txfilter ); - OUT_RING( tex[0].pp_txformat ); - OUT_RING( tex[0].pp_txoffset ); - OUT_RING( tex[0].pp_txcblend ); - OUT_RING( tex[0].pp_txablend ); - OUT_RING( tex[0].pp_tfactor ); - OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_0, 0 ) ); - OUT_RING( tex[0].pp_border_color ); - ADVANCE_RING(); - } - - if ( dirty & RADEON_UPLOAD_TEX1 ) { - if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, - &tex[1].pp_txoffset ) ) { - DRM_ERROR( "Invalid texture offset for unit 1\n" ); - return DRM_ERR( EINVAL ); - } - - BEGIN_RING( 9 ); - OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_1, 5 ) ); - OUT_RING( tex[1].pp_txfilter ); - OUT_RING( tex[1].pp_txformat ); - OUT_RING( tex[1].pp_txoffset ); - OUT_RING( tex[1].pp_txcblend ); - OUT_RING( tex[1].pp_txablend ); - OUT_RING( tex[1].pp_tfactor ); - OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_1, 0 ) ); - OUT_RING( tex[1].pp_border_color ); - ADVANCE_RING(); - } - - if ( dirty & RADEON_UPLOAD_TEX2 ) { - if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, - &tex[2].pp_txoffset ) ) { - DRM_ERROR( "Invalid texture offset for unit 2\n" ); - return DRM_ERR( EINVAL ); - } - - BEGIN_RING( 9 ); - OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_2, 5 ) ); - OUT_RING( tex[2].pp_txfilter ); - OUT_RING( tex[2].pp_txformat ); - OUT_RING( tex[2].pp_txoffset ); - OUT_RING( tex[2].pp_txcblend ); - OUT_RING( tex[2].pp_txablend ); - OUT_RING( tex[2].pp_tfactor ); - OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_2, 0 ) ); - OUT_RING( tex[2].pp_border_color ); - ADVANCE_RING(); - } - - return 0; -} - -/* Emit 1.2 state - */ -static int radeon_emit_state2( drm_radeon_private_t *dev_priv, - drm_file_t *filp_priv, - drm_radeon_state_t *state ) -{ - RING_LOCALS; - - if (state->dirty & RADEON_UPLOAD_ZBIAS) { - BEGIN_RING( 3 ); - OUT_RING( CP_PACKET0( RADEON_SE_ZBIAS_FACTOR, 1 ) ); - OUT_RING( state->context2.se_zbias_factor ); - OUT_RING( state->context2.se_zbias_constant ); - ADVANCE_RING(); - } - - return radeon_emit_state( dev_priv, filp_priv, &state->context, - state->tex, state->dirty ); -} - -/* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in - * 1.3 cmdbuffers allow all previous state to be updated as well as - * the tcl scalar and vector areas. - */ -static struct { - int start; - int len; - const char *name; -} packet[RADEON_MAX_STATE_PACKETS] = { - { RADEON_PP_MISC,7,"RADEON_PP_MISC" }, - { RADEON_PP_CNTL,3,"RADEON_PP_CNTL" }, - { RADEON_RB3D_COLORPITCH,1,"RADEON_RB3D_COLORPITCH" }, - { RADEON_RE_LINE_PATTERN,2,"RADEON_RE_LINE_PATTERN" }, - { RADEON_SE_LINE_WIDTH,1,"RADEON_SE_LINE_WIDTH" }, - { RADEON_PP_LUM_MATRIX,1,"RADEON_PP_LUM_MATRIX" }, - { RADEON_PP_ROT_MATRIX_0,2,"RADEON_PP_ROT_MATRIX_0" }, - { RADEON_RB3D_STENCILREFMASK,3,"RADEON_RB3D_STENCILREFMASK" }, - { RADEON_SE_VPORT_XSCALE,6,"RADEON_SE_VPORT_XSCALE" }, - { RADEON_SE_CNTL,2,"RADEON_SE_CNTL" }, - { RADEON_SE_CNTL_STATUS,1,"RADEON_SE_CNTL_STATUS" }, - { RADEON_RE_MISC,1,"RADEON_RE_MISC" }, - { RADEON_PP_TXFILTER_0,6,"RADEON_PP_TXFILTER_0" }, - { RADEON_PP_BORDER_COLOR_0,1,"RADEON_PP_BORDER_COLOR_0" }, - { RADEON_PP_TXFILTER_1,6,"RADEON_PP_TXFILTER_1" }, - { RADEON_PP_BORDER_COLOR_1,1,"RADEON_PP_BORDER_COLOR_1" }, - { RADEON_PP_TXFILTER_2,6,"RADEON_PP_TXFILTER_2" }, - { RADEON_PP_BORDER_COLOR_2,1,"RADEON_PP_BORDER_COLOR_2" }, - { RADEON_SE_ZBIAS_FACTOR,2,"RADEON_SE_ZBIAS_FACTOR" }, - { RADEON_SE_TCL_OUTPUT_VTX_FMT,11,"RADEON_SE_TCL_OUTPUT_VTX_FMT" }, - { RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED,17,"RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED" }, - { R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0" }, - { R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1" }, - { R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2" }, - { R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3" }, - { R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4" }, - { R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5" }, - { R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6" }, - { R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7" }, - { R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0" }, - { R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0" }, - { R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0" }, - { R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL" }, - { R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0" }, - { R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2" }, - { R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL" }, - { R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0" }, - { R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1" }, - { R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2" }, - { R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3" }, - { R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4" }, - { R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5" }, - { R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0" }, - { R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1" }, - { R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2" }, - { R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3" }, - { R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4" }, - { R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5" }, - { R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL" }, - { R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" }, - { R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3" }, - { R200_PP_CNTL_X, 1, "R200_PP_CNTL_X" }, - { R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET" }, - { R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL" }, - { R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0" }, - { R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1" }, - { R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2" }, - { R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS" }, - { R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL" }, - { R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE" }, - { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0" }, - { R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0" }, /* 61 */ - { R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0" }, /* 62 */ - { R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1" }, - { R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1" }, - { R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2" }, - { R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2" }, - { R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3" }, - { R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3" }, - { R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4" }, - { R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4" }, - { R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5" }, - { R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5" }, - { RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" }, - { RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" }, - { RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2" }, - { R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR" }, - { R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"}, - { RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"}, - { RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"}, - { RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"}, - { RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"}, - { RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"}, - { RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"}, - { R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"}, -}; - - - -/* ================================================================ - * Performance monitoring functions - */ - -static void radeon_clear_box( drm_radeon_private_t *dev_priv, - int x, int y, int w, int h, - int r, int g, int b ) -{ - u32 color; - RING_LOCALS; - - x += dev_priv->sarea_priv->boxes[0].x1; - y += dev_priv->sarea_priv->boxes[0].y1; - - switch ( dev_priv->color_fmt ) { - case RADEON_COLOR_FORMAT_RGB565: - color = (((r & 0xf8) << 8) | - ((g & 0xfc) << 3) | - ((b & 0xf8) >> 3)); - break; - case RADEON_COLOR_FORMAT_ARGB8888: - default: - color = (((0xff) << 24) | (r << 16) | (g << 8) | b); - break; - } - - BEGIN_RING( 4 ); - RADEON_WAIT_UNTIL_3D_IDLE(); - OUT_RING( CP_PACKET0( RADEON_DP_WRITE_MASK, 0 ) ); - OUT_RING( 0xffffffff ); - ADVANCE_RING(); - - BEGIN_RING( 6 ); - - OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) ); - OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL | - RADEON_GMC_BRUSH_SOLID_COLOR | - (dev_priv->color_fmt << 8) | - RADEON_GMC_SRC_DATATYPE_COLOR | - RADEON_ROP3_P | - RADEON_GMC_CLR_CMP_CNTL_DIS ); - - if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) { - OUT_RING( dev_priv->front_pitch_offset ); - } else { - OUT_RING( dev_priv->back_pitch_offset ); - } - - OUT_RING( color ); - - OUT_RING( (x << 16) | y ); - OUT_RING( (w << 16) | h ); - - ADVANCE_RING(); -} - -static void radeon_cp_performance_boxes( drm_radeon_private_t *dev_priv ) -{ - /* Collapse various things into a wait flag -- trying to - * guess if userspase slept -- better just to have them tell us. - */ - if (dev_priv->stats.last_frame_reads > 1 || - dev_priv->stats.last_clear_reads > dev_priv->stats.clears) { - dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; - } - - if (dev_priv->stats.freelist_loops) { - dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; - } - - /* Purple box for page flipping - */ - if ( dev_priv->stats.boxes & RADEON_BOX_FLIP ) - radeon_clear_box( dev_priv, 4, 4, 8, 8, 255, 0, 255 ); - - /* Red box if we have to wait for idle at any point - */ - if ( dev_priv->stats.boxes & RADEON_BOX_WAIT_IDLE ) - radeon_clear_box( dev_priv, 16, 4, 8, 8, 255, 0, 0 ); - - /* Blue box: lost context? - */ - - /* Yellow box for texture swaps - */ - if ( dev_priv->stats.boxes & RADEON_BOX_TEXTURE_LOAD ) - radeon_clear_box( dev_priv, 40, 4, 8, 8, 255, 255, 0 ); - - /* Green box if hardware never idles (as far as we can tell) - */ - if ( !(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE) ) - radeon_clear_box( dev_priv, 64, 4, 8, 8, 0, 255, 0 ); - - - /* Draw bars indicating number of buffers allocated - * (not a great measure, easily confused) - */ - if (dev_priv->stats.requested_bufs) { - if (dev_priv->stats.requested_bufs > 100) - dev_priv->stats.requested_bufs = 100; - - radeon_clear_box( dev_priv, 4, 16, - dev_priv->stats.requested_bufs, 4, - 196, 128, 128 ); - } - - memset( &dev_priv->stats, 0, sizeof(dev_priv->stats) ); - -} -/* ================================================================ - * CP command dispatch functions - */ - -static void radeon_cp_dispatch_clear( drm_device_t *dev, - drm_radeon_clear_t *clear, - drm_radeon_clear_rect_t *depth_boxes ) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_radeon_depth_clear_t *depth_clear = &dev_priv->depth_clear; - int nbox = sarea_priv->nbox; - drm_clip_rect_t *pbox = sarea_priv->boxes; - unsigned int flags = clear->flags; - u32 rb3d_cntl = 0, rb3d_stencilrefmask= 0; - int i; - RING_LOCALS; - DRM_DEBUG( "flags = 0x%x\n", flags ); - - dev_priv->stats.clears++; - - if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) { - unsigned int tmp = flags; - - flags &= ~(RADEON_FRONT | RADEON_BACK); - if ( tmp & RADEON_FRONT ) flags |= RADEON_BACK; - if ( tmp & RADEON_BACK ) flags |= RADEON_FRONT; - } - - if ( flags & (RADEON_FRONT | RADEON_BACK) ) { - - BEGIN_RING( 4 ); - - /* Ensure the 3D stream is idle before doing a - * 2D fill to clear the front or back buffer. - */ - RADEON_WAIT_UNTIL_3D_IDLE(); - - OUT_RING( CP_PACKET0( RADEON_DP_WRITE_MASK, 0 ) ); - OUT_RING( clear->color_mask ); - - ADVANCE_RING(); - - /* Make sure we restore the 3D state next time. - */ - dev_priv->sarea_priv->ctx_owner = 0; - - for ( i = 0 ; i < nbox ; i++ ) { - int x = pbox[i].x1; - int y = pbox[i].y1; - int w = pbox[i].x2 - x; - int h = pbox[i].y2 - y; - - DRM_DEBUG( "dispatch clear %d,%d-%d,%d flags 0x%x\n", - x, y, w, h, flags ); - - if ( flags & RADEON_FRONT ) { - BEGIN_RING( 6 ); - - OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) ); - OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL | - RADEON_GMC_BRUSH_SOLID_COLOR | - (dev_priv->color_fmt << 8) | - RADEON_GMC_SRC_DATATYPE_COLOR | - RADEON_ROP3_P | - RADEON_GMC_CLR_CMP_CNTL_DIS ); - - OUT_RING( dev_priv->front_pitch_offset ); - OUT_RING( clear->clear_color ); - - OUT_RING( (x << 16) | y ); - OUT_RING( (w << 16) | h ); - - ADVANCE_RING(); - } - - if ( flags & RADEON_BACK ) { - BEGIN_RING( 6 ); - - OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) ); - OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL | - RADEON_GMC_BRUSH_SOLID_COLOR | - (dev_priv->color_fmt << 8) | - RADEON_GMC_SRC_DATATYPE_COLOR | - RADEON_ROP3_P | - RADEON_GMC_CLR_CMP_CNTL_DIS ); - - OUT_RING( dev_priv->back_pitch_offset ); - OUT_RING( clear->clear_color ); - - OUT_RING( (x << 16) | y ); - OUT_RING( (w << 16) | h ); - - ADVANCE_RING(); - } - } - } - - /* hyper z clear */ - /* no docs available, based on reverse engeneering by Stephane Marchesin */ - if ((flags & (RADEON_DEPTH | RADEON_STENCIL)) && (flags & RADEON_CLEAR_FASTZ)) { - - int i; - int depthpixperline = dev_priv->depth_fmt==RADEON_DEPTH_FORMAT_16BIT_INT_Z? - (dev_priv->depth_pitch / 2): (dev_priv->depth_pitch / 4); - - u32 clearmask; - - u32 tempRB3D_DEPTHCLEARVALUE = clear->clear_depth | - ((clear->depth_mask & 0xff) << 24); - - - /* Make sure we restore the 3D state next time. - * we haven't touched any "normal" state - still need this? - */ - dev_priv->sarea_priv->ctx_owner = 0; - - if ((dev_priv->flags & CHIP_HAS_HIERZ) && (flags & RADEON_USE_HIERZ)) { - /* FIXME : reverse engineer that for Rx00 cards */ - /* FIXME : the mask supposedly contains low-res z values. So can't set - just to the max (0xff? or actually 0x3fff?), need to take z clear - value into account? */ - /* pattern seems to work for r100, though get slight - rendering errors with glxgears. If hierz is not enabled for r100, - only 4 bits which indicate clear (15,16,31,32, all zero) matter, the - other ones are ignored, and the same clear mask can be used. That's - very different behaviour than R200 which needs different clear mask - and different number of tiles to clear if hierz is enabled or not !?! - */ - clearmask = (0xff<<22)|(0xff<<6)| 0x003f003f; - } - else { - /* clear mask : chooses the clearing pattern. - rv250: could be used to clear only parts of macrotiles - (but that would get really complicated...)? - bit 0 and 1 (either or both of them ?!?!) are used to - not clear tile (or maybe one of the bits indicates if the tile is - compressed or not), bit 2 and 3 to not clear tile 1,...,. - Pattern is as follows: - | 0,1 | 4,5 | 8,9 |12,13|16,17|20,21|24,25|28,29| - bits ------------------------------------------------- - | 2,3 | 6,7 |10,11|14,15|18,19|22,23|26,27|30,31| - rv100: clearmask covers 2x8 4x1 tiles, but one clear still - covers 256 pixels ?!? - */ - clearmask = 0x0; - } - - BEGIN_RING( 8 ); - RADEON_WAIT_UNTIL_2D_IDLE(); - OUT_RING_REG( RADEON_RB3D_DEPTHCLEARVALUE, - tempRB3D_DEPTHCLEARVALUE); - /* what offset is this exactly ? */ - OUT_RING_REG( RADEON_RB3D_ZMASKOFFSET, 0 ); - /* need ctlstat, otherwise get some strange black flickering */ - OUT_RING_REG( RADEON_RB3D_ZCACHE_CTLSTAT, RADEON_RB3D_ZC_FLUSH_ALL ); - ADVANCE_RING(); - - for (i = 0; i < nbox; i++) { - int tileoffset, nrtilesx, nrtilesy, j; - /* it looks like r200 needs rv-style clears, at least if hierz is not enabled? */ - if ((dev_priv->flags&CHIP_HAS_HIERZ) && !(dev_priv->microcode_version==UCODE_R200)) { - /* FIXME : figure this out for r200 (when hierz is enabled). Or - maybe r200 actually doesn't need to put the low-res z value into - the tile cache like r100, but just needs to clear the hi-level z-buffer? - Works for R100, both with hierz and without. - R100 seems to operate on 2x1 8x8 tiles, but... - odd: offset/nrtiles need to be 64 pix (4 block) aligned? Potentially - problematic with resolutions which are not 64 pix aligned? */ - tileoffset = ((pbox[i].y1 >> 3) * depthpixperline + pbox[i].x1) >> 6; - nrtilesx = ((pbox[i].x2 & ~63) - (pbox[i].x1 & ~63)) >> 4; - nrtilesy = (pbox[i].y2 >> 3) - (pbox[i].y1 >> 3); - for (j = 0; j <= nrtilesy; j++) { - BEGIN_RING( 4 ); - OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_ZMASK, 2 ) ); - /* first tile */ - OUT_RING( tileoffset * 8 ); - /* the number of tiles to clear */ - OUT_RING( nrtilesx + 4 ); - /* clear mask : chooses the clearing pattern. */ - OUT_RING( clearmask ); - ADVANCE_RING(); - tileoffset += depthpixperline >> 6; - } - } - else if (dev_priv->microcode_version==UCODE_R200) { - /* works for rv250. */ - /* find first macro tile (8x2 4x4 z-pixels on rv250) */ - tileoffset = ((pbox[i].y1 >> 3) * depthpixperline + pbox[i].x1) >> 5; - nrtilesx = (pbox[i].x2 >> 5) - (pbox[i].x1 >> 5); - nrtilesy = (pbox[i].y2 >> 3) - (pbox[i].y1 >> 3); - for (j = 0; j <= nrtilesy; j++) { - BEGIN_RING( 4 ); - OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_ZMASK, 2 ) ); - /* first tile */ - /* judging by the first tile offset needed, could possibly - directly address/clear 4x4 tiles instead of 8x2 * 4x4 - macro tiles, though would still need clear mask for - right/bottom if truely 4x4 granularity is desired ? */ - OUT_RING( tileoffset * 16 ); - /* the number of tiles to clear */ - OUT_RING( nrtilesx + 1 ); - /* clear mask : chooses the clearing pattern. */ - OUT_RING( clearmask ); - ADVANCE_RING(); - tileoffset += depthpixperline >> 5; - } - } - else { /* rv 100 */ - /* rv100 might not need 64 pix alignment, who knows */ - /* offsets are, hmm, weird */ - tileoffset = ((pbox[i].y1 >> 4) * depthpixperline + pbox[i].x1) >> 6; - nrtilesx = ((pbox[i].x2 & ~63) - (pbox[i].x1 & ~63)) >> 4; - nrtilesy = (pbox[i].y2 >> 4) - (pbox[i].y1 >> 4); - for (j = 0; j <= nrtilesy; j++) { - BEGIN_RING( 4 ); - OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_ZMASK, 2 ) ); - OUT_RING( tileoffset * 128 ); - /* the number of tiles to clear */ - OUT_RING( nrtilesx + 4 ); - /* clear mask : chooses the clearing pattern. */ - OUT_RING( clearmask ); - ADVANCE_RING(); - tileoffset += depthpixperline >> 6; - } - } - } - - /* TODO don't always clear all hi-level z tiles */ - if ((dev_priv->flags & CHIP_HAS_HIERZ) && (dev_priv->microcode_version==UCODE_R200) - && (flags & RADEON_USE_HIERZ)) - /* r100 and cards without hierarchical z-buffer have no high-level z-buffer */ - /* FIXME : the mask supposedly contains low-res z values. So can't set - just to the max (0xff? or actually 0x3fff?), need to take z clear - value into account? */ - { - BEGIN_RING( 4 ); - OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_HIZ, 2 ) ); - OUT_RING( 0x0 ); /* First tile */ - OUT_RING( 0x3cc0 ); - OUT_RING( (0xff<<22)|(0xff<<6)| 0x003f003f); - ADVANCE_RING(); - } - } - - /* We have to clear the depth and/or stencil buffers by - * rendering a quad into just those buffers. Thus, we have to - * make sure the 3D engine is configured correctly. - */ - else if ((dev_priv->microcode_version == UCODE_R200) && - (flags & (RADEON_DEPTH | RADEON_STENCIL))) { - - int tempPP_CNTL; - int tempRE_CNTL; - int tempRB3D_CNTL; - int tempRB3D_ZSTENCILCNTL; - int tempRB3D_STENCILREFMASK; - int tempRB3D_PLANEMASK; - int tempSE_CNTL; - int tempSE_VTE_CNTL; - int tempSE_VTX_FMT_0; - int tempSE_VTX_FMT_1; - int tempSE_VAP_CNTL; - int tempRE_AUX_SCISSOR_CNTL; - - tempPP_CNTL = 0; - tempRE_CNTL = 0; - - tempRB3D_CNTL = depth_clear->rb3d_cntl; - - tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl; - tempRB3D_STENCILREFMASK = 0x0; - - tempSE_CNTL = depth_clear->se_cntl; - - - - /* Disable TCL */ - - tempSE_VAP_CNTL = (/* SE_VAP_CNTL__FORCE_W_TO_ONE_MASK | */ - (0x9 << SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT)); - - tempRB3D_PLANEMASK = 0x0; - - tempRE_AUX_SCISSOR_CNTL = 0x0; - - tempSE_VTE_CNTL = - SE_VTE_CNTL__VTX_XY_FMT_MASK | - SE_VTE_CNTL__VTX_Z_FMT_MASK; - - /* Vertex format (X, Y, Z, W)*/ - tempSE_VTX_FMT_0 = - SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK | - SE_VTX_FMT_0__VTX_W0_PRESENT_MASK; - tempSE_VTX_FMT_1 = 0x0; - - - /* - * Depth buffer specific enables - */ - if (flags & RADEON_DEPTH) { - /* Enable depth buffer */ - tempRB3D_CNTL |= RADEON_Z_ENABLE; - } else { - /* Disable depth buffer */ - tempRB3D_CNTL &= ~RADEON_Z_ENABLE; - } - - /* - * Stencil buffer specific enables - */ - if ( flags & RADEON_STENCIL ) { - tempRB3D_CNTL |= RADEON_STENCIL_ENABLE; - tempRB3D_STENCILREFMASK = clear->depth_mask; - } else { - tempRB3D_CNTL &= ~RADEON_STENCIL_ENABLE; - tempRB3D_STENCILREFMASK = 0x00000000; - } - - if (flags & RADEON_USE_COMP_ZBUF) { - tempRB3D_ZSTENCILCNTL |= RADEON_Z_COMPRESSION_ENABLE | - RADEON_Z_DECOMPRESSION_ENABLE; - } - if (flags & RADEON_USE_HIERZ) { - tempRB3D_ZSTENCILCNTL |= RADEON_Z_HIERARCHY_ENABLE; - } - - BEGIN_RING( 26 ); - RADEON_WAIT_UNTIL_2D_IDLE(); - - OUT_RING_REG( RADEON_PP_CNTL, tempPP_CNTL ); - OUT_RING_REG( R200_RE_CNTL, tempRE_CNTL ); - OUT_RING_REG( RADEON_RB3D_CNTL, tempRB3D_CNTL ); - OUT_RING_REG( RADEON_RB3D_ZSTENCILCNTL, - tempRB3D_ZSTENCILCNTL ); - OUT_RING_REG( RADEON_RB3D_STENCILREFMASK, - tempRB3D_STENCILREFMASK ); - OUT_RING_REG( RADEON_RB3D_PLANEMASK, tempRB3D_PLANEMASK ); - OUT_RING_REG( RADEON_SE_CNTL, tempSE_CNTL ); - OUT_RING_REG( R200_SE_VTE_CNTL, tempSE_VTE_CNTL ); - OUT_RING_REG( R200_SE_VTX_FMT_0, tempSE_VTX_FMT_0 ); - OUT_RING_REG( R200_SE_VTX_FMT_1, tempSE_VTX_FMT_1 ); - OUT_RING_REG( R200_SE_VAP_CNTL, tempSE_VAP_CNTL ); - OUT_RING_REG( R200_RE_AUX_SCISSOR_CNTL, - tempRE_AUX_SCISSOR_CNTL ); - ADVANCE_RING(); - - /* Make sure we restore the 3D state next time. - */ - dev_priv->sarea_priv->ctx_owner = 0; - - for ( i = 0 ; i < nbox ; i++ ) { - - /* Funny that this should be required -- - * sets top-left? - */ - radeon_emit_clip_rect( dev_priv, - &sarea_priv->boxes[i] ); - - BEGIN_RING( 14 ); - OUT_RING( CP_PACKET3( R200_3D_DRAW_IMMD_2, 12 ) ); - OUT_RING( (RADEON_PRIM_TYPE_RECT_LIST | - RADEON_PRIM_WALK_RING | - (3 << RADEON_NUM_VERTICES_SHIFT)) ); - OUT_RING( depth_boxes[i].ui[CLEAR_X1] ); - OUT_RING( depth_boxes[i].ui[CLEAR_Y1] ); - OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] ); - OUT_RING( 0x3f800000 ); - OUT_RING( depth_boxes[i].ui[CLEAR_X1] ); - OUT_RING( depth_boxes[i].ui[CLEAR_Y2] ); - OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] ); - OUT_RING( 0x3f800000 ); - OUT_RING( depth_boxes[i].ui[CLEAR_X2] ); - OUT_RING( depth_boxes[i].ui[CLEAR_Y2] ); - OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] ); - OUT_RING( 0x3f800000 ); - ADVANCE_RING(); - } - } - else if ( (flags & (RADEON_DEPTH | RADEON_STENCIL)) ) { - - int tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl; - - rb3d_cntl = depth_clear->rb3d_cntl; - - if ( flags & RADEON_DEPTH ) { - rb3d_cntl |= RADEON_Z_ENABLE; - } else { - rb3d_cntl &= ~RADEON_Z_ENABLE; - } - - if ( flags & RADEON_STENCIL ) { - rb3d_cntl |= RADEON_STENCIL_ENABLE; - rb3d_stencilrefmask = clear->depth_mask; /* misnamed field */ - } else { - rb3d_cntl &= ~RADEON_STENCIL_ENABLE; - rb3d_stencilrefmask = 0x00000000; - } - - if (flags & RADEON_USE_COMP_ZBUF) { - tempRB3D_ZSTENCILCNTL |= RADEON_Z_COMPRESSION_ENABLE | - RADEON_Z_DECOMPRESSION_ENABLE; - } - if (flags & RADEON_USE_HIERZ) { - tempRB3D_ZSTENCILCNTL |= RADEON_Z_HIERARCHY_ENABLE; - } - - BEGIN_RING( 13 ); - RADEON_WAIT_UNTIL_2D_IDLE(); - - OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 1 ) ); - OUT_RING( 0x00000000 ); - OUT_RING( rb3d_cntl ); - - OUT_RING_REG( RADEON_RB3D_ZSTENCILCNTL, - tempRB3D_ZSTENCILCNTL ); - OUT_RING_REG( RADEON_RB3D_STENCILREFMASK, - rb3d_stencilrefmask ); - OUT_RING_REG( RADEON_RB3D_PLANEMASK, - 0x00000000 ); - OUT_RING_REG( RADEON_SE_CNTL, - depth_clear->se_cntl ); - ADVANCE_RING(); - - /* Make sure we restore the 3D state next time. - */ - dev_priv->sarea_priv->ctx_owner = 0; - - for ( i = 0 ; i < nbox ; i++ ) { - - /* Funny that this should be required -- - * sets top-left? - */ - radeon_emit_clip_rect( dev_priv, - &sarea_priv->boxes[i] ); - - BEGIN_RING( 15 ); - - OUT_RING( CP_PACKET3( RADEON_3D_DRAW_IMMD, 13 ) ); - OUT_RING( RADEON_VTX_Z_PRESENT | - RADEON_VTX_PKCOLOR_PRESENT); - OUT_RING( (RADEON_PRIM_TYPE_RECT_LIST | - RADEON_PRIM_WALK_RING | - RADEON_MAOS_ENABLE | - RADEON_VTX_FMT_RADEON_MODE | - (3 << RADEON_NUM_VERTICES_SHIFT)) ); - - - OUT_RING( depth_boxes[i].ui[CLEAR_X1] ); - OUT_RING( depth_boxes[i].ui[CLEAR_Y1] ); - OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] ); - OUT_RING( 0x0 ); - - OUT_RING( depth_boxes[i].ui[CLEAR_X1] ); - OUT_RING( depth_boxes[i].ui[CLEAR_Y2] ); - OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] ); - OUT_RING( 0x0 ); - - OUT_RING( depth_boxes[i].ui[CLEAR_X2] ); - OUT_RING( depth_boxes[i].ui[CLEAR_Y2] ); - OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] ); - OUT_RING( 0x0 ); - - ADVANCE_RING(); - } - } - - /* Increment the clear counter. The client-side 3D driver must - * wait on this value before performing the clear ioctl. We - * need this because the card's so damned fast... - */ - dev_priv->sarea_priv->last_clear++; - - BEGIN_RING( 4 ); - - RADEON_CLEAR_AGE( dev_priv->sarea_priv->last_clear ); - RADEON_WAIT_UNTIL_IDLE(); - - ADVANCE_RING(); -} - -static void radeon_cp_dispatch_swap( drm_device_t *dev ) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; - int nbox = sarea_priv->nbox; - drm_clip_rect_t *pbox = sarea_priv->boxes; - int i; - RING_LOCALS; - DRM_DEBUG( "\n" ); - - /* Do some trivial performance monitoring... - */ - if (dev_priv->do_boxes) - radeon_cp_performance_boxes( dev_priv ); - - - /* Wait for the 3D stream to idle before dispatching the bitblt. - * This will prevent data corruption between the two streams. - */ - BEGIN_RING( 2 ); - - RADEON_WAIT_UNTIL_3D_IDLE(); - - ADVANCE_RING(); - - for ( i = 0 ; i < nbox ; i++ ) { - int x = pbox[i].x1; - int y = pbox[i].y1; - int w = pbox[i].x2 - x; - int h = pbox[i].y2 - y; - - DRM_DEBUG( "dispatch swap %d,%d-%d,%d\n", - x, y, w, h ); - - BEGIN_RING( 7 ); - - OUT_RING( CP_PACKET3( RADEON_CNTL_BITBLT_MULTI, 5 ) ); - OUT_RING( RADEON_GMC_SRC_PITCH_OFFSET_CNTL | - RADEON_GMC_DST_PITCH_OFFSET_CNTL | - RADEON_GMC_BRUSH_NONE | - (dev_priv->color_fmt << 8) | - RADEON_GMC_SRC_DATATYPE_COLOR | - RADEON_ROP3_S | - RADEON_DP_SRC_SOURCE_MEMORY | - RADEON_GMC_CLR_CMP_CNTL_DIS | - RADEON_GMC_WR_MSK_DIS ); - - /* Make this work even if front & back are flipped: - */ - if (dev_priv->current_page == 0) { - OUT_RING( dev_priv->back_pitch_offset ); - OUT_RING( dev_priv->front_pitch_offset ); - } - else { - OUT_RING( dev_priv->front_pitch_offset ); - OUT_RING( dev_priv->back_pitch_offset ); - } - - OUT_RING( (x << 16) | y ); - OUT_RING( (x << 16) | y ); - OUT_RING( (w << 16) | h ); - - ADVANCE_RING(); - } - - /* Increment the frame counter. The client-side 3D driver must - * throttle the framerate by waiting for this value before - * performing the swapbuffer ioctl. - */ - dev_priv->sarea_priv->last_frame++; - - BEGIN_RING( 4 ); - - RADEON_FRAME_AGE( dev_priv->sarea_priv->last_frame ); - RADEON_WAIT_UNTIL_2D_IDLE(); - - ADVANCE_RING(); -} - -static void radeon_cp_dispatch_flip( drm_device_t *dev ) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_sarea_t *sarea = (drm_sarea_t *)dev_priv->sarea->handle; - int offset = (dev_priv->current_page == 1) - ? dev_priv->front_offset : dev_priv->back_offset; - RING_LOCALS; - DRM_DEBUG( "%s: page=%d pfCurrentPage=%d\n", - __FUNCTION__, - dev_priv->current_page, - dev_priv->sarea_priv->pfCurrentPage); - - /* Do some trivial performance monitoring... - */ - if (dev_priv->do_boxes) { - dev_priv->stats.boxes |= RADEON_BOX_FLIP; - radeon_cp_performance_boxes( dev_priv ); - } - - /* Update the frame offsets for both CRTCs - */ - BEGIN_RING( 6 ); - - RADEON_WAIT_UNTIL_3D_IDLE(); - OUT_RING_REG( RADEON_CRTC_OFFSET, ( ( sarea->frame.y * dev_priv->front_pitch - + sarea->frame.x - * ( dev_priv->color_fmt - 2 ) ) & ~7 ) - + offset ); - OUT_RING_REG( RADEON_CRTC2_OFFSET, dev_priv->sarea_priv->crtc2_base - + offset ); - - ADVANCE_RING(); - - /* Increment the frame counter. The client-side 3D driver must - * throttle the framerate by waiting for this value before - * performing the swapbuffer ioctl. - */ - dev_priv->sarea_priv->last_frame++; - dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page = - 1 - dev_priv->current_page; - - BEGIN_RING( 2 ); - - RADEON_FRAME_AGE( dev_priv->sarea_priv->last_frame ); - - ADVANCE_RING(); -} - -static int bad_prim_vertex_nr( int primitive, int nr ) -{ - switch (primitive & RADEON_PRIM_TYPE_MASK) { - case RADEON_PRIM_TYPE_NONE: - case RADEON_PRIM_TYPE_POINT: - return nr < 1; - case RADEON_PRIM_TYPE_LINE: - return (nr & 1) || nr == 0; - case RADEON_PRIM_TYPE_LINE_STRIP: - return nr < 2; - case RADEON_PRIM_TYPE_TRI_LIST: - case RADEON_PRIM_TYPE_3VRT_POINT_LIST: - case RADEON_PRIM_TYPE_3VRT_LINE_LIST: - case RADEON_PRIM_TYPE_RECT_LIST: - return nr % 3 || nr == 0; - case RADEON_PRIM_TYPE_TRI_FAN: - case RADEON_PRIM_TYPE_TRI_STRIP: - return nr < 3; - default: - return 1; - } -} - - - -typedef struct { - unsigned int start; - unsigned int finish; - unsigned int prim; - unsigned int numverts; - unsigned int offset; - unsigned int vc_format; -} drm_radeon_tcl_prim_t; - -static void radeon_cp_dispatch_vertex( drm_device_t *dev, - drm_buf_t *buf, - drm_radeon_tcl_prim_t *prim ) - -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; - int offset = dev_priv->gart_buffers_offset + buf->offset + prim->start; - int numverts = (int)prim->numverts; - int nbox = sarea_priv->nbox; - int i = 0; - RING_LOCALS; - - DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d %d verts\n", - prim->prim, - prim->vc_format, - prim->start, - prim->finish, - prim->numverts); - - if (bad_prim_vertex_nr( prim->prim, prim->numverts )) { - DRM_ERROR( "bad prim %x numverts %d\n", - prim->prim, prim->numverts ); - return; - } - - do { - /* Emit the next cliprect */ - if ( i < nbox ) { - radeon_emit_clip_rect( dev_priv, - &sarea_priv->boxes[i] ); - } - - /* Emit the vertex buffer rendering commands */ - BEGIN_RING( 5 ); - - OUT_RING( CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, 3 ) ); - OUT_RING( offset ); - OUT_RING( numverts ); - OUT_RING( prim->vc_format ); - OUT_RING( prim->prim | RADEON_PRIM_WALK_LIST | - RADEON_COLOR_ORDER_RGBA | - RADEON_VTX_FMT_RADEON_MODE | - (numverts << RADEON_NUM_VERTICES_SHIFT) ); - - ADVANCE_RING(); - - i++; - } while ( i < nbox ); -} - - - -static void radeon_cp_discard_buffer( drm_device_t *dev, drm_buf_t *buf ) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_buf_priv_t *buf_priv = buf->dev_private; - RING_LOCALS; - - buf_priv->age = ++dev_priv->sarea_priv->last_dispatch; - - /* Emit the vertex buffer age */ - BEGIN_RING( 2 ); - RADEON_DISPATCH_AGE( buf_priv->age ); - ADVANCE_RING(); - - buf->pending = 1; - buf->used = 0; -} - -static void radeon_cp_dispatch_indirect( drm_device_t *dev, - drm_buf_t *buf, - int start, int end ) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - RING_LOCALS; - DRM_DEBUG( "indirect: buf=%d s=0x%x e=0x%x\n", - buf->idx, start, end ); - - if ( start != end ) { - int offset = (dev_priv->gart_buffers_offset - + buf->offset + start); - int dwords = (end - start + 3) / sizeof(u32); - - /* Indirect buffer data must be an even number of - * dwords, so if we've been given an odd number we must - * pad the data with a Type-2 CP packet. - */ - if ( dwords & 1 ) { - u32 *data = (u32 *) - ((char *)dev->agp_buffer_map->handle - + buf->offset + start); - data[dwords++] = RADEON_CP_PACKET2; - } - - /* Fire off the indirect buffer */ - BEGIN_RING( 3 ); - - OUT_RING( CP_PACKET0( RADEON_CP_IB_BASE, 1 ) ); - OUT_RING( offset ); - OUT_RING( dwords ); - - ADVANCE_RING(); - } -} - - -static void radeon_cp_dispatch_indices( drm_device_t *dev, - drm_buf_t *elt_buf, - drm_radeon_tcl_prim_t *prim ) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; - int offset = dev_priv->gart_buffers_offset + prim->offset; - u32 *data; - int dwords; - int i = 0; - int start = prim->start + RADEON_INDEX_PRIM_OFFSET; - int count = (prim->finish - start) / sizeof(u16); - int nbox = sarea_priv->nbox; - - DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d offset: %x nr %d\n", - prim->prim, - prim->vc_format, - prim->start, - prim->finish, - prim->offset, - prim->numverts); - - if (bad_prim_vertex_nr( prim->prim, count )) { - DRM_ERROR( "bad prim %x count %d\n", - prim->prim, count ); - return; - } - - - if ( start >= prim->finish || - (prim->start & 0x7) ) { - DRM_ERROR( "buffer prim %d\n", prim->prim ); - return; - } - - dwords = (prim->finish - prim->start + 3) / sizeof(u32); - - data = (u32 *)((char *)dev->agp_buffer_map->handle + - elt_buf->offset + prim->start); - - data[0] = CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, dwords-2 ); - data[1] = offset; - data[2] = prim->numverts; - data[3] = prim->vc_format; - data[4] = (prim->prim | - RADEON_PRIM_WALK_IND | - RADEON_COLOR_ORDER_RGBA | - RADEON_VTX_FMT_RADEON_MODE | - (count << RADEON_NUM_VERTICES_SHIFT) ); - - do { - if ( i < nbox ) - radeon_emit_clip_rect( dev_priv, - &sarea_priv->boxes[i] ); - - radeon_cp_dispatch_indirect( dev, elt_buf, - prim->start, - prim->finish ); - - i++; - } while ( i < nbox ); - -} - -#define RADEON_MAX_TEXTURE_SIZE (RADEON_BUFFER_SIZE - 8 * sizeof(u32)) - -static int radeon_cp_dispatch_texture( DRMFILE filp, - drm_device_t *dev, - drm_radeon_texture_t *tex, - drm_radeon_tex_image_t *image ) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_file_t *filp_priv; - drm_buf_t *buf; - u32 format; - u32 *buffer; - const u8 __user *data; - int size, dwords, tex_width, blit_width; - u32 height; - int i; - u32 texpitch, microtile; - RING_LOCALS; - - DRM_GET_PRIV_WITH_RETURN( filp_priv, filp ); - - if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, &tex->offset ) ) { - DRM_ERROR( "Invalid destination offset\n" ); - return DRM_ERR( EINVAL ); - } - - dev_priv->stats.boxes |= RADEON_BOX_TEXTURE_LOAD; - - /* Flush the pixel cache. This ensures no pixel data gets mixed - * up with the texture data from the host data blit, otherwise - * part of the texture image may be corrupted. - */ - BEGIN_RING( 4 ); - RADEON_FLUSH_CACHE(); - RADEON_WAIT_UNTIL_IDLE(); - ADVANCE_RING(); - -#ifdef __BIG_ENDIAN - /* The Mesa texture functions provide the data in little endian as the - * chip wants it, but we need to compensate for the fact that the CP - * ring gets byte-swapped - */ - BEGIN_RING( 2 ); - OUT_RING_REG( RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_32BIT ); - ADVANCE_RING(); -#endif - - - /* The compiler won't optimize away a division by a variable, - * even if the only legal values are powers of two. Thus, we'll - * use a shift instead. - */ - switch ( tex->format ) { - case RADEON_TXFORMAT_ARGB8888: - case RADEON_TXFORMAT_RGBA8888: - format = RADEON_COLOR_FORMAT_ARGB8888; - tex_width = tex->width * 4; - blit_width = image->width * 4; - break; - case RADEON_TXFORMAT_AI88: - case RADEON_TXFORMAT_ARGB1555: - case RADEON_TXFORMAT_RGB565: - case RADEON_TXFORMAT_ARGB4444: - case RADEON_TXFORMAT_VYUY422: - case RADEON_TXFORMAT_YVYU422: - format = RADEON_COLOR_FORMAT_RGB565; - tex_width = tex->width * 2; - blit_width = image->width * 2; - break; - case RADEON_TXFORMAT_I8: - case RADEON_TXFORMAT_RGB332: - format = RADEON_COLOR_FORMAT_CI8; - tex_width = tex->width * 1; - blit_width = image->width * 1; - break; - default: - DRM_ERROR( "invalid texture format %d\n", tex->format ); - return DRM_ERR(EINVAL); - } - texpitch = tex->pitch; - if ((texpitch << 22) & RADEON_DST_TILE_MICRO) { - microtile = 1; - if (tex_width < 64) { - texpitch &= ~(RADEON_DST_TILE_MICRO >> 22); - /* we got tiled coordinates, untile them */ - image->x *= 2; - } - } - else microtile = 0; - - DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width ); - - do { - DRM_DEBUG( "tex: ofs=0x%x p=%d f=%d x=%hd y=%hd w=%hd h=%hd\n", - tex->offset >> 10, tex->pitch, tex->format, - image->x, image->y, image->width, image->height ); - - /* Make a copy of some parameters in case we have to - * update them for a multi-pass texture blit. - */ - height = image->height; - data = (const u8 __user *)image->data; - - size = height * blit_width; - - if ( size > RADEON_MAX_TEXTURE_SIZE ) { - height = RADEON_MAX_TEXTURE_SIZE / blit_width; - size = height * blit_width; - } else if ( size < 4 && size > 0 ) { - size = 4; - } else if ( size == 0 ) { - return 0; - } - - buf = radeon_freelist_get( dev ); - if ( 0 && !buf ) { - radeon_do_cp_idle( dev_priv ); - buf = radeon_freelist_get( dev ); - } - if ( !buf ) { - DRM_DEBUG("radeon_cp_dispatch_texture: EAGAIN\n"); - if (DRM_COPY_TO_USER( tex->image, image, sizeof(*image) )) - return DRM_ERR(EFAULT); - return DRM_ERR(EAGAIN); - } - - - /* Dispatch the indirect buffer. - */ - buffer = (u32*)((char*)dev->agp_buffer_map->handle + buf->offset); - dwords = size / 4; - buffer[0] = CP_PACKET3( RADEON_CNTL_HOSTDATA_BLT, dwords + 6 ); - buffer[1] = (RADEON_GMC_DST_PITCH_OFFSET_CNTL | - RADEON_GMC_BRUSH_NONE | - (format << 8) | - RADEON_GMC_SRC_DATATYPE_COLOR | - RADEON_ROP3_S | - RADEON_DP_SRC_SOURCE_HOST_DATA | - RADEON_GMC_CLR_CMP_CNTL_DIS | - RADEON_GMC_WR_MSK_DIS); - - buffer[2] = (texpitch << 22) | (tex->offset >> 10); - buffer[3] = 0xffffffff; - buffer[4] = 0xffffffff; - buffer[5] = (image->y << 16) | image->x; - buffer[6] = (height << 16) | image->width; - buffer[7] = dwords; - buffer += 8; - - if (microtile) { - /* texture micro tiling in use, minimum texture width is thus 16 bytes. - however, we cannot use blitter directly for texture width < 64 bytes, - since minimum tex pitch is 64 bytes and we need this to match - the texture width, otherwise the blitter will tile it wrong. - Thus, tiling manually in this case. Additionally, need to special - case tex height = 1, since our actual image will have height 2 - and we need to ensure we don't read beyond the texture size - from user space. */ - if (tex->height == 1) { - if (tex_width >= 64 || tex_width <= 16) { - if (DRM_COPY_FROM_USER(buffer, data, - tex_width * sizeof(u32))) { - DRM_ERROR("EFAULT on pad, %d bytes\n", - tex_width); - return DRM_ERR(EFAULT); - } - } else if (tex_width == 32) { - if (DRM_COPY_FROM_USER(buffer, data, 16)) { - DRM_ERROR("EFAULT on pad, %d bytes\n", - tex_width); - return DRM_ERR(EFAULT); - } - if (DRM_COPY_FROM_USER(buffer + 8, data + 16, 16)) { - DRM_ERROR("EFAULT on pad, %d bytes\n", - tex_width); - return DRM_ERR(EFAULT); - } - } - } else if (tex_width >= 64 || tex_width == 16) { - if (DRM_COPY_FROM_USER(buffer, data, - dwords * sizeof(u32))) { - DRM_ERROR("EFAULT on data, %d dwords\n", - dwords); - return DRM_ERR(EFAULT); - } - } else if (tex_width < 16) { - for (i = 0; i < tex->height; i++) { - if (DRM_COPY_FROM_USER(buffer, data, tex_width)) { - DRM_ERROR("EFAULT on pad, %d bytes\n", - tex_width); - return DRM_ERR(EFAULT); - } - buffer += 4; - data += tex_width; - } - } else if (tex_width == 32) { - /* TODO: make sure this works when not fitting in one buffer - (i.e. 32bytes x 2048...) */ - for (i = 0; i < tex->height; i += 2) { - if (DRM_COPY_FROM_USER(buffer, data, 16)) { - DRM_ERROR("EFAULT on pad, %d bytes\n", - tex_width); - return DRM_ERR(EFAULT); - } - data += 16; - if (DRM_COPY_FROM_USER(buffer + 8, data, 16)) { - DRM_ERROR("EFAULT on pad, %d bytes\n", - tex_width); - return DRM_ERR(EFAULT); - } - data += 16; - if (DRM_COPY_FROM_USER(buffer + 4, data, 16)) { - DRM_ERROR("EFAULT on pad, %d bytes\n", - tex_width); - return DRM_ERR(EFAULT); - } - data += 16; - if (DRM_COPY_FROM_USER(buffer + 12, data, 16)) { - DRM_ERROR("EFAULT on pad, %d bytes\n", - tex_width); - return DRM_ERR(EFAULT); - } - data += 16; - buffer += 16; - } - } - } - else { - if (tex_width >= 32) { - /* Texture image width is larger than the minimum, so we - * can upload it directly. - */ - if (DRM_COPY_FROM_USER(buffer, data, - dwords * sizeof(u32))) { - DRM_ERROR("EFAULT on data, %d dwords\n", - dwords); - return DRM_ERR(EFAULT); - } - } else { - /* Texture image width is less than the minimum, so we - * need to pad out each image scanline to the minimum - * width. - */ - for (i = 0; i < tex->height; i++) { - if (DRM_COPY_FROM_USER(buffer, data, tex_width)) { - DRM_ERROR("EFAULT on pad, %d bytes\n", - tex_width); - return DRM_ERR(EFAULT); - } - buffer += 8; - data += tex_width; - } - } - } - - buf->filp = filp; - buf->used = (dwords + 8) * sizeof(u32); - radeon_cp_dispatch_indirect( dev, buf, 0, buf->used ); - radeon_cp_discard_buffer( dev, buf ); - - /* Update the input parameters for next time */ - image->y += height; - image->height -= height; - image->data = (const u8 __user *)image->data + size; - } while (image->height > 0); - - /* Flush the pixel cache after the blit completes. This ensures - * the texture data is written out to memory before rendering - * continues. - */ - BEGIN_RING( 4 ); - RADEON_FLUSH_CACHE(); - RADEON_WAIT_UNTIL_2D_IDLE(); - ADVANCE_RING(); - return 0; -} - - -static void radeon_cp_dispatch_stipple( drm_device_t *dev, u32 *stipple ) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - int i; - RING_LOCALS; - DRM_DEBUG( "\n" ); - - BEGIN_RING( 35 ); - - OUT_RING( CP_PACKET0( RADEON_RE_STIPPLE_ADDR, 0 ) ); - OUT_RING( 0x00000000 ); - - OUT_RING( CP_PACKET0_TABLE( RADEON_RE_STIPPLE_DATA, 31 ) ); - for ( i = 0 ; i < 32 ; i++ ) { - OUT_RING( stipple[i] ); - } - - ADVANCE_RING(); -} - -static void radeon_apply_surface_regs( int surf_index, drm_radeon_private_t *dev_priv ) -{ - if (!dev_priv->mmio) - return; - - radeon_do_cp_idle(dev_priv); - - RADEON_WRITE( RADEON_SURFACE0_INFO + 16*surf_index, - dev_priv->surfaces[surf_index].flags ); - RADEON_WRITE( RADEON_SURFACE0_LOWER_BOUND + 16*surf_index, - dev_priv->surfaces[surf_index].lower ); - RADEON_WRITE( RADEON_SURFACE0_UPPER_BOUND + 16*surf_index, - dev_priv->surfaces[surf_index].upper ); -} - -/* Allocates a virtual surface - * doesn't always allocate a real surface, will stretch an existing - * surface when possible. - * - * Note that refcount can be at most 2, since during a free refcount=3 - * might mean we have to allocate a new surface which might not always - * be available. - * For example : we allocate three contigous surfaces ABC. If B is - * freed, we suddenly need two surfaces to store A and C, which might - * not always be available. - */ -static int alloc_surface( drm_radeon_surface_alloc_t* new, - drm_radeon_private_t *dev_priv, DRMFILE filp ) -{ - struct radeon_virt_surface *s; - int i; - int virt_surface_index; - uint32_t new_upper, new_lower; - - new_lower = new->address; - new_upper = new_lower + new->size - 1; - - /* sanity check */ - if ((new_lower >= new_upper) || (new->flags == 0) || (new->size == 0) || - ((new_upper & RADEON_SURF_ADDRESS_FIXED_MASK) != RADEON_SURF_ADDRESS_FIXED_MASK) || - ((new_lower & RADEON_SURF_ADDRESS_FIXED_MASK) != 0)) - return -1; - - /* make sure there is no overlap with existing surfaces */ - for (i = 0; i < RADEON_MAX_SURFACES; i++) { - if ((dev_priv->surfaces[i].refcount != 0) && - (( (new_lower >= dev_priv->surfaces[i].lower) && - (new_lower < dev_priv->surfaces[i].upper) ) || - ( (new_lower < dev_priv->surfaces[i].lower) && - (new_upper > dev_priv->surfaces[i].lower) )) ) - return -1; - } - - /* find a virtual surface */ - for (i = 0; i < 2*RADEON_MAX_SURFACES; i++) - if (dev_priv->virt_surfaces[i].filp == 0) - break; - if (i == 2*RADEON_MAX_SURFACES) - return -1; - virt_surface_index = i; - - /* try to reuse an existing surface */ - for (i = 0; i < RADEON_MAX_SURFACES; i++) { - /* extend before */ - if ((dev_priv->surfaces[i].refcount == 1) && - (new->flags == dev_priv->surfaces[i].flags) && - (new_upper + 1 == dev_priv->surfaces[i].lower)) { - s = &(dev_priv->virt_surfaces[virt_surface_index]); - s->surface_index = i; - s->lower = new_lower; - s->upper = new_upper; - s->flags = new->flags; - s->filp = filp; - dev_priv->surfaces[i].refcount++; - dev_priv->surfaces[i].lower = s->lower; - radeon_apply_surface_regs(s->surface_index, dev_priv); - return virt_surface_index; - } - - /* extend after */ - if ((dev_priv->surfaces[i].refcount == 1) && - (new->flags == dev_priv->surfaces[i].flags) && - (new_lower == dev_priv->surfaces[i].upper + 1)) { - s = &(dev_priv->virt_surfaces[virt_surface_index]); - s->surface_index = i; - s->lower = new_lower; - s->upper = new_upper; - s->flags = new->flags; - s->filp = filp; - dev_priv->surfaces[i].refcount++; - dev_priv->surfaces[i].upper = s->upper; - radeon_apply_surface_regs(s->surface_index, dev_priv); - return virt_surface_index; - } - } - - /* okay, we need a new one */ - for (i = 0; i < RADEON_MAX_SURFACES; i++) { - if (dev_priv->surfaces[i].refcount == 0) { - s = &(dev_priv->virt_surfaces[virt_surface_index]); - s->surface_index = i; - s->lower = new_lower; - s->upper = new_upper; - s->flags = new->flags; - s->filp = filp; - dev_priv->surfaces[i].refcount = 1; - dev_priv->surfaces[i].lower = s->lower; - dev_priv->surfaces[i].upper = s->upper; - dev_priv->surfaces[i].flags = s->flags; - radeon_apply_surface_regs(s->surface_index, dev_priv); - return virt_surface_index; - } - } - - /* we didn't find anything */ - return -1; -} - -static int free_surface( DRMFILE filp, drm_radeon_private_t *dev_priv, int lower ) -{ - struct radeon_virt_surface *s; - int i; - /* find the virtual surface */ - for(i = 0; i < 2*RADEON_MAX_SURFACES; i++) { - s = &(dev_priv->virt_surfaces[i]); - if (s->filp) { - if ((lower == s->lower) && (filp == s->filp)) { - if (dev_priv->surfaces[s->surface_index].lower == s->lower) - dev_priv->surfaces[s->surface_index].lower = s->upper; - - if (dev_priv->surfaces[s->surface_index].upper == s->upper) - dev_priv->surfaces[s->surface_index].upper = s->lower; - - dev_priv->surfaces[s->surface_index].refcount--; - if (dev_priv->surfaces[s->surface_index].refcount == 0) - dev_priv->surfaces[s->surface_index].flags = 0; - s->filp = 0; - radeon_apply_surface_regs(s->surface_index, dev_priv); - return 0; - } - } - } - return 1; -} - -static void radeon_surfaces_release( DRMFILE filp, drm_radeon_private_t *dev_priv ) -{ - int i; - for( i = 0; i < 2*RADEON_MAX_SURFACES; i++) - { - if (dev_priv->virt_surfaces[i].filp == filp) - free_surface(filp, dev_priv, dev_priv->virt_surfaces[i].lower); - } -} - -/* ================================================================ - * IOCTL functions - */ - -int radeon_surface_alloc( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_surface_alloc_t alloc; - - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); - return DRM_ERR(EINVAL); -} - - DRM_COPY_FROM_USER_IOCTL( alloc, (drm_radeon_surface_alloc_t __user *)data, - sizeof(alloc) ); - - if ( alloc_surface( &alloc, dev_priv, filp) == -1 ) - return DRM_ERR(EINVAL); - else - return 0; -} - -int radeon_surface_free( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_surface_free_t memfree; - - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); - return DRM_ERR(EINVAL); - } - - DRM_COPY_FROM_USER_IOCTL( memfree, (drm_radeon_surface_free_t __user *)data, - sizeof(memfree) ); - - if ( free_surface( filp, dev_priv, memfree.address ) ) - return DRM_ERR(EINVAL); - else - return 0; -} - -int radeon_cp_clear( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_radeon_clear_t clear; - drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS]; - DRM_DEBUG( "\n" ); - - LOCK_TEST_WITH_RETURN( dev, filp ); - - DRM_COPY_FROM_USER_IOCTL( clear, (drm_radeon_clear_t __user *)data, - sizeof(clear) ); - - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - - if ( sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS ) - sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS; - - if ( DRM_COPY_FROM_USER( &depth_boxes, clear.depth_boxes, - sarea_priv->nbox * sizeof(depth_boxes[0]) ) ) - return DRM_ERR(EFAULT); - - radeon_cp_dispatch_clear( dev, &clear, depth_boxes ); - - COMMIT_RING(); - return 0; -} - - -/* Not sure why this isn't set all the time: - */ -static int radeon_do_init_pageflip( drm_device_t *dev ) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - RING_LOCALS; - - DRM_DEBUG( "\n" ); - - BEGIN_RING( 6 ); - RADEON_WAIT_UNTIL_3D_IDLE(); - OUT_RING( CP_PACKET0( RADEON_CRTC_OFFSET_CNTL, 0 ) ); - OUT_RING( RADEON_READ( RADEON_CRTC_OFFSET_CNTL ) | RADEON_CRTC_OFFSET_FLIP_CNTL ); - OUT_RING( CP_PACKET0( RADEON_CRTC2_OFFSET_CNTL, 0 ) ); - OUT_RING( RADEON_READ( RADEON_CRTC2_OFFSET_CNTL ) | RADEON_CRTC_OFFSET_FLIP_CNTL ); - ADVANCE_RING(); - - dev_priv->page_flipping = 1; - dev_priv->current_page = 0; - dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page; - - return 0; -} - -/* Called whenever a client dies, from DRM(release). - * NOTE: Lock isn't necessarily held when this is called! - */ -int radeon_do_cleanup_pageflip( drm_device_t *dev ) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "\n" ); - - if (dev_priv->current_page != 0) - radeon_cp_dispatch_flip( dev ); - - dev_priv->page_flipping = 0; - return 0; -} - -/* Swapping and flipping are different operations, need different ioctls. - * They can & should be intermixed to support multiple 3d windows. - */ -int radeon_cp_flip( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_radeon_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "\n" ); - - LOCK_TEST_WITH_RETURN( dev, filp ); - - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - - if (!dev_priv->page_flipping) - radeon_do_init_pageflip( dev ); - - radeon_cp_dispatch_flip( dev ); - - COMMIT_RING(); - return 0; -} - -int radeon_cp_swap( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; - DRM_DEBUG( "\n" ); - - LOCK_TEST_WITH_RETURN( dev, filp ); - - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - - if ( sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS ) - sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS; - - radeon_cp_dispatch_swap( dev ); - dev_priv->sarea_priv->ctx_owner = 0; - - COMMIT_RING(); - return 0; -} - -int radeon_cp_vertex( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_file_t *filp_priv; - drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_device_dma_t *dma = dev->dma; - drm_buf_t *buf; - drm_radeon_vertex_t vertex; - drm_radeon_tcl_prim_t prim; - - LOCK_TEST_WITH_RETURN( dev, filp ); - - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); - return DRM_ERR(EINVAL); - } - - DRM_GET_PRIV_WITH_RETURN( filp_priv, filp ); - - DRM_COPY_FROM_USER_IOCTL( vertex, (drm_radeon_vertex_t __user *)data, - sizeof(vertex) ); - - DRM_DEBUG( "pid=%d index=%d count=%d discard=%d\n", - DRM_CURRENTPID, - vertex.idx, vertex.count, vertex.discard ); - - if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) { - DRM_ERROR( "buffer index %d (of %d max)\n", - vertex.idx, dma->buf_count - 1 ); - return DRM_ERR(EINVAL); - } - if ( vertex.prim < 0 || - vertex.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST ) { - DRM_ERROR( "buffer prim %d\n", vertex.prim ); - return DRM_ERR(EINVAL); - } - - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - VB_AGE_TEST_WITH_RETURN( dev_priv ); - - buf = dma->buflist[vertex.idx]; - - if ( buf->filp != filp ) { - DRM_ERROR( "process %d using buffer owned by %p\n", - DRM_CURRENTPID, buf->filp ); - return DRM_ERR(EINVAL); - } - if ( buf->pending ) { - DRM_ERROR( "sending pending buffer %d\n", vertex.idx ); - return DRM_ERR(EINVAL); - } - - /* Build up a prim_t record: - */ - if (vertex.count) { - buf->used = vertex.count; /* not used? */ - - if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) { - if ( radeon_emit_state( dev_priv, filp_priv, - &sarea_priv->context_state, - sarea_priv->tex_state, - sarea_priv->dirty ) ) { - DRM_ERROR( "radeon_emit_state failed\n" ); - return DRM_ERR( EINVAL ); - } - - sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES | - RADEON_UPLOAD_TEX1IMAGES | - RADEON_UPLOAD_TEX2IMAGES | - RADEON_REQUIRE_QUIESCENCE); - } - - prim.start = 0; - prim.finish = vertex.count; /* unused */ - prim.prim = vertex.prim; - prim.numverts = vertex.count; - prim.vc_format = dev_priv->sarea_priv->vc_format; - - radeon_cp_dispatch_vertex( dev, buf, &prim ); - } - - if (vertex.discard) { - radeon_cp_discard_buffer( dev, buf ); - } - - COMMIT_RING(); - return 0; -} - -int radeon_cp_indices( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_file_t *filp_priv; - drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_device_dma_t *dma = dev->dma; - drm_buf_t *buf; - drm_radeon_indices_t elts; - drm_radeon_tcl_prim_t prim; - int count; - - LOCK_TEST_WITH_RETURN( dev, filp ); - - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); - return DRM_ERR(EINVAL); - } - - DRM_GET_PRIV_WITH_RETURN( filp_priv, filp ); - - DRM_COPY_FROM_USER_IOCTL( elts, (drm_radeon_indices_t __user *)data, - sizeof(elts) ); - - DRM_DEBUG( "pid=%d index=%d start=%d end=%d discard=%d\n", - DRM_CURRENTPID, - elts.idx, elts.start, elts.end, elts.discard ); - - if ( elts.idx < 0 || elts.idx >= dma->buf_count ) { - DRM_ERROR( "buffer index %d (of %d max)\n", - elts.idx, dma->buf_count - 1 ); - return DRM_ERR(EINVAL); - } - if ( elts.prim < 0 || - elts.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST ) { - DRM_ERROR( "buffer prim %d\n", elts.prim ); - return DRM_ERR(EINVAL); - } - - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - VB_AGE_TEST_WITH_RETURN( dev_priv ); - - buf = dma->buflist[elts.idx]; - - if ( buf->filp != filp ) { - DRM_ERROR( "process %d using buffer owned by %p\n", - DRM_CURRENTPID, buf->filp ); - return DRM_ERR(EINVAL); - } - if ( buf->pending ) { - DRM_ERROR( "sending pending buffer %d\n", elts.idx ); - return DRM_ERR(EINVAL); - } - - count = (elts.end - elts.start) / sizeof(u16); - elts.start -= RADEON_INDEX_PRIM_OFFSET; - - if ( elts.start & 0x7 ) { - DRM_ERROR( "misaligned buffer 0x%x\n", elts.start ); - return DRM_ERR(EINVAL); - } - if ( elts.start < buf->used ) { - DRM_ERROR( "no header 0x%x - 0x%x\n", elts.start, buf->used ); - return DRM_ERR(EINVAL); - } - - buf->used = elts.end; - - if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) { - if ( radeon_emit_state( dev_priv, filp_priv, - &sarea_priv->context_state, - sarea_priv->tex_state, - sarea_priv->dirty ) ) { - DRM_ERROR( "radeon_emit_state failed\n" ); - return DRM_ERR( EINVAL ); - } - - sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES | - RADEON_UPLOAD_TEX1IMAGES | - RADEON_UPLOAD_TEX2IMAGES | - RADEON_REQUIRE_QUIESCENCE); - } - - - /* Build up a prim_t record: - */ - prim.start = elts.start; - prim.finish = elts.end; - prim.prim = elts.prim; - prim.offset = 0; /* offset from start of dma buffers */ - prim.numverts = RADEON_MAX_VB_VERTS; /* duh */ - prim.vc_format = dev_priv->sarea_priv->vc_format; - - radeon_cp_dispatch_indices( dev, buf, &prim ); - if (elts.discard) { - radeon_cp_discard_buffer( dev, buf ); - } - - COMMIT_RING(); - return 0; -} - -int radeon_cp_texture( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_texture_t tex; - drm_radeon_tex_image_t image; - int ret; - - LOCK_TEST_WITH_RETURN( dev, filp ); - - DRM_COPY_FROM_USER_IOCTL( tex, (drm_radeon_texture_t __user *)data, sizeof(tex) ); - - if ( tex.image == NULL ) { - DRM_ERROR( "null texture image!\n" ); - return DRM_ERR(EINVAL); - } - - if ( DRM_COPY_FROM_USER( &image, - (drm_radeon_tex_image_t __user *)tex.image, - sizeof(image) ) ) - return DRM_ERR(EFAULT); - - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - VB_AGE_TEST_WITH_RETURN( dev_priv ); - - ret = radeon_cp_dispatch_texture( filp, dev, &tex, &image ); - - COMMIT_RING(); - return ret; -} - -int radeon_cp_stipple( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_stipple_t stipple; - u32 mask[32]; - - LOCK_TEST_WITH_RETURN( dev, filp ); - - DRM_COPY_FROM_USER_IOCTL( stipple, (drm_radeon_stipple_t __user *)data, - sizeof(stipple) ); - - if ( DRM_COPY_FROM_USER( &mask, stipple.mask, 32 * sizeof(u32) ) ) - return DRM_ERR(EFAULT); - - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - - radeon_cp_dispatch_stipple( dev, mask ); - - COMMIT_RING(); - return 0; -} - -int radeon_cp_indirect( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_device_dma_t *dma = dev->dma; - drm_buf_t *buf; - drm_radeon_indirect_t indirect; - RING_LOCALS; - - LOCK_TEST_WITH_RETURN( dev, filp ); - - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); - return DRM_ERR(EINVAL); - } - - DRM_COPY_FROM_USER_IOCTL( indirect, (drm_radeon_indirect_t __user *)data, - sizeof(indirect) ); - - DRM_DEBUG( "indirect: idx=%d s=%d e=%d d=%d\n", - indirect.idx, indirect.start, - indirect.end, indirect.discard ); - - if ( indirect.idx < 0 || indirect.idx >= dma->buf_count ) { - DRM_ERROR( "buffer index %d (of %d max)\n", - indirect.idx, dma->buf_count - 1 ); - return DRM_ERR(EINVAL); - } - - buf = dma->buflist[indirect.idx]; - - if ( buf->filp != filp ) { - DRM_ERROR( "process %d using buffer owned by %p\n", - DRM_CURRENTPID, buf->filp ); - return DRM_ERR(EINVAL); - } - if ( buf->pending ) { - DRM_ERROR( "sending pending buffer %d\n", indirect.idx ); - return DRM_ERR(EINVAL); - } - - if ( indirect.start < buf->used ) { - DRM_ERROR( "reusing indirect: start=0x%x actual=0x%x\n", - indirect.start, buf->used ); - return DRM_ERR(EINVAL); - } - - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - VB_AGE_TEST_WITH_RETURN( dev_priv ); - - buf->used = indirect.end; - - /* Wait for the 3D stream to idle before the indirect buffer - * containing 2D acceleration commands is processed. - */ - BEGIN_RING( 2 ); - - RADEON_WAIT_UNTIL_3D_IDLE(); - - ADVANCE_RING(); - - /* Dispatch the indirect buffer full of commands from the - * X server. This is insecure and is thus only available to - * privileged clients. - */ - radeon_cp_dispatch_indirect( dev, buf, indirect.start, indirect.end ); - if (indirect.discard) { - radeon_cp_discard_buffer( dev, buf ); - } - - - COMMIT_RING(); - return 0; -} - -int radeon_cp_vertex2( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_file_t *filp_priv; - drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_device_dma_t *dma = dev->dma; - drm_buf_t *buf; - drm_radeon_vertex2_t vertex; - int i; - unsigned char laststate; - - LOCK_TEST_WITH_RETURN( dev, filp ); - - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); - return DRM_ERR(EINVAL); - } - - DRM_GET_PRIV_WITH_RETURN( filp_priv, filp ); - - DRM_COPY_FROM_USER_IOCTL( vertex, (drm_radeon_vertex2_t __user *)data, - sizeof(vertex) ); - - DRM_DEBUG( "pid=%d index=%d discard=%d\n", - DRM_CURRENTPID, - vertex.idx, vertex.discard ); - - if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) { - DRM_ERROR( "buffer index %d (of %d max)\n", - vertex.idx, dma->buf_count - 1 ); - return DRM_ERR(EINVAL); - } - - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - VB_AGE_TEST_WITH_RETURN( dev_priv ); - - buf = dma->buflist[vertex.idx]; - - if ( buf->filp != filp ) { - DRM_ERROR( "process %d using buffer owned by %p\n", - DRM_CURRENTPID, buf->filp ); - return DRM_ERR(EINVAL); - } - - if ( buf->pending ) { - DRM_ERROR( "sending pending buffer %d\n", vertex.idx ); - return DRM_ERR(EINVAL); - } - - if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS) - return DRM_ERR(EINVAL); - - for (laststate = 0xff, i = 0 ; i < vertex.nr_prims ; i++) { - drm_radeon_prim_t prim; - drm_radeon_tcl_prim_t tclprim; - - if ( DRM_COPY_FROM_USER( &prim, &vertex.prim[i], sizeof(prim) ) ) - return DRM_ERR(EFAULT); - - if ( prim.stateidx != laststate ) { - drm_radeon_state_t state; - - if ( DRM_COPY_FROM_USER( &state, - &vertex.state[prim.stateidx], - sizeof(state) ) ) - return DRM_ERR(EFAULT); - - if ( radeon_emit_state2( dev_priv, filp_priv, &state ) ) { - DRM_ERROR( "radeon_emit_state2 failed\n" ); - return DRM_ERR( EINVAL ); - } - - laststate = prim.stateidx; - } - - tclprim.start = prim.start; - tclprim.finish = prim.finish; - tclprim.prim = prim.prim; - tclprim.vc_format = prim.vc_format; - - if ( prim.prim & RADEON_PRIM_WALK_IND ) { - tclprim.offset = prim.numverts * 64; - tclprim.numverts = RADEON_MAX_VB_VERTS; /* duh */ - - radeon_cp_dispatch_indices( dev, buf, &tclprim ); - } else { - tclprim.numverts = prim.numverts; - tclprim.offset = 0; /* not used */ - - radeon_cp_dispatch_vertex( dev, buf, &tclprim ); - } - - if (sarea_priv->nbox == 1) - sarea_priv->nbox = 0; - } - - if ( vertex.discard ) { - radeon_cp_discard_buffer( dev, buf ); - } - - COMMIT_RING(); - return 0; -} - - -static int radeon_emit_packets( - drm_radeon_private_t *dev_priv, - drm_file_t *filp_priv, - drm_radeon_cmd_header_t header, - drm_radeon_cmd_buffer_t *cmdbuf ) -{ - int id = (int)header.packet.packet_id; - int sz, reg; - int *data = (int *)cmdbuf->buf; - RING_LOCALS; - - if (id >= RADEON_MAX_STATE_PACKETS) - return DRM_ERR(EINVAL); - - sz = packet[id].len; - reg = packet[id].start; - - if (sz * sizeof(int) > cmdbuf->bufsz) { - DRM_ERROR( "Packet size provided larger than data provided\n" ); - return DRM_ERR(EINVAL); - } - - if ( radeon_check_and_fixup_packets( dev_priv, filp_priv, id, data ) ) { - DRM_ERROR( "Packet verification failed\n" ); - return DRM_ERR( EINVAL ); - } - - BEGIN_RING(sz+1); - OUT_RING( CP_PACKET0( reg, (sz-1) ) ); - OUT_RING_TABLE(data, sz); - ADVANCE_RING(); - - cmdbuf->buf += sz * sizeof(int); - cmdbuf->bufsz -= sz * sizeof(int); - return 0; -} - -static __inline__ int radeon_emit_scalars( - drm_radeon_private_t *dev_priv, - drm_radeon_cmd_header_t header, - drm_radeon_cmd_buffer_t *cmdbuf ) -{ - int sz = header.scalars.count; - int start = header.scalars.offset; - int stride = header.scalars.stride; - RING_LOCALS; - - BEGIN_RING( 3+sz ); - OUT_RING( CP_PACKET0( RADEON_SE_TCL_SCALAR_INDX_REG, 0 ) ); - OUT_RING( start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); - OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_SCALAR_DATA_REG, sz-1 ) ); - OUT_RING_TABLE(cmdbuf->buf, sz); - ADVANCE_RING(); - cmdbuf->buf += sz * sizeof(int); - cmdbuf->bufsz -= sz * sizeof(int); - return 0; -} - -/* God this is ugly - */ -static __inline__ int radeon_emit_scalars2( - drm_radeon_private_t *dev_priv, - drm_radeon_cmd_header_t header, - drm_radeon_cmd_buffer_t *cmdbuf ) -{ - int sz = header.scalars.count; - int start = ((unsigned int)header.scalars.offset) + 0x100; - int stride = header.scalars.stride; - RING_LOCALS; - - BEGIN_RING( 3+sz ); - OUT_RING( CP_PACKET0( RADEON_SE_TCL_SCALAR_INDX_REG, 0 ) ); - OUT_RING( start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); - OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_SCALAR_DATA_REG, sz-1 ) ); - OUT_RING_TABLE(cmdbuf->buf, sz); - ADVANCE_RING(); - cmdbuf->buf += sz * sizeof(int); - cmdbuf->bufsz -= sz * sizeof(int); - return 0; -} - -static __inline__ int radeon_emit_vectors( - drm_radeon_private_t *dev_priv, - drm_radeon_cmd_header_t header, - drm_radeon_cmd_buffer_t *cmdbuf ) -{ - int sz = header.vectors.count; - int start = header.vectors.offset; - int stride = header.vectors.stride; - RING_LOCALS; - - BEGIN_RING( 3+sz ); - OUT_RING( CP_PACKET0( RADEON_SE_TCL_VECTOR_INDX_REG, 0 ) ); - OUT_RING( start | (stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); - OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_VECTOR_DATA_REG, (sz-1) ) ); - OUT_RING_TABLE(cmdbuf->buf, sz); - ADVANCE_RING(); - - cmdbuf->buf += sz * sizeof(int); - cmdbuf->bufsz -= sz * sizeof(int); - return 0; -} - - -static int radeon_emit_packet3( drm_device_t *dev, - drm_file_t *filp_priv, - drm_radeon_cmd_buffer_t *cmdbuf ) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - unsigned int cmdsz; - int ret; - RING_LOCALS; - - DRM_DEBUG("\n"); - - if ( ( ret = radeon_check_and_fixup_packet3( dev_priv, filp_priv, - cmdbuf, &cmdsz ) ) ) { - DRM_ERROR( "Packet verification failed\n" ); - return ret; - } - - BEGIN_RING( cmdsz ); - OUT_RING_TABLE(cmdbuf->buf, cmdsz); - ADVANCE_RING(); - - cmdbuf->buf += cmdsz * 4; - cmdbuf->bufsz -= cmdsz * 4; - return 0; -} - - -static int radeon_emit_packet3_cliprect( drm_device_t *dev, - drm_file_t *filp_priv, - drm_radeon_cmd_buffer_t *cmdbuf, - int orig_nbox ) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_clip_rect_t box; - unsigned int cmdsz; - int ret; - drm_clip_rect_t __user *boxes = cmdbuf->boxes; - int i = 0; - RING_LOCALS; - - DRM_DEBUG("\n"); - - if ( ( ret = radeon_check_and_fixup_packet3( dev_priv, filp_priv, - cmdbuf, &cmdsz ) ) ) { - DRM_ERROR( "Packet verification failed\n" ); - return ret; - } - - if (!orig_nbox) - goto out; - - do { - if ( i < cmdbuf->nbox ) { - if (DRM_COPY_FROM_USER_UNCHECKED( &box, &boxes[i], sizeof(box) )) - return DRM_ERR(EFAULT); - /* FIXME The second and subsequent times round - * this loop, send a WAIT_UNTIL_3D_IDLE before - * calling emit_clip_rect(). This fixes a - * lockup on fast machines when sending - * several cliprects with a cmdbuf, as when - * waving a 2D window over a 3D - * window. Something in the commands from user - * space seems to hang the card when they're - * sent several times in a row. That would be - * the correct place to fix it but this works - * around it until I can figure that out - Tim - * Smith */ - if ( i ) { - BEGIN_RING( 2 ); - RADEON_WAIT_UNTIL_3D_IDLE(); - ADVANCE_RING(); - } - radeon_emit_clip_rect( dev_priv, &box ); - } - - BEGIN_RING( cmdsz ); - OUT_RING_TABLE(cmdbuf->buf, cmdsz); - ADVANCE_RING(); - - } while ( ++i < cmdbuf->nbox ); - if (cmdbuf->nbox == 1) - cmdbuf->nbox = 0; - - out: - cmdbuf->buf += cmdsz * 4; - cmdbuf->bufsz -= cmdsz * 4; - return 0; -} - - -static int radeon_emit_wait( drm_device_t *dev, int flags ) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - RING_LOCALS; - - DRM_DEBUG("%s: %x\n", __FUNCTION__, flags); - switch (flags) { - case RADEON_WAIT_2D: - BEGIN_RING( 2 ); - RADEON_WAIT_UNTIL_2D_IDLE(); - ADVANCE_RING(); - break; - case RADEON_WAIT_3D: - BEGIN_RING( 2 ); - RADEON_WAIT_UNTIL_3D_IDLE(); - ADVANCE_RING(); - break; - case RADEON_WAIT_2D|RADEON_WAIT_3D: - BEGIN_RING( 2 ); - RADEON_WAIT_UNTIL_IDLE(); - ADVANCE_RING(); - break; - default: - return DRM_ERR(EINVAL); - } - - return 0; -} - -int radeon_cp_cmdbuf( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_file_t *filp_priv; - drm_device_dma_t *dma = dev->dma; - drm_buf_t *buf = NULL; - int idx; - drm_radeon_cmd_buffer_t cmdbuf; - drm_radeon_cmd_header_t header; - int orig_nbox, orig_bufsz; - char *kbuf; - - LOCK_TEST_WITH_RETURN( dev, filp ); - - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); - return DRM_ERR(EINVAL); - } - - DRM_GET_PRIV_WITH_RETURN( filp_priv, filp ); - - DRM_COPY_FROM_USER_IOCTL( cmdbuf, (drm_radeon_cmd_buffer_t __user *)data, - sizeof(cmdbuf) ); - - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - VB_AGE_TEST_WITH_RETURN( dev_priv ); - - - if (cmdbuf.bufsz > 64 * 1024 || cmdbuf.bufsz < 0) { - return DRM_ERR(EINVAL); - } - - /* Allocate an in-kernel area and copy in the cmdbuf. Do this to avoid - * races between checking values and using those values in other code, - * and simply to avoid a lot of function calls to copy in data. - */ - orig_bufsz = cmdbuf.bufsz; - if (orig_bufsz != 0) { - kbuf = DRM(alloc)(cmdbuf.bufsz, DRM_MEM_DRIVER); - if (kbuf == NULL) - return DRM_ERR(ENOMEM); - if (DRM_COPY_FROM_USER(kbuf, cmdbuf.buf, cmdbuf.bufsz)) - return DRM_ERR(EFAULT); - cmdbuf.buf = kbuf; - } - - orig_nbox = cmdbuf.nbox; - - while ( cmdbuf.bufsz >= sizeof(header) ) { - header.i = *(int *)cmdbuf.buf; - cmdbuf.buf += sizeof(header); - cmdbuf.bufsz -= sizeof(header); - - switch (header.header.cmd_type) { - case RADEON_CMD_PACKET: - DRM_DEBUG("RADEON_CMD_PACKET\n"); - if (radeon_emit_packets( dev_priv, filp_priv, header, &cmdbuf )) { - DRM_ERROR("radeon_emit_packets failed\n"); - goto err; - } - break; - - case RADEON_CMD_SCALARS: - DRM_DEBUG("RADEON_CMD_SCALARS\n"); - if (radeon_emit_scalars( dev_priv, header, &cmdbuf )) { - DRM_ERROR("radeon_emit_scalars failed\n"); - goto err; - } - break; - - case RADEON_CMD_VECTORS: - DRM_DEBUG("RADEON_CMD_VECTORS\n"); - if (radeon_emit_vectors( dev_priv, header, &cmdbuf )) { - DRM_ERROR("radeon_emit_vectors failed\n"); - goto err; - } - break; - - case RADEON_CMD_DMA_DISCARD: - DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n"); - idx = header.dma.buf_idx; - if ( idx < 0 || idx >= dma->buf_count ) { - DRM_ERROR( "buffer index %d (of %d max)\n", - idx, dma->buf_count - 1 ); - goto err; - } - - buf = dma->buflist[idx]; - if ( buf->filp != filp || buf->pending ) { - DRM_ERROR( "bad buffer %p %p %d\n", - buf->filp, filp, buf->pending); - goto err; - } - - radeon_cp_discard_buffer( dev, buf ); - break; - - case RADEON_CMD_PACKET3: - DRM_DEBUG("RADEON_CMD_PACKET3\n"); - if (radeon_emit_packet3( dev, filp_priv, &cmdbuf )) { - DRM_ERROR("radeon_emit_packet3 failed\n"); - goto err; - } - break; - - case RADEON_CMD_PACKET3_CLIP: - DRM_DEBUG("RADEON_CMD_PACKET3_CLIP\n"); - if (radeon_emit_packet3_cliprect( dev, filp_priv, &cmdbuf, orig_nbox )) { - DRM_ERROR("radeon_emit_packet3_clip failed\n"); - goto err; - } - break; - - case RADEON_CMD_SCALARS2: - DRM_DEBUG("RADEON_CMD_SCALARS2\n"); - if (radeon_emit_scalars2( dev_priv, header, &cmdbuf )) { - DRM_ERROR("radeon_emit_scalars2 failed\n"); - goto err; - } - break; - - case RADEON_CMD_WAIT: - DRM_DEBUG("RADEON_CMD_WAIT\n"); - if (radeon_emit_wait( dev, header.wait.flags )) { - DRM_ERROR("radeon_emit_wait failed\n"); - goto err; - } - break; - default: - DRM_ERROR("bad cmd_type %d at %p\n", - header.header.cmd_type, - cmdbuf.buf - sizeof(header)); - goto err; - } - } - - if (orig_bufsz != 0) - DRM(free)(kbuf, orig_bufsz, DRM_MEM_DRIVER); - DRM_DEBUG("DONE\n"); - COMMIT_RING(); - return 0; - -err: - if (orig_bufsz != 0) - DRM(free)(kbuf, orig_bufsz, DRM_MEM_DRIVER); - return DRM_ERR(EINVAL); -} - - - -int radeon_cp_getparam( DRM_IOCTL_ARGS ) -{ - DRM_DEVICE; - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_radeon_getparam_t param; - int value; - - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); - return DRM_ERR(EINVAL); - } - - DRM_COPY_FROM_USER_IOCTL( param, (drm_radeon_getparam_t __user *)data, - sizeof(param) ); - - DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID ); - - switch( param.param ) { - case RADEON_PARAM_GART_BUFFER_OFFSET: - value = dev_priv->gart_buffers_offset; - break; - case RADEON_PARAM_LAST_FRAME: - dev_priv->stats.last_frame_reads++; - value = GET_SCRATCH( 0 ); - break; - case RADEON_PARAM_LAST_DISPATCH: - value = GET_SCRATCH( 1 ); - break; - case RADEON_PARAM_LAST_CLEAR: - dev_priv->stats.last_clear_reads++; - value = GET_SCRATCH( 2 ); - break; - case RADEON_PARAM_IRQ_NR: - value = dev->irq; - break; - case RADEON_PARAM_GART_BASE: - value = dev_priv->gart_vm_start; - break; - case RADEON_PARAM_REGISTER_HANDLE: - value = dev_priv->mmio_offset; - break; - case RADEON_PARAM_STATUS_HANDLE: - value = dev_priv->ring_rptr_offset; - break; -#if BITS_PER_LONG == 32 - /* - * This ioctl() doesn't work on 64-bit platforms because hw_lock is a - * pointer which can't fit into an int-sized variable. According to - * Michel Dänzer, the ioctl() is only used on embedded platforms, so - * not supporting it shouldn't be a problem. If the same functionality - * is needed on 64-bit platforms, a new ioctl() would have to be added, - * so backwards-compatibility for the embedded platforms can be - * maintained. --davidm 4-Feb-2004. - */ - case RADEON_PARAM_SAREA_HANDLE: - /* The lock is the first dword in the sarea. */ - value = (long)dev->lock.hw_lock; - break; -#endif - case RADEON_PARAM_GART_TEX_HANDLE: - value = dev_priv->gart_textures_offset; - break; - default: - return DRM_ERR(EINVAL); - } - - if ( DRM_COPY_TO_USER( param.value, &value, sizeof(int) ) ) { - DRM_ERROR( "copy_to_user\n" ); - return DRM_ERR(EFAULT); - } - - return 0; -} - -int radeon_cp_setparam( DRM_IOCTL_ARGS ) { - DRM_DEVICE; - drm_radeon_private_t *dev_priv = dev->dev_private; - drm_file_t *filp_priv; - drm_radeon_setparam_t sp; - struct drm_radeon_driver_file_fields *radeon_priv; - - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); - return DRM_ERR( EINVAL ); - } - - DRM_GET_PRIV_WITH_RETURN( filp_priv, filp ); - - DRM_COPY_FROM_USER_IOCTL( sp, ( drm_radeon_setparam_t __user * )data, - sizeof( sp ) ); - - switch( sp.param ) { - case RADEON_SETPARAM_FB_LOCATION: - radeon_priv = filp_priv->driver_priv; - radeon_priv->radeon_fb_delta = dev_priv->fb_location - sp.value; - break; - case RADEON_SETPARAM_SWITCH_TILING: - if (sp.value == 0) { - DRM_DEBUG( "color tiling disabled\n" ); - dev_priv->front_pitch_offset &= ~RADEON_DST_TILE_MACRO; - dev_priv->back_pitch_offset &= ~RADEON_DST_TILE_MACRO; - dev_priv->sarea_priv->tiling_enabled = 0; - } - else if (sp.value == 1) { - DRM_DEBUG( "color tiling enabled\n" ); - dev_priv->front_pitch_offset |= RADEON_DST_TILE_MACRO; - dev_priv->back_pitch_offset |= RADEON_DST_TILE_MACRO; - dev_priv->sarea_priv->tiling_enabled = 1; - } - break; - default: - DRM_DEBUG( "Invalid parameter %d\n", sp.param ); - return DRM_ERR( EINVAL ); - } - - return 0; -} - -/* When a client dies: - * - Check for and clean up flipped page state - * - Free any alloced GART memory. - * - Free any alloced radeon surfaces. - * - * DRM infrastructure takes care of reclaiming dma buffers. - */ -static void radeon_driver_prerelease(drm_device_t *dev, DRMFILE filp) -{ - if ( dev->dev_private ) { - drm_radeon_private_t *dev_priv = dev->dev_private; - if ( dev_priv->page_flipping ) { - radeon_do_cleanup_pageflip( dev ); - } - radeon_mem_release( filp, dev_priv->gart_heap ); - radeon_mem_release( filp, dev_priv->fb_heap ); - radeon_surfaces_release( filp, dev_priv ); - } -} - -static void radeon_driver_pretakedown(drm_device_t *dev) -{ - radeon_do_release(dev); -} - -static int radeon_driver_open_helper(drm_device_t *dev, drm_file_t *filp_priv) -{ - drm_radeon_private_t *dev_priv = dev->dev_private; - struct drm_radeon_driver_file_fields *radeon_priv; - - radeon_priv = (struct drm_radeon_driver_file_fields *)DRM(alloc)(sizeof(*radeon_priv), DRM_MEM_FILES); - - if (!radeon_priv) - return -ENOMEM; - - filp_priv->driver_priv = radeon_priv; - - if ( dev_priv ) - radeon_priv->radeon_fb_delta = dev_priv->fb_location; - else - radeon_priv->radeon_fb_delta = 0; - return 0; -} - -static void radeon_driver_free_filp_priv(drm_device_t *dev, drm_file_t *filp_priv) -{ - struct drm_radeon_driver_file_fields *radeon_priv = filp_priv->driver_priv; - - DRM(free)(radeon_priv, sizeof(*radeon_priv), DRM_MEM_FILES); -} - -void radeon_driver_register_fns(struct drm_device *dev) -{ - dev->driver_features = DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG | DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED | DRIVER_IRQ_VBL; - dev->dev_priv_size = sizeof(drm_radeon_buf_priv_t); - dev->fn_tbl.preinit = radeon_preinit; - dev->fn_tbl.postinit = radeon_postinit; - dev->fn_tbl.postcleanup = radeon_postcleanup; - dev->fn_tbl.prerelease = radeon_driver_prerelease; - dev->fn_tbl.pretakedown = radeon_driver_pretakedown; - dev->fn_tbl.open_helper = radeon_driver_open_helper; - dev->fn_tbl.vblank_wait = radeon_driver_vblank_wait; - dev->fn_tbl.irq_preinstall = radeon_driver_irq_preinstall; - dev->fn_tbl.irq_postinstall = radeon_driver_irq_postinstall; - dev->fn_tbl.irq_uninstall = radeon_driver_irq_uninstall; - dev->fn_tbl.irq_handler = radeon_driver_irq_handler; - dev->fn_tbl.free_filp_priv = radeon_driver_free_filp_priv; -} diff --git a/nx-X11/extras/drm/shared/sis.h b/nx-X11/extras/drm/shared/sis.h deleted file mode 100644 index 5f7037000..000000000 --- a/nx-X11/extras/drm/shared/sis.h +++ /dev/null @@ -1,57 +0,0 @@ -/* sis_drv.h -- Private header for sis driver -*- linux-c -*- - * - * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. - * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. - * All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - */ -/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/sis.h,v 1.3 2002/10/30 12:52:38 alanh Exp $ */ - -#ifndef __SIS_H__ -#define __SIS_H__ - -/* This remains constant for all DRM template files. - * Name it sisdrv_##x as there's a conflict with sis_free/malloc in the kernel - * that's used for fb devices - */ -#define DRM(x) sisdrv_##x - -/* General customization: - */ - -#define DRIVER_AUTHOR "SIS" -#define DRIVER_NAME "sis" -#define DRIVER_DESC "SIS 300/630/540" -#define DRIVER_DATE "20030826" -#define DRIVER_MAJOR 1 -#define DRIVER_MINOR 1 -#define DRIVER_PATCHLEVEL 0 - -#define DRIVER_IOCTLS \ - [DRM_IOCTL_NR(DRM_IOCTL_SIS_FB_ALLOC)] = { sis_fb_alloc, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_SIS_FB_FREE)] = { sis_fb_free, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_SIS_AGP_INIT)] = { sis_ioctl_agp_init, 1, 1 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_SIS_AGP_ALLOC)] = { sis_ioctl_agp_alloc, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_SIS_AGP_FREE)] = { sis_ioctl_agp_free, 1, 0 }, \ - [DRM_IOCTL_NR(DRM_IOCTL_SIS_FB_INIT)] = { sis_fb_init, 1, 1 } - -#endif diff --git a/nx-X11/extras/drm/shared/sis_drm.h b/nx-X11/extras/drm/shared/sis_drm.h deleted file mode 100644 index 49505719c..000000000 --- a/nx-X11/extras/drm/shared/sis_drm.h +++ /dev/null @@ -1,33 +0,0 @@ - -#ifndef __SIS_DRM_H__ -#define __SIS_DRM_H__ - -/* SiS specific ioctls */ -#define DRM_IOCTL_SIS_FB_ALLOC DRM_IOWR(0x44, drm_sis_mem_t) -#define DRM_IOCTL_SIS_FB_FREE DRM_IOW( 0x45, drm_sis_mem_t) -#define DRM_IOCTL_SIS_AGP_INIT DRM_IOWR(0x53, drm_sis_agp_t) -#define DRM_IOCTL_SIS_AGP_ALLOC DRM_IOWR(0x54, drm_sis_mem_t) -#define DRM_IOCTL_SIS_AGP_FREE DRM_IOW( 0x55, drm_sis_mem_t) -#define DRM_IOCTL_SIS_FB_INIT DRM_IOW( 0x56, drm_sis_fb_t) -/* -#define DRM_IOCTL_SIS_FLIP DRM_IOW( 0x48, drm_sis_flip_t) -#define DRM_IOCTL_SIS_FLIP_INIT DRM_IO( 0x49) -#define DRM_IOCTL_SIS_FLIP_FINAL DRM_IO( 0x50) -*/ - -typedef struct { - int context; - unsigned int offset; - unsigned int size; - unsigned long free; -} drm_sis_mem_t; - -typedef struct { - unsigned int offset, size; -} drm_sis_agp_t; - -typedef struct { - unsigned int offset, size; -} drm_sis_fb_t; - -#endif /* __SIS_DRM_H__ */ diff --git a/nx-X11/extras/drm/shared/sis_drv.h b/nx-X11/extras/drm/shared/sis_drv.h deleted file mode 100644 index 1ca618cf5..000000000 --- a/nx-X11/extras/drm/shared/sis_drv.h +++ /dev/null @@ -1,48 +0,0 @@ -/* sis_drv.h -- Private header for sis driver -*- linux-c -*- - * - * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. - * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. - * All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef _SIS_DRV_H_ -#define _SIS_DRV_H_ - -#include "sis_ds.h" - -typedef struct drm_sis_private { - memHeap_t *AGPHeap; - memHeap_t *FBHeap; -} drm_sis_private_t; - -extern int sis_fb_alloc( DRM_IOCTL_ARGS ); -extern int sis_fb_free( DRM_IOCTL_ARGS ); -extern int sis_ioctl_agp_init( DRM_IOCTL_ARGS ); -extern int sis_ioctl_agp_alloc( DRM_IOCTL_ARGS ); -extern int sis_ioctl_agp_free( DRM_IOCTL_ARGS ); -extern int sis_fb_init( DRM_IOCTL_ARGS ); - -extern int sis_init_context(drm_device_t *dev, int context); -extern int sis_final_context(drm_device_t *dev, int context); - -#endif diff --git a/nx-X11/extras/drm/shared/sis_ds.c b/nx-X11/extras/drm/shared/sis_ds.c deleted file mode 100644 index e3ae4aea4..000000000 --- a/nx-X11/extras/drm/shared/sis_ds.c +++ /dev/null @@ -1,386 +0,0 @@ -/* sis_ds.c -- Private header for Direct Rendering Manager -*- linux-c -*- - * Created: Mon Jan 4 10:05:05 1999 by sclin@sis.com.tw - * - * Copyright 2000 Silicon Integrated Systems Corp, Inc., HsinChu, Taiwan. - * All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Sung-Ching Lin - * - */ - -#include "sis.h" -#include "drmP.h" -#include "drm.h" -#include "sis_ds.h" - -/* Set Data Structure, not check repeated value - * temporarily used - */ - -set_t *setInit(void) -{ - int i; - set_t *set; - - set = (set_t *)DRM(alloc)(sizeof(set_t), DRM_MEM_DRIVER); - if (set != NULL) { - for (i = 0; i < SET_SIZE; i++) { - set->list[i].free_next = i + 1; - set->list[i].alloc_next = -1; - } - set->list[SET_SIZE-1].free_next = -1; - set->free = 0; - set->alloc = -1; - set->trace = -1; - } - return set; -} - -int setAdd(set_t *set, ITEM_TYPE item) -{ - int free = set->free; - - if (free != -1) { - set->list[free].val = item; - set->free = set->list[free].free_next; - } else { - return 0; - } - - set->list[free].alloc_next = set->alloc; - set->alloc = free; - set->list[free].free_next = -1; - - return 1; -} - -int setDel(set_t *set, ITEM_TYPE item) -{ - int alloc = set->alloc; - int prev = -1; - - while (alloc != -1) { - if (set->list[alloc].val == item) { - if (prev != -1) - set->list[prev].alloc_next = - set->list[alloc].alloc_next; - else - set->alloc = set->list[alloc].alloc_next; - break; - } - prev = alloc; - alloc = set->list[alloc].alloc_next; - } - - if (alloc == -1) - return 0; - - set->list[alloc].free_next = set->free; - set->free = alloc; - set->list[alloc].alloc_next = -1; - - return 1; -} - -/* setFirst -> setAdd -> setNext is wrong */ - -int setFirst(set_t *set, ITEM_TYPE *item) -{ - if (set->alloc == -1) - return 0; - - *item = set->list[set->alloc].val; - set->trace = set->list[set->alloc].alloc_next; - - return 1; -} - -int setNext(set_t *set, ITEM_TYPE *item) -{ - if (set->trace == -1) - return 0; - - *item = set->list[set->trace].val; - set->trace = set->list[set->trace].alloc_next; - - return 1; -} - -int setDestroy(set_t *set) -{ - DRM(free)(set, sizeof(set_t), DRM_MEM_DRIVER); - - return 1; -} - -/* - * GLX Hardware Device Driver common code - * Copyright (C) 1999 Wittawat Yamwong - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * KEITH WHITWELL, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE - * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#define ISFREE(bptr) ((bptr)->free) - -memHeap_t *mmInit(int ofs, - int size) -{ - PMemBlock blocks; - - if (size <= 0) - return NULL; - - blocks = (TMemBlock *)DRM(calloc)(1, sizeof(TMemBlock), DRM_MEM_DRIVER); - if (blocks != NULL) { - blocks->ofs = ofs; - blocks->size = size; - blocks->free = 1; - return (memHeap_t *)blocks; - } else - return NULL; -} - -/* Checks if a pointer 'b' is part of the heap 'heap' */ -int mmBlockInHeap(memHeap_t *heap, PMemBlock b) -{ - TMemBlock *p; - - if (heap == NULL || b == NULL) - return 0; - - p = heap; - while (p != NULL && p != b) { - p = p->next; - } - if (p == b) - return 1; - else - return 0; -} - -/* Kludgey workaround for existing i810 server. Remove soon. - */ -memHeap_t *mmAddRange( memHeap_t *heap, - int ofs, - int size ) -{ - PMemBlock blocks; - blocks = (TMemBlock *)DRM(calloc)(2, sizeof(TMemBlock), DRM_MEM_DRIVER); - if (blocks != NULL) { - blocks[0].size = size; - blocks[0].free = 1; - blocks[0].ofs = ofs; - blocks[0].next = &blocks[1]; - - /* Discontinuity - stops JoinBlock from trying to join - * non-adjacent ranges. - */ - blocks[1].size = 0; - blocks[1].free = 0; - blocks[1].ofs = ofs+size; - blocks[1].next = (PMemBlock)heap; - return (memHeap_t *)blocks; - } else - return heap; -} - -static TMemBlock* SliceBlock(TMemBlock *p, - int startofs, int size, - int reserved, int alignment) -{ - TMemBlock *newblock; - - /* break left */ - if (startofs > p->ofs) { - newblock = (TMemBlock*) DRM(calloc)(1, sizeof(TMemBlock), - DRM_MEM_DRIVER); - newblock->ofs = startofs; - newblock->size = p->size - (startofs - p->ofs); - newblock->free = 1; - newblock->next = p->next; - p->size -= newblock->size; - p->next = newblock; - p = newblock; - } - - /* break right */ - if (size < p->size) { - newblock = (TMemBlock*) DRM(calloc)(1, sizeof(TMemBlock), - DRM_MEM_DRIVER); - newblock->ofs = startofs + size; - newblock->size = p->size - size; - newblock->free = 1; - newblock->next = p->next; - p->size = size; - p->next = newblock; - } - - /* p = middle block */ - p->align = alignment; - p->free = 0; - p->reserved = reserved; - return p; -} - -PMemBlock mmAllocMem( memHeap_t *heap, int size, int align2, int startSearch) -{ - int mask,startofs, endofs; - TMemBlock *p; - - if (heap == NULL || align2 < 0 || size <= 0) - return NULL; - - mask = (1 << align2)-1; - startofs = 0; - p = (TMemBlock *)heap; - while (p != NULL) { - if (ISFREE(p)) { - startofs = (p->ofs + mask) & ~mask; - if ( startofs < startSearch ) { - startofs = startSearch; - } - endofs = startofs+size; - if (endofs <= (p->ofs+p->size)) - break; - } - p = p->next; - } - if (p == NULL) - return NULL; - p = SliceBlock(p,startofs,size,0,mask+1); - p->heap = heap; - return p; -} - -static __inline__ int Join2Blocks(TMemBlock *p) -{ - if (p->free && p->next && p->next->free) { - TMemBlock *q = p->next; - p->size += q->size; - p->next = q->next; - DRM(free)(q, sizeof(TMemBlock), DRM_MEM_DRIVER); - return 1; - } - return 0; -} - -int mmFreeMem(PMemBlock b) -{ - TMemBlock *p, *prev; - - if (b == NULL) - return 0; - if (b->heap == NULL) - return -1; - - p = b->heap; - prev = NULL; - while (p != NULL && p != b) { - prev = p; - p = p->next; - } - if (p == NULL || p->free || p->reserved) - return -1; - - p->free = 1; - Join2Blocks(p); - if (prev) - Join2Blocks(prev); - return 0; -} - -int mmReserveMem(memHeap_t *heap, int offset,int size) -{ - int endofs; - TMemBlock *p; - - if (heap == NULL || size <= 0) - return -1; - - endofs = offset + size; - p = (TMemBlock *)heap; - while (p && p->ofs <= offset) { - if (ISFREE(p) && endofs <= (p->ofs+p->size)) { - SliceBlock(p,offset,size,1,1); - return 0; - } - p = p->next; - } - return -1; -} - -int mmFreeReserved(memHeap_t *heap, int offset) -{ - TMemBlock *p,*prev; - - if (heap == NULL) - return -1; - - p = (TMemBlock *)heap; - prev = NULL; - while (p != NULL && p->ofs != offset) { - prev = p; - p = p->next; - } - if (p == NULL || !p->reserved) - return -1; - - p->free = 1; - p->reserved = 0; - Join2Blocks(p); - if (prev != NULL) - Join2Blocks(prev); - return 0; -} - -void mmDestroy(memHeap_t *heap) -{ - TMemBlock *p,*q; - - if (heap == NULL) - return; - - p = (TMemBlock *)heap; - while (p != NULL) { - q = p->next; - DRM(free)(p, sizeof(TMemBlock), DRM_MEM_DRIVER); - p = q; - } -} diff --git a/nx-X11/extras/drm/shared/sis_ds.h b/nx-X11/extras/drm/shared/sis_ds.h deleted file mode 100644 index 8d33f87ba..000000000 --- a/nx-X11/extras/drm/shared/sis_ds.h +++ /dev/null @@ -1,164 +0,0 @@ -/* sis_ds.h -- Private header for Direct Rendering Manager -*- linux-c -*- - * Created: Mon Jan 4 10:05:05 1999 by sclin@sis.com.tw - * - * Copyright 2000 Silicon Integrated Systems Corp, Inc., HsinChu, Taiwan. - * All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Sung-Ching Lin - * - */ - -#ifndef __SIS_DS_H__ -#define __SIS_DS_H__ - -/* Set Data Structure */ - -#define SET_SIZE 5000 - -typedef unsigned long ITEM_TYPE; - -typedef struct { - ITEM_TYPE val; - int alloc_next, free_next; -} list_item_t; - -typedef struct { - int alloc; - int free; - int trace; - list_item_t list[SET_SIZE]; -} set_t; - -set_t *setInit(void); -int setAdd(set_t *set, ITEM_TYPE item); -int setDel(set_t *set, ITEM_TYPE item); -int setFirst(set_t *set, ITEM_TYPE *item); -int setNext(set_t *set, ITEM_TYPE *item); -int setDestroy(set_t *set); - -/* - * GLX Hardware Device Driver common code - * Copyright (C) 1999 Wittawat Yamwong - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * KEITH WHITWELL, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE - * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -struct mem_block_t { - struct mem_block_t *next; - struct mem_block_t *heap; - int ofs,size; - int align; - unsigned int free:1; - unsigned int reserved:1; -}; -typedef struct mem_block_t TMemBlock; -typedef struct mem_block_t *PMemBlock; - -/* a heap is just the first block in a chain */ -typedef struct mem_block_t memHeap_t; - -static __inline__ int mmBlockSize(PMemBlock b) -{ - return b->size; -} - -static __inline__ int mmOffset(PMemBlock b) -{ - return b->ofs; -} - -static __inline__ void mmMarkReserved(PMemBlock b) -{ - b->reserved = 1; -} - -/* - * input: total size in bytes - * return: a heap pointer if OK, NULL if error - */ -memHeap_t *mmInit( int ofs, int size ); - -memHeap_t *mmAddRange( memHeap_t *heap, - int ofs, - int size ); - -/* - * Allocate 'size' bytes with 2^align2 bytes alignment, - * restrict the search to free memory after 'startSearch' - * depth and back buffers should be in different 4mb banks - * to get better page hits if possible - * input: size = size of block - * align2 = 2^align2 bytes alignment - * startSearch = linear offset from start of heap to begin search - * return: pointer to the allocated block, 0 if error - */ -PMemBlock mmAllocMem( memHeap_t *heap, int size, int align2, int startSearch ); - -/* - * Returns 1 if the block 'b' is part of the heap 'heap' - */ -int mmBlockInHeap( PMemBlock heap, PMemBlock b ); - -/* - * Free block starts at offset - * input: pointer to a block - * return: 0 if OK, -1 if error - */ -int mmFreeMem( PMemBlock b ); - -/* - * Reserve 'size' bytes block start at offset - * This is used to prevent allocation of memory already used - * by the X server for the front buffer, pixmaps, and cursor - * input: size, offset - * output: 0 if OK, -1 if error - */ -int mmReserveMem( memHeap_t *heap, int offset,int size ); -int mmFreeReserved( memHeap_t *heap, int offset ); - -/* - * destroy MM - */ -void mmDestroy( memHeap_t *mmInit ); - -/* For debuging purpose. */ -void mmDumpMemInfo( memHeap_t *mmInit ); - -#endif /* __SIS_DS_H__ */ diff --git a/nx-X11/extras/drm/shared/sis_mm.c b/nx-X11/extras/drm/shared/sis_mm.c deleted file mode 100644 index 27b904fc7..000000000 --- a/nx-X11/extras/drm/shared/sis_mm.c +++ /dev/null @@ -1,417 +0,0 @@ -/* sis_mm.c -- Private header for Direct Rendering Manager -*- linux-c -*- - * Created: Mon Jan 4 10:05:05 1999 by sclin@sis.com.tw - * - * Copyright 2000 Silicon Integrated Systems Corp, Inc., HsinChu, Taiwan. - * All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * Sung-Ching Lin - * - */ - -#include "sis.h" -#include "drmP.h" -#include "sis_drm.h" -#include "sis_drv.h" -#include "sis_ds.h" -#if defined(__linux__) && defined(CONFIG_FB_SIS) -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) -#include