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| author | marha <marha@users.sourceforge.net> | 2013-04-08 08:17:23 +0200 |
|---|---|---|
| committer | marha <marha@users.sourceforge.net> | 2013-04-08 08:17:23 +0200 |
| commit | 95fb19d661154ba8cfc6c793a0daa25657294b3b (patch) | |
| tree | 4abbb540731ff40c75c4a4282670dba886e60cd7 /mesalib/src/mesa/state_tracker/st_glsl_to_tgsi.cpp | |
| parent | 176eab9e8277db1549bfc6c9ae805c4e1858f0b0 (diff) | |
| download | vcxsrv-95fb19d661154ba8cfc6c793a0daa25657294b3b.tar.gz vcxsrv-95fb19d661154ba8cfc6c793a0daa25657294b3b.tar.bz2 vcxsrv-95fb19d661154ba8cfc6c793a0daa25657294b3b.zip | |
fontconfig libXau mesa xserver xkeyboard-config git update 8 Apr 2013
xserver commit 8928f8fa0bb154ce437af703ff702016f0dcf127
xkeyboard-config commit e5c6729f3679fe87a703eb1d7ec1cf0a61814ca8
libXau commit f5a57d8a21a34d7084cce294e24c0422e02ef8ef
fontconfig commit 18bf57c70aafcad031c0b43756b754dcaf6a756a
mesa commit eff66bc9f855fff5c4f5f57f247254a97431e8ad
Diffstat (limited to 'mesalib/src/mesa/state_tracker/st_glsl_to_tgsi.cpp')
| -rw-r--r-- | mesalib/src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/mesalib/src/mesa/state_tracker/st_glsl_to_tgsi.cpp b/mesalib/src/mesa/state_tracker/st_glsl_to_tgsi.cpp index e3718eeda..338c652cb 100644 --- a/mesalib/src/mesa/state_tracker/st_glsl_to_tgsi.cpp +++ b/mesalib/src/mesa/state_tracker/st_glsl_to_tgsi.cpp @@ -1009,7 +1009,9 @@ glsl_to_tgsi_visitor::get_temp(const glsl_type *type) src.reladdr = NULL; src.negate = 0; - if (type->is_array() || type->is_matrix()) { + if (!options->EmitNoIndirectTemp && + (type->is_array() || type->is_matrix())) { + src.file = PROGRAM_ARRAY; src.index = next_array << 16 | 0x8000; array_sizes[next_array] = type_size(type); @@ -2772,6 +2774,9 @@ glsl_to_tgsi_visitor::visit(ir_texture *ir) case ir_txf_ms: assert(!"Unexpected ir_txf_ms opcode"); break; + case ir_lod: + assert(!"Unexpected ir_lod opcode"); + break; } if (ir->projector) { @@ -3191,7 +3196,7 @@ glsl_to_tgsi_visitor::simplify_cmp(void) prevWriteMask = tempWrites[inst->dst.index]; tempWrites[inst->dst.index] |= inst->dst.writemask; } else - break; + continue; /* For a CMP to be considered a conditional write, the destination * register and source register two must be the same. */ |