Checked in the following released items:

xkeyboard-config-1.4.tar.gz ttf-bitstream-vera-1.10.tar.gz font-alias-1.0.1.tar.gz font-sun-misc-1.0.0.tar.gz font-sun-misc-1.0.0.tar.gz font-sony-misc-1.0.0.tar.gz font-schumacher-misc-1.0.0.tar.gz font-mutt-misc-1.0.0.tar.gz font-misc-misc-1.0.0.tar.gz font-misc-meltho-1.0.0.tar.gz font-micro-misc-1.0.0.tar.gz font-jis-misc-1.0.0.tar.gz font-isas-misc-1.0.0.tar.gz font-dec-misc-1.0.0.tar.gz font-daewoo-misc-1.0.0.tar.gz font-cursor-misc-1.0.0.tar.gz font-arabic-misc-1.0.0.tar.gz font-winitzki-cyrillic-1.0.0.tar.gz font-misc-cyrillic-1.0.0.tar.gz font-cronyx-cyrillic-1.0.0.tar.gz font-screen-cyrillic-1.0.1.tar.gz font-xfree86-type1-1.0.1.tar.gz font-adobe-utopia-type1-1.0.1.tar.gz font-ibm-type1-1.0.0.tar.gz font-bitstream-type1-1.0.0.tar.gz font-bitstream-speedo-1.0.0.tar.gz font-bh-ttf-1.0.0.tar.gz font-bh-type1-1.0.0.tar.gz font-bitstream-100dpi-1.0.0.tar.gz font-bh-lucidatypewriter-100dpi-1.0.0.tar.gz font-bh-100dpi-1.0.0.tar.gz font-adobe-utopia-100dpi-1.0.1.tar.gz font-adobe-100dpi-1.0.0.tar.gz font-util-1.0.1.tar.gz font-bitstream-75dpi-1.0.0.tar.gz font-bh-lucidatypewriter-75dpi-1.0.0.tar.gz font-adobe-utopia-75dpi-1.0.1.tar.gz font-bh-75dpi-1.0.0.tar.gz bdftopcf-1.0.1.tar.gz font-adobe-75dpi-1.0.0.tar.gz mkfontscale-1.0.6.tar.gz openssl-0.9.8k.tar.gz bigreqsproto-1.0.2.tar.gz xtrans-1.2.2.tar.gz resourceproto-1.0.2.tar.gz inputproto-1.4.4.tar.gz compositeproto-0.4.tar.gz damageproto-1.1.0.tar.gz zlib-1.2.3.tar.gz xkbcomp-1.0.5.tar.gz freetype-2.3.9.tar.gz pthreads-w32-2-8-0-release.tar.gz pixman-0.12.0.tar.gz kbproto-1.0.3.tar.gz evieext-1.0.2.tar.gz fixesproto-4.0.tar.gz recordproto-1.13.2.tar.gz randrproto-1.2.2.tar.gz scrnsaverproto-1.1.0.tar.gz renderproto-0.9.3.tar.gz xcmiscproto-1.1.2.tar.gz fontsproto-2.0.2.tar.gz xextproto-7.0.3.tar.gz xproto-7.0.14.tar.gz libXdmcp-1.0.2.tar.gz libxkbfile-1.0.5.tar.gz libfontenc-1.0.4.tar.gz libXfont-1.3.4.tar.gz libX11-1.1.5.tar.gz libXau-1.0.4.tar.gz libxcb-1.1.tar.gz xorg-server-1.5.3.tar.gz
author: marha <marha@users.sourceforge.net> 2009-06-28 22:07:26 +0000
committer: marha <marha@users.sourceforge.net> 2009-06-28 22:07:26 +0000
commit: 3562e78743202e43aec8727005182a2558117eca (patch)
tree: 8f9113a77d12470c5c851a2a8e4cb02e89df7d43 /xorg-server/hw/xfree86/os-support/bus
download: vcxsrv-3562e78743202e43aec8727005182a2558117eca.tar.gz
vcxsrv-3562e78743202e43aec8727005182a2558117eca.tar.bz2
vcxsrv-3562e78743202e43aec8727005182a2558117eca.zip
12 files changed, 4646 insertions, 0 deletions
diff --git a/xorg-server/hw/xfree86/os-support/bus/Makefile.am b/xorg-server/hw/xfree86/os-support/bus/Makefile.am
new file mode 100644
index 000000000..d48fcb67d
--- /dev/null
+++ b/xorg-server/hw/xfree86/os-support/bus/Makefile.am
@@ -0,0 +1,38 @@
+noinst_LTLIBRARIES = libbus.la
+sdk_HEADERS = xf86Pci.h
+
+PCI_SOURCES =
+
+if XORG_BUS_LINUXPCI
+PCI_SOURCES += linuxPci.c
+endif
+
+if XORG_BUS_BSDPCI
+PCI_SOURCES += bsd_pci.c
+endif
+
+if XORG_BUS_IX86PCI
+PCI_SOURCES += ix86Pci.c
+endif
+
+if XORG_BUS_PPCPCI
+PCI_SOURCES += ppcPci.c
+endif
+
+if XORG_BUS_SPARCPCI
+PCI_SOURCES += sparcPci.c
+endif
+
+if XORG_BUS_SPARC
+PLATFORM_SOURCES = Sbus.c
+sdk_HEADERS += xf86Sbus.h
+endif
+
+libbus_la_SOURCES = Pci.c Pci.h $(PCI_SOURCES) $(PLATFORM_PCI_SOURCES) \
+                    $(PLATFORM_SOURCES)
+
+INCLUDES = $(XORG_INCS)
+
+AM_CFLAGS = $(XORG_CFLAGS) $(DIX_CFLAGS)
+
+EXTRA_DIST = $(sdk_HEADERS)
diff --git a/xorg-server/hw/xfree86/os-support/bus/Makefile.in b/xorg-server/hw/xfree86/os-support/bus/Makefile.in
new file mode 100644
index 000000000..fb2391280
--- /dev/null
+++ b/xorg-server/hw/xfree86/os-support/bus/Makefile.in
@@ -0,0 +1,705 @@
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+# @configure_input@
+
+# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+# 2003, 2004, 2005, 2006, 2007, 2008  Free Software Foundation, Inc.
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
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+
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+@XORG_BUS_PPCPCI_TRUE@am__append_4 = ppcPci.c
+@XORG_BUS_SPARCPCI_TRUE@am__append_5 = sparcPci.c
+@XORG_BUS_SPARC_TRUE@am__append_6 = xf86Sbus.h
+subdir = hw/xfree86/os-support/bus
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+	$(top_builddir)/include/xorg-server.h \
+	$(top_builddir)/include/dix-config.h \
+	$(top_builddir)/include/xgl-config.h \
+	$(top_builddir)/include/xorg-config.h \
+	$(top_builddir)/include/xkb-config.h \
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+                    $(PLATFORM_SOURCES)
+
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+	  case '$(am__configure_deps)' in \
+	    *$$dep*) \
+	      cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh \
+		&& exit 0; \
+	      exit 1;; \
+	  esac; \
+	done; \
+	echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign  hw/xfree86/os-support/bus/Makefile'; \
+	cd $(top_srcdir) && \
+	  $(AUTOMAKE) --foreign  hw/xfree86/os-support/bus/Makefile
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+	    echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
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+	cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
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+	cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+clean-noinstLTLIBRARIES:
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+	@list='$(noinst_LTLIBRARIES)'; for p in $$list; do \
+	  dir="`echo $$p | sed -e 's|/[^/]*$$||'`"; \
+	  test "$$dir" != "$$p" || dir=.; \
+	  echo "rm -f \"$${dir}/so_locations\""; \
+	  rm -f "$${dir}/so_locations"; \
+	done
+libbus.la: $(libbus_la_OBJECTS) $(libbus_la_DEPENDENCIES) 
+	$(LINK)  $(libbus_la_OBJECTS) $(libbus_la_LIBADD) $(LIBS)
+
+mostlyclean-compile:
+	-rm -f *.$(OBJEXT)
+
+distclean-compile:
+	-rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/Pci.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/Sbus.Plo@am__quote@
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+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sparcPci.Plo@am__quote@
+
+.c.o:
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+	-rm -f *.lo
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+clean-libtool:
+	-rm -rf .libs _libs
+install-sdkHEADERS: $(sdk_HEADERS)
+	@$(NORMAL_INSTALL)
+	test -z "$(sdkdir)" || $(MKDIR_P) "$(DESTDIR)$(sdkdir)"
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+	done
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+	@$(NORMAL_UNINSTALL)
+	@list='$(sdk_HEADERS)'; for p in $$list; do \
+	  f=$(am__strip_dir) \
+	  echo " rm -f '$(DESTDIR)$(sdkdir)/$$f'"; \
+	  rm -f "$(DESTDIR)$(sdkdir)/$$f"; \
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+	mkid -fID $$unique
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+	    $$tags $$unique; \
+	fi
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+		$(TAGS_FILES) $(LISP)
+	tags=; \
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+	    echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install
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+distclean-generic:
+	-test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
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+	@echo "This command is intended for maintainers to use"
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+# Tell versions [3.59,3.63) of GNU make to not export all variables.
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diff --git a/xorg-server/hw/xfree86/os-support/bus/Pci.c b/xorg-server/hw/xfree86/os-support/bus/Pci.c
new file mode 100644
index 000000000..064533c77
--- /dev/null
+++ b/xorg-server/hw/xfree86/os-support/bus/Pci.c
@@ -0,0 +1,193 @@
+/*
+ * Copyright 1998 by Concurrent Computer Corporation
+ *
+ * Permission to use, copy, modify, distribute, and sell this software
+ * and its documentation for any purpose is hereby granted without fee,
+ * provided that the above copyright notice appear in all copies and that
+ * both that copyright notice and this permission notice appear in
+ * supporting documentation, and that the name of Concurrent Computer
+ * Corporation not be used in advertising or publicity pertaining to
+ * distribution of the software without specific, written prior
+ * permission.  Concurrent Computer Corporation makes no representations
+ * about the suitability of this software for any purpose.  It is
+ * provided "as is" without express or implied warranty.
+ *
+ * CONCURRENT COMPUTER CORPORATION DISCLAIMS ALL WARRANTIES WITH REGARD
+ * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL CONCURRENT COMPUTER CORPORATION BE
+ * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY
+ * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
+ * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,
+ * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS
+ * SOFTWARE.
+ *
+ * Copyright 1998 by Metro Link Incorporated
+ *
+ * Permission to use, copy, modify, distribute, and sell this software
+ * and its documentation for any purpose is hereby granted without fee,
+ * provided that the above copyright notice appear in all copies and that
+ * both that copyright notice and this permission notice appear in
+ * supporting documentation, and that the name of Metro Link
+ * Incorporated not be used in advertising or publicity pertaining to
+ * distribution of the software without specific, written prior
+ * permission.  Metro Link Incorporated makes no representations
+ * about the suitability of this software for any purpose.  It is
+ * provided "as is" without express or implied warranty.
+ *
+ * METRO LINK INCORPORATED DISCLAIMS ALL WARRANTIES WITH REGARD
+ * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL METRO LINK INCORPORATED BE
+ * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY
+ * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
+ * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,
+ * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS
+ * SOFTWARE.
+ *
+ * This software is derived from the original XFree86 PCI code
+ * which includes the following copyright notices as well:
+ *
+ * Copyright 1995 by Robin Cutshaw <robin@XFree86.Org>
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that
+ * copyright notice and this permission notice appear in supporting
+ * documentation, and that the names of the above listed copyright holder(s)
+ * not be used in advertising or publicity pertaining to distribution of
+ * the software without specific, written prior permission.  The above listed
+ * copyright holder(s) make(s) no representations about the suitability of this
+ * software for any purpose.  It is provided "as is" without express or
+ * implied warranty.
+ *
+ * THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM(S) ALL WARRANTIES WITH REGARD
+ * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE
+ * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY
+ * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER
+ * IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * This code is also based heavily on the code in FreeBSD-current, which was
+ * written by Wolfgang Stanglmeier, and contains the following copyright:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+/*
+ * Copyright (c) 1999-2003 by The XFree86 Project, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of the copyright holder(s)
+ * and author(s) shall not be used in advertising or otherwise to promote
+ * the sale, use or other dealings in this Software without prior written
+ * authorization from the copyright holder(s) and author(s).
+ */
+
+#ifdef HAVE_XORG_CONFIG_H
+#include <xorg-config.h>
+#endif
+
+#include <errno.h>
+#include <signal.h>
+#include <X11/Xarch.h>
+#include "compiler.h"
+#include "xf86.h"
+#include "xf86Priv.h"
+#define XF86_OS_PRIVS
+#include "xf86_OSproc.h"
+#include "Pci.h"
+
+#include <pciaccess.h>
+
+#define PCI_MFDEV_SUPPORT   1 /* Include PCI multifunction device support */
+#define PCI_BRIDGE_SUPPORT  1 /* Include support for PCI-to-PCI bridges */
+
+/*
+ * Global data
+ */
+
+pciBusInfo_t  *pciBusInfo[MAX_PCI_BUSES] = { NULL, };
+_X_EXPORT int            pciNumBuses = 0;     /* Actual number of PCI buses */
+int            pciMaxBusNum = MAX_PCI_BUSES;
+
+
+_X_EXPORT ADDRESS
+pciBusAddrToHostAddr(PCITAG tag, PciAddrType type, ADDRESS addr)
+{
+  int bus = PCI_BUS_FROM_TAG(tag);
+
+  if ((bus >= 0) && (bus < pciNumBuses) && pciBusInfo[bus] &&
+	pciBusInfo[bus]->funcs->pciAddrBusToHost)
+	  return (*pciBusInfo[bus]->funcs->pciAddrBusToHost)(tag, type, addr);
+  else
+	  return(addr);
+}
+
+_X_EXPORT PCITAG
+pciTag(int busnum, int devnum, int funcnum)
+{
+	return(PCI_MAKE_TAG(busnum,devnum,funcnum));
+}
+
+ADDRESS
+pciAddrNOOP(PCITAG tag, PciAddrType type, ADDRESS addr)
+{
+	return(addr);
+}
+
+_X_EXPORT Bool
+xf86scanpci(void)
+{
+    Bool  success = FALSE;
+
+    success = (pci_system_init() == 0);
+
+	/* XXX */
+#if defined(DEBUGPCI)
+	if (DEBUGPCI >= xf86Verbose) {
+	    xf86Verbose = DEBUGPCI;
+	}
+#endif
+
+    /* choose correct platform/OS specific PCI init routine */
+	ARCH_PCI_INIT();
+
+    return success;
+}
diff --git a/xorg-server/hw/xfree86/os-support/bus/Pci.h b/xorg-server/hw/xfree86/os-support/bus/Pci.h
new file mode 100644
index 000000000..557483b9b
--- /dev/null
+++ b/xorg-server/hw/xfree86/os-support/bus/Pci.h
@@ -0,0 +1,269 @@
+/*
+ * Copyright 1998 by Concurrent Computer Corporation
+ *
+ * Permission to use, copy, modify, distribute, and sell this software
+ * and its documentation for any purpose is hereby granted without fee,
+ * provided that the above copyright notice appear in all copies and that
+ * both that copyright notice and this permission notice appear in
+ * supporting documentation, and that the name of Concurrent Computer
+ * Corporation not be used in advertising or publicity pertaining to
+ * distribution of the software without specific, written prior
+ * permission.  Concurrent Computer Corporation makes no representations
+ * about the suitability of this software for any purpose.  It is
+ * provided "as is" without express or implied warranty.
+ *
+ * CONCURRENT COMPUTER CORPORATION DISCLAIMS ALL WARRANTIES WITH REGARD
+ * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL CONCURRENT COMPUTER CORPORATION BE
+ * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY
+ * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
+ * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,
+ * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS
+ * SOFTWARE.
+ *
+ * Copyright 1998 by Metro Link Incorporated
+ *
+ * Permission to use, copy, modify, distribute, and sell this software
+ * and its documentation for any purpose is hereby granted without fee,
+ * provided that the above copyright notice appear in all copies and that
+ * both that copyright notice and this permission notice appear in
+ * supporting documentation, and that the name of Metro Link
+ * Incorporated not be used in advertising or publicity pertaining to
+ * distribution of the software without specific, written prior
+ * permission.  Metro Link Incorporated makes no representations
+ * about the suitability of this software for any purpose.  It is
+ * provided "as is" without express or implied warranty.
+ *
+ * METRO LINK INCORPORATED DISCLAIMS ALL WARRANTIES WITH REGARD
+ * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL METRO LINK INCORPORATED BE
+ * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY
+ * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
+ * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,
+ * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS
+ * SOFTWARE.
+ *
+ * This file is derived in part from the original xf86_PCI.h that included
+ * following copyright message:
+ *
+ * Copyright 1995 by Robin Cutshaw <robin@XFree86.Org>
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that
+ * copyright notice and this permission notice appear in supporting
+ * documentation, and that the names of the above listed copyright holder(s)
+ * not be used in advertising or publicity pertaining to distribution of
+ * the software without specific, written prior permission.  The above listed
+ * copyright holder(s) make(s) no representations about the suitability of this
+ * software for any purpose.  It is provided "as is" without express or
+ * implied warranty.
+ *
+ * THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM(S) ALL WARRANTIES WITH REGARD
+ * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE
+ * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY
+ * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER
+ * IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+/*
+ * Copyright (c) 1999-2003 by The XFree86 Project, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of the copyright holder(s)
+ * and author(s) shall not be used in advertising or otherwise to promote
+ * the sale, use or other dealings in this Software without prior written
+ * authorization from the copyright holder(s) and author(s).
+ */
+
+
+/*
+ * This file has the private Pci definitions.  The public ones are imported
+ * from xf86Pci.h.  Drivers should not use this file.
+ */
+#ifdef HAVE_XORG_CONFIG_H
+#include <xorg-config.h>
+#endif
+
+#ifndef _PCI_H
+#define _PCI_H 1
+
+#include <X11/Xarch.h>
+#include <X11/Xfuncproto.h>
+#include "xf86Pci.h"
+#include "xf86PciInfo.h"
+
+/*
+ * Global Definitions
+ */
+#define MAX_PCI_DEVICES 128	/* Max number of devices accomodated */
+				/* by xf86scanpci		     */
+#if defined(sun) && defined(SVR4) && defined(sparc)
+# define MAX_PCI_BUSES   4096	/* Max number of PCI buses           */
+#elif (defined(__alpha__) || defined(__ia64__)) && defined (linux)
+# define MAX_PCI_DOMAINS	512
+# define PCI_DOM_MASK	0x01fful
+# define MAX_PCI_BUSES	(MAX_PCI_DOMAINS*256) /* 256 per domain      */
+#else
+# define MAX_PCI_BUSES   256	/* Max number of PCI buses           */
+#endif
+
+#define DEVID(vendor, device) \
+    ((CARD32)((PCI_##device << 16) | PCI_##vendor))
+
+#ifndef PCI_DOM_MASK
+# define PCI_DOM_MASK 0x0ffu
+#endif
+#define PCI_DOMBUS_MASK (((PCI_DOM_MASK) << 8) | 0x0ffu)
+
+/*
+ * "b" contains an optional domain number.
+ */
+#define PCI_MAKE_TAG(b,d,f)  ((((b) & (PCI_DOMBUS_MASK)) << 16) | \
+			      (((d) & 0x00001fu) << 11) | \
+			      (((f) & 0x000007u) << 8))
+
+#define PCI_MAKE_BUS(d,b)    ((((d) & (PCI_DOM_MASK)) << 8) | ((b) & 0xffu))
+
+#define PCI_DOM_FROM_TAG(tag)  (((tag) >> 24) & (PCI_DOM_MASK))
+#define PCI_BUS_FROM_TAG(tag)  (((tag) >> 16) & (PCI_DOMBUS_MASK))
+#define PCI_DEV_FROM_TAG(tag)  (((tag) & 0x0000f800u) >> 11)
+#define PCI_FUNC_FROM_TAG(tag) (((tag) & 0x00000700u) >> 8)
+
+#define PCI_DFN_FROM_TAG(tag)  (((tag) & 0x0000ff00u) >> 8)
+#define PCI_BDEV_FROM_TAG(tag) ((tag) & 0x00fff800u)
+
+#define PCI_DOM_FROM_BUS(bus)  (((bus) >> 8) & (PCI_DOM_MASK))
+#define PCI_BUS_NO_DOMAIN(bus) ((bus) & 0xffu)
+#define PCI_TAG_NO_DOMAIN(tag) ((tag) & 0x00ffff00u)
+
+/*
+ * Debug Macros/Definitions
+ */
+/* #define DEBUGPCI  2 */    /* Disable/enable trace in PCI code */
+
+#if defined(DEBUGPCI)
+
+# define PCITRACE(lvl,printfargs) \
+	if (lvl > xf86Verbose) { \
+		ErrorF printfargs; \
+	}
+
+#else /* !defined(DEBUGPCI) */
+
+# define PCITRACE(lvl,printfargs)
+
+#endif /* !defined(DEBUGPCI) */
+
+/*
+ * PCI Config mechanism definitions
+ */
+#define PCI_EN 0x80000000
+
+#define	PCI_CFGMECH1_ADDRESS_REG	0xCF8
+#define	PCI_CFGMECH1_DATA_REG		0xCFC
+
+#define PCI_CFGMECH1_MAXDEV	32
+
+#if defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__NetBSD__) || \
+	defined(__DragonFly__)
+#define ARCH_PCI_INIT bsdPciInit
+#endif
+
+#if defined(linux)
+# define ARCH_PCI_INIT linuxPciInit
+# if defined(__m32r__)
+#  define INCLUDE_XF86_MAP_PCI_MEM
+#  define INCLUDE_XF86_NO_DOMAIN
+# endif
+#endif /* defined(linux) */
+
+
+#if !defined(ARCH_PCI_INIT)
+/*
+ * Select architecture specific PCI init function
+ */
+#if defined(__i386__) || defined(__i386) ||  defined(__amd64__) || defined(__amd64) || defined(__x86_64__)
+# define ARCH_PCI_INIT ix86PciInit
+#elif defined(__powerpc__) || defined(__powerpc64__)
+# define ARCH_PCI_INIT ppcPciInit
+#elif defined(__sparc__) || defined(sparc)
+# define ARCH_PCI_INIT sparcPciInit
+# define ARCH_PCI_PCI_BRIDGE sparcPciPciBridge
+#endif
+#endif /* !defined(ARCH_PCI_INIT) */
+
+#ifndef ARCH_PCI_INIT
+#error No PCI support available for this architecture/OS combination
+#endif
+
+extern void ARCH_PCI_INIT(void);
+
+#if defined(XF86SCANPCI_WRAPPER)
+typedef enum {
+    SCANPCI_INIT,
+    SCANPCI_TERM
+} scanpciWrapperOpt;
+extern void XF86SCANPCI_WRAPPER(scanpciWrapperOpt flags);
+#endif
+
+/*
+ * Table of functions used to access a specific PCI bus domain
+ * (e.g. a primary PCI bus and all of its secondaries)
+ */
+typedef struct pci_bus_funcs {
+	ADDRESS (*pciAddrBusToHost)(PCITAG, PciAddrType, ADDRESS);
+} pciBusFuncs_t, *pciBusFuncs_p;
+
+/*
+ * pciBusInfo_t - One structure per defined PCI bus
+ */
+typedef struct pci_bus_info {
+	unsigned char  configMech;   /* PCI config type to use      */
+	unsigned char  numDevices;   /* Range of valid devnums      */
+	unsigned char  secondary;    /* Boolean: bus is a secondary */
+	int            primary_bus;  /* Parent bus                  */
+	pciBusFuncs_p  funcs;        /* PCI access functions        */
+	void          *pciBusPriv;   /* Implementation private data */
+	struct pci_device *bridge;       /* bridge that opens this bus  */
+} pciBusInfo_t;
+
+#define HOST_NO_BUS ((pciBusInfo_t *)(-1))
+
+/* configMech values */
+#define PCI_CFG_MECH_UNKNOWN 0 /* Not yet known  */
+#define PCI_CFG_MECH_1       1 /* Most machines  */
+#define PCI_CFG_MECH_2       2 /* Older PC's     */
+#define PCI_CFG_MECH_OTHER   3 /* Something else */
+
+/* Generic PCI service functions and helpers */
+CARD32        pciCfgMech1Read(PCITAG tag, int offset);
+void          pciCfgMech1Write(PCITAG tag, int offset, CARD32 val);
+void          pciCfgMech1SetBits(PCITAG tag, int offset, CARD32 mask,
+				 CARD32 val);
+ADDRESS       pciAddrNOOP(PCITAG tag, PciAddrType type, ADDRESS);
+
+extern int    pciMaxBusNum;
+
+extern pciBusInfo_t  *pciBusInfo[];
+
+#endif /* _PCI_H */
diff --git a/xorg-server/hw/xfree86/os-support/bus/Sbus.c b/xorg-server/hw/xfree86/os-support/bus/Sbus.c
new file mode 100644
index 000000000..ff257a8c7
--- /dev/null
+++ b/xorg-server/hw/xfree86/os-support/bus/Sbus.c
@@ -0,0 +1,636 @@
+/*
+ * SBUS and OpenPROM access functions.
+ *
+ * Copyright (C) 2000 Jakub Jelinek (jakub@redhat.com)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * JAKUB JELINEK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifdef HAVE_XORG_CONFIG_H
+#include <xorg-config.h>
+#endif
+
+#include <fcntl.h>
+#include <stdio.h>
+#include <unistd.h>
+#include <stdlib.h>
+#include <sys/ioctl.h>
+#include <sys/mman.h>
+#ifdef sun
+#include <sys/utsname.h>
+#endif
+#include "xf86.h"
+#include "xf86Priv.h"
+#include "xf86_OSlib.h"
+
+#include "xf86sbusBus.h"
+#include "xf86Sbus.h"
+
+int promRootNode;
+
+static int promFd = -1;
+static int promCurrentNode;
+static int promOpenCount = 0;
+static int promP1275 = -1;
+#define MAX_PROP	128
+#define MAX_VAL		(4096-128-4)
+static struct openpromio *promOpio;
+
+sbusDevicePtr *xf86SbusInfo = NULL;
+
+struct sbus_devtable sbusDeviceTable[] = {
+    { SBUS_DEVICE_BW2, FBTYPE_SUN2BW, "bwtwo", "Sun Monochrome (bwtwo)" },
+    { SBUS_DEVICE_CG2, FBTYPE_SUN2COLOR, "cgtwo", "Sun Color2 (cgtwo)" },
+    { SBUS_DEVICE_CG3, FBTYPE_SUN3COLOR, "cgthree", "Sun Color3 (cgthree)" },
+    { SBUS_DEVICE_CG4, FBTYPE_SUN4COLOR, "cgfour", "Sun Color4 (cgfour)" },
+    { SBUS_DEVICE_CG6, FBTYPE_SUNFAST_COLOR, "cgsix", "Sun GX" },
+    { SBUS_DEVICE_CG8, FBTYPE_MEMCOLOR, "cgeight", "Sun CG8/RasterOps" },
+    { SBUS_DEVICE_CG12, FBTYPE_SUNGP3, "cgtwelve", "Sun GS (cgtwelve)" },
+    { SBUS_DEVICE_CG14, FBTYPE_MDICOLOR, "cgfourteen", "Sun SX" },
+    { SBUS_DEVICE_GT, FBTYPE_SUNGT, "gt", "Sun Graphics Tower" },
+    { SBUS_DEVICE_MGX, -1, "mgx", "Quantum 3D MGXplus" },
+    { SBUS_DEVICE_LEO, FBTYPE_SUNLEO, "leo", "Sun ZX or Turbo ZX" },
+    { SBUS_DEVICE_TCX, FBTYPE_TCXCOLOR, "tcx", "Sun TCX" },
+    { SBUS_DEVICE_FFB, FBTYPE_CREATOR, "ffb", "Sun FFB" },
+    { SBUS_DEVICE_FFB, FBTYPE_CREATOR, "afb", "Sun Elite3D" },
+    { 0, 0, NULL }
+};
+
+int
+promGetSibling(int node)
+{
+    promOpio->oprom_size = sizeof(int);
+
+    if (node == -1) return 0;
+    *(int *)promOpio->oprom_array = node;
+    if (ioctl(promFd, OPROMNEXT, promOpio) < 0)
+	return 0;
+    promCurrentNode = *(int *)promOpio->oprom_array;
+    return *(int *)promOpio->oprom_array;
+}
+
+int
+promGetChild(int node)
+{
+    promOpio->oprom_size = sizeof(int);
+
+    if (!node || node == -1) return 0;
+    *(int *)promOpio->oprom_array = node;
+    if (ioctl(promFd, OPROMCHILD, promOpio) < 0)
+	return 0;
+    promCurrentNode = *(int *)promOpio->oprom_array;
+    return *(int *)promOpio->oprom_array;
+}
+
+char *
+promGetProperty(const char *prop, int *lenp)
+{
+    promOpio->oprom_size = MAX_VAL;
+
+    strcpy(promOpio->oprom_array, prop);
+    if (ioctl(promFd, OPROMGETPROP, promOpio) < 0)
+	return 0;
+    if (lenp) *lenp = promOpio->oprom_size;
+    return promOpio->oprom_array;
+}
+
+int
+promGetBool(const char *prop)
+{
+    promOpio->oprom_size = 0;
+
+    *(int *)promOpio->oprom_array = 0;
+    for (;;) {
+	promOpio->oprom_size = MAX_PROP;
+	if (ioctl(promFd, OPROMNXTPROP, promOpio) < 0)
+	    return 0;
+	if (!promOpio->oprom_size)
+	    return 0;
+	if (!strcmp(promOpio->oprom_array, prop))
+	    return 1;
+    }
+}
+
+#define PROM_NODE_SIBLING 0x01
+#define PROM_NODE_PREF    0x02
+#define PROM_NODE_SBUS    0x04
+#define PROM_NODE_EBUS    0x08
+#define PROM_NODE_PCI     0x10
+
+static int
+promSetNode(sbusPromNodePtr pnode)
+{
+    int node;
+
+    if (!pnode->node || pnode->node == -1)
+	return -1;
+    if (pnode->cookie[0] & PROM_NODE_SIBLING)
+	node = promGetSibling(pnode->cookie[1]);
+    else
+	node = promGetChild(pnode->cookie[1]);
+    if (pnode->node != node)
+	return -1;
+    return 0;
+}
+
+static void
+promIsP1275(void)
+{
+#ifdef linux
+    FILE *f;
+    char buffer[1024];
+
+    if (promP1275 != -1)
+	return;
+    promP1275 = 0;
+    f = fopen("/proc/cpuinfo","r");
+    if (!f) return;
+    while (fgets(buffer, 1024, f) != NULL)
+	if (!strncmp (buffer, "type", 4) && strstr (buffer, "sun4u")) {
+	    promP1275 = 1;
+	    break;
+	}
+    fclose(f);
+#elif defined(sun)
+    struct utsname buffer;
+
+    if ((uname(&buffer) >= 0) && !strcmp(buffer.machine, "sun4u"))
+	promP1275 = TRUE;
+    else
+	promP1275 = FALSE;
+#elif defined(__FreeBSD__)
+    promP1275 = TRUE;
+#else
+#error Missing promIsP1275() function for this OS
+#endif
+}
+
+_X_EXPORT void
+sparcPromClose(void)
+{
+    if (promOpenCount > 1) {
+	promOpenCount--;
+	return;
+    }
+    if (promFd != -1) {
+	close(promFd);
+	promFd = -1;
+    }
+    if (promOpio) {
+	xfree(promOpio);
+	promOpio = NULL;
+    }
+    promOpenCount = 0;
+}
+
+_X_EXPORT int
+sparcPromInit(void)
+{
+    if (promOpenCount) {
+	promOpenCount++;
+	return 0;
+    }
+    promFd = open("/dev/openprom", O_RDONLY, 0);
+    if (promFd == -1)
+	return -1;
+    promOpio = (struct openpromio *)xalloc(4096);
+    if (!promOpio) {
+	sparcPromClose();
+	return -1;
+    }
+    promRootNode = promGetSibling(0);
+    if (!promRootNode) {
+	sparcPromClose();
+	return -1;
+    }
+    promIsP1275();
+    promOpenCount++;
+
+    return 0;
+}
+
+_X_EXPORT char *
+sparcPromGetProperty(sbusPromNodePtr pnode, const char *prop, int *lenp)
+{
+    if (promSetNode(pnode))
+	return NULL;
+    return promGetProperty(prop, lenp);
+}
+
+_X_EXPORT int
+sparcPromGetBool(sbusPromNodePtr pnode, const char *prop)
+{
+    if (promSetNode(pnode))
+	return 0;
+    return promGetBool(prop);
+}
+
+static void
+promWalkAssignNodes(int node, int oldnode, int flags, sbusDevicePtr *devicePtrs)
+{
+    int nextnode;
+    int len, sbus = flags & PROM_NODE_SBUS;
+    char *prop;
+    int devId, i, j;
+    sbusPromNode pNode, pNode2;
+
+    prop = promGetProperty("device_type", &len);
+    if (prop && (len > 0)) do {
+	if (!strcmp(prop, "display")) {
+	    prop = promGetProperty("name", &len);
+	    if (!prop || len <= 0)
+		break;
+	    while ((*prop >= 'A' && *prop <= 'Z') || *prop == ',')
+		prop++;
+	    for (i = 0; sbusDeviceTable[i].devId; i++)
+		if (!strcmp(prop, sbusDeviceTable[i].promName))
+		    break;
+	    devId = sbusDeviceTable[i].devId;
+	    if (!devId)
+		break;
+	    if (!sbus) {
+		if (devId == SBUS_DEVICE_FFB) {
+		    /*
+		     * All /SUNW,ffb outside of SBUS tree come before all
+		     * /SUNW,afb outside of SBUS tree in Linux.
+		     */
+		    if (!strcmp(prop, "afb"))
+			flags |= PROM_NODE_PREF;
+		} else if (devId != SBUS_DEVICE_CG14)
+		    break;
+	    }
+	    for (i = 0; i < 32; i++) {
+		if (!devicePtrs[i] || devicePtrs[i]->devId != devId)
+		    continue;
+		if (devicePtrs[i]->node.node) {
+		    if ((devicePtrs[i]->node.cookie[0] & ~PROM_NODE_SIBLING) <=
+			(flags & ~PROM_NODE_SIBLING))
+			continue;
+		    for (j = i + 1, pNode = devicePtrs[i]->node; j < 32; j++) {
+			if (!devicePtrs[j] || devicePtrs[j]->devId != devId)
+			    continue;
+			pNode2 = devicePtrs[j]->node;
+			devicePtrs[j]->node = pNode;
+			pNode = pNode2;
+		    }
+		}
+		devicePtrs[i]->node.node = node;
+		devicePtrs[i]->node.cookie[0] = flags;
+		devicePtrs[i]->node.cookie[1] = oldnode;
+		break;
+	    }
+	    break;
+	}
+    } while (0);
+
+    prop = promGetProperty("name", &len);
+    if (prop && len > 0) {
+	if (!strcmp(prop, "sbus") || !strcmp(prop, "sbi"))
+	    sbus = PROM_NODE_SBUS;
+    }
+
+    nextnode = promGetChild(node);
+    if (nextnode)
+	promWalkAssignNodes(nextnode, node, sbus, devicePtrs);
+
+    nextnode = promGetSibling(node);
+    if (nextnode)
+	promWalkAssignNodes(nextnode, node, PROM_NODE_SIBLING | sbus, devicePtrs);
+}
+
+void
+sparcPromAssignNodes(void)
+{
+    sbusDevicePtr psdp, *psdpp;
+    int n, holes = 0, i, j;
+    FILE *f;
+    sbusDevicePtr devicePtrs[32];
+
+    (void)memset(devicePtrs, 0, sizeof(devicePtrs));
+    for (psdpp = xf86SbusInfo, n = 0; (psdp = *psdpp); psdpp++, n++) {
+	if (psdp->fbNum != n)
+	    holes = 1;
+	devicePtrs[psdp->fbNum] = psdp;
+    }
+    if (holes && (f = fopen("/proc/fb", "r")) != NULL) {
+	/* We could not open one of fb devices, check /proc/fb to see what
+	 * were the types of the cards missed. */
+	char buffer[64];
+	int fbNum, devId;
+	static struct {
+	    int devId;
+	    char *prefix;
+	} procFbPrefixes[] = {
+	    { SBUS_DEVICE_BW2, "BWtwo" },
+	    { SBUS_DEVICE_CG14, "CGfourteen" },
+	    { SBUS_DEVICE_CG6, "CGsix" },
+	    { SBUS_DEVICE_CG3, "CGthree" },
+	    { SBUS_DEVICE_FFB, "Creator" },
+	    { SBUS_DEVICE_FFB, "Elite 3D" },
+	    { SBUS_DEVICE_LEO, "Leo" },
+	    { SBUS_DEVICE_TCX, "TCX" },
+	    { 0, NULL },
+	};
+
+	while (fscanf(f, "%d %63s\n", &fbNum, buffer) == 2) {
+	    for (i = 0; procFbPrefixes[i].devId; i++)
+		if (! strncmp(procFbPrefixes[i].prefix, buffer,
+		      strlen(procFbPrefixes[i].prefix)))
+		    break;
+	    devId = procFbPrefixes[i].devId;
+	    if (! devId) continue;
+	    if (devicePtrs[fbNum]) {
+		if (devicePtrs[fbNum]->devId != devId)
+		    xf86ErrorF("Inconsistent /proc/fb with FBIOGATTR\n");
+	    } else if (!devicePtrs[fbNum]) {
+		devicePtrs[fbNum] = psdp = xnfcalloc(sizeof (sbusDevice), 1);
+		psdp->devId = devId;
+		psdp->fbNum = fbNum;
+		psdp->fd = -2;
+	    }
+	}
+	fclose(f);
+    }
+    promGetSibling(0);
+    promWalkAssignNodes(promRootNode, 0, PROM_NODE_PREF, devicePtrs);
+    for (i = 0, j = 0; i < 32; i++)
+	if (devicePtrs[i] && devicePtrs[i]->fbNum == -1)
+	    j++;
+    xf86SbusInfo = xnfrealloc(xf86SbusInfo, sizeof(psdp) * (n + j + 1));
+    for (i = 0, psdpp = xf86SbusInfo; i < 32; i++)
+	if (devicePtrs[i]) {
+	    if (devicePtrs[i]->fbNum == -1) {
+		memmove(psdpp + 1, psdpp, sizeof(psdpp) * (n + 1));
+		*psdpp = devicePtrs[i];
+	    } else
+		n--;
+	}
+}
+
+static char *
+promGetReg(int type)
+{
+    char *prop;
+    int len;
+    static char regstr[40];
+
+    regstr[0] = 0;
+    prop = promGetProperty("reg", &len);
+    if (prop && len >= 4) {
+	unsigned int *reg = (unsigned int *)prop;
+	if (!promP1275 || (type == PROM_NODE_SBUS) || (type == PROM_NODE_EBUS))
+	    sprintf (regstr, "@%x,%x", reg[0], reg[1]);
+	else if (type == PROM_NODE_PCI) {
+	    if ((reg[0] >> 8) & 7)
+		sprintf (regstr, "@%x,%x", (reg[0] >> 11) & 0x1f, (reg[0] >> 8) & 7);
+	    else
+		sprintf (regstr, "@%x", (reg[0] >> 11) & 0x1f);
+	} else if (len == 4)
+	    sprintf (regstr, "@%x", reg[0]);
+	else {
+	    unsigned int regs[2];
+
+	    /* Things get more complicated on UPA. If upa-portid exists,
+	       then address is @upa-portid,second-int-in-reg, otherwise
+	       it is @first-int-in-reg/16,second-int-in-reg (well, probably
+	       upa-portid always exists, but just to be safe). */
+	    memcpy (regs, reg, sizeof(regs));
+	    prop = promGetProperty("upa-portid", &len);
+	    if (prop && len == 4) {
+		reg = (unsigned int *)prop;
+		sprintf (regstr, "@%x,%x", reg[0], regs[1]);
+	    } else
+		sprintf (regstr, "@%x,%x", regs[0] >> 4, regs[1]);
+	}
+    }
+    return regstr;
+}
+
+static int
+promWalkNode2Pathname(char *path, int parent, int node, int searchNode, int type)
+{
+    int nextnode;
+    int len, ntype = type;
+    char *prop, *p;
+
+    prop = promGetProperty("name", &len);
+    *path = '/';
+    if (!prop || len <= 0)
+	return 0;
+    if ((!strcmp(prop, "sbus") || !strcmp(prop, "sbi")) && !type)
+	ntype = PROM_NODE_SBUS;
+    else if (!strcmp(prop, "ebus") && type == PROM_NODE_PCI)
+	ntype = PROM_NODE_EBUS;
+    else if (!strcmp(prop, "pci") && !type)
+	ntype = PROM_NODE_PCI;
+    strcpy (path + 1, prop);
+    p = promGetReg(type);
+    if (*p)
+	strcat (path, p);
+    if (node == searchNode)
+	return 1;
+    nextnode = promGetChild(node);
+    if (nextnode &&
+	promWalkNode2Pathname(strchr(path, 0), node, nextnode, searchNode, ntype))
+	return 1;
+    nextnode = promGetSibling(node);
+    if (nextnode &&
+	promWalkNode2Pathname(path, parent, nextnode, searchNode, type))
+	return 1;
+    return 0;
+}
+
+char *
+sparcPromNode2Pathname(sbusPromNodePtr pnode)
+{
+    char *ret;
+
+    if (!pnode->node) return NULL;
+    ret = xalloc(4096);
+    if (!ret) return NULL;
+    if (promWalkNode2Pathname(ret, promRootNode, promGetChild(promRootNode), pnode->node, 0))
+	return ret;
+    xfree(ret);
+    return NULL;
+}
+
+static int
+promWalkPathname2Node(char *name, char *regstr, int parent, int type)
+{
+    int len, node, ret;
+    char *prop, *p;
+
+    for (;;) {
+	prop = promGetProperty("name", &len);
+	if (!prop || len <= 0)
+	    return 0;
+	if ((!strcmp(prop, "sbus") || !strcmp(prop, "sbi")) && !type)
+	    type = PROM_NODE_SBUS;
+	else if (!strcmp(prop, "ebus") && type == PROM_NODE_PCI)
+	    type = PROM_NODE_EBUS;
+	else if (!strcmp(prop, "pci") && !type)
+	    type = PROM_NODE_PCI;
+	for (node = promGetChild(parent); node; node = promGetSibling(node)) {
+	    prop = promGetProperty("name", &len);
+	    if (!prop || len <= 0)
+		continue;
+	    if (*name && strcmp(name, prop))
+		continue;
+	    if (*regstr) {
+		p = promGetReg(type);
+		if (! *p || strcmp(p + 1, regstr))
+		    continue;
+	    }
+	    break;
+	}
+	if (!node) {
+	    for (node = promGetChild(parent); node; node = promGetSibling(node)) {
+		ret = promWalkPathname2Node(name, regstr, node, type);
+		if (ret) return ret;
+	    }
+	    return 0;
+	}
+	name = strchr(regstr, 0) + 1;
+	if (! *name)
+	    return node;
+	p = strchr(name, '/');
+	if (p)
+	    *p = 0;
+	else
+	    p = strchr(name, 0);
+	regstr = strchr(name, '@');
+	if (regstr)
+	    *regstr++ = 0;
+	else
+	    regstr = p;
+	if (name == regstr)
+	    return 0;
+	parent = node;
+    }
+}
+
+int
+sparcPromPathname2Node(const char *pathName)
+{
+    int i;
+    char *name, *regstr, *p;
+
+    i = strlen(pathName);
+    name = xalloc(i + 2);
+    if (! name) return 0;
+    strcpy (name, pathName);
+    name [i + 1] = 0;
+    if (name[0] != '/')
+	return 0;
+    p = strchr(name + 1, '/');
+    if (p)
+	*p = 0;
+    else
+	p = strchr(name, 0);
+    regstr = strchr(name, '@');
+    if (regstr)
+	*regstr++ = 0;
+    else
+	regstr = p;
+    if (name + 1 == regstr)
+	return 0;
+    promGetSibling(0);
+    i = promWalkPathname2Node(name + 1, regstr, promRootNode, 0);
+    xfree(name);
+    return i;
+}
+
+_X_EXPORT pointer
+xf86MapSbusMem(sbusDevicePtr psdp, unsigned long offset, unsigned long size)
+{
+    pointer ret;
+    unsigned long pagemask = getpagesize() - 1;
+    unsigned long off = offset & ~pagemask;
+    unsigned long len = ((offset + size + pagemask) & ~pagemask) - off;
+
+    if (psdp->fd == -1) {
+	psdp->fd = open(psdp->device, O_RDWR);
+	if (psdp->fd == -1)
+	    return NULL;
+    } else if (psdp->fd < 0)
+	return NULL;
+
+    ret = (pointer) mmap (NULL, len, PROT_READ | PROT_WRITE, MAP_PRIVATE,
+			  psdp->fd, off);
+    if (ret == (pointer) -1) {
+	ret = (pointer) mmap (NULL, len, PROT_READ | PROT_WRITE, MAP_SHARED,
+			      psdp->fd, off);
+    }
+    if (ret == (pointer) -1)
+	return NULL;
+
+    return (char *)ret + (offset - off);
+}
+
+_X_EXPORT void
+xf86UnmapSbusMem(sbusDevicePtr psdp, pointer addr, unsigned long size)
+{
+    unsigned long mask = getpagesize() - 1;
+    unsigned long base = (unsigned long)addr & ~mask;
+    unsigned long len = (((unsigned long)addr + size + mask) & ~mask) - base;
+
+    munmap ((pointer)base, len);
+}
+
+/* Tell OS that we are driving the HW cursor ourselves. */
+_X_EXPORT void
+xf86SbusHideOsHwCursor(sbusDevicePtr psdp)
+{
+    struct fbcursor fbcursor;
+    unsigned char zeros[8];
+
+    memset(&fbcursor, 0, sizeof(fbcursor));
+    memset(&zeros, 0, sizeof(zeros));
+    fbcursor.cmap.count = 2;
+    fbcursor.cmap.red = zeros;
+    fbcursor.cmap.green = zeros;
+    fbcursor.cmap.blue = zeros;
+    fbcursor.image = (char *)zeros;
+    fbcursor.mask = (char *)zeros;
+    fbcursor.size.x = 32;
+    fbcursor.size.y = 1;
+    fbcursor.set = FB_CUR_SETALL;
+    ioctl(psdp->fd, FBIOSCURSOR, &fbcursor);
+}
+
+/* Set HW cursor colormap. */
+_X_EXPORT void
+xf86SbusSetOsHwCursorCmap(sbusDevicePtr psdp, int bg, int fg)
+{
+    struct fbcursor fbcursor;
+    unsigned char red[2], green[2], blue[2];
+
+    memset(&fbcursor, 0, sizeof(fbcursor));
+    red[0] = bg >> 16;
+    green[0] = bg >> 8;
+    blue[0] = bg;
+    red[1] = fg >> 16;
+    green[1] = fg >> 8;
+    blue[1] = fg;
+    fbcursor.cmap.count = 2;
+    fbcursor.cmap.red = red;
+    fbcursor.cmap.green = green;
+    fbcursor.cmap.blue = blue;
+    fbcursor.set = FB_CUR_SETCMAP;
+    ioctl(psdp->fd, FBIOSCURSOR, &fbcursor);
+}
diff --git a/xorg-server/hw/xfree86/os-support/bus/bsd_pci.c b/xorg-server/hw/xfree86/os-support/bus/bsd_pci.c
new file mode 100644
index 000000000..57ad09b6a
--- /dev/null
+++ b/xorg-server/hw/xfree86/os-support/bus/bsd_pci.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright © 2007 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Eric Anholt <eric@anholt.net>
+ *
+ */
+
+/**
+ * @file bsd_pci.c
+ *
+ * This is a trivial implementation of the remaining PCI support hooks in the
+ * X Server that is unaware of domains.
+ *
+ * Most of even this should go away once drivers are converted and the
+ * old interfaces are confirmed to all be obsolete.
+ */
+
+#ifdef HAVE_XORG_CONFIG_H
+#include <xorg-config.h>
+#endif
+
+#include <stdio.h>
+#include "compiler.h"
+#include "xf86.h"
+#include "xf86Priv.h"
+#include "xf86_OSlib.h"
+#include "Pci.h"
+
+#include "pciaccess.h"
+
+static pciBusFuncs_t bsd_funcs = {
+    .pciAddrBusToHost = pciAddrNOOP,
+};
+
+static pciBusInfo_t bsd_pci = {
+    .configMech = PCI_CFG_MECH_OTHER,
+    .numDevices = 32,
+    .secondary = FALSE,
+    .primary_bus = 0,
+    .funcs = &bsd_funcs,
+    .pciBusPriv = NULL,
+    .bridge = NULL,
+};
+
+_X_EXPORT pointer
+xf86MapDomainMemory(int ScreenNum, int Flags, struct pci_device *dev,
+		    ADDRESS Base, unsigned long Size)
+{
+    return xf86MapVidMem(ScreenNum, Flags, Base, Size);
+}
+
+IOADDRESS
+xf86MapLegacyIO(struct pci_device *dev)
+{
+    (void)dev;
+    return 0;
+}
+
+void
+bsdPciInit(void)
+{
+    pciNumBuses = 1;
+    pciBusInfo[0] = &bsd_pci;
+
+    xf86InitVidMem();
+}
diff --git a/xorg-server/hw/xfree86/os-support/bus/ix86Pci.c b/xorg-server/hw/xfree86/os-support/bus/ix86Pci.c
new file mode 100644
index 000000000..e54246355
--- /dev/null
+++ b/xorg-server/hw/xfree86/os-support/bus/ix86Pci.c
@@ -0,0 +1,718 @@
+/*
+ * ix86Pci.c - x86 PCI driver
+ *
+ * The XFree86 server PCI access functions have been reimplemented as a
+ * framework that allows each supported platform/OS to have their own
+ * platform/OS specific PCI driver.
+ *
+ * Most of the code of these functions was simply lifted from the
+ * Intel architecture specifric portion of the original Xfree86
+ * PCI code in hw/xfree86/common_hw/xf86_PCI.C...
+ *
+ * Gary Barton
+ * Concurrent Computer Corporation
+ * garyb@gate.net
+ */
+
+/*
+ * Copyright 1998 by Concurrent Computer Corporation
+ *
+ * Permission to use, copy, modify, distribute, and sell this software
+ * and its documentation for any purpose is hereby granted without fee,
+ * provided that the above copyright notice appear in all copies and that
+ * both that copyright notice and this permission notice appear in
+ * supporting documentation, and that the name of Concurrent Computer
+ * Corporation not be used in advertising or publicity pertaining to
+ * distribution of the software without specific, written prior
+ * permission.  Concurrent Computer Corporation makes no representations
+ * about the suitability of this software for any purpose.  It is
+ * provided "as is" without express or implied warranty.
+ *
+ * CONCURRENT COMPUTER CORPORATION DISCLAIMS ALL WARRANTIES WITH REGARD
+ * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL CONCURRENT COMPUTER CORPORATION BE
+ * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY
+ * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
+ * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,
+ * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS
+ * SOFTWARE.
+ *
+ * Copyright 1998 by Metro Link Incorporated
+ *
+ * Permission to use, copy, modify, distribute, and sell this software
+ * and its documentation for any purpose is hereby granted without fee,
+ * provided that the above copyright notice appear in all copies and that
+ * both that copyright notice and this permission notice appear in
+ * supporting documentation, and that the name of Metro Link
+ * Incorporated not be used in advertising or publicity pertaining to
+ * distribution of the software without specific, written prior
+ * permission.  Metro Link Incorporated makes no representations
+ * about the suitability of this software for any purpose.  It is
+ * provided "as is" without express or implied warranty.
+ *
+ * METRO LINK INCORPORATED DISCLAIMS ALL WARRANTIES WITH REGARD
+ * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL METRO LINK INCORPORATED BE
+ * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY
+ * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
+ * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,
+ * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS
+ * SOFTWARE.
+ *
+ * This software is derived from the original XFree86 PCI code
+ * which includes the following copyright notices as well:
+ *
+ * Copyright 1995 by Robin Cutshaw <robin@XFree86.Org>
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that
+ * copyright notice and this permission notice appear in supporting
+ * documentation, and that the names of the above listed copyright holder(s)
+ * not be used in advertising or publicity pertaining to distribution of
+ * the software without specific, written prior permission.  The above listed
+ * copyright holder(s) make(s) no representations about the suitability of this
+ * software for any purpose.  It is provided "as is" without express or
+ * implied warranty.
+ *
+ * THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM(S) ALL WARRANTIES WITH REGARD
+ * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE
+ * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY
+ * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER
+ * IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ * This code is also based heavily on the code in FreeBSD-current, which was
+ * written by Wolfgang Stanglmeier, and contains the following copyright:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ * Copyright (c) 1999-2003 by The XFree86 Project, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of the copyright holder(s)
+ * and author(s) shall not be used in advertising or otherwise to promote
+ * the sale, use or other dealings in this Software without prior written
+ * authorization from the copyright holder(s) and author(s).
+ */
+
+#ifdef HAVE_XORG_CONFIG_H
+#include <xorg-config.h>
+#endif
+
+#include <stdio.h>
+#include "compiler.h"
+#include "xf86.h"
+#include "xf86Priv.h"
+#include "xf86_OSlib.h"
+#include "Pci.h"
+
+#ifdef PC98
+#define outb(port,data) _outb(port,data)
+#define outl(port,data) _outl(port,data)
+#define inb(port) _inb(port)
+#define inl(port) _inl(port)
+#endif
+
+#define	PCI_CFGMECH2_ENABLE_REG		0xCF8
+#ifdef PC98
+#define	PCI_CFGMECH2_FORWARD_REG	0xCF9
+#else
+#define	PCI_CFGMECH2_FORWARD_REG	0xCFA
+#endif
+
+#define PCI_CFGMECH2_MAXDEV	16
+
+#define PCI_ADDR_FROM_TAG_CFG1(tag,reg) (PCI_EN | tag | (reg & 0xfc))
+#define PCI_FORWARD_FROM_TAG(tag)       PCI_BUS_FROM_TAG(tag)
+#define PCI_ENABLE_FROM_TAG(tag)        (0xf0 | (((tag) & 0x00000700) >> 7))
+#define PCI_ADDR_FROM_TAG_CFG2(tag,reg) (0xc000 | (((tag) & 0x0000f800) >> 3) \
+                                        | (reg & 0xfc))
+
+/*
+ * Intel x86 platform specific PCI access functions
+ */
+#if 0
+static CARD32 ix86PciReadLongSetup(PCITAG tag, int off);
+static void ix86PciWriteLongSetup(PCITAG, int off, CARD32 val);
+static void ix86PciSetBitsLongSetup(PCITAG, int off, CARD32 mask, CARD32 val);
+static CARD32 ix86PciReadLongCFG1(PCITAG tag, int off);
+static void ix86PciWriteLongCFG1(PCITAG, int off, CARD32 val);
+static void ix86PciSetBitsLongCFG1(PCITAG, int off, CARD32 mask, CARD32 val);
+static CARD32 ix86PciReadLongCFG2(PCITAG tag, int off);
+static void ix86PciWriteLongCFG2(PCITAG, int off, CARD32 val);
+static void ix86PciSetBitsLongCFG2(PCITAG, int off, CARD32 mask, CARD32 val);
+#endif
+
+static pciBusFuncs_t ix86Funcs0 = {
+#if 0
+/* pciReadLong      */	ix86PciReadLongSetup,
+/* pciWriteLong     */	ix86PciWriteLongSetup,
+/* pciSetBitsLong   */	ix86PciSetBitsLongSetup,
+/* pciAddrHostToBus */	pciAddrNOOP,
+#endif
+/* pciAddrBusToHost */	pciAddrNOOP
+};
+
+static pciBusFuncs_t ix86Funcs1 = {
+#if 0
+/* pciReadLong      */	ix86PciReadLongCFG1,
+/* pciWriteLong     */	ix86PciWriteLongCFG1,
+/* pciSetBitsLong   */	ix86PciSetBitsLongCFG1,
+/* pciAddrHostToBus */	pciAddrNOOP,
+#endif
+/* pciAddrBusToHost */	pciAddrNOOP
+};
+
+static pciBusFuncs_t ix86Funcs2 = {
+#if 0
+/* pciReadLong      */	ix86PciReadLongCFG2,
+/* pciWriteLong     */	ix86PciWriteLongCFG2,
+/* pciSetBitsLong   */	ix86PciSetBitsLongCFG2,
+/* pciAddrHostToBus */	pciAddrNOOP,
+#endif
+/* pciAddrBusToHost */	pciAddrNOOP
+};
+
+static pciBusInfo_t ix86Pci0 = {
+/* configMech  */	PCI_CFG_MECH_UNKNOWN,	/* Set by ix86PciInit() */
+/* numDevices  */	0,			/* Set by ix86PciInit() */
+/* secondary   */	FALSE,
+/* primary_bus */	0,
+/* funcs       */	&ix86Funcs0,		/* Set by ix86PciInit() */
+/* pciBusPriv  */	NULL,
+/* bridge      */	NULL
+};
+
+_X_EXPORT pointer
+xf86MapDomainMemory(int ScreenNum, int Flags, struct pci_device *dev,
+                    ADDRESS Base, unsigned long Size)
+{
+    return xf86MapVidMem(ScreenNum, Flags, Base, Size);
+}
+
+IOADDRESS
+xf86MapLegacyIO(struct pci_device *dev)
+{
+    (void)dev;
+    return 0;
+}
+
+static Bool
+ix86PciBusCheck(void)
+{
+#if 0
+    PCITAG tag;
+    CARD32 id, class;
+    CARD8 device;
+
+    for (device = 0; device < ix86Pci0.numDevices; device++) {
+	tag = PCI_MAKE_TAG(0, device, 0);
+	id = (*ix86Pci0.funcs->pciReadLong)(tag, PCI_ID_REG);
+
+	if ((CARD16)(id + 1U) <= (CARD16)1UL)
+		continue;
+
+	/* The rest of this is inspired by the Linux kernel */
+	class = (*ix86Pci0.funcs->pciReadLong)(tag, PCI_CLASS_REG);
+
+	/* Ignore revision id and programming interface */
+	switch (class >> 16) {
+	case (PCI_CLASS_PREHISTORIC << 8) | PCI_SUBCLASS_PREHISTORIC_MISC:
+	    /* Check for vendors of known buggy chipsets */
+	    id &= 0x0000ffff;
+	    if ((id == PCI_VENDOR_INTEL) || (id == PCI_VENDOR_COMPAQ))
+		return TRUE;
+	    continue;
+
+	case (PCI_CLASS_PREHISTORIC << 8) | PCI_SUBCLASS_PREHISTORIC_VGA:
+	case (PCI_CLASS_DISPLAY << 8) | PCI_SUBCLASS_DISPLAY_VGA:
+	case (PCI_CLASS_BRIDGE << 8) | PCI_SUBCLASS_BRIDGE_HOST:
+	    return TRUE;
+
+	default:
+	    break;
+	}
+    }
+#endif
+    return FALSE;
+}
+
+static
+void ix86PciSelectCfgmech(void)
+{
+    static Bool beenhere = FALSE;
+    CARD32 mode1Res1 = 0, mode1Res2 = 0, oldVal1 = 0;
+    CARD8  mode2Res1 = 0, mode2Res2 = 0, oldVal2 = 0;
+    int stages = 0;
+
+    if (beenhere)
+	return; /* Been there, done that */
+
+    beenhere = TRUE;
+
+    /*
+     * Determine if motherboard chipset supports PCI Config Mech 1 or 2
+     * We rely on xf86Info.pciFlags to tell which mechanisms to try....
+     */
+    switch (xf86Info.pciFlags) {
+	case PCIOsConfig:
+	case PCIProbe1:
+	    if (!xf86EnableIO())
+		return;
+
+	    xf86MsgVerb(X_INFO, 2,
+			"PCI: Probing config type using method 1\n");
+	    oldVal1 = inl(PCI_CFGMECH1_ADDRESS_REG);
+
+#ifdef DEBUGPCI
+      if (xf86Verbose > 2) {
+	ErrorF("Checking config type 1:\n"
+		"\tinitial value of MODE1_ADDR_REG is 0x%08x\n", oldVal1);
+	ErrorF("\tChecking that all bits in mask 0x7f000000 are clear\n");
+      }
+#endif
+
+      /* Assuming config type 1 to start with */
+      if ((oldVal1 & 0x7f000000) == 0) {
+
+	stages |= 0x01;
+
+#ifdef DEBUGPCI
+	if (xf86Verbose > 2) {
+	    ErrorF("\tValue indicates possibly config type 1\n");
+	    ErrorF("\tWriting 32-bit value 0x%08x to MODE1_ADDR_REG\n", PCI_EN);
+#if 0
+	    ErrorF("\tWriting 8-bit value 0x00 to MODE1_ADDR_REG + 3\n");
+#endif
+	}
+#endif
+
+	ix86Pci0.configMech = PCI_CFG_MECH_1;
+	ix86Pci0.numDevices = PCI_CFGMECH1_MAXDEV;
+	ix86Pci0.funcs = &ix86Funcs1;
+
+	outl(PCI_CFGMECH1_ADDRESS_REG, PCI_EN);
+
+#if 0
+	/*
+	 * This seems to cause some Neptune-based PCI machines to switch
+	 * from config type 1 to config type 2
+	 */
+	outb(PCI_CFGMECH1_ADDRESS_REG + 3, 0);
+#endif
+	mode1Res1 = inl(PCI_CFGMECH1_ADDRESS_REG);
+
+#ifdef DEBUGPCI
+	if (xf86Verbose > 2) {
+	    ErrorF("\tValue read back from MODE1_ADDR_REG is 0x%08x\n",
+			mode1Res1);
+	    ErrorF("\tRestoring original contents of MODE1_ADDR_REG\n");
+	}
+#endif
+
+	outl(PCI_CFGMECH1_ADDRESS_REG, oldVal1);
+
+	if (mode1Res1) {
+
+	    stages |= 0x02;
+
+#ifdef DEBUGPCI
+	    if (xf86Verbose > 2) {
+		ErrorF("\tValue read back is non-zero, and indicates possible"
+			" config type 1\n");
+	    }
+#endif
+
+	    if (ix86PciBusCheck()) {
+
+#ifdef DEBUGPCI
+		if (xf86Verbose > 2)
+		    ErrorF("\tBus check Confirms this: ");
+#endif
+
+		xf86MsgVerb(X_INFO, 2, "PCI: Config type is 1\n");
+		xf86MsgVerb(X_INFO, 3,
+			"PCI: stages = 0x%02x, oldVal1 = 0x%08lx, mode1Res1"
+			" = 0x%08lx\n", stages, (unsigned long)oldVal1,
+			(unsigned long)mode1Res1);
+		return;
+	    }
+
+#ifdef DEBUGPCI
+	    if (xf86Verbose > 2) {
+		ErrorF("\tBus check fails to confirm this, continuing type 1"
+			" check ...\n");
+	    }
+#endif
+
+	}
+
+	stages |= 0x04;
+
+#ifdef DEBUGPCI
+	if (xf86Verbose > 2) {
+	    ErrorF("\tWriting 0xff000001 to MODE1_ADDR_REG\n");
+	}
+#endif
+	outl(PCI_CFGMECH1_ADDRESS_REG, 0xff000001);
+	mode1Res2 = inl(PCI_CFGMECH1_ADDRESS_REG);
+
+#ifdef DEBUGPCI
+	if (xf86Verbose > 2) {
+	    ErrorF("\tValue read back from MODE1_ADDR_REG is 0x%08x\n",
+			mode1Res2);
+	    ErrorF("\tRestoring original contents of MODE1_ADDR_REG\n");
+	}
+#endif
+
+	outl(PCI_CFGMECH1_ADDRESS_REG, oldVal1);
+
+	if ((mode1Res2 & 0x80000001) == 0x80000000) {
+
+	    stages |= 0x08;
+
+#ifdef DEBUGPCI
+	    if (xf86Verbose > 2) {
+		ErrorF("\tValue read back has only the msb set\n"
+			"\tThis indicates possible config type 1\n");
+	    }
+#endif
+
+	    if (ix86PciBusCheck()) {
+
+#ifdef DEBUGPCI
+		if (xf86Verbose > 2)
+		    ErrorF("\tBus check Confirms this: ");
+#endif
+
+		xf86MsgVerb(X_INFO, 2, "PCI: Config type is 1\n");
+		xf86MsgVerb(X_INFO, 3,
+			"PCI: stages = 0x%02x, oldVal1 = 0x%08lx,\n"
+			"\tmode1Res1 = 0x%08lx, mode1Res2 = 0x%08lx\n",
+			stages, (unsigned long)oldVal1,
+			(unsigned long)mode1Res1, (unsigned long)mode1Res2);
+		return;
+	    }
+
+#ifdef DEBUGPCI
+	    if (xf86Verbose > 2) {
+		ErrorF("\tBus check fails to confirm this.\n");
+	    }
+#endif
+
+	}
+      }
+
+      xf86MsgVerb(X_INFO, 3, "PCI: Standard check for type 1 failed.\n");
+      xf86MsgVerb(X_INFO, 3, "PCI: stages = 0x%02x, oldVal1 = 0x%08lx,\n"
+	       "\tmode1Res1 = 0x%08lx, mode1Res2 = 0x%08lx\n",
+	       stages, (unsigned long)oldVal1, (unsigned long)mode1Res1,
+	       (unsigned long)mode1Res2);
+
+      /* Try config type 2 */
+      oldVal2 = inb(PCI_CFGMECH2_ENABLE_REG);
+      if ((oldVal2 & 0xf0) == 0) {
+	ix86Pci0.configMech = PCI_CFG_MECH_2;
+	ix86Pci0.numDevices = PCI_CFGMECH2_MAXDEV;
+	ix86Pci0.funcs = &ix86Funcs2;
+
+	outb(PCI_CFGMECH2_ENABLE_REG, 0x0e);
+	mode2Res1 = inb(PCI_CFGMECH2_ENABLE_REG);
+	outb(PCI_CFGMECH2_ENABLE_REG, oldVal2);
+
+	if (mode2Res1 == 0x0e) {
+	    if (ix86PciBusCheck()) {
+		xf86MsgVerb(X_INFO, 2, "PCI: Config type is 2\n");
+		return;
+	    }
+	}
+      }
+      break; /* } */
+
+    case PCIProbe2: /* { */
+	if (!xf86EnableIO())
+	    return;
+
+      /* The scanpci-style detection method */
+
+      xf86MsgVerb(X_INFO, 2, "PCI: Probing config type using method 2\n");
+
+      outb(PCI_CFGMECH2_ENABLE_REG, 0x00);
+      outb(PCI_CFGMECH2_FORWARD_REG, 0x00);
+      mode2Res1 = inb(PCI_CFGMECH2_ENABLE_REG);
+      mode2Res2 = inb(PCI_CFGMECH2_FORWARD_REG);
+
+      if (mode2Res1 == 0 && mode2Res2 == 0) {
+	xf86MsgVerb(X_INFO, 2, "PCI: Config type is 2\n");
+	ix86Pci0.configMech = PCI_CFG_MECH_2;
+	ix86Pci0.numDevices = PCI_CFGMECH2_MAXDEV;
+	ix86Pci0.funcs = &ix86Funcs2;
+	return;
+      }
+
+      oldVal1 = inl(PCI_CFGMECH1_ADDRESS_REG);
+      outl(PCI_CFGMECH1_ADDRESS_REG, PCI_EN);
+      mode1Res1 = inl(PCI_CFGMECH1_ADDRESS_REG);
+      outl(PCI_CFGMECH1_ADDRESS_REG, oldVal1);
+      if (mode1Res1 == PCI_EN) {
+	xf86MsgVerb(X_INFO, 2, "PCI: Config type is 1\n");
+	ix86Pci0.configMech = PCI_CFG_MECH_1;
+	ix86Pci0.numDevices = PCI_CFGMECH1_MAXDEV;
+	ix86Pci0.funcs = &ix86Funcs1;
+	return;
+      }
+      break; /* } */
+
+    case PCIForceConfig1:
+	if (!xf86EnableIO())
+	    return;
+
+      xf86MsgVerb(X_INFO, 2, "PCI: Forcing config type 1\n");
+
+      ix86Pci0.configMech = PCI_CFG_MECH_1;
+      ix86Pci0.numDevices = PCI_CFGMECH1_MAXDEV;
+      ix86Pci0.funcs = &ix86Funcs1;
+      return;
+
+    case PCIForceConfig2:
+	if (!xf86EnableIO())
+	    return;
+
+      xf86MsgVerb(X_INFO, 2, "PCI: Forcing config type 2\n");
+
+      ix86Pci0.configMech = PCI_CFG_MECH_2;
+      ix86Pci0.numDevices = PCI_CFGMECH2_MAXDEV;
+      ix86Pci0.funcs = &ix86Funcs2;
+      return;
+
+    case PCIForceNone:
+	break;
+    }
+
+    /* No PCI found */
+    ix86Pci0.configMech = PCI_CFG_MECH_UNKNOWN;
+    xf86MsgVerb(X_INFO, 2, "PCI: No PCI bus found or probed for\n");
+}
+
+#if 0
+static pciTagRec
+ix86PcibusTag(CARD8 bus, CARD8 cardnum, CARD8 func)
+{
+    pciTagRec tag;
+
+    tag.cfg1 = 0;
+
+    if (func > 7 || cardnum >= pciBusInfo[bus]->numDevices)
+	return tag;
+
+    switch (ix86Pci0.configMech) {
+    case PCI_CFG_MECH_1:
+	    tag.cfg1 = PCI_EN | ((CARD32)bus << 16) |
+		       ((CARD32)cardnum << 11) |
+		       ((CARD32)func << 8);
+	    break;
+
+    case PCI_CFG_MECH_2:
+	    tag.cfg2.port    = 0xc000 | ((CARD16)cardnum << 8);
+	    tag.cfg2.enable  = 0xf0 | (func << 1);
+	    tag.cfg2.forward = bus;
+	    break;
+    }
+
+    return tag;
+}
+#endif
+
+#if 0
+static CARD32
+ix86PciReadLongSetup(PCITAG Tag, int reg)
+{
+    ix86PciSelectCfgmech();
+    return (*ix86Pci0.funcs->pciReadLong)(Tag,reg);
+}
+
+static CARD32
+ix86PciReadLongCFG1(PCITAG Tag, int reg)
+{
+    CARD32    addr, data = 0;
+
+#ifdef DEBUGPCI
+    ErrorF("ix86PciReadLong 0x%lx, %d\n", Tag, reg);
+#endif
+
+    addr = PCI_ADDR_FROM_TAG_CFG1(Tag,reg);
+    outl(PCI_CFGMECH1_ADDRESS_REG, addr);
+    data = inl(PCI_CFGMECH1_DATA_REG);
+    outl(PCI_CFGMECH1_ADDRESS_REG, 0);
+
+#ifdef DEBUGPCI
+    ErrorF("ix86PciReadLong 0x%lx\n", data);
+#endif
+
+    return data;
+}
+
+static CARD32
+ix86PciReadLongCFG2(PCITAG Tag, int reg)
+{
+    CARD32    addr, data = 0;
+    CARD8     forward, enable;
+
+#ifdef DEBUGPCI
+    ErrorF("ix86PciReadLong 0x%lx, %d\n", Tag, reg);
+#endif
+
+    forward  = PCI_FORWARD_FROM_TAG(Tag);
+    enable   = PCI_ENABLE_FROM_TAG(Tag);
+    addr     = PCI_ADDR_FROM_TAG_CFG2(Tag,reg);
+
+    outb(PCI_CFGMECH2_ENABLE_REG, enable);
+    outb(PCI_CFGMECH2_FORWARD_REG, forward);
+    data = inl((CARD16)addr);
+    outb(PCI_CFGMECH2_ENABLE_REG, 0);
+    outb(PCI_CFGMECH2_FORWARD_REG, 0);
+
+#ifdef DEBUGPCI
+    ErrorF("ix86PciReadLong 0x%lx\n", data);
+#endif
+
+    return data;
+}
+
+static void
+ix86PciWriteLongSetup(PCITAG Tag, int reg, CARD32 data)
+{
+    ix86PciSelectCfgmech();
+    (*ix86Pci0.funcs->pciWriteLong)(Tag,reg,data);
+}
+
+static void
+ix86PciWriteLongCFG1(PCITAG Tag, int reg, CARD32 data)
+{
+    CARD32    addr;
+
+    addr = PCI_ADDR_FROM_TAG_CFG1(Tag,reg);
+    outl(PCI_CFGMECH1_ADDRESS_REG, addr);
+    outl(PCI_CFGMECH1_DATA_REG, data);
+    outl(PCI_CFGMECH1_ADDRESS_REG, 0);
+}
+
+static void
+ix86PciWriteLongCFG2(PCITAG Tag, int reg, CARD32 data)
+{
+    CARD32    addr;
+    CARD8 forward, enable;
+
+    forward  = PCI_FORWARD_FROM_TAG(Tag);
+    enable   = PCI_ENABLE_FROM_TAG(Tag);
+    addr     = PCI_ADDR_FROM_TAG_CFG2(Tag,reg);
+
+    outb(PCI_CFGMECH2_ENABLE_REG, enable);
+    outb(PCI_CFGMECH2_FORWARD_REG, forward);
+    outl((CARD16)addr, data);
+    outb(PCI_CFGMECH2_ENABLE_REG, 0);
+    outb(PCI_CFGMECH2_FORWARD_REG, 0);
+}
+
+static void
+ix86PciSetBitsLongSetup(PCITAG Tag, int reg, CARD32 mask, CARD32 val)
+{
+    ix86PciSelectCfgmech();
+    (*ix86Pci0.funcs->pciSetBitsLong)(Tag,reg,mask,val);
+}
+
+static void
+ix86PciSetBitsLongCFG1(PCITAG Tag, int reg, CARD32 mask, CARD32 val)
+{
+    CARD32    addr, data = 0;
+
+#ifdef DEBUGPCI
+    ErrorF("ix86PciSetBitsLong 0x%lx, %d\n", Tag, reg);
+#endif
+
+    addr = PCI_ADDR_FROM_TAG_CFG1(Tag,reg);
+    outl(PCI_CFGMECH1_ADDRESS_REG, addr);
+    data = inl(PCI_CFGMECH1_DATA_REG);
+    data = (data & ~mask) | (val & mask);
+    outl(PCI_CFGMECH1_DATA_REG, data);
+    outl(PCI_CFGMECH1_ADDRESS_REG, 0);
+}
+
+static void
+ix86PciSetBitsLongCFG2(PCITAG Tag, int reg, CARD32 mask, CARD32 val)
+{
+    CARD32    addr, data = 0;
+    CARD8 enable, forward;
+
+#ifdef DEBUGPCI
+    ErrorF("ix86PciSetBitsLong 0x%lx, %d\n", Tag, reg);
+#endif
+
+    forward  = PCI_FORWARD_FROM_TAG(Tag);
+    enable   = PCI_ENABLE_FROM_TAG(Tag);
+    addr     = PCI_ADDR_FROM_TAG_CFG2(Tag,reg);
+
+    outb(PCI_CFGMECH2_ENABLE_REG, enable);
+    outb(PCI_CFGMECH2_FORWARD_REG, forward);
+    data = inl((CARD16)addr);
+    data = (data & ~mask) | (val & mask);
+    outl((CARD16)addr, data);
+    outb(PCI_CFGMECH2_ENABLE_REG, 0);
+    outb(PCI_CFGMECH2_FORWARD_REG, 0);
+}
+#endif
+
+void
+ix86PciInit()
+{
+    /* Initialize pciBusInfo[] array and function pointers */
+    pciNumBuses    = 1;
+    pciBusInfo[0]  = &ix86Pci0;
+
+    /* Make sure that there is a PCI bus present. */
+    ix86PciSelectCfgmech();
+    if (ix86Pci0.configMech == PCI_CFG_MECH_UNKNOWN) {
+	pciNumBuses    = 0;
+	pciBusInfo[0]  = NULL;
+    }
+}
diff --git a/xorg-server/hw/xfree86/os-support/bus/linuxPci.c b/xorg-server/hw/xfree86/os-support/bus/linuxPci.c
new file mode 100644
index 000000000..11eb4f9e8
--- /dev/null
+++ b/xorg-server/hw/xfree86/os-support/bus/linuxPci.c
@@ -0,0 +1,606 @@
+/*
+ * Copyright 1998 by Concurrent Computer Corporation
+ *
+ * Permission to use, copy, modify, distribute, and sell this software
+ * and its documentation for any purpose is hereby granted without fee,
+ * provided that the above copyright notice appear in all copies and that
+ * both that copyright notice and this permission notice appear in
+ * supporting documentation, and that the name of Concurrent Computer
+ * Corporation not be used in advertising or publicity pertaining to
+ * distribution of the software without specific, written prior
+ * permission.  Concurrent Computer Corporation makes no representations
+ * about the suitability of this software for any purpose.  It is
+ * provided "as is" without express or implied warranty.
+ *
+ * CONCURRENT COMPUTER CORPORATION DISCLAIMS ALL WARRANTIES WITH REGARD
+ * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL CONCURRENT COMPUTER CORPORATION BE
+ * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY
+ * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
+ * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,
+ * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS
+ * SOFTWARE.
+ *
+ * Copyright 1998 by Metro Link Incorporated
+ *
+ * Permission to use, copy, modify, distribute, and sell this software
+ * and its documentation for any purpose is hereby granted without fee,
+ * provided that the above copyright notice appear in all copies and that
+ * both that copyright notice and this permission notice appear in
+ * supporting documentation, and that the name of Metro Link
+ * Incorporated not be used in advertising or publicity pertaining to
+ * distribution of the software without specific, written prior
+ * permission.  Metro Link Incorporated makes no representations
+ * about the suitability of this software for any purpose.  It is
+ * provided "as is" without express or implied warranty.
+ *
+ * METRO LINK INCORPORATED DISCLAIMS ALL WARRANTIES WITH REGARD
+ * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL METRO LINK INCORPORATED BE
+ * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY
+ * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
+ * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,
+ * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS
+ * SOFTWARE.
+ */
+
+#ifdef HAVE_XORG_CONFIG_H
+#include <xorg-config.h>
+#endif
+
+#include <stdio.h>
+#include "compiler.h"
+#include "xf86.h"
+#include "xf86Priv.h"
+#include "xf86_OSlib.h"
+#include "Pci.h"
+#include <dirent.h>
+
+/*
+ * linux platform specific PCI access functions -- using /proc/bus/pci
+ * needs kernel version 2.2.x
+ */
+static ADDRESS linuxTransAddrBusToHost(PCITAG tag, PciAddrType type, ADDRESS addr);
+#if defined(__powerpc__)
+static ADDRESS linuxPpcBusAddrToHostAddr(PCITAG, PciAddrType, ADDRESS);
+#endif
+
+static pciBusFuncs_t linuxFuncs0 = {
+#if defined(__powerpc__)
+/* pciAddrBusToHost */	linuxPpcBusAddrToHostAddr,
+#else
+/* linuxTransAddrBusToHost is busted on sparc64 but the PCI rework tree
+ * makes it all moot, so we kludge it for now */
+#if defined(__sparc__)
+/* pciAddrBusToHost */  pciAddrNOOP,
+#else
+/* pciAddrBusToHost */	linuxTransAddrBusToHost,
+#endif /* __sparc64__ */
+#endif
+};
+
+static pciBusInfo_t linuxPci0 = {
+/* configMech  */	PCI_CFG_MECH_OTHER,
+/* numDevices  */	32,
+/* secondary   */	FALSE,
+/* primary_bus */	0,
+/* funcs       */	&linuxFuncs0,
+/* pciBusPriv  */	NULL,
+/* bridge      */	NULL
+};
+
+static const struct pci_id_match match_host_bridge = {
+    PCI_MATCH_ANY, PCI_MATCH_ANY, PCI_MATCH_ANY, PCI_MATCH_ANY,
+    (PCI_CLASS_BRIDGE << 16) | (PCI_SUBCLASS_BRIDGE_HOST << 8),
+    0x0000ffff00, 0
+};
+
+#ifndef INCLUDE_XF86_NO_DOMAIN
+#define MAX_DOMAINS 257
+static pointer DomainMmappedIO[MAX_DOMAINS];
+#endif
+
+void
+linuxPciInit(void)
+{
+	struct stat st;
+
+#ifndef INCLUDE_XF86_NO_DOMAIN
+    (void) memset(DomainMmappedIO, 0, sizeof(DomainMmappedIO));
+#endif
+
+	if ((xf86Info.pciFlags == PCIForceNone) ||
+	    (-1 == stat("/proc/bus/pci", &st))) {
+		/* when using this as default for all linux architectures,
+		   we'll need a fallback for 2.0 kernels here */
+		return;
+	}
+	pciNumBuses    = 1;
+	pciBusInfo[0]  = &linuxPci0;
+}
+
+/**
+ * \bug
+ * The generation of the procfs file name for the domain != 0 case may not be 
+ * correct.
+ */
+static int
+linuxPciOpenFile(struct pci_device *dev, Bool write)
+{
+    static struct pci_device *last_dev = NULL;
+    static int	fd = -1,is_write = 0;
+    char		file[64];
+    struct stat	ignored;
+    static int is26 = -1;
+
+    if (dev == NULL) {
+	return -1;
+    }
+
+    if (is26 == -1) {
+	is26 = (stat("/sys/bus/pci", &ignored) < 0) ? 0 : 1;
+    }
+	
+    if (fd == -1 || (write && (!is_write)) || (last_dev != dev)) {
+	if (fd != -1) {
+	    close(fd);
+	    fd = -1;
+	}
+
+	if (is26) {
+	    sprintf(file,"/sys/bus/pci/devices/%04u:%02x:%02x.%01x/config",
+		    dev->domain, dev->bus, dev->dev, dev->func);
+	} else {
+	    if (dev->domain == 0) {
+		sprintf(file,"/proc/bus/pci/%02x", dev->bus);
+		if (stat(file, &ignored) < 0) {
+		    sprintf(file, "/proc/bus/pci/0000:%02x/%02x.%1x",
+			    dev->bus, dev->dev, dev->func);
+		} else {
+		    sprintf(file, "/proc/bus/pci/%02x/%02x.%1x",
+			    dev->bus, dev->dev, dev->func);
+		}
+	    } else {
+		sprintf(file,"/proc/bus/pci/%02x%02x", dev->domain, dev->bus);
+		if (stat(file, &ignored) < 0) {
+		    sprintf(file, "/proc/bus/pci/%04x:%04x/%02x.%1x",
+			    dev->domain, dev->bus, dev->dev, dev->func);
+		} else {
+		    sprintf(file, "/proc/bus/pci/%02x%02x/%02x.%1x",
+			    dev->domain, dev->bus, dev->dev, dev->func);
+		}
+	    }
+	}
+
+	if (write) {
+	    fd = open(file,O_RDWR);
+	    if (fd != -1) is_write = TRUE;
+	} else {
+	    switch (is_write) {
+	    case TRUE:
+		fd = open(file,O_RDWR);
+		if (fd > -1)
+		    break;
+	    default:
+		fd = open(file,O_RDONLY);
+		is_write = FALSE;
+	    }
+	}
+
+	last_dev = dev;
+    }
+
+    return fd;
+}
+
+/*
+ * This function will convert a BAR address into a host address
+ * suitable for passing into the mmap function of a /proc/bus
+ * device.
+ */
+ADDRESS linuxTransAddrBusToHost(PCITAG tag, PciAddrType type, ADDRESS addr)
+{
+    ADDRESS ret = xf86GetOSOffsetFromPCI(tag, PCI_MEM|PCI_IO, addr);
+
+    if (ret)
+	return ret;
+
+    /*
+     * if it is not a BAR address, it must be legacy, (or wrong)
+     * return it as is..
+     */
+    return addr;
+}
+
+
+#if defined(__powerpc__)
+
+#ifndef __NR_pciconfig_iobase
+#define __NR_pciconfig_iobase   200
+#endif
+
+static ADDRESS
+linuxPpcBusAddrToHostAddr(PCITAG tag, PciAddrType type, ADDRESS addr)
+{
+    if (type == PCI_MEM)
+    {
+	ADDRESS membase = syscall(__NR_pciconfig_iobase, 1,
+		    PCI_BUS_FROM_TAG(tag), PCI_DFN_FROM_TAG(tag));
+	return (addr + membase);
+    }
+    else if (type == PCI_IO)
+    {
+	ADDRESS iobase = syscall(__NR_pciconfig_iobase, 2,
+		    PCI_BUS_FROM_TAG(tag), PCI_DFN_FROM_TAG(tag));
+	return (addr + iobase);
+    }
+    else return addr;
+}
+
+#endif /* __powerpc__ */
+
+#ifndef INCLUDE_XF86_NO_DOMAIN
+
+/*
+ * Compiling the following simply requires the presence of <linux/pci.c>.
+ * Actually running this is another matter altogether...
+ *
+ * This scheme requires that the kernel allow mmap()'ing of a host bridge's I/O
+ * and memory spaces through its /proc/bus/pci/BUS/DFN entry.  Which one is
+ * determined by a prior ioctl().
+ *
+ * For the sparc64 port, this means 2.4.12 or later.  For ppc, this
+ * functionality is almost, but not quite there yet.  Alpha and other kernel
+ * ports to multi-domain architectures still need to implement this.
+ *
+ * This scheme is also predicated on the use of an IOADDRESS compatible type to
+ * designate I/O addresses.  Although IOADDRESS is defined as an unsigned
+ * integral type, it is actually the virtual address of, i.e. a pointer to, the
+ * I/O port to access.  And so, the inX/outX macros in "compiler.h" need to be
+ * #define'd appropriately (as is done on SPARC's).
+ *
+ * Another requirement to port this scheme to another multi-domain architecture
+ * is to add the appropriate entries in the pciControllerSizes array below.
+ *
+ * TO DO:  Address the deleterious reaction some host bridges have to master
+ *         aborts.  This is already done for secondary PCI buses, but not yet
+ *         for accesses to primary buses (except for the SPARC port, where
+ *         master aborts are avoided during PCI scans).
+ */
+
+#include <linux/pci.h>
+
+#ifndef PCIIOC_BASE		/* Ioctls for /proc/bus/pci/X/Y nodes. */
+#define PCIIOC_BASE		('P' << 24 | 'C' << 16 | 'I' << 8)
+
+/* Get controller for PCI device. */
+#define PCIIOC_CONTROLLER	(PCIIOC_BASE | 0x00)
+/* Set mmap state to I/O space. */
+#define PCIIOC_MMAP_IS_IO	(PCIIOC_BASE | 0x01)
+/* Set mmap state to MEM space. */
+#define PCIIOC_MMAP_IS_MEM	(PCIIOC_BASE | 0x02)
+/* Enable/disable write-combining. */
+#define PCIIOC_WRITE_COMBINE	(PCIIOC_BASE | 0x03)
+
+#endif
+
+/* This probably shouldn't be Linux-specific */
+static struct pci_device *
+get_parent_bridge(struct pci_device *dev)
+{
+    struct pci_id_match bridge_match = {
+	PCI_MATCH_ANY, PCI_MATCH_ANY, PCI_MATCH_ANY, PCI_MATCH_ANY,
+	(PCI_CLASS_BRIDGE << 16) | (PCI_SUBCLASS_BRIDGE_PCI << 8),
+	0
+    };
+    struct pci_device *bridge;
+    struct pci_device_iterator *iter;
+
+    if (dev == NULL) {
+	return NULL;
+    }
+
+    iter = pci_id_match_iterator_create(& bridge_match);
+    if (iter == NULL) {
+	return NULL;
+    }
+
+    while ((bridge = pci_device_next(iter)) != NULL) {
+	if (bridge->domain == dev->domain) {
+	    const struct pci_bridge_info *info = 
+		pci_device_get_bridge_info(bridge);
+
+	    if (info != NULL) {
+		if (info->secondary_bus == dev->bus) {
+		    break;
+		}
+	    }
+	}
+    }
+
+    pci_iterator_destroy(iter);
+
+    return bridge;
+}
+
+/*
+ * This is ugly, but until I can extract this information from the kernel,
+ * it'll have to do.  The default I/O space size is 64K, and 4G for memory.
+ * Anything else needs to go in this table.  (PowerPC folk take note.)
+ *
+ * Note that Linux/SPARC userland is 32-bit, so 4G overflows to zero here.
+ *
+ * Please keep this table in ascending vendor/device order.
+ */
+static const struct pciSizes {
+    unsigned short vendor, device;
+    unsigned long io_size, mem_size;
+} pciControllerSizes[] = {
+    {
+	PCI_VENDOR_SUN, PCI_CHIP_PSYCHO,
+	1U << 16, 1U << 31
+    },
+    {
+	PCI_VENDOR_SUN, PCI_CHIP_SCHIZO,
+	1U << 24, 1U << 31	/* ??? */
+    },
+    {
+	PCI_VENDOR_SUN, PCI_CHIP_SABRE,
+	1U << 24, (unsigned long)(1ULL << 32)
+    },
+    {
+	PCI_VENDOR_SUN, PCI_CHIP_HUMMINGBIRD,
+	1U << 24, (unsigned long)(1ULL << 32)
+    }
+};
+#define NUM_SIZES (sizeof(pciControllerSizes) / sizeof(pciControllerSizes[0]))
+
+static const struct pciSizes *
+linuxGetSizesStruct(const struct pci_device *dev)
+{
+    static const struct pciSizes default_size = {
+	0, 0, 1U << 16, (unsigned long)(1ULL << 32)
+    };
+    int          i;
+
+    /* Look up vendor/device */
+    if (dev != NULL) {
+	for (i = 0;  i < NUM_SIZES;  i++) {
+	    if ((dev->vendor_id == pciControllerSizes[i].vendor)
+		&& (dev->device_id == pciControllerSizes[i].device)) {
+		return & pciControllerSizes[i];
+	    }
+	}
+    }
+
+    /* Default to 64KB I/O and 4GB memory. */
+    return & default_size;
+}
+
+static __inline__ unsigned long
+linuxGetIOSize(const struct pci_device *dev)
+{
+    const struct pciSizes * const sizes = linuxGetSizesStruct(dev);
+    return sizes->io_size;
+}
+
+static pointer
+linuxMapPci(int ScreenNum, int Flags, struct pci_device *dev,
+	    ADDRESS Base, unsigned long Size, int mmap_ioctl)
+{
+    /* Align to page boundary */
+    const ADDRESS realBase = Base & ~(getpagesize() - 1);
+    const ADDRESS Offset = Base - realBase;
+
+    do {
+	unsigned char *result;
+	int fd, mmapflags, prot;
+
+	xf86InitVidMem();
+
+	/* If dev is NULL, linuxPciOpenFile will return -1, and this routine
+	 * will fail gracefully.
+	 */
+        prot = ((Flags & VIDMEM_READONLY) == 0);
+        if (((fd = linuxPciOpenFile(dev, prot)) < 0) ||
+	    (ioctl(fd, mmap_ioctl, 0) < 0))
+	    break;
+
+/* Note:  IA-64 doesn't compile this and doesn't need to */
+#ifdef __ia64__
+
+# ifndef  MAP_WRITECOMBINED
+#  define MAP_WRITECOMBINED 0x00010000
+# endif
+# ifndef  MAP_NONCACHED
+#  define MAP_NONCACHED     0x00020000
+# endif
+
+	if (Flags & VIDMEM_FRAMEBUFFER)
+	    mmapflags = MAP_SHARED | MAP_WRITECOMBINED;
+	else
+	    mmapflags = MAP_SHARED | MAP_NONCACHED;
+
+#else /* !__ia64__ */
+
+	mmapflags = (Flags & VIDMEM_FRAMEBUFFER) / VIDMEM_FRAMEBUFFER;
+
+	if (ioctl(fd, PCIIOC_WRITE_COMBINE, mmapflags) < 0)
+	    break;
+
+	mmapflags = MAP_SHARED;
+
+#endif /* ?__ia64__ */
+
+
+	if (Flags & VIDMEM_READONLY)
+	    prot = PROT_READ;
+	else
+	    prot = PROT_READ | PROT_WRITE;
+
+	result = mmap(NULL, Size + Offset, prot, mmapflags, fd, realBase);
+
+	if (!result || ((pointer)result == MAP_FAILED))
+	    return NULL;
+
+	xf86MakeNewMapping(ScreenNum, Flags, realBase, Size + Offset, result);
+
+	return result + Offset;
+    } while (0);
+
+    if (mmap_ioctl == PCIIOC_MMAP_IS_MEM)
+	return xf86MapVidMem(ScreenNum, Flags, Base, Size);
+
+    return NULL;
+}
+
+static int
+linuxOpenLegacy(struct pci_device *dev, char *name)
+{
+    static const char PREFIX[] = "/sys/class/pci_bus/%04x:%02x/%s";
+    char path[sizeof(PREFIX) + 10];
+    int fd = -1;
+
+    while (dev != NULL) {
+	snprintf(path, sizeof(path) - 1, PREFIX, dev->domain, dev->bus, name);
+	fd = open(path, O_RDWR);
+	if (fd >= 0) {
+	    return fd;
+	}
+
+	dev = get_parent_bridge(dev);
+    }
+
+    return fd;
+}
+
+/*
+ * xf86MapDomainMemory - memory map PCI domain memory
+ *
+ * This routine maps the memory region in the domain specified by Tag and
+ * returns a pointer to it.  The pointer is saved for future use if it's in
+ * the legacy ISA memory space (memory in a domain between 0 and 1MB).
+ */
+_X_EXPORT pointer
+xf86MapDomainMemory(int ScreenNum, int Flags, struct pci_device *dev,
+		    ADDRESS Base, unsigned long Size)
+{
+    int fd = -1;
+    pointer addr;
+
+    /*
+     * We use /proc/bus/pci on non-legacy addresses or if the Linux sysfs
+     * legacy_mem interface is unavailable.
+     */
+    if ((Base > 1024*1024) || ((fd = linuxOpenLegacy(dev, "legacy_mem")) < 0))
+	return linuxMapPci(ScreenNum, Flags, dev, Base, Size,
+			   PCIIOC_MMAP_IS_MEM);
+    else
+	addr = mmap(NULL, Size, PROT_READ|PROT_WRITE, MAP_SHARED, fd, Base);
+
+    if (fd >= 0)
+	close(fd);
+    if (addr == NULL || addr == MAP_FAILED) {
+	perror("mmap failure");
+	FatalError("xf86MapDomainMem():  mmap() failure\n");
+    }
+    return addr;
+}
+
+/**
+ * Map I/O space in this domain
+ *
+ * Each domain has a legacy ISA I/O space.  This routine will try to
+ * map it using the Linux sysfs legacy_io interface.  If that fails,
+ * it'll fall back to using /proc/bus/pci.
+ *
+ * If the legacy_io interface \b does exist, the file descriptor (\c fd below)
+ * will be saved in the \c DomainMmappedIO array in the upper bits of the
+ * pointer.  Callers will do I/O with small port numbers (<64k values), so
+ * the platform I/O code can extract the port number and the \c fd, \c lseek
+ * to the port number in the legacy_io file, and issue the read or write.
+ *
+ * This has no means of returning failure, so all errors are fatal
+ */
+IOADDRESS
+xf86MapLegacyIO(struct pci_device *dev)
+{
+    const int domain = dev->domain;
+    struct pci_device *bridge = get_parent_bridge(dev);
+    int fd;
+
+    if (domain >= MAX_DOMAINS)
+	FatalError("xf86MapLegacyIO():  domain out of range\n");
+
+    if (DomainMmappedIO[domain] == NULL) {
+	/* Permanently map all of I/O space */
+	fd = linuxOpenLegacy(bridge, "legacy_io");
+	if (fd < 0) {
+	    DomainMmappedIO[domain] = linuxMapPci(-1, VIDMEM_MMIO, bridge,
+						  0, linuxGetIOSize(bridge),
+						  PCIIOC_MMAP_IS_IO);
+	}
+	else { /* legacy_io file exists, encode fd */
+	    DomainMmappedIO[domain] = (pointer)(fd << 24);
+	}
+    }
+
+    return (IOADDRESS)DomainMmappedIO[domain];
+}
+
+resPtr
+xf86AccResFromOS(resPtr pRes)
+{
+    struct pci_device *dev;
+    struct pci_device_iterator *iter;
+    resRange      range;
+
+    iter = pci_id_match_iterator_create(& match_host_bridge);
+    while ((dev = pci_device_next(iter)) != NULL) {
+	const int domain = dev->domain;
+	const struct pciSizes * const sizes = linuxGetSizesStruct(dev);
+
+	/*
+	 * At minimum, the top and bottom resources must be claimed, so
+	 * that resources that are (or appear to be) unallocated can be
+	 * relocated.
+	 */
+	RANGE(range, 0x00000000u, 0x0009ffffu,
+	      RANGE_TYPE(ResExcMemBlock, domain));
+	pRes = xf86AddResToList(pRes, &range, -1);
+	RANGE(range, 0x000c0000u, 0x000effffu,
+	      RANGE_TYPE(ResExcMemBlock, domain));
+	pRes = xf86AddResToList(pRes, &range, -1);
+	RANGE(range, 0x000f0000u, 0x000fffffu,
+	      RANGE_TYPE(ResExcMemBlock, domain));
+	pRes = xf86AddResToList(pRes, &range, -1);
+
+	RANGE(range, (ADDRESS)(sizes->mem_size - 1), 
+	      (ADDRESS)(sizes->mem_size - 1),
+	      RANGE_TYPE(ResExcMemBlock, domain));
+	pRes = xf86AddResToList(pRes, &range, -1);
+
+	RANGE(range, 0x00000000u, 0x00000000u,
+	      RANGE_TYPE(ResExcIoBlock, domain));
+	pRes = xf86AddResToList(pRes, &range, -1);
+	RANGE(range, (IOADDRESS)(sizes->io_size - 1), 
+	      (IOADDRESS)(sizes->io_size - 1),
+	      RANGE_TYPE(ResExcIoBlock, domain));
+	pRes = xf86AddResToList(pRes, &range, -1);
+
+	/* FIXME: The old code reserved domain 0 for a special purpose.  The
+	 * FIXME: new code just uses whatever domains the kernel tells it,
+	 * FIXME: but there is no way to get a domain < 0.  What should
+	 * FIXME: happen here?
+	 *
+	if (domain <= 0)
+	  break;
+	 */
+    }
+
+    pci_iterator_destroy(iter);
+
+    return pRes;
+}
+
+#endif /* !INCLUDE_XF86_NO_DOMAIN */
diff --git a/xorg-server/hw/xfree86/os-support/bus/ppcPci.c b/xorg-server/hw/xfree86/os-support/bus/ppcPci.c
new file mode 100644
index 000000000..49c1a2a39
--- /dev/null
+++ b/xorg-server/hw/xfree86/os-support/bus/ppcPci.c
@@ -0,0 +1,82 @@
+/*
+ * ppcPci.c - PowerPC PCI access functions
+ *
+ * PCI driver functions supporting Motorola PowerPC platforms
+ * including Powerstack(RiscPC/RiscPC+), PowerStackII, MTX, and
+ * MVME 160x/260x/360x/460x VME boards
+ *
+ * Gary Barton
+ * Concurrent Computer Corporation
+ * garyb@gate.net
+ *
+ */
+
+/*
+ * Copyright 1998 by Concurrent Computer Corporation
+ *
+ * Permission to use, copy, modify, distribute, and sell this software
+ * and its documentation for any purpose is hereby granted without fee,
+ * provided that the above copyright notice appear in all copies and that
+ * both that copyright notice and this permission notice appear in
+ * supporting documentation, and that the name of Concurrent Computer
+ * Corporation not be used in advertising or publicity pertaining to
+ * distribution of the software without specific, written prior
+ * permission.  Concurrent Computer Corporation makes no representations
+ * about the suitability of this software for any purpose.  It is
+ * provided "as is" without express or implied warranty.
+ *
+ * CONCURRENT COMPUTER CORPORATION DISCLAIMS ALL WARRANTIES WITH REGARD
+ * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL CONCURRENT COMPUTER CORPORATION BE
+ * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY
+ * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
+ * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,
+ * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS
+ * SOFTWARE.
+ *
+ * Copyright 1998 by Metro Link Incorporated
+ *
+ * Permission to use, copy, modify, distribute, and sell this software
+ * and its documentation for any purpose is hereby granted without fee,
+ * provided that the above copyright notice appear in all copies and that
+ * both that copyright notice and this permission notice appear in
+ * supporting documentation, and that the name of Metro Link
+ * Incorporated not be used in advertising or publicity pertaining to
+ * distribution of the software without specific, written prior
+ * permission.  Metro Link Incorporated makes no representations
+ * about the suitability of this software for any purpose.  It is
+ * provided "as is" without express or implied warranty.
+ *
+ * METRO LINK INCORPORATED DISCLAIMS ALL WARRANTIES WITH REGARD
+ * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL METRO LINK INCORPORATED BE
+ * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY
+ * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
+ * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,
+ * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS
+ * SOFTWARE.
+ */
+
+#ifdef HAVE_XORG_CONFIG_H
+#include <xorg-config.h>
+#endif
+
+#include <stdio.h>
+#include "compiler.h"
+#include "xf86.h"
+#include "xf86Priv.h"
+#include "xf86_OSlib.h"
+#include "Pci.h"
+
+#ifndef MAP_FAILED
+#define MAP_FAILED (pointer)(-1)
+#endif
+
+void
+ppcPciInit()
+{
+  
+  static void motoppcPciInit(void);
+  motoppcPciInit();
+
+}
diff --git a/xorg-server/hw/xfree86/os-support/bus/sparcPci.c b/xorg-server/hw/xfree86/os-support/bus/sparcPci.c
new file mode 100644
index 000000000..2d8039c29
--- /dev/null
+++ b/xorg-server/hw/xfree86/os-support/bus/sparcPci.c
@@ -0,0 +1,979 @@
+/*
+ * Copyright (C) 2001-2003 The XFree86 Project, Inc.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+ * XFREE86 PROJECT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of the XFree86 Project shall
+ * not be used in advertising or otherwise to promote the sale, use or other
+ * dealings in this Software without prior written authorization from the
+ * XFree86 Project.
+ */
+
+#ifdef HAVE_XORG_CONFIG_H
+#include <xorg-config.h>
+#endif
+
+#include "xf86.h"
+#include "xf86Priv.h"
+#include "xf86_OSlib.h"
+#include "Pci.h"
+#include "xf86sbusBus.h"
+
+#if defined(sun)
+
+extern char *apertureDevName;
+static int  apertureFd = -1;
+
+/*
+ * A version of xf86MapVidMem() that allows for 64-bit displacements (but not
+ * sizes).  Areas thus mapped can be unmapped by xf86UnMapVidMem().
+ */
+static pointer
+sparcMapAperture(int iScreen, int Flags,
+		 unsigned long long Base, unsigned long Size)
+{
+    pointer result;
+    static int lastFlags = 0;
+
+    /* Assume both Base & Size are multiples of the page size */
+
+    if ((apertureFd < 0) || (Flags != lastFlags)) {
+	if (apertureFd >= 0)
+	    close(apertureFd);
+	lastFlags = Flags;
+	apertureFd = open(apertureDevName,
+	    (Flags & VIDMEM_READONLY) ? O_RDONLY : O_RDWR);
+	if (apertureFd < 0)
+	    FatalError("sparcMapAperture:  open failure:  %s\n",
+		       strerror(errno));
+    }
+
+    result = mmap(NULL, Size,
+		  (Flags & VIDMEM_READONLY) ?
+		      PROT_READ : (PROT_READ | PROT_WRITE),
+		  MAP_SHARED, apertureFd, (off_t)Base);
+
+    if (result == MAP_FAILED)
+	FatalError("sparcMapAperture:  mmap failure:  %s\n", strerror(errno));
+
+    return result;
+}
+
+/*
+ * Platform-specific bus privates.
+ */
+typedef struct _sparcDomainRec {
+    unsigned long long io_addr, io_size;
+    unsigned long long mem_addr, mem_size;
+    pointer pci, io;
+    int bus_min, bus_max;
+    unsigned char dfn_mask[256 / 8];
+} sparcDomainRec, *sparcDomainPtr;
+
+#define SetBitInMap(bit, map) \
+    do { \
+	int _bit = (bit); \
+	(map)[_bit >> 3] |= 1 << (_bit & 7); \
+    } while (0)
+
+#define IsBitSetInMap(bit, map) \
+    ((map)[(bit) >> 3] & (1 << ((bit) & 7)))
+
+/*
+ * Domain 0 is reserved for the one that represents the system as a whole, i.e.
+ * the one without any resource relocations.
+ */
+#define MAX_DOMAINS (MAX_PCI_BUSES / 256)
+static sparcDomainPtr xf86DomainInfo[MAX_DOMAINS];
+static int            pciNumDomains = 1;
+
+/* Variables that are assigned this must be declared volatile */
+#define PciReg(base, tag, off, type) \
+    *(volatile type *)(pointer)((char *)(base) + \
+	(PCI_TAG_NO_DOMAIN(tag) | (off)))
+
+/* Generic SPARC PCI access functions */
+static CARD32
+sparcPciCfgRead32(PCITAG tag, int off)
+{
+    pciBusInfo_t    *pBusInfo;
+    sparcDomainPtr  pDomain;
+    volatile CARD32 result = (CARD32)(-1);	/* Must be volatile */
+    int             bus;
+
+    if ((off >= 0) && (off <= 252) && !(off & 3) &&
+	((bus = PCI_BUS_FROM_TAG(tag)) < pciNumBuses) &&
+	(pBusInfo = pciBusInfo[bus]) && (pDomain = pBusInfo->pciBusPriv) &&
+	(bus >= pDomain->bus_min) && (bus < pDomain->bus_max) &&
+	((bus > pDomain->bus_min) ||
+	 IsBitSetInMap(PCI_DFN_FROM_TAG(tag), pDomain->dfn_mask))) {
+	result = PciReg(pDomain->pci, tag, off, CARD32);
+
+	result = PCI_CPU(result);
+    }
+
+    return result;
+}
+
+static void
+sparcPciCfgWrite32(PCITAG tag, int off, CARD32 val)
+{
+    pciBusInfo_t   *pBusInfo;
+    sparcDomainPtr pDomain;
+    int            bus;
+
+    if ((off < 0) || (off > 252) || (off & 3) ||
+	((bus = PCI_BUS_FROM_TAG(tag)) >= pciNumBuses) ||
+	!(pBusInfo = pciBusInfo[bus]) || !(pDomain = pBusInfo->pciBusPriv) ||
+	(bus < pDomain->bus_min) || (bus >= pDomain->bus_max) ||
+	((bus == pDomain->bus_min) &&
+	 !IsBitSetInMap(PCI_DFN_FROM_TAG(tag), pDomain->dfn_mask)))
+	return;
+
+    val = PCI_CPU(val);
+    PciReg(pDomain->pci, tag, off, CARD32) = val;
+}
+
+static void
+sparcPciCfgSetBits32(PCITAG tag, int off, CARD32 mask, CARD32 bits)
+{
+    CARD32 PciVal;
+
+    PciVal = sparcPciCfgRead32(tag, off);
+    PciVal &= ~mask;
+    PciVal |= bits;
+    sparcPciCfgWrite32(tag, off, PciVal);
+}
+
+static pciBusFuncs_t sparcPCIFunctions =
+{
+    sparcPciCfgRead32,
+    sparcPciCfgWrite32,
+    sparcPciCfgSetBits32,
+    pciAddrNOOP,
+    pciAddrNOOP
+};
+
+/*
+ * Sabre-specific versions of the above because of its peculiar access size
+ * requirements.
+ */
+static CARD32
+sabrePciCfgRead32(PCITAG tag, int off)
+{
+    pciBusInfo_t    *pBusInfo;
+    sparcDomainPtr  pDomain;
+    volatile CARD32 result;			/* Must be volatile */
+    int             bus;
+
+    if (PCI_BDEV_FROM_TAG(tag))
+	return sparcPciCfgRead32(tag, off);
+
+    if (PCI_FUNC_FROM_TAG(tag) || (off < 0) || (off > 252) || (off & 3) ||
+	((bus = PCI_BUS_FROM_TAG(tag)) >= pciNumBuses) ||
+	!(pBusInfo = pciBusInfo[bus]) || !(pDomain = pBusInfo->pciBusPriv) ||
+	(bus != pDomain->bus_min))
+	return (CARD32)(-1);
+
+    if (off < 8) {
+	result = (PciReg(pDomain->pci, tag, off, CARD16) << 16) |
+		  PciReg(pDomain->pci, tag, off + 2, CARD16);
+	return PCI_CPU(result);
+    }
+
+    result = (PciReg(pDomain->pci, tag, off + 3, CARD8) << 24) |
+	     (PciReg(pDomain->pci, tag, off + 2, CARD8) << 16) |
+	     (PciReg(pDomain->pci, tag, off + 1, CARD8) <<  8) |
+	     (PciReg(pDomain->pci, tag, off    , CARD8)      );
+    return result;
+}
+
+static void
+sabrePciCfgWrite32(PCITAG tag, int off, CARD32 val)
+{
+    pciBusInfo_t   *pBusInfo;
+    sparcDomainPtr pDomain;
+    int            bus;
+
+    if (PCI_BDEV_FROM_TAG(tag))
+	sparcPciCfgWrite32(tag, off, val);
+    else if (!PCI_FUNC_FROM_TAG(tag) &&
+	     (off >= 0) && (off <= 252) && !(off & 3) &&
+	     ((bus = PCI_BUS_FROM_TAG(tag)) < pciNumBuses) &&
+	     (pBusInfo = pciBusInfo[bus]) &&
+	     (pDomain = pBusInfo->pciBusPriv) &&
+	     (bus == pDomain->bus_min)) {
+	if (off < 8) {
+	    val = PCI_CPU(val);
+	    PciReg(pDomain->pci, tag, off    , CARD16) = val >> 16;
+	    PciReg(pDomain->pci, tag, off + 2, CARD16) = val;
+	} else {
+	    PciReg(pDomain->pci, tag, off    , CARD8) = val;
+	    PciReg(pDomain->pci, tag, off + 1, CARD8) = val >> 8;
+	    PciReg(pDomain->pci, tag, off + 2, CARD8) = val >> 16;
+	    PciReg(pDomain->pci, tag, off + 3, CARD8) = val >> 24;
+	}
+    }
+}
+
+static void
+sabrePciCfgSetBits32(PCITAG tag, int off, CARD32 mask, CARD32 bits)
+{
+    CARD32 PciVal;
+
+    PciVal = sabrePciCfgRead32(tag, off);
+    PciVal &= ~mask;
+    PciVal |= bits;
+    sabrePciCfgWrite32(tag, off, PciVal);
+}
+
+static pciBusFuncs_t sabrePCIFunctions =
+{
+    sabrePciCfgRead32,
+    sabrePciCfgWrite32,
+    sabrePciCfgSetBits32,
+    pciAddrNOOP,
+    pciAddrNOOP
+};
+
+static int pagemask;
+
+/* Scan PROM for all PCI host bridges in the system */
+void
+sparcPciInit(void)
+{
+    int node, node2;
+
+    if (!xf86LinearVidMem())
+	return;
+
+    apertureFd = open(apertureDevName, O_RDWR);
+    if (apertureFd < 0) {
+	xf86Msg(X_ERROR,
+	    "sparcPciInit:  open failure:  %s\n", strerror(errno));
+	return;
+    }
+
+    sparcPromInit();
+    pagemask = getpagesize() - 1;
+
+    for (node = promGetChild(promRootNode);
+	 node;
+	 node = promGetSibling(node)) {
+	unsigned long long pci_addr;
+	sparcDomainRec     domain;
+	sparcDomainPtr     pDomain;
+	pciBusFuncs_p      pFunctions;
+	char               *prop_val;
+	int                prop_len, bus;
+
+	prop_val = promGetProperty("name", &prop_len);
+	/* Some PROMs include the trailing null;  some don't */
+	if (!prop_val || (prop_len < 3) || (prop_len > 4) ||
+	    strcmp(prop_val, "pci"))
+	    continue;
+
+	prop_val = promGetProperty("model", &prop_len);
+	if (!prop_val || (prop_len <= 0)) {
+	    prop_val = promGetProperty("compatible", &prop_len);
+	    if (!prop_val || (prop_len <= 0))
+		continue;
+	}
+
+	pFunctions = &sparcPCIFunctions;
+	(void)memset(&domain, 0, sizeof(domain));
+
+	if (!strncmp("SUNW,sabre",   prop_val, prop_len) ||
+	    !strncmp("pci108e,a000", prop_val, prop_len) ||
+	    !strncmp("pci108e,a001", prop_val, prop_len)) {
+	    /*
+	     * There can only be one "Sabre" bridge in a system.  It provides
+	     * PCI configuration space, a 24-bit I/O space and a 32-bit memory
+	     * space, all three of which are at fixed physical CPU addresses.
+	     */
+	    static Bool sabre_seen = FALSE;
+
+	    xf86Msg(X_INFO,
+		"Sabre or Hummingbird PCI host bridge found (\"%s\")\n",
+		prop_val);
+
+	    /* There can only be one Sabre */
+	    if (sabre_seen)
+		continue;
+	    sabre_seen = TRUE;
+
+	    /* Get "bus-range" property */
+	    prop_val = promGetProperty("bus-range", &prop_len);
+	    if (!prop_val || (prop_len != 8) ||
+		(((unsigned int *)prop_val)[0]) ||
+		(((unsigned int *)prop_val)[1] >= 256))
+		continue;
+
+	    pci_addr         = 0x01fe01000000ull;
+	    domain.io_addr   = 0x01fe02000000ull;
+	    domain.io_size   = 0x000001000000ull;
+	    domain.mem_addr  = 0x01ff00000000ull;
+	    domain.mem_size  = 0x000100000000ull;
+	    domain.bus_min   = 0;			/* Always */
+	    domain.bus_max   = ((int *)prop_val)[1];
+
+	    pFunctions = &sabrePCIFunctions;
+	} else
+	if (!strncmp("SUNW,psycho",  prop_val, prop_len) ||
+	    !strncmp("pci108e,8000", prop_val, prop_len)) {
+	    /*
+	     * A "Psycho" host bridge provides two PCI interfaces, each with
+	     * its own 16-bit I/O and 31-bit memory spaces.  Both share the
+	     * same PCI configuration space.  Here, they are assigned separate
+	     * domain numbers to prevent unintentional I/O and/or memory
+	     * resource conflicts.
+	     */
+	    xf86Msg(X_INFO,
+		"Psycho PCI host bridge found (\"%s\")\n", prop_val);
+
+	    /* Get "bus-range" property */
+	    prop_val = promGetProperty("bus-range", &prop_len);
+	    if (!prop_val || (prop_len != 8) ||
+		(((unsigned int *)prop_val)[1] >= 256) ||
+		(((unsigned int *)prop_val)[0] > ((unsigned int *)prop_val)[1]))
+		continue;
+
+	    domain.bus_min = ((int *)prop_val)[0];
+	    domain.bus_max = ((int *)prop_val)[1];
+
+	    /* Get "ranges" property */
+	    prop_val = promGetProperty("ranges", &prop_len);
+	    if (!prop_val || (prop_len != 112) ||
+		prop_val[0] || (prop_val[28] != 0x01u) ||
+		(prop_val[56] != 0x02u) || (prop_val[84] != 0x03u) ||
+		(((unsigned int *)prop_val)[4] != 0x01000000u) ||
+		((unsigned int *)prop_val)[5] ||
+		((unsigned int *)prop_val)[12] ||
+		(((unsigned int *)prop_val)[13] != 0x00010000u) ||
+		((unsigned int *)prop_val)[19] ||
+		(((unsigned int *)prop_val)[20] != 0x80000000u) ||
+		((((unsigned int *)prop_val)[11] & ~0x00010000u) !=
+		 0x02000000u) ||
+		(((unsigned int *)prop_val)[18] & ~0x80000000u) ||
+		(((unsigned int *)prop_val)[3] !=
+		 ((unsigned int *)prop_val)[10]) ||
+		(((unsigned int *)prop_val)[17] !=
+		 ((unsigned int *)prop_val)[24]) ||
+		(((unsigned int *)prop_val)[18] !=
+		 ((unsigned int *)prop_val)[25]) ||
+		(((unsigned int *)prop_val)[19] !=
+		 ((unsigned int *)prop_val)[26]) ||
+		(((unsigned int *)prop_val)[20] !=
+		 ((unsigned int *)prop_val)[27]))
+		continue;
+
+	    /* Use memcpy() to avoid alignment issues */
+	    (void)memcpy(&pci_addr, prop_val + 12,
+			 sizeof(pci_addr));
+	    (void)memcpy(&domain.io_addr, prop_val + 40,
+			 sizeof(domain.io_addr));
+	    (void)memcpy(&domain.mem_addr, prop_val + 68,
+			 sizeof(domain.mem_addr));
+
+	    domain.io_size  = 0x000000010000ull;
+	    domain.mem_size = 0x000080000000ull;
+	} else
+	if (!strncmp("SUNW,schizo",  prop_val, prop_len) ||
+	    !strncmp("pci108e,8001", prop_val, prop_len)) {
+	    /*
+	     * I have no docs on the "Schizo", but judging from the Linux
+	     * kernel, it also provides two PCI domains.  Each PCI
+	     * configuration space is the usual 16M in size, followed by a
+	     * variable-length I/O space.  Each domain also provides a
+	     * variable-length memory space.  The kernel seems to think the I/O
+	     * spaces are 16M long, and the memory spaces, 2G, but these
+	     * assumptions are actually only present in source code comments.
+	     * Sun has, however, confirmed to me the validity of these
+	     * assumptions.
+	     */
+	    volatile unsigned long long mem_match, mem_mask, io_match, io_mask;
+	    unsigned long Offset;
+	    pointer pSchizo;
+
+	    xf86Msg(X_INFO,
+		"Schizo PCI host bridge found (\"%s\")\n", prop_val);
+
+	    /* Get "bus-range" property */
+	    prop_val = promGetProperty("bus-range", &prop_len);
+	    if (!prop_val || (prop_len != 8) ||
+		(((unsigned int *)prop_val)[1] >= 256) ||
+		(((unsigned int *)prop_val)[0] > ((unsigned int *)prop_val)[1]))
+		continue;
+
+	    domain.bus_min = ((int *)prop_val)[0];
+	    domain.bus_max = ((int *)prop_val)[1];
+
+	    /* Get "reg" property */
+	    prop_val = promGetProperty("reg", &prop_len);
+	    if (!prop_val || (prop_len != 48))
+		continue;
+
+	    /* Temporarily map some of Schizo's registers */
+	    pSchizo = sparcMapAperture(-1, VIDMEM_MMIO,
+		((unsigned long long *)prop_val)[2] - 0x000000010000ull,
+		0x00010000ul);
+
+	    /* Determine where PCI config, I/O and memory spaces reside */
+	    if ((((unsigned long long *)prop_val)[0] & 0x000000700000ull) ==
+		0x000000600000ull)
+		Offset = 0x0040;
+	    else
+		Offset = 0x0060;
+
+	    mem_match = PciReg(pSchizo, 0, Offset, unsigned long long);
+	    mem_mask  = PciReg(pSchizo, 0, Offset + 8, unsigned long long);
+	    io_match  = PciReg(pSchizo, 0, Offset + 16, unsigned long long);
+	    io_mask   = PciReg(pSchizo, 0, Offset + 24, unsigned long long);
+
+	    /* Unmap Schizo registers */
+	    xf86UnMapVidMem(-1, pSchizo, 0x00010000ul);
+
+	    /* Calculate sizes */
+	    mem_mask = (((mem_mask - 1) ^ mem_mask) >> 1) + 1;
+	    io_mask  = (((io_mask  - 1) ^ io_mask ) >> 1) + 1;
+
+	    if (io_mask <= 0x000001000000ull)	/* Nothing left for I/O */
+		continue;
+
+	    domain.mem_addr = mem_match & ~0x8000000000000000ull;
+	    domain.mem_size = mem_mask;
+	    pci_addr        = io_match  & ~0x8000000000000000ull;
+	    domain.io_addr  = pci_addr  +  0x0000000001000000ull;
+	    domain.io_size  = io_mask   -  0x0000000001000000ull;
+	} else {
+	    xf86Msg(X_WARNING, "Unknown PCI host bridge: \"%s\"\n", prop_val);
+	    continue;
+	}
+
+	/* Only map as much PCI configuration as we need */
+	domain.pci = (char *)sparcMapAperture(-1, VIDMEM_MMIO,
+	    pci_addr + PCI_MAKE_TAG(domain.bus_min, 0, 0),
+	    PCI_MAKE_TAG(domain.bus_max - domain.bus_min + 1, 0, 0)) -
+	    PCI_MAKE_TAG(domain.bus_min, 0, 0);
+
+	/* Allocate a domain record */
+	pDomain = xnfalloc(sizeof(sparcDomainRec));
+	*pDomain = domain;
+
+	/*
+	 * Allocate and prime pciBusInfo records.  These are allocated one at a
+	 * time because those for empty buses are eventually released.
+	 */
+	bus = pDomain->bus_min =
+	    PCI_MAKE_BUS(pciNumDomains, domain.bus_min);
+	pciNumBuses = pDomain->bus_max =
+	    PCI_MAKE_BUS(pciNumDomains, domain.bus_max) + 1;
+
+	pciBusInfo[bus] = xnfcalloc(1, sizeof(pciBusInfo_t));
+	pciBusInfo[bus]->configMech = PCI_CFG_MECH_OTHER;
+	pciBusInfo[bus]->numDevices = 32;
+	pciBusInfo[bus]->funcs = pFunctions;
+	pciBusInfo[bus]->pciBusPriv = pDomain;
+	while (++bus < pciNumBuses) {
+	    pciBusInfo[bus] = xnfalloc(sizeof(pciBusInfo_t));
+	    *(pciBusInfo[bus]) = *(pciBusInfo[bus - 1]);
+	    pciBusInfo[bus]->funcs = &sparcPCIFunctions;
+	}
+
+	/* Next domain, please... */
+	xf86DomainInfo[pciNumDomains++] = pDomain;
+
+	/*
+	 * OK, enough of the straight-forward stuff.  Time to deal with some
+	 * brokenness...
+	 *
+	 * The PCI specs require that when a bus transaction remains unclaimed
+	 * for too long, the master entity on that bus is to cancel the
+	 * transaction it issued or passed on with a master abort.  Two
+	 * outcomes are possible:
+	 *
+	 * - the master abort can be treated as an error that is propogated
+	 *   back through the bus tree to the entity that ultimately originated
+	 *   the transaction; or
+	 * - the transaction can be allowed to complete normally, which means
+	 *   that writes are ignored and reads return all ones.
+	 *
+	 * In the first case, if the CPU happens to be at the tail end of the
+	 * tree path through one of its host bridges, it will be told there is
+	 * a hardware mal-function, despite being generated by software.
+	 *
+	 * For a software function (be it firmware, OS or userland application)
+	 * to determine how a PCI bus tree is populated, it must be able to
+	 * detect when master aborts occur.  Obviously, PCI discovery is much
+	 * simpler when master aborts are allowed to complete normally.
+	 *
+	 * Unfortunately, a number of non-Intel PCI implementations have chosen
+	 * to treat master aborts as severe errors.  The net effect is to
+	 * cripple PCI discovery algorithms in userland.
+	 *
+	 * On SPARCs, master aborts cause a number of different behaviours,
+	 * including delivering a signal to the userland application, rebooting
+	 * the system, "dropping down" to firmware, or, worst of all, bus
+	 * lockouts.  Even in the first case, the SIGBUS signal that is
+	 * eventually generated isn't delivered in a timely enough fashion to
+	 * allow an application to reliably detect the master abort that
+	 * ultimately caused it.
+	 *
+	 * This can be somewhat mitigated.  On all architectures, master aborts
+	 * that occur on secondary buses can be forced to complete normally
+	 * because the PCI-to-PCI bridges that serve them are governed by an
+	 * industry-wide specification.  (This is just another way of saying
+	 * that whatever justification there might be for erroring out master
+	 * aborts is deemed by the industry as insufficient to generate more
+	 * PCI non-compliance than there already is...)
+	 *
+	 * This leaves us with master aborts that occur on primary buses.
+	 * There is no specification for host-to-PCI bridges.  Bridges used in
+	 * SPARCs can be told to ignore all PCI errors, but not specifically
+	 * master aborts.  Not only is this too coarse-grained, but
+	 * master-aborted read transactions on the primary bus end up returning
+	 * garbage rather than all ones.
+	 *
+	 * I have elected to work around this the only way I can think of doing
+	 * so right now.  The following scans an additional PROM level and
+	 * builds a device/function map for the primary bus.  I can only hope
+	 * this PROM information represents all devices on the primary bus,
+	 * rather than only a subset of them.
+	 *
+	 * Master aborts are useful in other ways too, that are not addressed
+	 * here.  These include determining whether or not a domain provides
+	 * VGA, or if a PCI device actually implements PCI disablement.
+	 *
+	 * ---  TSI @ UQV  2001.09.19
+	 */
+	for (node2 = promGetChild(node);
+	     node2;
+	     node2 = promGetSibling(node2)) {
+	    /* Get "reg" property */
+	    prop_val = promGetProperty("reg", &prop_len);
+	    if (!prop_val || (prop_len % 20))
+		continue;
+
+	    /*
+	     * It's unnecessary to scan the entire "reg" property, but I'll do
+	     * so anyway.
+	     */
+	    prop_len /= 20;
+	    for (;  prop_len--;  prop_val += 20)
+		SetBitInMap(PCI_DFN_FROM_TAG(*(PCITAG *)prop_val),
+		    pDomain->dfn_mask);
+	}
+
+	/* Assume the host bridge is device 0, function 0 on its bus */
+	SetBitInMap(0, pDomain->dfn_mask);
+    }
+
+    sparcPromClose();
+
+    close(apertureFd);
+    apertureFd = -1;
+}
+
+#ifndef INCLUDE_XF86_NO_DOMAIN
+
+_X_EXPORT int
+xf86GetPciDomain(PCITAG Tag)
+{
+    return PCI_DOM_FROM_TAG(Tag);
+}
+
+_X_EXPORT pointer
+xf86MapDomainMemory(int ScreenNum, int Flags, PCITAG Tag,
+		    ADDRESS Base, unsigned long Size)
+{
+    sparcDomainPtr pDomain;
+    pointer        result;
+    int            domain = PCI_DOM_FROM_TAG(Tag);
+
+    if ((domain <= 0) || (domain >= pciNumDomains) ||
+	!(pDomain = xf86DomainInfo[domain]) ||
+	(((unsigned long long)Base + (unsigned long long)Size) >
+	 pDomain->mem_size))
+	FatalError("xf86MapDomainMemory() called with invalid parameters.\n");
+
+    result = sparcMapAperture(ScreenNum, Flags, pDomain->mem_addr + Base, Size);
+
+    if (apertureFd >= 0) {
+	close(apertureFd);
+	apertureFd = -1;
+    }
+
+    return result;
+}
+
+_X_EXPORT IOADDRESS
+xf86MapLegacyIO(int ScreenNum, int Flags, PCITAG Tag,
+		IOADDRESS Base, unsigned long Size)
+{
+    sparcDomainPtr pDomain;
+    int            domain = PCI_DOM_FROM_TAG(Tag);
+
+    if ((domain <= 0) || (domain >= pciNumDomains) ||
+	!(pDomain = xf86DomainInfo[domain]) ||
+	(((unsigned long long)Base + (unsigned long long)Size) >
+	 pDomain->io_size))
+	FatalError("xf86MapLegacyIO() called with invalid parameters.\n");
+
+    /* Permanently map all of I/O space */
+    if (!pDomain->io) {
+	pDomain->io = sparcMapAperture(ScreenNum, Flags,
+	    pDomain->io_addr, pDomain->io_size);
+
+	if (apertureFd >= 0) {
+	    close(apertureFd);
+	    apertureFd = -1;
+	}
+    }
+
+    return (IOADDRESS)pDomain->io + Base;
+}
+
+resPtr
+xf86AccResFromOS(resPtr pRes)
+{
+    sparcDomainPtr pDomain;
+    resRange       range;
+    int            domain;
+
+    for (domain = 1;  domain < pciNumDomains;  domain++) {
+	if (!(pDomain = xf86DomainInfo[domain]))
+	    continue;
+
+	/*
+	 * At minimum, the top and bottom resources must be claimed, so that
+	 * resources that are (or appear to be) unallocated can be relocated.
+	 */
+	RANGE(range, 0x00000000u, 0x0009ffffu,
+	      RANGE_TYPE(ResExcMemBlock, domain));
+	pRes = xf86AddResToList(pRes, &range, -1);
+	RANGE(range, 0x000c0000u, 0x000effffu,
+	      RANGE_TYPE(ResExcMemBlock, domain));
+	pRes = xf86AddResToList(pRes, &range, -1);
+	RANGE(range, 0x000f0000u, 0x000fffffu,
+	      RANGE_TYPE(ResExcMemBlock, domain));
+	pRes = xf86AddResToList(pRes, &range, -1);
+
+	RANGE(range, pDomain->mem_size - 1, pDomain->mem_size - 1,
+	      RANGE_TYPE(ResExcMemBlock, domain));
+	pRes = xf86AddResToList(pRes, &range, -1);
+
+	RANGE(range, 0x00000000u, 0x00000000u,
+	      RANGE_TYPE(ResExcIoBlock, domain));
+	pRes = xf86AddResToList(pRes, &range, -1);
+	RANGE(range, pDomain->io_size - 1, pDomain->io_size - 1,
+	      RANGE_TYPE(ResExcIoBlock, domain));
+	pRes = xf86AddResToList(pRes, &range, -1);
+    }
+
+    return pRes;
+}
+
+#endif /* !INCLUDE_XF86_NO_DOMAIN */
+
+#endif /* defined(sun) */
+
+#if defined(ARCH_PCI_PCI_BRIDGE)
+
+/* Definitions specific to Sun's APB P2P bridge (a.k.a. Simba) */
+#define APB_IO_ADDRESS_MAP	0xDE
+#define APB_MEM_ADDRESS_MAP	0xDF
+
+/*
+ * Simba's can only occur on bus 0.  Furthermore, Simba's must have a non-zero
+ * device/function number because the Sabre interface they must connect to
+ * occupies the 0:0:0 slot.  Also, there can be only one Sabre interface in the
+ * system, and therefore, only one Simba function can route any particular
+ * resource.  Thus, it is appropriate to use a single set of static variables
+ * to hold the tag of the Simba function routing a VGA resource range at any
+ * one time, and to test these variables for non-zero to determine whether or
+ * not the Sabre would master-abort a VGA access (and kill the system).
+ *
+ * The trick is to determine when it is safe to re-route VGA, because doing so
+ * re-routes much more.
+ */
+static PCITAG simbavgaIOTag = 0, simbavgaMemTag = 0;
+static Bool simbavgaRoutingAllow = TRUE;
+
+/*
+ * Scan the bus subtree rooted at 'bus' for a non-display device that might be
+ * decoding the bottom 2 MB of I/O space and/or the bottom 512 MB of memory
+ * space.  Reset simbavgaRoutingAllow if such a device is found.
+ *
+ * XXX For now, this is very conservative and should be made less so as the
+ *     need arises.
+ */
+static void
+simbaCheckBus(CARD16 pcicommand, int bus)
+{
+    pciConfigPtr pPCI, *ppPCI = xf86scanpci(0);
+
+    while ((pPCI = *ppPCI++)) {
+	if (pPCI->busnum < bus)
+	    continue;
+	if (pPCI->busnum > bus)
+	    break;
+
+	/* XXX Assume all devices respect PCI disablement */
+	if (!(pcicommand & pPCI->pci_command))
+	    continue;
+
+	/* XXX This doesn't deal with mis-advertised classes */
+	switch (pPCI->pci_base_class) {
+	case PCI_CLASS_PREHISTORIC:
+	    if (pPCI->pci_sub_class == PCI_SUBCLASS_PREHISTORIC_VGA)
+		continue;	/* Ignore VGA */
+	    break;
+
+	case PCI_CLASS_DISPLAY:
+	    continue;
+
+	case PCI_CLASS_BRIDGE:
+	    switch (pPCI->pci_sub_class) {
+	    case PCI_SUBCLASS_BRIDGE_PCI:
+	    case PCI_SUBCLASS_BRIDGE_CARDBUS:
+		/* Scan secondary bus */
+		/* XXX First check bridge routing? */
+		simbaCheckBus(pcicommand & pPCI->pci_command,
+		    PCI_SECONDARY_BUS_EXTRACT(pPCI->pci_pp_bus_register,
+			pPCI->tag));
+		if (!simbavgaRoutingAllow)
+		    return;
+
+	    default:
+		break;
+	    }
+
+	default:
+	    break;
+	}
+
+	/*
+	 * XXX We could check the device's bases here, but PCI doesn't limit
+	 *     the device's decoding to them.
+	 */
+
+	simbavgaRoutingAllow = FALSE;
+	break;
+    }
+}
+
+static pciConfigPtr
+simbaVerifyBus(int bus)
+{
+    pciConfigPtr pPCI;
+    if ((bus < 0) || (bus >= pciNumBuses) ||
+	!pciBusInfo[bus] || !(pPCI = pciBusInfo[bus]->bridge) ||
+	(pPCI->pci_device_vendor != DEVID(VENDOR_SUN, CHIP_SIMBA)))
+	return NULL;
+
+    return pPCI;
+}
+
+static CARD16
+simbaControlBridge(int bus, CARD16 mask, CARD16 value)
+{
+    pciConfigPtr pPCI;
+    CARD16 current = 0, tmp;
+    CARD8 iomap, memmap;
+
+    if ((pPCI = simbaVerifyBus(bus))) {
+	/*
+	 * The Simba does not implement VGA enablement as described in the P2P
+	 * spec.  It does however route I/O and memory in large enough chunks
+	 * so that we can determine were VGA resources would be routed
+	 * (including ISA VGA I/O aliases).  We can allow changes to that
+	 * routing only under certain circumstances.
+	 */
+	iomap = pciReadByte(pPCI->tag, APB_IO_ADDRESS_MAP);
+	memmap = pciReadByte(pPCI->tag, APB_MEM_ADDRESS_MAP);
+	if (iomap & memmap & 0x01) {
+	    current |= PCI_PCI_BRIDGE_VGA_EN;
+	    if ((mask & PCI_PCI_BRIDGE_VGA_EN) &&
+		!(value & PCI_PCI_BRIDGE_VGA_EN)) {
+		if (!simbavgaRoutingAllow) {
+		    xf86MsgVerb(X_WARNING, 3, "Attempt to disable VGA routing"
+				" through Simba at %x:%x:%x disallowed.\n",
+				pPCI->busnum, pPCI->devnum, pPCI->funcnum);
+		    value |= PCI_PCI_BRIDGE_VGA_EN;
+		} else {
+		    pciWriteByte(pPCI->tag, APB_IO_ADDRESS_MAP,
+				 iomap & ~0x01);
+		    pciWriteByte(pPCI->tag, APB_MEM_ADDRESS_MAP,
+				 memmap & ~0x01);
+		    simbavgaIOTag = simbavgaMemTag = 0;
+		}
+	    }
+	} else {
+	    if (mask & value & PCI_PCI_BRIDGE_VGA_EN) {
+		if (!simbavgaRoutingAllow) {
+		    xf86MsgVerb(X_WARNING, 3, "Attempt to enable VGA routing"
+				" through Simba at %x:%x:%x disallowed.\n",
+				pPCI->busnum, pPCI->devnum, pPCI->funcnum);
+		    value &= ~PCI_PCI_BRIDGE_VGA_EN;
+		} else {
+		    if (pPCI->tag != simbavgaIOTag) {
+			if (simbavgaIOTag) {
+			    tmp = pciReadByte(simbavgaIOTag,
+					      APB_IO_ADDRESS_MAP);
+			    pciWriteByte(simbavgaIOTag, APB_IO_ADDRESS_MAP,
+					 tmp & ~0x01);
+			}
+
+			pciWriteByte(pPCI->tag, APB_IO_ADDRESS_MAP,
+				     iomap | 0x01);
+			simbavgaIOTag = pPCI->tag;
+		    }
+
+		    if (pPCI->tag != simbavgaMemTag) {
+			if (simbavgaMemTag) {
+			    tmp = pciReadByte(simbavgaMemTag,
+					      APB_MEM_ADDRESS_MAP);
+			    pciWriteByte(simbavgaMemTag, APB_MEM_ADDRESS_MAP,
+					 tmp & ~0x01);
+			}
+
+			pciWriteByte(pPCI->tag, APB_MEM_ADDRESS_MAP,
+				     memmap | 0x01);
+			simbavgaMemTag = pPCI->tag;
+		    }
+		}
+	    }
+	}
+
+	/* Move on to master abort failure enablement (as per P2P spec) */
+	tmp = pciReadWord(pPCI->tag, PCI_PCI_BRIDGE_CONTROL_REG);
+	current |= tmp;
+	if (tmp & PCI_PCI_BRIDGE_MASTER_ABORT_EN) {
+	    if ((mask & PCI_PCI_BRIDGE_MASTER_ABORT_EN) &&
+		!(value & PCI_PCI_BRIDGE_MASTER_ABORT_EN))
+		pciWriteWord(pPCI->tag, PCI_PCI_BRIDGE_CONTROL_REG,
+			     tmp & ~PCI_PCI_BRIDGE_MASTER_ABORT_EN);
+	} else {
+	    if (mask & value & PCI_PCI_BRIDGE_MASTER_ABORT_EN)
+		pciWriteWord(pPCI->tag, PCI_PCI_BRIDGE_CONTROL_REG,
+			     tmp | PCI_PCI_BRIDGE_MASTER_ABORT_EN);
+	}
+
+	/* Insert emulation of other P2P controls here */
+    }
+
+    return (current & ~mask) | (value & mask);
+}
+
+static void
+simbaGetBridgeResources(int bus,
+			pointer *ppIoRes,
+			pointer *ppMemRes,
+			pointer *ppPmemRes)
+{
+    pciConfigPtr pPCI = simbaVerifyBus(bus);
+    resRange range;
+    int i;
+
+    if (!pPCI)
+	return;
+
+    if (ppIoRes) {
+	xf86FreeResList(*ppIoRes);
+	*ppIoRes = NULL;
+
+	if (pPCI->pci_command & PCI_CMD_IO_ENABLE) {
+	    unsigned char iomap = pciReadByte(pPCI->tag, APB_IO_ADDRESS_MAP);
+	    if (simbavgaRoutingAllow)
+		iomap |= 0x01;
+	    for (i = 0;  i < 8;  i++) {
+		if (iomap & (1 << i)) {
+		    RANGE(range, i << 21, ((i + 1) << 21) - 1,
+			  RANGE_TYPE(ResExcIoBlock,
+				     xf86GetPciDomain(pPCI->tag)));
+		    *ppIoRes = xf86AddResToList(*ppIoRes, &range, -1);
+		}
+	    }
+	}
+    }
+
+    if (ppMemRes) {
+	xf86FreeResList(*ppMemRes);
+	*ppMemRes = NULL;
+
+	if (pPCI->pci_command & PCI_CMD_MEM_ENABLE) {
+	    unsigned char memmap = pciReadByte(pPCI->tag, APB_MEM_ADDRESS_MAP);
+	    if (simbavgaRoutingAllow)
+		memmap |= 0x01;
+	    for (i = 0;  i < 8;  i++) {
+		if (memmap & (1 << i)) {
+		    RANGE(range, i << 29, ((i + 1) << 29) - 1,
+			  RANGE_TYPE(ResExcMemBlock,
+				     xf86GetPciDomain(pPCI->tag)));
+		    *ppMemRes = xf86AddResToList(*ppMemRes, &range, -1);
+		}
+	    }
+	}
+    }
+
+    if (ppPmemRes) {
+	xf86FreeResList(*ppPmemRes);
+	*ppPmemRes = NULL;
+    }
+}
+
+void ARCH_PCI_PCI_BRIDGE(pciConfigPtr pPCI)
+{
+    static pciBusFuncs_t simbaBusFuncs;
+    pciBusInfo_t *pBusInfo;
+    CARD16 pcicommand;
+
+    if (pPCI->pci_device_vendor != DEVID(VENDOR_SUN, CHIP_SIMBA))
+	return;
+
+    pBusInfo = pPCI->businfo;
+
+    simbaBusFuncs = *(pBusInfo->funcs);
+    simbaBusFuncs.pciControlBridge = simbaControlBridge;
+    simbaBusFuncs.pciGetBridgeResources = simbaGetBridgeResources;
+
+    pBusInfo->funcs = &simbaBusFuncs;
+
+    if (!simbavgaRoutingAllow)
+	return;
+
+    pcicommand = 0;
+
+    if (pciReadByte(pPCI->tag, APB_IO_ADDRESS_MAP) & 0x01) {
+	pcicommand |= PCI_CMD_IO_ENABLE;
+	simbavgaIOTag = pPCI->tag;
+    }
+
+    if (pciReadByte(pPCI->tag, APB_MEM_ADDRESS_MAP) & 0x01) {
+	pcicommand |= PCI_CMD_MEM_ENABLE;
+	simbavgaMemTag = pPCI->tag;
+    }
+
+    if (!pcicommand)
+	return;
+
+    simbaCheckBus(pcicommand,
+	PCI_SECONDARY_BUS_EXTRACT(pPCI->pci_pp_bus_register, pPCI->tag));
+}
+
+#endif /* defined(ARCH_PCI_PCI_BRIDGE) */
diff --git a/xorg-server/hw/xfree86/os-support/bus/xf86Pci.h b/xorg-server/hw/xfree86/os-support/bus/xf86Pci.h
new file mode 100644
index 000000000..2b8a4f76b
--- /dev/null
+++ b/xorg-server/hw/xfree86/os-support/bus/xf86Pci.h
@@ -0,0 +1,265 @@
+/*
+ * Copyright 1998 by Concurrent Computer Corporation
+ *
+ * Permission to use, copy, modify, distribute, and sell this software
+ * and its documentation for any purpose is hereby granted without fee,
+ * provided that the above copyright notice appear in all copies and that
+ * both that copyright notice and this permission notice appear in
+ * supporting documentation, and that the name of Concurrent Computer
+ * Corporation not be used in advertising or publicity pertaining to
+ * distribution of the software without specific, written prior
+ * permission.  Concurrent Computer Corporation makes no representations
+ * about the suitability of this software for any purpose.  It is
+ * provided "as is" without express or implied warranty.
+ *
+ * CONCURRENT COMPUTER CORPORATION DISCLAIMS ALL WARRANTIES WITH REGARD
+ * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL CONCURRENT COMPUTER CORPORATION BE
+ * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY
+ * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
+ * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,
+ * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS
+ * SOFTWARE.
+ *
+ * Copyright 1998 by Metro Link Incorporated
+ *
+ * Permission to use, copy, modify, distribute, and sell this software
+ * and its documentation for any purpose is hereby granted without fee,
+ * provided that the above copyright notice appear in all copies and that
+ * both that copyright notice and this permission notice appear in
+ * supporting documentation, and that the name of Metro Link
+ * Incorporated not be used in advertising or publicity pertaining to
+ * distribution of the software without specific, written prior
+ * permission.  Metro Link Incorporated makes no representations
+ * about the suitability of this software for any purpose.  It is
+ * provided "as is" without express or implied warranty.
+ *
+ * METRO LINK INCORPORATED DISCLAIMS ALL WARRANTIES WITH REGARD
+ * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL METRO LINK INCORPORATED BE
+ * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY
+ * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
+ * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,
+ * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS
+ * SOFTWARE.
+ *
+ * This file is derived in part from the original xf86_PCI.h that included
+ * following copyright message:
+ *
+ * Copyright 1995 by Robin Cutshaw <robin@XFree86.Org>
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that
+ * copyright notice and this permission notice appear in supporting
+ * documentation, and that the names of the above listed copyright holder(s)
+ * not be used in advertising or publicity pertaining to distribution of
+ * the software without specific, written prior permission.  The above listed
+ * copyright holder(s) make(s) no representations about the suitability of this
+ * software for any purpose.  It is provided "as is" without express or
+ * implied warranty.
+ *
+ * THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM(S) ALL WARRANTIES WITH REGARD
+ * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE
+ * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY
+ * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER
+ * IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
+ * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+/*
+ * Copyright (c) 1999-2003 by The XFree86 Project, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of the copyright holder(s)
+ * and author(s) shall not be used in advertising or otherwise to promote
+ * the sale, use or other dealings in this Software without prior written
+ * authorization from the copyright holder(s) and author(s).
+ */
+
+
+/*
+ * This file contains just the public interface to the PCI code.
+ * Drivers should use this file rather than Pci.h.
+ */
+
+#ifndef _XF86PCI_H
+#define _XF86PCI_H 1
+#include <X11/Xarch.h>
+#include <X11/Xfuncproto.h>
+#include "misc.h"
+#include <pciaccess.h>
+
+/*
+ * PCI cfg space definitions (e.g. stuff right out of the PCI spec)
+ */
+
+/* Device identification register */
+#define PCI_ID_REG			0x00
+
+/* Command and status register */
+#define PCI_CMD_STAT_REG		0x04
+#define PCI_CMD_BASE_REG		0x10
+#define PCI_CMD_BIOS_REG		0x30
+#define PCI_CMD_MASK			0xffff
+#define PCI_CMD_IO_ENABLE		0x01
+#define PCI_CMD_MEM_ENABLE		0x02
+#define PCI_CMD_MASTER_ENABLE		0x04
+#define PCI_CMD_SPECIAL_ENABLE		0x08
+#define PCI_CMD_INVALIDATE_ENABLE	0x10
+#define PCI_CMD_PALETTE_ENABLE		0x20
+#define PCI_CMD_PARITY_ENABLE		0x40
+#define PCI_CMD_STEPPING_ENABLE		0x80
+#define PCI_CMD_SERR_ENABLE		0x100
+#define PCI_CMD_BACKTOBACK_ENABLE	0x200
+#define PCI_CMD_BIOS_ENABLE		0x01
+
+/* base class */
+#define PCI_CLASS_REG		0x08
+#define PCI_CLASS_MASK		0xff000000
+#define PCI_CLASS_SHIFT		24
+#define PCI_CLASS_EXTRACT(x)	\
+	(((x) & PCI_CLASS_MASK) >> PCI_CLASS_SHIFT)
+
+/* base class values */
+#define PCI_CLASS_PREHISTORIC		0x00
+#define PCI_CLASS_MASS_STORAGE		0x01
+#define PCI_CLASS_NETWORK		0x02
+#define PCI_CLASS_DISPLAY		0x03
+#define PCI_CLASS_MULTIMEDIA		0x04
+#define PCI_CLASS_MEMORY		0x05
+#define PCI_CLASS_BRIDGE		0x06
+#define PCI_CLASS_COMMUNICATIONS	0x07
+#define PCI_CLASS_SYSPERIPH		0x08
+#define PCI_CLASS_INPUT			0x09
+#define PCI_CLASS_DOCKING		0x0a
+#define PCI_CLASS_PROCESSOR		0x0b
+#define PCI_CLASS_SERIALBUS		0x0c
+#define PCI_CLASS_WIRELESS		0x0d
+#define PCI_CLASS_I2O			0x0e
+#define PCI_CLASS_SATELLITE		0x0f
+#define PCI_CLASS_CRYPT			0x10
+#define PCI_CLASS_DATA_ACQUISTION	0x11
+#define PCI_CLASS_UNDEFINED		0xff
+
+/* sub class */
+#define PCI_SUBCLASS_MASK	0x00ff0000
+#define PCI_SUBCLASS_SHIFT	16
+#define PCI_SUBCLASS_EXTRACT(x)	\
+	(((x) & PCI_SUBCLASS_MASK) >> PCI_SUBCLASS_SHIFT)
+
+/* Sub class values */
+/* 0x00 prehistoric subclasses */
+#define PCI_SUBCLASS_PREHISTORIC_MISC	0x00
+#define PCI_SUBCLASS_PREHISTORIC_VGA	0x01
+
+/* 0x03 display subclasses */
+#define PCI_SUBCLASS_DISPLAY_VGA	0x00
+#define PCI_SUBCLASS_DISPLAY_XGA	0x01
+#define PCI_SUBCLASS_DISPLAY_MISC	0x80
+
+/* 0x04 multimedia subclasses */
+#define PCI_SUBCLASS_MULTIMEDIA_VIDEO	0x00
+#define PCI_SUBCLASS_MULTIMEDIA_AUDIO	0x01
+#define PCI_SUBCLASS_MULTIMEDIA_MISC	0x80
+
+/* 0x06 bridge subclasses */
+#define PCI_SUBCLASS_BRIDGE_HOST	0x00
+#define PCI_SUBCLASS_BRIDGE_ISA		0x01
+#define PCI_SUBCLASS_BRIDGE_EISA	0x02
+#define PCI_SUBCLASS_BRIDGE_MC		0x03
+#define PCI_SUBCLASS_BRIDGE_PCI		0x04
+#define PCI_SUBCLASS_BRIDGE_PCMCIA	0x05
+#define PCI_SUBCLASS_BRIDGE_NUBUS	0x06
+#define PCI_SUBCLASS_BRIDGE_CARDBUS	0x07
+#define PCI_SUBCLASS_BRIDGE_RACEWAY	0x08
+#define PCI_SUBCLASS_BRIDGE_MISC	0x80
+#define PCI_IF_BRIDGE_PCI_SUBTRACTIVE	0x01
+
+/* 0x0b processor subclasses */
+#define PCI_SUBCLASS_PROCESSOR_386	0x00
+#define PCI_SUBCLASS_PROCESSOR_486	0x01
+#define PCI_SUBCLASS_PROCESSOR_PENTIUM	0x02
+#define PCI_SUBCLASS_PROCESSOR_ALPHA	0x10
+#define PCI_SUBCLASS_PROCESSOR_POWERPC	0x20
+#define PCI_SUBCLASS_PROCESSOR_MIPS	0x30
+#define PCI_SUBCLASS_PROCESSOR_COPROC	0x40
+
+/* PCI-PCI bridge mapping registers */
+#define PCI_PCI_BRIDGE_BUS_REG		0x18
+#define PCI_SUBORDINATE_BUS_MASK	0x00ff0000
+#define PCI_SECONDARY_BUS_MASK		0x0000ff00
+#define PCI_PRIMARY_BUS_MASK		0x000000ff
+
+#define PCI_PCI_BRIDGE_IO_REG		0x1c
+#define PCI_PCI_BRIDGE_MEM_REG		0x20
+#define PCI_PCI_BRIDGE_PMEM_REG		0x24
+
+#define PCI_PCI_BRIDGE_CONTROL_REG	0x3E
+#define PCI_PCI_BRIDGE_PARITY_EN	0x01
+#define PCI_PCI_BRIDGE_SERR_EN		0x02
+#define PCI_PCI_BRIDGE_ISA_EN		0x04
+#define PCI_PCI_BRIDGE_VGA_EN		0x08
+#define PCI_PCI_BRIDGE_MASTER_ABORT_EN	0x20
+#define PCI_PCI_BRIDGE_SECONDARY_RESET	0x40
+#define PCI_PCI_BRIDGE_FAST_B2B_EN	0x80
+
+/* Subsystem identification register */
+#define PCI_SUBSYSTEM_ID_REG		0x2c
+
+/* User defined cfg space regs */
+#define PCI_REG_USERCONFIG		0x40
+#define PCI_OPTION_REG			0x40
+
+/*
+ * Typedefs, etc...
+ */
+
+/* Primitive Types */
+typedef unsigned long ADDRESS;		/* Memory/PCI address */
+typedef unsigned long IOADDRESS;	/* Must be large enough for a pointer */
+typedef unsigned long PCITAG;
+
+typedef enum {
+    PCI_MEM,
+    PCI_MEM_SIZE,
+    PCI_MEM_SPARSE_BASE,
+    PCI_MEM_SPARSE_MASK,
+    PCI_IO,
+    PCI_IO_SIZE,
+    PCI_IO_SPARSE_BASE,
+    PCI_IO_SPARSE_MASK
+} PciAddrType;
+
+
+/* Public PCI access functions */
+ADDRESS	      pciBusAddrToHostAddr(PCITAG tag, PciAddrType type, ADDRESS addr);
+PCITAG	      pciTag(int busnum, int devnum, int funcnum);
+Bool xf86scanpci(void);
+
+extern int pciNumBuses;
+
+/* Domain access functions.  Some of these probably shouldn't be public */
+pointer xf86MapDomainMemory(int ScreenNum, int Flags, struct pci_device *dev,
+    ADDRESS Base, unsigned long Size);
+IOADDRESS xf86MapLegacyIO(struct pci_device *dev);
+
+#endif /* _XF86PCI_H */
diff --git a/xorg-server/hw/xfree86/os-support/bus/xf86Sbus.h b/xorg-server/hw/xfree86/os-support/bus/xf86Sbus.h
new file mode 100644
index 000000000..cff5e808a
--- /dev/null
+++ b/xorg-server/hw/xfree86/os-support/bus/xf86Sbus.h
@@ -0,0 +1,69 @@
+/*
+ * Platform specific SBUS and OpenPROM access declarations.
+ *
+ * Copyright (C) 2000 Jakub Jelinek (jakub@redhat.com)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * JAKUB JELINEK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifdef HAVE_XORG_CONFIG_H
+#include <xorg-config.h>
+#endif
+
+#ifndef _XF86_SBUS_H
+#define _XF86_SBUS_H
+
+#if defined(linux)
+#include <asm/types.h>
+#include <linux/fb.h>
+#include <asm/fbio.h>
+#include <asm/openpromio.h>
+#elif defined(SVR4)
+#include <sys/fbio.h>
+#include <sys/openpromio.h>
+#elif defined(__OpenBSD__) && defined(__sparc64__)
+/* XXX */
+#elif defined(CSRG_BASED)
+#if defined(__FreeBSD__)
+#include <sys/types.h>
+#include <sys/fbio.h>
+#include <dev/ofw/openpromio.h>
+#else
+#include <machine/fbio.h>
+#endif
+#else
+#include <sun/fbio.h>
+#endif
+
+#ifndef FBTYPE_SUNGP3
+#define FBTYPE_SUNGP3 -1
+#endif
+#ifndef FBTYPE_MDICOLOR
+#define FBTYPE_MDICOLOR -1
+#endif
+#ifndef FBTYPE_SUNLEO
+#define FBTYPE_SUNLEO -1
+#endif
+#ifndef FBTYPE_TCXCOLOR
+#define FBTYPE_TCXCOLOR -1
+#endif
+#ifndef FBTYPE_CREATOR
+#define FBTYPE_CREATOR -1
+#endif
+
+#endif /* _XF86_SBUS_H */
author	marha <marha@users.sourceforge.net>	2009-06-28 22:07:26 +0000
committer	marha <marha@users.sourceforge.net>	2009-06-28 22:07:26 +0000
commit	3562e78743202e43aec8727005182a2558117eca (patch)
tree	8f9113a77d12470c5c851a2a8e4cb02e89df7d43 /xorg-server/hw/xfree86/os-support/bus
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