svn merge https://vcxsrv.svn.sourceforge.net/svnroot/vcxsrv/branches/released .

1 files changed, 52 insertions, 0 deletions

diff --git a/xorg-server/hw/xfree86/os-support/misc/SlowBcopy.c b/xorg-server/hw/xfree86/os-support/misc/SlowBcopy.c
index 8a5017e52..182a3e6ec 100644
--- a/xorg-server/hw/xfree86/os-support/misc/SlowBcopy.c
+++ b/xorg-server/hw/xfree86/os-support/misc/SlowBcopy.c
@@ -1,8 +1,15 @@
+/*******************************************************************************
+  for Alpha Linux
+*******************************************************************************/
+ 
 /* 
  *   Create a dependency that should be immune from the effect of register
  *   renaming as is commonly seen in superscalar processors.  This should
  *   insert a minimum of 100-ns delays between reads/writes at clock rates
  *   up to 100 MHz---GGL
+ *   
+ *   Slowbcopy(char *src, char *dst, int count)   
+ *   
  */ 
 
 #ifdef HAVE_XORG_CONFIG_H
@@ -47,3 +54,48 @@ xf86SlowBcopy(unsigned char *src, unsigned char *dst, int len)
     while(len--)
 	*dst++ = *src++;
 }
+
+#ifdef __alpha__
+
+#ifdef linux
+
+#define SPARSE (7)
+
+#else
+
+#define SPARSE 0
+
+#endif
+
+void
+xf86SlowBCopyFromBus(unsigned char *src, unsigned char *dst, int count)
+{
+    unsigned long addr;
+    long result;
+
+    addr = (unsigned long) src;
+    while( count ){
+	result = *(volatile int *) addr;
+	result >>= ((addr>>SPARSE) & 3) * 8;
+	*dst++ = (unsigned char) (0xffUL & result);
+	addr += 1<<SPARSE;
+	count--;
+	outb(0x80, 0x00);
+    }
+}
+  
+void
+xf86SlowBCopyToBus(unsigned char *src, unsigned char *dst, int count)
+{
+    unsigned long addr;
+
+    addr = (unsigned long) dst;
+    while(count) {
+	*(volatile unsigned int *) addr = (unsigned short)(*src) * 0x01010101;
+	src++;
+	addr += 1<<SPARSE;
+	count--;
+	outb(0x80, 0x00);
+    }
+}
+#endif