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authormarha <marha@users.sourceforge.net>2010-06-11 12:14:52 +0000
committermarha <marha@users.sourceforge.net>2010-06-11 12:14:52 +0000
commit4c61bf84b11e26e6f22648668c95ea760a379163 (patch)
tree0ac762ab2815eae283dded7447ad7cb5a54b926a /xorg-server/hw/xfree86/ramdac
parente1dabd2ce8be0d70c6c15353b58de256129dfd1f (diff)
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xserver git update 11/6/2010
Diffstat (limited to 'xorg-server/hw/xfree86/ramdac')
-rw-r--r--xorg-server/hw/xfree86/ramdac/IBM.c1278
-rw-r--r--xorg-server/hw/xfree86/ramdac/TI.c1434
-rw-r--r--xorg-server/hw/xfree86/ramdac/xf86Cursor.c6
-rw-r--r--xorg-server/hw/xfree86/ramdac/xf86CursorPriv.h101
-rw-r--r--xorg-server/hw/xfree86/ramdac/xf86RamDac.c8
5 files changed, 1414 insertions, 1413 deletions
diff --git a/xorg-server/hw/xfree86/ramdac/IBM.c b/xorg-server/hw/xfree86/ramdac/IBM.c
index 2d9fe4d8f..3a477d7be 100644
--- a/xorg-server/hw/xfree86/ramdac/IBM.c
+++ b/xorg-server/hw/xfree86/ramdac/IBM.c
@@ -1,639 +1,639 @@
-/*
- * Copyright 1998 by Alan Hourihane, Wigan, England.
- *
- * Permission to use, copy, modify, distribute, and sell this software and its
- * documentation for any purpose is hereby granted without fee, provided that
- * the above copyright notice appear in all copies and that both that
- * copyright notice and this permission notice appear in supporting
- * documentation, and that the name of Alan Hourihane not be used in
- * advertising or publicity pertaining to distribution of the software without
- * specific, written prior permission. Alan Hourihane makes no representations
- * about the suitability of this software for any purpose. It is provided
- * "as is" without express or implied warranty.
- *
- * ALAN HOURIHANE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
- * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
- * EVENT SHALL ALAN HOURIHANE BE LIABLE FOR ANY SPECIAL, INDIRECT OR
- * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
- * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- *
- * Authors: Alan Hourihane, <alanh@fairlite.demon.co.uk>
- *
- * IBM RAMDAC routines.
- */
-
-#ifdef HAVE_XORG_CONFIG_H
-#include <xorg-config.h>
-#endif
-
-#include "xf86.h"
-#include "xf86_OSproc.h"
-
-#include "xf86Cursor.h"
-
-#define INIT_IBM_RAMDAC_INFO
-#include "IBMPriv.h"
-#include "xf86RamDacPriv.h"
-
-#define INITIALFREQERR 100000
-
-unsigned long
-IBMramdac640CalculateMNPCForClock(
- unsigned long RefClock, /* In 100Hz units */
- unsigned long ReqClock, /* In 100Hz units */
- char IsPixClock, /* boolean, is this the pixel or the sys clock */
- unsigned long MinClock, /* Min VCO rating */
- unsigned long MaxClock, /* Max VCO rating */
- unsigned long *rM, /* M Out */
- unsigned long *rN, /* N Out */
- unsigned long *rP, /* Min P In, P Out */
- unsigned long *rC /* C Out */
-)
-{
- unsigned long M, N, P, iP = *rP;
- unsigned long IntRef, VCO, Clock;
- long freqErr, lowestFreqErr = INITIALFREQERR;
- unsigned long ActualClock = 0;
-
- for (N = 0; N <= 63; N++)
- {
- IntRef = RefClock / (N + 1);
- if (IntRef < 10000)
- break; /* IntRef needs to be >= 1MHz */
- for (M = 2; M <= 127; M++)
- {
- VCO = IntRef * (M + 1);
- if ((VCO < MinClock) || (VCO > MaxClock))
- continue;
- for (P = iP; P <= 4; P++)
- {
- if (P != 0)
- Clock = (RefClock * (M + 1)) / ((N + 1) * 2 * P);
- else
- Clock = (RefClock * (M + 1)) / (N + 1);
-
- freqErr = (Clock - ReqClock);
-
- if (freqErr < 0)
- {
- /* PixelClock gets rounded up always so monitor reports
- correct frequency. */
- if (IsPixClock)
- continue;
- freqErr = -freqErr;
- }
-
- if (freqErr < lowestFreqErr)
- {
- *rM = M;
- *rN = N;
- *rP = P;
- *rC = (VCO <= 1280000 ? 1 : 2);
- ActualClock = Clock;
-
- lowestFreqErr = freqErr;
- /* Return if we found an exact match */
- if (freqErr == 0)
- return (ActualClock);
- }
- }
- }
- }
-
- return (ActualClock);
-}
-
-unsigned long
-IBMramdac526CalculateMNPCForClock(
- unsigned long RefClock, /* In 100Hz units */
- unsigned long ReqClock, /* In 100Hz units */
- char IsPixClock, /* boolean, is this the pixel or the sys clock */
- unsigned long MinClock, /* Min VCO rating */
- unsigned long MaxClock, /* Max VCO rating */
- unsigned long *rM, /* M Out */
- unsigned long *rN, /* N Out */
- unsigned long *rP, /* Min P In, P Out */
- unsigned long *rC /* C Out */
-)
-{
- unsigned long M, N, P, iP = *rP;
- unsigned long IntRef, VCO, Clock;
- long freqErr, lowestFreqErr = INITIALFREQERR;
- unsigned long ActualClock = 0;
-
- for (N = 0; N <= 63; N++)
- {
- IntRef = RefClock / (N + 1);
- if (IntRef < 10000)
- break; /* IntRef needs to be >= 1MHz */
- for (M = 0; M <= 63; M++)
- {
- VCO = IntRef * (M + 1);
- if ((VCO < MinClock) || (VCO > MaxClock))
- continue;
- for (P = iP; P <= 4; P++)
- {
- if (P)
- Clock = (RefClock * (M + 1)) / ((N + 1) * 2 * P);
- else
- Clock = VCO;
-
- freqErr = (Clock - ReqClock);
-
- if (freqErr < 0)
- {
- /* PixelClock gets rounded up always so monitor reports
- correct frequency. */
- if (IsPixClock)
- continue;
- freqErr = -freqErr;
- }
-
- if (freqErr < lowestFreqErr)
- {
- *rM = M;
- *rN = N;
- *rP = P;
- *rC = (VCO <= 1280000 ? 1 : 2);
- ActualClock = Clock;
-
- lowestFreqErr = freqErr;
- /* Return if we found an exact match */
- if (freqErr == 0)
- return (ActualClock);
- }
- }
- }
- }
-
- return (ActualClock);
-}
-
-void
-IBMramdacRestore(ScrnInfoPtr pScrn, RamDacRecPtr ramdacPtr,
- RamDacRegRecPtr ramdacReg)
-{
- int i, maxreg, dacreg;
-
- switch (ramdacPtr->RamDacType) {
- case IBM640_RAMDAC:
- maxreg = 0x300;
- dacreg = 1024;
- break;
- default:
- maxreg = 0x100;
- dacreg = 768;
- break;
- }
-
- /* Here we pass a short, so that we can evaluate a mask too */
- /* So that the mask is the high byte and the data the low byte */
- for (i=0;i<maxreg;i++)
- (*ramdacPtr->WriteDAC)
- (pScrn, i, (ramdacReg->DacRegs[i] & 0xFF00) >> 8,
- ramdacReg->DacRegs[i]);
-
- (*ramdacPtr->WriteAddress)(pScrn, 0);
- for (i=0;i<dacreg;i++)
- (*ramdacPtr->WriteData)(pScrn, ramdacReg->DAC[i]);
-}
-
-void
-IBMramdacSave(ScrnInfoPtr pScrn, RamDacRecPtr ramdacPtr,
- RamDacRegRecPtr ramdacReg)
-{
- int i, maxreg, dacreg;
-
- switch (ramdacPtr->RamDacType) {
- case IBM640_RAMDAC:
- maxreg = 0x300;
- dacreg = 1024;
- break;
- default:
- maxreg = 0x100;
- dacreg = 768;
- break;
- }
-
- (*ramdacPtr->ReadAddress)(pScrn, 0);
- for (i=0;i<dacreg;i++)
- ramdacReg->DAC[i] = (*ramdacPtr->ReadData)(pScrn);
-
- for (i=0;i<maxreg;i++)
- ramdacReg->DacRegs[i] = (*ramdacPtr->ReadDAC)(pScrn, i);
-}
-
-RamDacHelperRecPtr
-IBMramdacProbe(ScrnInfoPtr pScrn, RamDacSupportedInfoRecPtr ramdacs/* , RamDacRecPtr ramdacPtr*/)
-{
- RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
- RamDacHelperRecPtr ramdacHelperPtr = NULL;
- Bool RamDacIsSupported = FALSE;
- int IBMramdac_ID = -1;
- int i;
- unsigned char id, rev, id2, rev2;
-
- /* read ID and revision */
- rev = (*ramdacPtr->ReadDAC)(pScrn, IBMRGB_rev);
- id = (*ramdacPtr->ReadDAC)(pScrn, IBMRGB_id);
-
- /* check if ID and revision are read only */
- (*ramdacPtr->WriteDAC)(pScrn, ~rev, 0, IBMRGB_rev);
- (*ramdacPtr->WriteDAC)(pScrn, ~id, 0, IBMRGB_id);
- rev2 = (*ramdacPtr->ReadDAC)(pScrn, IBMRGB_rev);
- id2 = (*ramdacPtr->ReadDAC)(pScrn, IBMRGB_id);
-
- switch (id) {
- case 0x30:
- if (rev == 0xc0) IBMramdac_ID = IBM624_RAMDAC;
- if (rev == 0x80) IBMramdac_ID = IBM624DB_RAMDAC;
- break;
- case 0x12:
- if (rev == 0x1c) IBMramdac_ID = IBM640_RAMDAC;
- break;
- case 0x01:
- IBMramdac_ID = IBM525_RAMDAC;
- break;
- case 0x02:
- if (rev == 0xf0) IBMramdac_ID = IBM524_RAMDAC;
- if (rev == 0xe0) IBMramdac_ID = IBM524A_RAMDAC;
- if (rev == 0xc0) IBMramdac_ID = IBM526_RAMDAC;
- if (rev == 0x80) IBMramdac_ID = IBM526DB_RAMDAC;
- break;
- }
-
- if (id == 1 || id == 2) {
- if (id == id2 && rev == rev2) { /* IBM RGB52x found */
- /* check for 128bit VRAM -> RGB528 */
- if (((*ramdacPtr->ReadDAC)(pScrn, IBMRGB_misc1) & 0x03) == 0x03) {
- IBMramdac_ID = IBM528_RAMDAC; /* 128bit DAC found */
- if (rev == 0xe0)
- IBMramdac_ID = IBM528A_RAMDAC;
- }
- }
- }
-
- (*ramdacPtr->WriteDAC)(pScrn, rev, 0, IBMRGB_rev);
- (*ramdacPtr->WriteDAC)(pScrn, id, 0, IBMRGB_id);
-
- if (IBMramdac_ID == -1) {
- xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
- "Cannot determine IBM RAMDAC type, aborting\n");
- return NULL;
- } else {
- xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
- "Attached RAMDAC is %s\n", IBMramdacDeviceInfo[IBMramdac_ID&0xFFFF].DeviceName);
- }
-
- for (i=0;ramdacs[i].token != -1;i++) {
- if (ramdacs[i].token == IBMramdac_ID)
- RamDacIsSupported = TRUE;
- }
-
- if (!RamDacIsSupported) {
- xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
- "This IBM RAMDAC is NOT supported by this driver, aborting\n");
- return NULL;
- }
-
- ramdacHelperPtr = RamDacHelperCreateInfoRec();
- switch (IBMramdac_ID) {
- case IBM526_RAMDAC:
- case IBM526DB_RAMDAC:
- ramdacHelperPtr->SetBpp = IBMramdac526SetBpp;
- ramdacHelperPtr->HWCursorInit = IBMramdac526HWCursorInit;
- break;
- case IBM640_RAMDAC:
- ramdacHelperPtr->SetBpp = IBMramdac640SetBpp;
- ramdacHelperPtr->HWCursorInit = IBMramdac640HWCursorInit;
- break;
- }
- ramdacPtr->RamDacType = IBMramdac_ID;
- ramdacHelperPtr->RamDacType = IBMramdac_ID;
- ramdacHelperPtr->Save = IBMramdacSave;
- ramdacHelperPtr->Restore = IBMramdacRestore;
-
- return ramdacHelperPtr;
-}
-
-void
-IBMramdac526SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr ramdacReg)
-{
- ramdacReg->DacRegs[IBMRGB_key_control] = 0x00; /* Disable Chroma Key */
-
- switch (pScrn->bitsPerPixel) {
- case 32:
- ramdacReg->DacRegs[IBMRGB_pix_fmt] = PIXEL_FORMAT_32BPP;
- ramdacReg->DacRegs[IBMRGB_32bpp] = B32_DCOL_DIRECT;
- ramdacReg->DacRegs[IBMRGB_24bpp] = 0;
- ramdacReg->DacRegs[IBMRGB_16bpp] = 0;
- ramdacReg->DacRegs[IBMRGB_8bpp] = 0;
- if (pScrn->overlayFlags & OVERLAY_8_32_PLANAR) {
- ramdacReg->DacRegs[IBMRGB_key_control] = 0x01; /* Enable Key */
- ramdacReg->DacRegs[IBMRGB_key] = 0xFF;
- ramdacReg->DacRegs[IBMRGB_key_mask] = 0xFF;
- }
- break;
- case 24:
- ramdacReg->DacRegs[IBMRGB_pix_fmt] = PIXEL_FORMAT_24BPP;
- ramdacReg->DacRegs[IBMRGB_32bpp] = 0;
- ramdacReg->DacRegs[IBMRGB_24bpp] = B24_DCOL_DIRECT;
- ramdacReg->DacRegs[IBMRGB_16bpp] = 0;
- ramdacReg->DacRegs[IBMRGB_8bpp] = 0;
- break;
- case 16:
- if (pScrn->depth == 16) {
- ramdacReg->DacRegs[IBMRGB_pix_fmt] = PIXEL_FORMAT_16BPP;
- ramdacReg->DacRegs[IBMRGB_32bpp] = 0;
- ramdacReg->DacRegs[IBMRGB_24bpp] = 0;
- ramdacReg->DacRegs[IBMRGB_16bpp] = B16_DCOL_DIRECT|B16_LINEAR |
- B16_CONTIGUOUS | B16_565;
- ramdacReg->DacRegs[IBMRGB_8bpp] = 0;
- } else {
- ramdacReg->DacRegs[IBMRGB_pix_fmt] = PIXEL_FORMAT_16BPP;
- ramdacReg->DacRegs[IBMRGB_32bpp] = 0;
- ramdacReg->DacRegs[IBMRGB_24bpp] = 0;
- ramdacReg->DacRegs[IBMRGB_16bpp] = B16_DCOL_DIRECT|B16_LINEAR |
- B16_CONTIGUOUS | B16_555;
- ramdacReg->DacRegs[IBMRGB_8bpp] = 0;
- }
- break;
- case 8:
- ramdacReg->DacRegs[IBMRGB_pix_fmt] = PIXEL_FORMAT_8BPP;
- ramdacReg->DacRegs[IBMRGB_32bpp] = 0;
- ramdacReg->DacRegs[IBMRGB_24bpp] = 0;
- ramdacReg->DacRegs[IBMRGB_16bpp] = 0;
- ramdacReg->DacRegs[IBMRGB_8bpp] = B8_DCOL_INDIRECT;
- break;
- case 4:
- ramdacReg->DacRegs[IBMRGB_pix_fmt] = PIXEL_FORMAT_4BPP;
- ramdacReg->DacRegs[IBMRGB_32bpp] = 0;
- ramdacReg->DacRegs[IBMRGB_24bpp] = 0;
- ramdacReg->DacRegs[IBMRGB_16bpp] = 0;
- ramdacReg->DacRegs[IBMRGB_8bpp] = 0;
- }
-}
-
-IBMramdac526SetBppProc *IBMramdac526SetBppWeak(void) {
- return IBMramdac526SetBpp;
-}
-
-void
-IBMramdac640SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr ramdacReg)
-{
- unsigned char bpp = 0x00;
- unsigned char overlaybpp = 0x00;
- unsigned char offset = 0x00;
- unsigned char dispcont = 0x44;
-
- ramdacReg->DacRegs[RGB640_SER_WID_03_00] = 0x00;
- ramdacReg->DacRegs[RGB640_SER_WID_07_04] = 0x00;
- ramdacReg->DacRegs[RGB640_DIAGS] = 0x07;
-
- switch (pScrn->depth) {
- case 8:
- ramdacReg->DacRegs[RGB640_SER_07_00] = 0x00;
- ramdacReg->DacRegs[RGB640_SER_15_08] = 0x00;
- ramdacReg->DacRegs[RGB640_SER_23_16] = 0x00;
- ramdacReg->DacRegs[RGB640_SER_31_24] = 0x00;
- ramdacReg->DacRegs[RGB640_SER_MODE] = IBM640_SER_16_1; /*16:1 Mux*/
- ramdacReg->DacRegs[RGB640_MISC_CONF] = IBM640_PCLK_8; /* pll / 8 */
- bpp = 0x03;
- break;
- case 15:
- ramdacReg->DacRegs[RGB640_SER_07_00] = 0x10;
- ramdacReg->DacRegs[RGB640_SER_15_08] = 0x11;
- ramdacReg->DacRegs[RGB640_SER_23_16] = 0x00;
- ramdacReg->DacRegs[RGB640_SER_31_24] = 0x00;
- ramdacReg->DacRegs[RGB640_SER_MODE] = IBM640_SER_8_1; /* 8:1 Mux*/
- ramdacReg->DacRegs[RGB640_MISC_CONF] = IBM640_PCLK_8; /* pll / 8 */
- bpp = 0x0E;
- break;
- case 16:
- ramdacReg->DacRegs[RGB640_SER_07_00] = 0x10;
- ramdacReg->DacRegs[RGB640_SER_15_08] = 0x11;
- ramdacReg->DacRegs[RGB640_SER_23_16] = 0x00;
- ramdacReg->DacRegs[RGB640_SER_31_24] = 0x00;
- ramdacReg->DacRegs[RGB640_SER_MODE] = IBM640_SER_8_1; /* 8:1 Mux*/
- ramdacReg->DacRegs[RGB640_MISC_CONF] = IBM640_PCLK_8; /* pll / 8 */
- bpp = 0x05;
- break;
- case 24:
- ramdacReg->DacRegs[RGB640_SER_07_00] = 0x30;
- ramdacReg->DacRegs[RGB640_SER_15_08] = 0x31;
- ramdacReg->DacRegs[RGB640_SER_23_16] = 0x32;
- ramdacReg->DacRegs[RGB640_SER_31_24] = 0x33;
- ramdacReg->DacRegs[RGB640_SER_MODE] = IBM640_SER_4_1; /* 4:1 Mux*/
- ramdacReg->DacRegs[RGB640_MISC_CONF] = IBM640_PCLK_8; /* pll / 8 */
- bpp = 0x09;
- if (pScrn->overlayFlags & OVERLAY_8_32_PLANAR) {
- ramdacReg->DacRegs[RGB640_SER_WID_07_04] = 0x04;
- ramdacReg->DacRegs[RGB640_CHROMA_KEY0] = 0xFF;
- ramdacReg->DacRegs[RGB640_CHROMA_MASK0] = 0xFF;
- offset = 0x04;
- overlaybpp = 0x04;
- dispcont = 0x48;
- }
- break;
- case 30: /* 10 bit dac */
- ramdacReg->DacRegs[RGB640_SER_07_00] = 0x30;
- ramdacReg->DacRegs[RGB640_SER_15_08] = 0x31;
- ramdacReg->DacRegs[RGB640_SER_23_16] = 0x32;
- ramdacReg->DacRegs[RGB640_SER_31_24] = 0x33;
- ramdacReg->DacRegs[RGB640_SER_MODE] = IBM640_SER_4_1; /* 4:1 Mux*/
- ramdacReg->DacRegs[RGB640_MISC_CONF] = IBM640_PSIZE10 |
- IBM640_PCLK_8; /* pll / 8 */
- bpp = 0x0D;
- break;
- }
-
- {
- int i;
- for (i=0x100;i<0x140;i+=4) {
- /* Initialize FrameBuffer Window Attribute Table */
- ramdacReg->DacRegs[i+0] = bpp;
- ramdacReg->DacRegs[i+1] = offset;
- ramdacReg->DacRegs[i+2] = 0x00;
- ramdacReg->DacRegs[i+3] = 0x00;
- /* Initialize Overlay Window Attribute Table */
- ramdacReg->DacRegs[i+0x100] = overlaybpp;
- ramdacReg->DacRegs[i+0x101] = 0x00;
- ramdacReg->DacRegs[i+0x102] = 0x00;
- ramdacReg->DacRegs[i+0x103] = dispcont;
- }
- }
-}
-
-static void
-IBMramdac526ShowCursor(ScrnInfoPtr pScrn)
-{
- RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
-
- /* Enable cursor - X11 mode */
- (*ramdacPtr->WriteDAC)(pScrn, IBMRGB_curs, 0x00, 0x07);
-}
-
-static void
-IBMramdac640ShowCursor(ScrnInfoPtr pScrn)
-{
- RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
-
- /* Enable cursor - mode2 (x11 mode) */
- (*ramdacPtr->WriteDAC)(pScrn, RGB640_CURSOR_CONTROL, 0x00, 0x0B);
- (*ramdacPtr->WriteDAC)(pScrn, RGB640_CROSSHAIR_CONTROL, 0x00, 0x00);
-}
-
-static void
-IBMramdac526HideCursor(ScrnInfoPtr pScrn)
-{
- RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
-
- /* Disable cursor - X11 mode */
- (*ramdacPtr->WriteDAC)(pScrn, IBMRGB_curs, 0x00, 0x24);
-}
-
-static void
-IBMramdac640HideCursor(ScrnInfoPtr pScrn)
-{
- RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
-
- /* Disable cursor - mode2 (x11 mode) */
- (*ramdacPtr->WriteDAC)(pScrn, RGB640_CURSOR_CONTROL, 0x00, 0x08);
-}
-
-static void
-IBMramdac526SetCursorPosition(ScrnInfoPtr pScrn, int x, int y)
-{
- RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
-
- x += 64;
- y += 64;
-
- (*ramdacPtr->WriteDAC)(pScrn, IBMRGB_curs_hot_x, 0x00, 0x3f);
- (*ramdacPtr->WriteDAC)(pScrn, IBMRGB_curs_hot_y, 0x00, 0x3f);
- (*ramdacPtr->WriteDAC)(pScrn, IBMRGB_curs_xl, 0x00, x & 0xff);
- (*ramdacPtr->WriteDAC)(pScrn, IBMRGB_curs_xh, 0x00, (x>>8) & 0xf);
- (*ramdacPtr->WriteDAC)(pScrn, IBMRGB_curs_yl, 0x00, y & 0xff);
- (*ramdacPtr->WriteDAC)(pScrn, IBMRGB_curs_yh, 0x00, (y>>8) & 0xf);
-}
-
-static void
-IBMramdac640SetCursorPosition(ScrnInfoPtr pScrn, int x, int y)
-{
- RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
-
- x += 64;
- y += 64;
-
- (*ramdacPtr->WriteDAC)(pScrn, RGB640_CURS_OFFSETX, 0x00, 0x3f);
- (*ramdacPtr->WriteDAC)(pScrn, RGB640_CURS_OFFSETY, 0x00, 0x3f);
- (*ramdacPtr->WriteDAC)(pScrn, RGB640_CURS_X_LOW, 0x00, x & 0xff);
- (*ramdacPtr->WriteDAC)(pScrn, RGB640_CURS_X_HIGH, 0x00, (x>>8) & 0xf);
- (*ramdacPtr->WriteDAC)(pScrn, RGB640_CURS_Y_LOW, 0x00, y & 0xff);
- (*ramdacPtr->WriteDAC)(pScrn, RGB640_CURS_Y_HIGH, 0x00, (y>>8) & 0xf);
-}
-
-static void
-IBMramdac526SetCursorColors(ScrnInfoPtr pScrn, int bg, int fg)
-{
- RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
-
- (*ramdacPtr->WriteDAC)(pScrn, IBMRGB_curs_col1_r, 0x00, bg >> 16);
- (*ramdacPtr->WriteDAC)(pScrn, IBMRGB_curs_col1_g, 0x00, bg >> 8);
- (*ramdacPtr->WriteDAC)(pScrn, IBMRGB_curs_col1_b, 0x00, bg);
- (*ramdacPtr->WriteDAC)(pScrn, IBMRGB_curs_col2_r, 0x00, fg >> 16);
- (*ramdacPtr->WriteDAC)(pScrn, IBMRGB_curs_col2_g, 0x00, fg >> 8);
- (*ramdacPtr->WriteDAC)(pScrn, IBMRGB_curs_col2_b, 0x00, fg);
-}
-
-static void
-IBMramdac640SetCursorColors(ScrnInfoPtr pScrn, int bg, int fg)
-{
- RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
-
- (*ramdacPtr->WriteDAC)(pScrn, RGB640_CURS_COL0, 0x00, 0);
- (*ramdacPtr->WriteData)(pScrn, fg>>16);
- (*ramdacPtr->WriteData)(pScrn, fg>>8);
- (*ramdacPtr->WriteData)(pScrn, fg);
- (*ramdacPtr->WriteData)(pScrn, bg>>16);
- (*ramdacPtr->WriteData)(pScrn, bg>>8);
- (*ramdacPtr->WriteData)(pScrn, bg);
- (*ramdacPtr->WriteData)(pScrn, fg>>16);
- (*ramdacPtr->WriteData)(pScrn, fg>>8);
- (*ramdacPtr->WriteData)(pScrn, fg);
- (*ramdacPtr->WriteData)(pScrn, bg>>16);
- (*ramdacPtr->WriteData)(pScrn, bg>>8);
- (*ramdacPtr->WriteData)(pScrn, bg);
-}
-
-static void
-IBMramdac526LoadCursorImage(ScrnInfoPtr pScrn, unsigned char *src)
-{
- RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
- int i;
- /*
- * Output the cursor data. The realize function has put the planes into
- * their correct order, so we can just blast this out.
- */
- for (i = 0; i < 1024; i++)
- (*ramdacPtr->WriteDAC)(pScrn, IBMRGB_curs_array + i, 0x00, (*src++));
-}
-
-static void
-IBMramdac640LoadCursorImage(ScrnInfoPtr pScrn, unsigned char *src)
-{
- RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
- int i;
- /*
- * Output the cursor data. The realize function has put the planes into
- * their correct order, so we can just blast this out.
- */
- for (i = 0; i < 1024; i++)
- (*ramdacPtr->WriteDAC)(pScrn, RGB640_CURS_WRITE + i, 0x00, (*src++));
-}
-
-static Bool
-IBMramdac526UseHWCursor(ScreenPtr pScr, CursorPtr pCurs)
-{
- return TRUE;
-}
-
-static Bool
-IBMramdac640UseHWCursor(ScreenPtr pScr, CursorPtr pCurs)
-{
- return TRUE;
-}
-
-void
-IBMramdac526HWCursorInit(xf86CursorInfoPtr infoPtr)
-{
- infoPtr->MaxWidth = 64;
- infoPtr->MaxHeight = 64;
- infoPtr->Flags = HARDWARE_CURSOR_TRUECOLOR_AT_8BPP |
- HARDWARE_CURSOR_AND_SOURCE_WITH_MASK |
- HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE_1;
- infoPtr->SetCursorColors = IBMramdac526SetCursorColors;
- infoPtr->SetCursorPosition = IBMramdac526SetCursorPosition;
- infoPtr->LoadCursorImage = IBMramdac526LoadCursorImage;
- infoPtr->HideCursor = IBMramdac526HideCursor;
- infoPtr->ShowCursor = IBMramdac526ShowCursor;
- infoPtr->UseHWCursor = IBMramdac526UseHWCursor;
-}
-
-void
-IBMramdac640HWCursorInit(xf86CursorInfoPtr infoPtr)
-{
- infoPtr->MaxWidth = 64;
- infoPtr->MaxHeight = 64;
- infoPtr->Flags = HARDWARE_CURSOR_TRUECOLOR_AT_8BPP |
- HARDWARE_CURSOR_AND_SOURCE_WITH_MASK |
- HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE_1;
- infoPtr->SetCursorColors = IBMramdac640SetCursorColors;
- infoPtr->SetCursorPosition = IBMramdac640SetCursorPosition;
- infoPtr->LoadCursorImage = IBMramdac640LoadCursorImage;
- infoPtr->HideCursor = IBMramdac640HideCursor;
- infoPtr->ShowCursor = IBMramdac640ShowCursor;
- infoPtr->UseHWCursor = IBMramdac640UseHWCursor;
-}
+/*
+ * Copyright 1998 by Alan Hourihane, Wigan, England.
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that
+ * copyright notice and this permission notice appear in supporting
+ * documentation, and that the name of Alan Hourihane not be used in
+ * advertising or publicity pertaining to distribution of the software without
+ * specific, written prior permission. Alan Hourihane makes no representations
+ * about the suitability of this software for any purpose. It is provided
+ * "as is" without express or implied warranty.
+ *
+ * ALAN HOURIHANE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+ * EVENT SHALL ALAN HOURIHANE BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ *
+ * Authors: Alan Hourihane, <alanh@fairlite.demon.co.uk>
+ *
+ * IBM RAMDAC routines.
+ */
+
+#ifdef HAVE_XORG_CONFIG_H
+#include <xorg-config.h>
+#endif
+
+#include "xf86.h"
+#include "xf86_OSproc.h"
+
+#include "xf86Cursor.h"
+
+#define INIT_IBM_RAMDAC_INFO
+#include "IBMPriv.h"
+#include "xf86RamDacPriv.h"
+
+#define INITIALFREQERR 100000
+
+unsigned long
+IBMramdac640CalculateMNPCForClock(
+ unsigned long RefClock, /* In 100Hz units */
+ unsigned long ReqClock, /* In 100Hz units */
+ char IsPixClock, /* boolean, is this the pixel or the sys clock */
+ unsigned long MinClock, /* Min VCO rating */
+ unsigned long MaxClock, /* Max VCO rating */
+ unsigned long *rM, /* M Out */
+ unsigned long *rN, /* N Out */
+ unsigned long *rP, /* Min P In, P Out */
+ unsigned long *rC /* C Out */
+)
+{
+ unsigned long M, N, P, iP = *rP;
+ unsigned long IntRef, VCO, Clock;
+ long freqErr, lowestFreqErr = INITIALFREQERR;
+ unsigned long ActualClock = 0;
+
+ for (N = 0; N <= 63; N++)
+ {
+ IntRef = RefClock / (N + 1);
+ if (IntRef < 10000)
+ break; /* IntRef needs to be >= 1MHz */
+ for (M = 2; M <= 127; M++)
+ {
+ VCO = IntRef * (M + 1);
+ if ((VCO < MinClock) || (VCO > MaxClock))
+ continue;
+ for (P = iP; P <= 4; P++)
+ {
+ if (P != 0)
+ Clock = (RefClock * (M + 1)) / ((N + 1) * 2 * P);
+ else
+ Clock = (RefClock * (M + 1)) / (N + 1);
+
+ freqErr = (Clock - ReqClock);
+
+ if (freqErr < 0)
+ {
+ /* PixelClock gets rounded up always so monitor reports
+ correct frequency. */
+ if (IsPixClock)
+ continue;
+ freqErr = -freqErr;
+ }
+
+ if (freqErr < lowestFreqErr)
+ {
+ *rM = M;
+ *rN = N;
+ *rP = P;
+ *rC = (VCO <= 1280000 ? 1 : 2);
+ ActualClock = Clock;
+
+ lowestFreqErr = freqErr;
+ /* Return if we found an exact match */
+ if (freqErr == 0)
+ return ActualClock;
+ }
+ }
+ }
+ }
+
+ return ActualClock;
+}
+
+unsigned long
+IBMramdac526CalculateMNPCForClock(
+ unsigned long RefClock, /* In 100Hz units */
+ unsigned long ReqClock, /* In 100Hz units */
+ char IsPixClock, /* boolean, is this the pixel or the sys clock */
+ unsigned long MinClock, /* Min VCO rating */
+ unsigned long MaxClock, /* Max VCO rating */
+ unsigned long *rM, /* M Out */
+ unsigned long *rN, /* N Out */
+ unsigned long *rP, /* Min P In, P Out */
+ unsigned long *rC /* C Out */
+)
+{
+ unsigned long M, N, P, iP = *rP;
+ unsigned long IntRef, VCO, Clock;
+ long freqErr, lowestFreqErr = INITIALFREQERR;
+ unsigned long ActualClock = 0;
+
+ for (N = 0; N <= 63; N++)
+ {
+ IntRef = RefClock / (N + 1);
+ if (IntRef < 10000)
+ break; /* IntRef needs to be >= 1MHz */
+ for (M = 0; M <= 63; M++)
+ {
+ VCO = IntRef * (M + 1);
+ if ((VCO < MinClock) || (VCO > MaxClock))
+ continue;
+ for (P = iP; P <= 4; P++)
+ {
+ if (P)
+ Clock = (RefClock * (M + 1)) / ((N + 1) * 2 * P);
+ else
+ Clock = VCO;
+
+ freqErr = (Clock - ReqClock);
+
+ if (freqErr < 0)
+ {
+ /* PixelClock gets rounded up always so monitor reports
+ correct frequency. */
+ if (IsPixClock)
+ continue;
+ freqErr = -freqErr;
+ }
+
+ if (freqErr < lowestFreqErr)
+ {
+ *rM = M;
+ *rN = N;
+ *rP = P;
+ *rC = (VCO <= 1280000 ? 1 : 2);
+ ActualClock = Clock;
+
+ lowestFreqErr = freqErr;
+ /* Return if we found an exact match */
+ if (freqErr == 0)
+ return ActualClock;
+ }
+ }
+ }
+ }
+
+ return ActualClock;
+}
+
+void
+IBMramdacRestore(ScrnInfoPtr pScrn, RamDacRecPtr ramdacPtr,
+ RamDacRegRecPtr ramdacReg)
+{
+ int i, maxreg, dacreg;
+
+ switch (ramdacPtr->RamDacType) {
+ case IBM640_RAMDAC:
+ maxreg = 0x300;
+ dacreg = 1024;
+ break;
+ default:
+ maxreg = 0x100;
+ dacreg = 768;
+ break;
+ }
+
+ /* Here we pass a short, so that we can evaluate a mask too */
+ /* So that the mask is the high byte and the data the low byte */
+ for (i=0;i<maxreg;i++)
+ (*ramdacPtr->WriteDAC)
+ (pScrn, i, (ramdacReg->DacRegs[i] & 0xFF00) >> 8,
+ ramdacReg->DacRegs[i]);
+
+ (*ramdacPtr->WriteAddress)(pScrn, 0);
+ for (i=0;i<dacreg;i++)
+ (*ramdacPtr->WriteData)(pScrn, ramdacReg->DAC[i]);
+}
+
+void
+IBMramdacSave(ScrnInfoPtr pScrn, RamDacRecPtr ramdacPtr,
+ RamDacRegRecPtr ramdacReg)
+{
+ int i, maxreg, dacreg;
+
+ switch (ramdacPtr->RamDacType) {
+ case IBM640_RAMDAC:
+ maxreg = 0x300;
+ dacreg = 1024;
+ break;
+ default:
+ maxreg = 0x100;
+ dacreg = 768;
+ break;
+ }
+
+ (*ramdacPtr->ReadAddress)(pScrn, 0);
+ for (i=0;i<dacreg;i++)
+ ramdacReg->DAC[i] = (*ramdacPtr->ReadData)(pScrn);
+
+ for (i=0;i<maxreg;i++)
+ ramdacReg->DacRegs[i] = (*ramdacPtr->ReadDAC)(pScrn, i);
+}
+
+RamDacHelperRecPtr
+IBMramdacProbe(ScrnInfoPtr pScrn, RamDacSupportedInfoRecPtr ramdacs/* , RamDacRecPtr ramdacPtr*/)
+{
+ RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
+ RamDacHelperRecPtr ramdacHelperPtr = NULL;
+ Bool RamDacIsSupported = FALSE;
+ int IBMramdac_ID = -1;
+ int i;
+ unsigned char id, rev, id2, rev2;
+
+ /* read ID and revision */
+ rev = (*ramdacPtr->ReadDAC)(pScrn, IBMRGB_rev);
+ id = (*ramdacPtr->ReadDAC)(pScrn, IBMRGB_id);
+
+ /* check if ID and revision are read only */
+ (*ramdacPtr->WriteDAC)(pScrn, ~rev, 0, IBMRGB_rev);
+ (*ramdacPtr->WriteDAC)(pScrn, ~id, 0, IBMRGB_id);
+ rev2 = (*ramdacPtr->ReadDAC)(pScrn, IBMRGB_rev);
+ id2 = (*ramdacPtr->ReadDAC)(pScrn, IBMRGB_id);
+
+ switch (id) {
+ case 0x30:
+ if (rev == 0xc0) IBMramdac_ID = IBM624_RAMDAC;
+ if (rev == 0x80) IBMramdac_ID = IBM624DB_RAMDAC;
+ break;
+ case 0x12:
+ if (rev == 0x1c) IBMramdac_ID = IBM640_RAMDAC;
+ break;
+ case 0x01:
+ IBMramdac_ID = IBM525_RAMDAC;
+ break;
+ case 0x02:
+ if (rev == 0xf0) IBMramdac_ID = IBM524_RAMDAC;
+ if (rev == 0xe0) IBMramdac_ID = IBM524A_RAMDAC;
+ if (rev == 0xc0) IBMramdac_ID = IBM526_RAMDAC;
+ if (rev == 0x80) IBMramdac_ID = IBM526DB_RAMDAC;
+ break;
+ }
+
+ if (id == 1 || id == 2) {
+ if (id == id2 && rev == rev2) { /* IBM RGB52x found */
+ /* check for 128bit VRAM -> RGB528 */
+ if (((*ramdacPtr->ReadDAC)(pScrn, IBMRGB_misc1) & 0x03) == 0x03) {
+ IBMramdac_ID = IBM528_RAMDAC; /* 128bit DAC found */
+ if (rev == 0xe0)
+ IBMramdac_ID = IBM528A_RAMDAC;
+ }
+ }
+ }
+
+ (*ramdacPtr->WriteDAC)(pScrn, rev, 0, IBMRGB_rev);
+ (*ramdacPtr->WriteDAC)(pScrn, id, 0, IBMRGB_id);
+
+ if (IBMramdac_ID == -1) {
+ xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
+ "Cannot determine IBM RAMDAC type, aborting\n");
+ return NULL;
+ } else {
+ xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
+ "Attached RAMDAC is %s\n", IBMramdacDeviceInfo[IBMramdac_ID&0xFFFF].DeviceName);
+ }
+
+ for (i=0;ramdacs[i].token != -1;i++) {
+ if (ramdacs[i].token == IBMramdac_ID)
+ RamDacIsSupported = TRUE;
+ }
+
+ if (!RamDacIsSupported) {
+ xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
+ "This IBM RAMDAC is NOT supported by this driver, aborting\n");
+ return NULL;
+ }
+
+ ramdacHelperPtr = RamDacHelperCreateInfoRec();
+ switch (IBMramdac_ID) {
+ case IBM526_RAMDAC:
+ case IBM526DB_RAMDAC:
+ ramdacHelperPtr->SetBpp = IBMramdac526SetBpp;
+ ramdacHelperPtr->HWCursorInit = IBMramdac526HWCursorInit;
+ break;
+ case IBM640_RAMDAC:
+ ramdacHelperPtr->SetBpp = IBMramdac640SetBpp;
+ ramdacHelperPtr->HWCursorInit = IBMramdac640HWCursorInit;
+ break;
+ }
+ ramdacPtr->RamDacType = IBMramdac_ID;
+ ramdacHelperPtr->RamDacType = IBMramdac_ID;
+ ramdacHelperPtr->Save = IBMramdacSave;
+ ramdacHelperPtr->Restore = IBMramdacRestore;
+
+ return ramdacHelperPtr;
+}
+
+void
+IBMramdac526SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr ramdacReg)
+{
+ ramdacReg->DacRegs[IBMRGB_key_control] = 0x00; /* Disable Chroma Key */
+
+ switch (pScrn->bitsPerPixel) {
+ case 32:
+ ramdacReg->DacRegs[IBMRGB_pix_fmt] = PIXEL_FORMAT_32BPP;
+ ramdacReg->DacRegs[IBMRGB_32bpp] = B32_DCOL_DIRECT;
+ ramdacReg->DacRegs[IBMRGB_24bpp] = 0;
+ ramdacReg->DacRegs[IBMRGB_16bpp] = 0;
+ ramdacReg->DacRegs[IBMRGB_8bpp] = 0;
+ if (pScrn->overlayFlags & OVERLAY_8_32_PLANAR) {
+ ramdacReg->DacRegs[IBMRGB_key_control] = 0x01; /* Enable Key */
+ ramdacReg->DacRegs[IBMRGB_key] = 0xFF;
+ ramdacReg->DacRegs[IBMRGB_key_mask] = 0xFF;
+ }
+ break;
+ case 24:
+ ramdacReg->DacRegs[IBMRGB_pix_fmt] = PIXEL_FORMAT_24BPP;
+ ramdacReg->DacRegs[IBMRGB_32bpp] = 0;
+ ramdacReg->DacRegs[IBMRGB_24bpp] = B24_DCOL_DIRECT;
+ ramdacReg->DacRegs[IBMRGB_16bpp] = 0;
+ ramdacReg->DacRegs[IBMRGB_8bpp] = 0;
+ break;
+ case 16:
+ if (pScrn->depth == 16) {
+ ramdacReg->DacRegs[IBMRGB_pix_fmt] = PIXEL_FORMAT_16BPP;
+ ramdacReg->DacRegs[IBMRGB_32bpp] = 0;
+ ramdacReg->DacRegs[IBMRGB_24bpp] = 0;
+ ramdacReg->DacRegs[IBMRGB_16bpp] = B16_DCOL_DIRECT|B16_LINEAR |
+ B16_CONTIGUOUS | B16_565;
+ ramdacReg->DacRegs[IBMRGB_8bpp] = 0;
+ } else {
+ ramdacReg->DacRegs[IBMRGB_pix_fmt] = PIXEL_FORMAT_16BPP;
+ ramdacReg->DacRegs[IBMRGB_32bpp] = 0;
+ ramdacReg->DacRegs[IBMRGB_24bpp] = 0;
+ ramdacReg->DacRegs[IBMRGB_16bpp] = B16_DCOL_DIRECT|B16_LINEAR |
+ B16_CONTIGUOUS | B16_555;
+ ramdacReg->DacRegs[IBMRGB_8bpp] = 0;
+ }
+ break;
+ case 8:
+ ramdacReg->DacRegs[IBMRGB_pix_fmt] = PIXEL_FORMAT_8BPP;
+ ramdacReg->DacRegs[IBMRGB_32bpp] = 0;
+ ramdacReg->DacRegs[IBMRGB_24bpp] = 0;
+ ramdacReg->DacRegs[IBMRGB_16bpp] = 0;
+ ramdacReg->DacRegs[IBMRGB_8bpp] = B8_DCOL_INDIRECT;
+ break;
+ case 4:
+ ramdacReg->DacRegs[IBMRGB_pix_fmt] = PIXEL_FORMAT_4BPP;
+ ramdacReg->DacRegs[IBMRGB_32bpp] = 0;
+ ramdacReg->DacRegs[IBMRGB_24bpp] = 0;
+ ramdacReg->DacRegs[IBMRGB_16bpp] = 0;
+ ramdacReg->DacRegs[IBMRGB_8bpp] = 0;
+ }
+}
+
+IBMramdac526SetBppProc *IBMramdac526SetBppWeak(void) {
+ return IBMramdac526SetBpp;
+}
+
+void
+IBMramdac640SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr ramdacReg)
+{
+ unsigned char bpp = 0x00;
+ unsigned char overlaybpp = 0x00;
+ unsigned char offset = 0x00;
+ unsigned char dispcont = 0x44;
+
+ ramdacReg->DacRegs[RGB640_SER_WID_03_00] = 0x00;
+ ramdacReg->DacRegs[RGB640_SER_WID_07_04] = 0x00;
+ ramdacReg->DacRegs[RGB640_DIAGS] = 0x07;
+
+ switch (pScrn->depth) {
+ case 8:
+ ramdacReg->DacRegs[RGB640_SER_07_00] = 0x00;
+ ramdacReg->DacRegs[RGB640_SER_15_08] = 0x00;
+ ramdacReg->DacRegs[RGB640_SER_23_16] = 0x00;
+ ramdacReg->DacRegs[RGB640_SER_31_24] = 0x00;
+ ramdacReg->DacRegs[RGB640_SER_MODE] = IBM640_SER_16_1; /*16:1 Mux*/
+ ramdacReg->DacRegs[RGB640_MISC_CONF] = IBM640_PCLK_8; /* pll / 8 */
+ bpp = 0x03;
+ break;
+ case 15:
+ ramdacReg->DacRegs[RGB640_SER_07_00] = 0x10;
+ ramdacReg->DacRegs[RGB640_SER_15_08] = 0x11;
+ ramdacReg->DacRegs[RGB640_SER_23_16] = 0x00;
+ ramdacReg->DacRegs[RGB640_SER_31_24] = 0x00;
+ ramdacReg->DacRegs[RGB640_SER_MODE] = IBM640_SER_8_1; /* 8:1 Mux*/
+ ramdacReg->DacRegs[RGB640_MISC_CONF] = IBM640_PCLK_8; /* pll / 8 */
+ bpp = 0x0E;
+ break;
+ case 16:
+ ramdacReg->DacRegs[RGB640_SER_07_00] = 0x10;
+ ramdacReg->DacRegs[RGB640_SER_15_08] = 0x11;
+ ramdacReg->DacRegs[RGB640_SER_23_16] = 0x00;
+ ramdacReg->DacRegs[RGB640_SER_31_24] = 0x00;
+ ramdacReg->DacRegs[RGB640_SER_MODE] = IBM640_SER_8_1; /* 8:1 Mux*/
+ ramdacReg->DacRegs[RGB640_MISC_CONF] = IBM640_PCLK_8; /* pll / 8 */
+ bpp = 0x05;
+ break;
+ case 24:
+ ramdacReg->DacRegs[RGB640_SER_07_00] = 0x30;
+ ramdacReg->DacRegs[RGB640_SER_15_08] = 0x31;
+ ramdacReg->DacRegs[RGB640_SER_23_16] = 0x32;
+ ramdacReg->DacRegs[RGB640_SER_31_24] = 0x33;
+ ramdacReg->DacRegs[RGB640_SER_MODE] = IBM640_SER_4_1; /* 4:1 Mux*/
+ ramdacReg->DacRegs[RGB640_MISC_CONF] = IBM640_PCLK_8; /* pll / 8 */
+ bpp = 0x09;
+ if (pScrn->overlayFlags & OVERLAY_8_32_PLANAR) {
+ ramdacReg->DacRegs[RGB640_SER_WID_07_04] = 0x04;
+ ramdacReg->DacRegs[RGB640_CHROMA_KEY0] = 0xFF;
+ ramdacReg->DacRegs[RGB640_CHROMA_MASK0] = 0xFF;
+ offset = 0x04;
+ overlaybpp = 0x04;
+ dispcont = 0x48;
+ }
+ break;
+ case 30: /* 10 bit dac */
+ ramdacReg->DacRegs[RGB640_SER_07_00] = 0x30;
+ ramdacReg->DacRegs[RGB640_SER_15_08] = 0x31;
+ ramdacReg->DacRegs[RGB640_SER_23_16] = 0x32;
+ ramdacReg->DacRegs[RGB640_SER_31_24] = 0x33;
+ ramdacReg->DacRegs[RGB640_SER_MODE] = IBM640_SER_4_1; /* 4:1 Mux*/
+ ramdacReg->DacRegs[RGB640_MISC_CONF] = IBM640_PSIZE10 |
+ IBM640_PCLK_8; /* pll / 8 */
+ bpp = 0x0D;
+ break;
+ }
+
+ {
+ int i;
+ for (i=0x100;i<0x140;i+=4) {
+ /* Initialize FrameBuffer Window Attribute Table */
+ ramdacReg->DacRegs[i+0] = bpp;
+ ramdacReg->DacRegs[i+1] = offset;
+ ramdacReg->DacRegs[i+2] = 0x00;
+ ramdacReg->DacRegs[i+3] = 0x00;
+ /* Initialize Overlay Window Attribute Table */
+ ramdacReg->DacRegs[i+0x100] = overlaybpp;
+ ramdacReg->DacRegs[i+0x101] = 0x00;
+ ramdacReg->DacRegs[i+0x102] = 0x00;
+ ramdacReg->DacRegs[i+0x103] = dispcont;
+ }
+ }
+}
+
+static void
+IBMramdac526ShowCursor(ScrnInfoPtr pScrn)
+{
+ RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
+
+ /* Enable cursor - X11 mode */
+ (*ramdacPtr->WriteDAC)(pScrn, IBMRGB_curs, 0x00, 0x07);
+}
+
+static void
+IBMramdac640ShowCursor(ScrnInfoPtr pScrn)
+{
+ RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
+
+ /* Enable cursor - mode2 (x11 mode) */
+ (*ramdacPtr->WriteDAC)(pScrn, RGB640_CURSOR_CONTROL, 0x00, 0x0B);
+ (*ramdacPtr->WriteDAC)(pScrn, RGB640_CROSSHAIR_CONTROL, 0x00, 0x00);
+}
+
+static void
+IBMramdac526HideCursor(ScrnInfoPtr pScrn)
+{
+ RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
+
+ /* Disable cursor - X11 mode */
+ (*ramdacPtr->WriteDAC)(pScrn, IBMRGB_curs, 0x00, 0x24);
+}
+
+static void
+IBMramdac640HideCursor(ScrnInfoPtr pScrn)
+{
+ RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
+
+ /* Disable cursor - mode2 (x11 mode) */
+ (*ramdacPtr->WriteDAC)(pScrn, RGB640_CURSOR_CONTROL, 0x00, 0x08);
+}
+
+static void
+IBMramdac526SetCursorPosition(ScrnInfoPtr pScrn, int x, int y)
+{
+ RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
+
+ x += 64;
+ y += 64;
+
+ (*ramdacPtr->WriteDAC)(pScrn, IBMRGB_curs_hot_x, 0x00, 0x3f);
+ (*ramdacPtr->WriteDAC)(pScrn, IBMRGB_curs_hot_y, 0x00, 0x3f);
+ (*ramdacPtr->WriteDAC)(pScrn, IBMRGB_curs_xl, 0x00, x & 0xff);
+ (*ramdacPtr->WriteDAC)(pScrn, IBMRGB_curs_xh, 0x00, (x>>8) & 0xf);
+ (*ramdacPtr->WriteDAC)(pScrn, IBMRGB_curs_yl, 0x00, y & 0xff);
+ (*ramdacPtr->WriteDAC)(pScrn, IBMRGB_curs_yh, 0x00, (y>>8) & 0xf);
+}
+
+static void
+IBMramdac640SetCursorPosition(ScrnInfoPtr pScrn, int x, int y)
+{
+ RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
+
+ x += 64;
+ y += 64;
+
+ (*ramdacPtr->WriteDAC)(pScrn, RGB640_CURS_OFFSETX, 0x00, 0x3f);
+ (*ramdacPtr->WriteDAC)(pScrn, RGB640_CURS_OFFSETY, 0x00, 0x3f);
+ (*ramdacPtr->WriteDAC)(pScrn, RGB640_CURS_X_LOW, 0x00, x & 0xff);
+ (*ramdacPtr->WriteDAC)(pScrn, RGB640_CURS_X_HIGH, 0x00, (x>>8) & 0xf);
+ (*ramdacPtr->WriteDAC)(pScrn, RGB640_CURS_Y_LOW, 0x00, y & 0xff);
+ (*ramdacPtr->WriteDAC)(pScrn, RGB640_CURS_Y_HIGH, 0x00, (y>>8) & 0xf);
+}
+
+static void
+IBMramdac526SetCursorColors(ScrnInfoPtr pScrn, int bg, int fg)
+{
+ RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
+
+ (*ramdacPtr->WriteDAC)(pScrn, IBMRGB_curs_col1_r, 0x00, bg >> 16);
+ (*ramdacPtr->WriteDAC)(pScrn, IBMRGB_curs_col1_g, 0x00, bg >> 8);
+ (*ramdacPtr->WriteDAC)(pScrn, IBMRGB_curs_col1_b, 0x00, bg);
+ (*ramdacPtr->WriteDAC)(pScrn, IBMRGB_curs_col2_r, 0x00, fg >> 16);
+ (*ramdacPtr->WriteDAC)(pScrn, IBMRGB_curs_col2_g, 0x00, fg >> 8);
+ (*ramdacPtr->WriteDAC)(pScrn, IBMRGB_curs_col2_b, 0x00, fg);
+}
+
+static void
+IBMramdac640SetCursorColors(ScrnInfoPtr pScrn, int bg, int fg)
+{
+ RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
+
+ (*ramdacPtr->WriteDAC)(pScrn, RGB640_CURS_COL0, 0x00, 0);
+ (*ramdacPtr->WriteData)(pScrn, fg>>16);
+ (*ramdacPtr->WriteData)(pScrn, fg>>8);
+ (*ramdacPtr->WriteData)(pScrn, fg);
+ (*ramdacPtr->WriteData)(pScrn, bg>>16);
+ (*ramdacPtr->WriteData)(pScrn, bg>>8);
+ (*ramdacPtr->WriteData)(pScrn, bg);
+ (*ramdacPtr->WriteData)(pScrn, fg>>16);
+ (*ramdacPtr->WriteData)(pScrn, fg>>8);
+ (*ramdacPtr->WriteData)(pScrn, fg);
+ (*ramdacPtr->WriteData)(pScrn, bg>>16);
+ (*ramdacPtr->WriteData)(pScrn, bg>>8);
+ (*ramdacPtr->WriteData)(pScrn, bg);
+}
+
+static void
+IBMramdac526LoadCursorImage(ScrnInfoPtr pScrn, unsigned char *src)
+{
+ RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
+ int i;
+ /*
+ * Output the cursor data. The realize function has put the planes into
+ * their correct order, so we can just blast this out.
+ */
+ for (i = 0; i < 1024; i++)
+ (*ramdacPtr->WriteDAC)(pScrn, IBMRGB_curs_array + i, 0x00, (*src++));
+}
+
+static void
+IBMramdac640LoadCursorImage(ScrnInfoPtr pScrn, unsigned char *src)
+{
+ RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
+ int i;
+ /*
+ * Output the cursor data. The realize function has put the planes into
+ * their correct order, so we can just blast this out.
+ */
+ for (i = 0; i < 1024; i++)
+ (*ramdacPtr->WriteDAC)(pScrn, RGB640_CURS_WRITE + i, 0x00, (*src++));
+}
+
+static Bool
+IBMramdac526UseHWCursor(ScreenPtr pScr, CursorPtr pCurs)
+{
+ return TRUE;
+}
+
+static Bool
+IBMramdac640UseHWCursor(ScreenPtr pScr, CursorPtr pCurs)
+{
+ return TRUE;
+}
+
+void
+IBMramdac526HWCursorInit(xf86CursorInfoPtr infoPtr)
+{
+ infoPtr->MaxWidth = 64;
+ infoPtr->MaxHeight = 64;
+ infoPtr->Flags = HARDWARE_CURSOR_TRUECOLOR_AT_8BPP |
+ HARDWARE_CURSOR_AND_SOURCE_WITH_MASK |
+ HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE_1;
+ infoPtr->SetCursorColors = IBMramdac526SetCursorColors;
+ infoPtr->SetCursorPosition = IBMramdac526SetCursorPosition;
+ infoPtr->LoadCursorImage = IBMramdac526LoadCursorImage;
+ infoPtr->HideCursor = IBMramdac526HideCursor;
+ infoPtr->ShowCursor = IBMramdac526ShowCursor;
+ infoPtr->UseHWCursor = IBMramdac526UseHWCursor;
+}
+
+void
+IBMramdac640HWCursorInit(xf86CursorInfoPtr infoPtr)
+{
+ infoPtr->MaxWidth = 64;
+ infoPtr->MaxHeight = 64;
+ infoPtr->Flags = HARDWARE_CURSOR_TRUECOLOR_AT_8BPP |
+ HARDWARE_CURSOR_AND_SOURCE_WITH_MASK |
+ HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE_1;
+ infoPtr->SetCursorColors = IBMramdac640SetCursorColors;
+ infoPtr->SetCursorPosition = IBMramdac640SetCursorPosition;
+ infoPtr->LoadCursorImage = IBMramdac640LoadCursorImage;
+ infoPtr->HideCursor = IBMramdac640HideCursor;
+ infoPtr->ShowCursor = IBMramdac640ShowCursor;
+ infoPtr->UseHWCursor = IBMramdac640UseHWCursor;
+}
diff --git a/xorg-server/hw/xfree86/ramdac/TI.c b/xorg-server/hw/xfree86/ramdac/TI.c
index 1c541d76b..f189fed25 100644
--- a/xorg-server/hw/xfree86/ramdac/TI.c
+++ b/xorg-server/hw/xfree86/ramdac/TI.c
@@ -1,717 +1,717 @@
-/*
- * Copyright 1998 by Alan Hourihane, Wigan, England.
- *
- * Permission to use, copy, modify, distribute, and sell this software and its
- * documentation for any purpose is hereby granted without fee, provided that
- * the above copyright notice appear in all copies and that both that
- * copyright notice and this permission notice appear in supporting
- * documentation, and that the name of Alan Hourihane not be used in
- * advertising or publicity pertaining to distribution of the software without
- * specific, written prior permission. Alan Hourihane makes no representations
- * about the suitability of this software for any purpose. It is provided
- * "as is" without express or implied warranty.
- *
- * ALAN HOURIHANE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
- * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
- * EVENT SHALL ALAN HOURIHANE BE LIABLE FOR ANY SPECIAL, INDIRECT OR
- * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
- * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
- * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- *
- * Authors: Alan Hourihane, <alanh@fairlite.demon.co.uk>
- *
- * Modified from IBM.c to support TI RAMDAC routines
- * by Jens Owen, <jens@tungstengraphics.com>.
- */
-
-#ifdef HAVE_XORG_CONFIG_H
-#include <xorg-config.h>
-#endif
-
-#include "xf86.h"
-#include "xf86_OSproc.h"
-
-#include "xf86Cursor.h"
-
-#define INIT_TI_RAMDAC_INFO
-#include "TIPriv.h"
-#include "xf86RamDacPriv.h"
-
-/* The following values are in kHz */
-#define TI_MIN_VCO_FREQ 110000
-#define TI_MAX_VCO_FREQ 220000
-
-unsigned long
-TIramdacCalculateMNPForClock(
- unsigned long RefClock, /* In 100Hz units */
- unsigned long ReqClock, /* In 100Hz units */
- char IsPixClock, /* boolean, is this the pixel or the sys clock */
- unsigned long MinClock, /* Min VCO rating */
- unsigned long MaxClock, /* Max VCO rating */
- unsigned long *rM, /* M Out */
- unsigned long *rN, /* N Out */
- unsigned long *rP /* Min P In, P Out */
-)
-{
- unsigned long n, p;
- unsigned long best_m = 0, best_n = 0;
- double VCO, IntRef = (double)RefClock;
- double m_err, inc_m, calc_m;
- unsigned long ActualClock;
-
- /* Make sure that MinClock <= ReqClock <= MaxClock */
- if ( ReqClock < MinClock)
- ReqClock = MinClock;
- if ( ReqClock > MaxClock )
- ReqClock = MaxClock;
-
- /*
- * ActualClock = VCO / 2 ^ p
- * Choose p so that TI_MIN_VCO_FREQ <= VCO <= TI_MAX_VCO_FREQ
- * Note that since TI_MAX_VCO_FREQ = 2 * TI_MIN_VCO_FREQ
- * we don't have to bother checking for this maximum limit.
- */
- VCO = (double)ReqClock;
- for ( p = 0; p < 3 && VCO < TI_MIN_VCO_FREQ; ( p )++ )
- VCO *= 2.0;
-
- /*
- * We avoid doing multiplications by ( 65 - n ),
- * and add an increment instead - this keeps any error small.
- */
- inc_m = VCO / ( IntRef * 8.0 );
-
- /* Initial value of calc_m for the loop */
- calc_m = inc_m + inc_m + inc_m;
-
- /* Initial amount of error for an integer - impossibly large */
- m_err = 2.0;
-
- /* Search for the closest INTEGER value of ( 65 - m ) */
- for ( n = 3; n <= 25; ( n )++, calc_m += inc_m ) {
-
- /* Ignore values of ( 65 - m ) which we can't use */
- if ( calc_m < 3.0 || calc_m > 64.0 )
- continue;
-
- /*
- * Pick the closest INTEGER (has smallest fractional part).
- * The optimizer should clean this up for us.
- */
- if (( calc_m - ( int ) calc_m ) < m_err ) {
- m_err = calc_m - ( int ) calc_m;
- best_m = ( int ) calc_m;
- best_n = n;
- }
- }
-
- /* 65 - ( 65 - x ) = x */
- *rM = 65 - best_m;
- *rN = 65 - best_n;
- *rP = p;
-
- /* Now all the calculations can be completed */
- VCO = 8.0 * IntRef * best_m / best_n;
- ActualClock = VCO / ( 1 << p );
-
- DebugF( "f_out=%ld f_vco=%.1f n=%d m=%d p=%d\n",
- ActualClock, VCO, *rN, *rM, *rP);
-
- return (ActualClock);
-}
-
-void
-TIramdacRestore(ScrnInfoPtr pScrn, RamDacRecPtr ramdacPtr,
- RamDacRegRecPtr ramdacReg)
-{
- int i;
- unsigned long status;
-
- /* Here we pass a short, so that we can evaluate a mask too
- * So that the mask is the high byte and the data the low byte
- * Order is important
- */
- TIRESTORE(TIDAC_latch_ctrl);
- TIRESTORE(TIDAC_true_color_ctrl);
- TIRESTORE(TIDAC_multiplex_ctrl);
- TIRESTORE(TIDAC_clock_select);
- TIRESTORE(TIDAC_palette_page);
- TIRESTORE(TIDAC_general_ctrl);
- TIRESTORE(TIDAC_misc_ctrl);
- /* 0x2A & 0x2B are reserved */
- TIRESTORE(TIDAC_key_over_low);
- TIRESTORE(TIDAC_key_over_high);
- TIRESTORE(TIDAC_key_red_low);
- TIRESTORE(TIDAC_key_red_high);
- TIRESTORE(TIDAC_key_green_low);
- TIRESTORE(TIDAC_key_green_high);
- TIRESTORE(TIDAC_key_blue_low);
- TIRESTORE(TIDAC_key_blue_high);
- TIRESTORE(TIDAC_key_ctrl);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_clock_ctrl, 0, 0x30);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_clock_ctrl, 0, 0x38);
- TIRESTORE(TIDAC_clock_ctrl);
- TIRESTORE(TIDAC_sense_test);
- TIRESTORE(TIDAC_ind_curs_ctrl);
-
- /* only restore clocks if they were valid to begin with */
-
- if (ramdacReg->DacRegs[TIDAC_PIXEL_VALID]) {
- /* Reset pixel clock */
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0x22);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_pixel_data, 0, 0x3c);
-
- /* Restore N, M & P values for pixel clocks */
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_pixel_data, 0,
- ramdacReg->DacRegs[TIDAC_PIXEL_N]);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_pixel_data, 0,
- ramdacReg->DacRegs[TIDAC_PIXEL_M]);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_pixel_data, 0,
- ramdacReg->DacRegs[TIDAC_PIXEL_P]);
-
- /* wait for pixel clock to lock */
- i = 1000000;
- do {
- status = (*ramdacPtr->ReadDAC)(pScrn, TIDAC_pll_pixel_data);
- } while ((!(status & 0x40)) && (--i));
- if (!(status & 0x40)) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Pixel clock setup timed out\n");
- return;
- }
- }
-
- if (ramdacReg->DacRegs[TIDAC_LOOP_VALID]) {
- /* Reset loop clock */
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0x22);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_loop_data, 0, 0x70);
-
- /* Restore N, M & P values for pixel clocks */
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_loop_data, 0,
- ramdacReg->DacRegs[TIDAC_LOOP_N]);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_loop_data, 0,
- ramdacReg->DacRegs[TIDAC_LOOP_M]);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_loop_data, 0,
- ramdacReg->DacRegs[TIDAC_LOOP_P]);
-
- /* wait for loop clock to lock */
- i = 1000000;
- do {
- status = (*ramdacPtr->ReadDAC)(pScrn, TIDAC_pll_loop_data);
- } while ((!(status & 0x40)) && (--i));
- if (!(status & 0x40)) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Loop clock setup timed out\n");
- return;
- }
- }
-
- /* restore palette */
- (*ramdacPtr->WriteAddress)(pScrn, 0);
-#ifndef NOT_DONE
- for (i=0;i<768;i++)
- (*ramdacPtr->WriteData)(pScrn, ramdacReg->DAC[i]);
-#else
- (*ramdacPtr->WriteData)(pScrn, 0);
- (*ramdacPtr->WriteData)(pScrn, 0);
- (*ramdacPtr->WriteData)(pScrn, 0);
- for (i=0;i<765;i++)
- (*ramdacPtr->WriteData)(pScrn, 0xff);
-#endif
-}
-
-void
-TIramdacSave(ScrnInfoPtr pScrn, RamDacRecPtr ramdacPtr,
- RamDacRegRecPtr ramdacReg)
-{
- int i;
-
- (*ramdacPtr->ReadAddress)(pScrn, 0);
- for (i=0;i<768;i++)
- ramdacReg->DAC[i] = (*ramdacPtr->ReadData)(pScrn);
-
- /* Read back N,M and P values for pixel clock */
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0);
- ramdacReg->DacRegs[TIDAC_PIXEL_N] =
- (*ramdacPtr->ReadDAC)(pScrn, TIDAC_pll_pixel_data);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0x11);
- ramdacReg->DacRegs[TIDAC_PIXEL_M] =
- (*ramdacPtr->ReadDAC)(pScrn, TIDAC_pll_pixel_data);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0x22);
- ramdacReg->DacRegs[TIDAC_PIXEL_P] =
- (*ramdacPtr->ReadDAC)(pScrn, TIDAC_pll_pixel_data);
-
- /* Read back N,M and P values for loop clock */
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0);
- ramdacReg->DacRegs[TIDAC_LOOP_N] =
- (*ramdacPtr->ReadDAC)(pScrn, TIDAC_pll_loop_data);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0x11);
- ramdacReg->DacRegs[TIDAC_LOOP_M] =
- (*ramdacPtr->ReadDAC)(pScrn, TIDAC_pll_loop_data);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0x22);
- ramdacReg->DacRegs[TIDAC_LOOP_P] =
- (*ramdacPtr->ReadDAC)(pScrn, TIDAC_pll_loop_data);
-
- /* Order is important */
- TISAVE(TIDAC_latch_ctrl);
- TISAVE(TIDAC_true_color_ctrl);
- TISAVE(TIDAC_multiplex_ctrl);
- TISAVE(TIDAC_clock_select);
- TISAVE(TIDAC_palette_page);
- TISAVE(TIDAC_general_ctrl);
- TISAVE(TIDAC_misc_ctrl);
- /* 0x2A & 0x2B are reserved */
- TISAVE(TIDAC_key_over_low);
- TISAVE(TIDAC_key_over_high);
- TISAVE(TIDAC_key_red_low);
- TISAVE(TIDAC_key_red_high);
- TISAVE(TIDAC_key_green_low);
- TISAVE(TIDAC_key_green_high);
- TISAVE(TIDAC_key_blue_low);
- TISAVE(TIDAC_key_blue_high);
- TISAVE(TIDAC_key_ctrl);
- TISAVE(TIDAC_clock_ctrl);
- TISAVE(TIDAC_sense_test);
- TISAVE(TIDAC_ind_curs_ctrl);
-}
-
-RamDacHelperRecPtr
-TIramdacProbe(ScrnInfoPtr pScrn, RamDacSupportedInfoRecPtr ramdacs)
-{
- RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
- RamDacHelperRecPtr ramdacHelperPtr = NULL;
- Bool RamDacIsSupported = FALSE;
- int TIramdac_ID = -1;
- int i;
- unsigned char id, rev, rev2, id2;
-
- /* read ID and revision */
- rev = (*ramdacPtr->ReadDAC)(pScrn, TIDAC_rev);
- id = (*ramdacPtr->ReadDAC)(pScrn, TIDAC_id);
-
- /* check if ID and revision are read only */
- (*ramdacPtr->WriteDAC)(pScrn, ~rev, 0, TIDAC_rev);
- (*ramdacPtr->WriteDAC)(pScrn, ~id, 0, TIDAC_id);
- rev2 = (*ramdacPtr->ReadDAC)(pScrn, TIDAC_rev);
- id2 = (*ramdacPtr->ReadDAC)(pScrn, TIDAC_id);
-
- switch (id) {
- case TIDAC_TVP_3030_ID:
- if (id == id2 && rev == rev2) /* check for READ ONLY */
- TIramdac_ID = TI3030_RAMDAC;
- break;
- case TIDAC_TVP_3026_ID:
- if (id == id2 && rev == rev2) /* check for READ ONLY */
- TIramdac_ID = TI3026_RAMDAC;
- break;
- }
-
- (*ramdacPtr->WriteDAC)(pScrn, rev, 0, TIDAC_rev);
- (*ramdacPtr->WriteDAC)(pScrn, id, 0, TIDAC_id);
-
- if (TIramdac_ID == -1) {
- xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
- "Cannot determine TI RAMDAC type, aborting\n");
- return NULL;
- } else {
- xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
- "Attached RAMDAC is %s\n", TIramdacDeviceInfo[TIramdac_ID&0xFFFF].DeviceName);
- }
-
- for (i=0;ramdacs[i].token != -1;i++) {
- if (ramdacs[i].token == TIramdac_ID)
- RamDacIsSupported = TRUE;
- }
-
- if (!RamDacIsSupported) {
- xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
- "This TI RAMDAC is NOT supported by this driver, aborting\n");
- return NULL;
- }
-
- ramdacHelperPtr = RamDacHelperCreateInfoRec();
- switch (TIramdac_ID) {
- case TI3030_RAMDAC:
- ramdacHelperPtr->SetBpp = TIramdac3030SetBpp;
- ramdacHelperPtr->HWCursorInit = TIramdacHWCursorInit;
- break;
- case TI3026_RAMDAC:
- ramdacHelperPtr->SetBpp = TIramdac3026SetBpp;
- ramdacHelperPtr->HWCursorInit = TIramdacHWCursorInit;
- break;
- }
- ramdacPtr->RamDacType = TIramdac_ID;
- ramdacHelperPtr->RamDacType = TIramdac_ID;
- ramdacHelperPtr->Save = TIramdacSave;
- ramdacHelperPtr->Restore = TIramdacRestore;
-
- return ramdacHelperPtr;
-}
-
-void
-TIramdac3026SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr ramdacReg)
-{
- switch (pScrn->bitsPerPixel) {
- case 32:
- /* order is important */
- ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
- ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x46;
- ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x5c;
- ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
- ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
- ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
- ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x3C;
- /* 0x2A & 0x2B are reserved */
- ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
- ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
- ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
- if (pScrn->overlayFlags & OVERLAY_8_32_PLANAR) {
- ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x06;
- ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x3C;
- ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x01;
- }
- ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
- break;
- case 24:
- /* order is important */
- ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
- ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x56;
- ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x58;
- ramdacReg->DacRegs[TIDAC_clock_select] = 0x25;
- ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
- ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x00;
- ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C;
- /* 0x2A & 0x2B are reserved */
- ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
- ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
- ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
- ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
- break;
- case 16:
- /* order is important */
-#if 0
- /* Matrox driver uses this */
- ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x07;
-#else
- ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
-#endif
- if (pScrn->depth == 16) {
- ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x45;
- } else {
- ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x44;
- }
-#if 0
- /* Matrox driver uses this */
- ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x50;
- ramdacReg->DacRegs[TIDAC_clock_select] = 0x15;
- ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
- ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x00;
-#else
- ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x54;
- ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
- ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
- ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
-#endif
- ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C;
- /* 0x2A & 0x2B are reserved */
- ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
- ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
- ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
- ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
- break;
- case 8:
- /* order is important */
- ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
- ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x80;
- ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x4c;
- ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
- ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
- ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
- ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x1C;
- /* 0x2A & 0x2B are reserved */
- ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_blue_low] = 0x00;
- ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
- ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x00;
- ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
- ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
- break;
- }
-}
-
-void
-TIramdac3030SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr ramdacReg)
-{
- switch (pScrn->bitsPerPixel) {
- case 32:
- /* order is important */
- ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
- ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x46;
- ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x5D;
- ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
- ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
- ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
- ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x3C;
- /* 0x2A & 0x2B are reserved */
- ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
- ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
- ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
- if (pScrn->overlayFlags & OVERLAY_8_32_PLANAR) {
- ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x06;
- ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x3C;
- ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x01;
- }
- ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
- break;
- case 24:
- /* order is important */
- ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
- ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x56;
- ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x58;
- ramdacReg->DacRegs[TIDAC_clock_select] = 0x25;
- ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
- ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x00;
- ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C;
- /* 0x2A & 0x2B are reserved */
- ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
- ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
- ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
- ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
- break;
- case 16:
- /* order is important */
-#if 0
- /* Matrox driver uses this */
- ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x07;
-#else
- ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
-#endif
- if (pScrn->depth == 16) {
- ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x45;
- } else {
- ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x44;
- }
-#if 0
- /* Matrox driver uses this */
- ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x50;
- ramdacReg->DacRegs[TIDAC_clock_select] = 0x15;
- ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
- ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x00;
-#else
- ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x55;
- ramdacReg->DacRegs[TIDAC_clock_select] = 0x85;
- ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
- ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
-#endif
- ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C;
- /* 0x2A & 0x2B are reserved */
- ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
- ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
- ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
- ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
- break;
- case 8:
- /* order is important */
- ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
- ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x80;
- ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x4d;
- ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
- ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
- ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
- ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x1C;
- /* 0x2A & 0x2B are reserved */
- ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
- ramdacReg->DacRegs[TIDAC_key_blue_low] = 0x00;
- ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
- ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x00;
- ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
- ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
- break;
- }
-}
-
-static void
-TIramdacShowCursor(ScrnInfoPtr pScrn)
-{
- RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
-
- /* Enable cursor - X11 mode */
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_ind_curs_ctrl, 0, 0x03);
-}
-
-static void
-TIramdacHideCursor(ScrnInfoPtr pScrn)
-{
- RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
-
- /* Disable cursor - X11 mode */
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_ind_curs_ctrl, 0, 0x00);
-}
-
-static void
-TIramdacSetCursorPosition(ScrnInfoPtr pScrn, int x, int y)
-{
- RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
-
- x += 64;
- y += 64;
-
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_XLOW, 0, x & 0xff);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_XHIGH, 0, (x >> 8) & 0x0f);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_YLOW, 0, y & 0xff);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_YHIGH, 0, (y >> 8) & 0x0f);
-}
-
-static void
-TIramdacSetCursorColors(ScrnInfoPtr pScrn, int bg, int fg)
-{
- RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
-
- /* Background color */
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_WRITE_ADDR, 0, 1);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_COLOR, 0, ((bg&0x00ff0000) >> 16));
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_COLOR, 0, ((bg&0x0000ff00) >> 8));
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_COLOR, 0, (bg&0x000000ff) );
-
- /* Foreground color */
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_WRITE_ADDR, 0, 2);
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_COLOR, 0, ((fg&0x00ff0000) >> 16));
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_COLOR, 0, ((fg&0x0000ff00) >> 8));
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_COLOR, 0, (fg&0x000000ff) );
-}
-
-static void
-TIramdacLoadCursorImage(ScrnInfoPtr pScrn, unsigned char *src)
-{
- RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
- int i = 1024;
-
- /* reset A9,A8 */
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_ind_curs_ctrl, 0, 0x00);
- /* reset cursor RAM load address A7..A0 */
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_INDEX, 0x00, 0x00);
-
- while(i--) {
- /* NOT_DONE: might need a delay here */
- (*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_RAM_DATA, 0, *(src++));
- }
-}
-
-static Bool
-TIramdacUseHWCursor(ScreenPtr pScr, CursorPtr pCurs)
-{
- return TRUE;
-}
-
-void
-TIramdacHWCursorInit(xf86CursorInfoPtr infoPtr)
-{
- infoPtr->MaxWidth = 64;
- infoPtr->MaxHeight = 64;
- infoPtr->Flags = HARDWARE_CURSOR_BIT_ORDER_MSBFIRST |
- HARDWARE_CURSOR_TRUECOLOR_AT_8BPP |
- HARDWARE_CURSOR_SOURCE_MASK_NOT_INTERLEAVED;
- infoPtr->SetCursorColors = TIramdacSetCursorColors;
- infoPtr->SetCursorPosition = TIramdacSetCursorPosition;
- infoPtr->LoadCursorImage = TIramdacLoadCursorImage;
- infoPtr->HideCursor = TIramdacHideCursor;
- infoPtr->ShowCursor = TIramdacShowCursor;
- infoPtr->UseHWCursor = TIramdacUseHWCursor;
-}
-
-void TIramdacLoadPalette(
- ScrnInfoPtr pScrn,
- int numColors,
- int *indices,
- LOCO *colors,
- VisualPtr pVisual
-){
- RamDacRecPtr hwp = RAMDACSCRPTR(pScrn);
- int i, index, shift;
-
- if (pScrn->depth == 16) {
- for(i = 0; i < numColors; i++) {
- index = indices[i];
- (*hwp->WriteAddress)(pScrn, index << 2);
- (*hwp->WriteData)(pScrn, colors[index >> 1].red);
- (*hwp->WriteData)(pScrn, colors[index].green);
- (*hwp->WriteData)(pScrn, colors[index >> 1].blue);
-
- if(index <= 31) {
- (*hwp->WriteAddress)(pScrn, index << 3);
- (*hwp->WriteData)(pScrn, colors[index].red);
- (*hwp->WriteData)(pScrn, colors[(index << 1) + 1].green);
- (*hwp->WriteData)(pScrn, colors[index].blue);
- }
- }
-} else {
- shift = (pScrn->depth == 15) ? 3 : 0;
-
- for(i = 0; i < numColors; i++) {
- index = indices[i];
- (*hwp->WriteAddress)(pScrn, index << shift);
- (*hwp->WriteData)(pScrn, colors[index].red);
- (*hwp->WriteData)(pScrn, colors[index].green);
- (*hwp->WriteData)(pScrn, colors[index].blue);
- }
-}
-}
-
-TIramdacLoadPaletteProc *TIramdacLoadPaletteWeak(void) {
- return TIramdacLoadPalette;
-}
+/*
+ * Copyright 1998 by Alan Hourihane, Wigan, England.
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that
+ * copyright notice and this permission notice appear in supporting
+ * documentation, and that the name of Alan Hourihane not be used in
+ * advertising or publicity pertaining to distribution of the software without
+ * specific, written prior permission. Alan Hourihane makes no representations
+ * about the suitability of this software for any purpose. It is provided
+ * "as is" without express or implied warranty.
+ *
+ * ALAN HOURIHANE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+ * EVENT SHALL ALAN HOURIHANE BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ *
+ * Authors: Alan Hourihane, <alanh@fairlite.demon.co.uk>
+ *
+ * Modified from IBM.c to support TI RAMDAC routines
+ * by Jens Owen, <jens@tungstengraphics.com>.
+ */
+
+#ifdef HAVE_XORG_CONFIG_H
+#include <xorg-config.h>
+#endif
+
+#include "xf86.h"
+#include "xf86_OSproc.h"
+
+#include "xf86Cursor.h"
+
+#define INIT_TI_RAMDAC_INFO
+#include "TIPriv.h"
+#include "xf86RamDacPriv.h"
+
+/* The following values are in kHz */
+#define TI_MIN_VCO_FREQ 110000
+#define TI_MAX_VCO_FREQ 220000
+
+unsigned long
+TIramdacCalculateMNPForClock(
+ unsigned long RefClock, /* In 100Hz units */
+ unsigned long ReqClock, /* In 100Hz units */
+ char IsPixClock, /* boolean, is this the pixel or the sys clock */
+ unsigned long MinClock, /* Min VCO rating */
+ unsigned long MaxClock, /* Max VCO rating */
+ unsigned long *rM, /* M Out */
+ unsigned long *rN, /* N Out */
+ unsigned long *rP /* Min P In, P Out */
+)
+{
+ unsigned long n, p;
+ unsigned long best_m = 0, best_n = 0;
+ double VCO, IntRef = (double)RefClock;
+ double m_err, inc_m, calc_m;
+ unsigned long ActualClock;
+
+ /* Make sure that MinClock <= ReqClock <= MaxClock */
+ if ( ReqClock < MinClock)
+ ReqClock = MinClock;
+ if ( ReqClock > MaxClock )
+ ReqClock = MaxClock;
+
+ /*
+ * ActualClock = VCO / 2 ^ p
+ * Choose p so that TI_MIN_VCO_FREQ <= VCO <= TI_MAX_VCO_FREQ
+ * Note that since TI_MAX_VCO_FREQ = 2 * TI_MIN_VCO_FREQ
+ * we don't have to bother checking for this maximum limit.
+ */
+ VCO = (double)ReqClock;
+ for ( p = 0; p < 3 && VCO < TI_MIN_VCO_FREQ; ( p )++ )
+ VCO *= 2.0;
+
+ /*
+ * We avoid doing multiplications by ( 65 - n ),
+ * and add an increment instead - this keeps any error small.
+ */
+ inc_m = VCO / ( IntRef * 8.0 );
+
+ /* Initial value of calc_m for the loop */
+ calc_m = inc_m + inc_m + inc_m;
+
+ /* Initial amount of error for an integer - impossibly large */
+ m_err = 2.0;
+
+ /* Search for the closest INTEGER value of ( 65 - m ) */
+ for ( n = 3; n <= 25; ( n )++, calc_m += inc_m ) {
+
+ /* Ignore values of ( 65 - m ) which we can't use */
+ if ( calc_m < 3.0 || calc_m > 64.0 )
+ continue;
+
+ /*
+ * Pick the closest INTEGER (has smallest fractional part).
+ * The optimizer should clean this up for us.
+ */
+ if (( calc_m - ( int ) calc_m ) < m_err ) {
+ m_err = calc_m - ( int ) calc_m;
+ best_m = ( int ) calc_m;
+ best_n = n;
+ }
+ }
+
+ /* 65 - ( 65 - x ) = x */
+ *rM = 65 - best_m;
+ *rN = 65 - best_n;
+ *rP = p;
+
+ /* Now all the calculations can be completed */
+ VCO = 8.0 * IntRef * best_m / best_n;
+ ActualClock = VCO / ( 1 << p );
+
+ DebugF( "f_out=%ld f_vco=%.1f n=%d m=%d p=%d\n",
+ ActualClock, VCO, *rN, *rM, *rP);
+
+ return ActualClock;
+}
+
+void
+TIramdacRestore(ScrnInfoPtr pScrn, RamDacRecPtr ramdacPtr,
+ RamDacRegRecPtr ramdacReg)
+{
+ int i;
+ unsigned long status;
+
+ /* Here we pass a short, so that we can evaluate a mask too
+ * So that the mask is the high byte and the data the low byte
+ * Order is important
+ */
+ TIRESTORE(TIDAC_latch_ctrl);
+ TIRESTORE(TIDAC_true_color_ctrl);
+ TIRESTORE(TIDAC_multiplex_ctrl);
+ TIRESTORE(TIDAC_clock_select);
+ TIRESTORE(TIDAC_palette_page);
+ TIRESTORE(TIDAC_general_ctrl);
+ TIRESTORE(TIDAC_misc_ctrl);
+ /* 0x2A & 0x2B are reserved */
+ TIRESTORE(TIDAC_key_over_low);
+ TIRESTORE(TIDAC_key_over_high);
+ TIRESTORE(TIDAC_key_red_low);
+ TIRESTORE(TIDAC_key_red_high);
+ TIRESTORE(TIDAC_key_green_low);
+ TIRESTORE(TIDAC_key_green_high);
+ TIRESTORE(TIDAC_key_blue_low);
+ TIRESTORE(TIDAC_key_blue_high);
+ TIRESTORE(TIDAC_key_ctrl);
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_clock_ctrl, 0, 0x30);
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_clock_ctrl, 0, 0x38);
+ TIRESTORE(TIDAC_clock_ctrl);
+ TIRESTORE(TIDAC_sense_test);
+ TIRESTORE(TIDAC_ind_curs_ctrl);
+
+ /* only restore clocks if they were valid to begin with */
+
+ if (ramdacReg->DacRegs[TIDAC_PIXEL_VALID]) {
+ /* Reset pixel clock */
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0x22);
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_pixel_data, 0, 0x3c);
+
+ /* Restore N, M & P values for pixel clocks */
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0);
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_pixel_data, 0,
+ ramdacReg->DacRegs[TIDAC_PIXEL_N]);
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_pixel_data, 0,
+ ramdacReg->DacRegs[TIDAC_PIXEL_M]);
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_pixel_data, 0,
+ ramdacReg->DacRegs[TIDAC_PIXEL_P]);
+
+ /* wait for pixel clock to lock */
+ i = 1000000;
+ do {
+ status = (*ramdacPtr->ReadDAC)(pScrn, TIDAC_pll_pixel_data);
+ } while ((!(status & 0x40)) && (--i));
+ if (!(status & 0x40)) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "Pixel clock setup timed out\n");
+ return;
+ }
+ }
+
+ if (ramdacReg->DacRegs[TIDAC_LOOP_VALID]) {
+ /* Reset loop clock */
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0x22);
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_loop_data, 0, 0x70);
+
+ /* Restore N, M & P values for pixel clocks */
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0);
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_loop_data, 0,
+ ramdacReg->DacRegs[TIDAC_LOOP_N]);
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_loop_data, 0,
+ ramdacReg->DacRegs[TIDAC_LOOP_M]);
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_loop_data, 0,
+ ramdacReg->DacRegs[TIDAC_LOOP_P]);
+
+ /* wait for loop clock to lock */
+ i = 1000000;
+ do {
+ status = (*ramdacPtr->ReadDAC)(pScrn, TIDAC_pll_loop_data);
+ } while ((!(status & 0x40)) && (--i));
+ if (!(status & 0x40)) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "Loop clock setup timed out\n");
+ return;
+ }
+ }
+
+ /* restore palette */
+ (*ramdacPtr->WriteAddress)(pScrn, 0);
+#ifndef NOT_DONE
+ for (i=0;i<768;i++)
+ (*ramdacPtr->WriteData)(pScrn, ramdacReg->DAC[i]);
+#else
+ (*ramdacPtr->WriteData)(pScrn, 0);
+ (*ramdacPtr->WriteData)(pScrn, 0);
+ (*ramdacPtr->WriteData)(pScrn, 0);
+ for (i=0;i<765;i++)
+ (*ramdacPtr->WriteData)(pScrn, 0xff);
+#endif
+}
+
+void
+TIramdacSave(ScrnInfoPtr pScrn, RamDacRecPtr ramdacPtr,
+ RamDacRegRecPtr ramdacReg)
+{
+ int i;
+
+ (*ramdacPtr->ReadAddress)(pScrn, 0);
+ for (i=0;i<768;i++)
+ ramdacReg->DAC[i] = (*ramdacPtr->ReadData)(pScrn);
+
+ /* Read back N,M and P values for pixel clock */
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0);
+ ramdacReg->DacRegs[TIDAC_PIXEL_N] =
+ (*ramdacPtr->ReadDAC)(pScrn, TIDAC_pll_pixel_data);
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0x11);
+ ramdacReg->DacRegs[TIDAC_PIXEL_M] =
+ (*ramdacPtr->ReadDAC)(pScrn, TIDAC_pll_pixel_data);
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0x22);
+ ramdacReg->DacRegs[TIDAC_PIXEL_P] =
+ (*ramdacPtr->ReadDAC)(pScrn, TIDAC_pll_pixel_data);
+
+ /* Read back N,M and P values for loop clock */
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0);
+ ramdacReg->DacRegs[TIDAC_LOOP_N] =
+ (*ramdacPtr->ReadDAC)(pScrn, TIDAC_pll_loop_data);
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0x11);
+ ramdacReg->DacRegs[TIDAC_LOOP_M] =
+ (*ramdacPtr->ReadDAC)(pScrn, TIDAC_pll_loop_data);
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_pll_addr, 0, 0x22);
+ ramdacReg->DacRegs[TIDAC_LOOP_P] =
+ (*ramdacPtr->ReadDAC)(pScrn, TIDAC_pll_loop_data);
+
+ /* Order is important */
+ TISAVE(TIDAC_latch_ctrl);
+ TISAVE(TIDAC_true_color_ctrl);
+ TISAVE(TIDAC_multiplex_ctrl);
+ TISAVE(TIDAC_clock_select);
+ TISAVE(TIDAC_palette_page);
+ TISAVE(TIDAC_general_ctrl);
+ TISAVE(TIDAC_misc_ctrl);
+ /* 0x2A & 0x2B are reserved */
+ TISAVE(TIDAC_key_over_low);
+ TISAVE(TIDAC_key_over_high);
+ TISAVE(TIDAC_key_red_low);
+ TISAVE(TIDAC_key_red_high);
+ TISAVE(TIDAC_key_green_low);
+ TISAVE(TIDAC_key_green_high);
+ TISAVE(TIDAC_key_blue_low);
+ TISAVE(TIDAC_key_blue_high);
+ TISAVE(TIDAC_key_ctrl);
+ TISAVE(TIDAC_clock_ctrl);
+ TISAVE(TIDAC_sense_test);
+ TISAVE(TIDAC_ind_curs_ctrl);
+}
+
+RamDacHelperRecPtr
+TIramdacProbe(ScrnInfoPtr pScrn, RamDacSupportedInfoRecPtr ramdacs)
+{
+ RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
+ RamDacHelperRecPtr ramdacHelperPtr = NULL;
+ Bool RamDacIsSupported = FALSE;
+ int TIramdac_ID = -1;
+ int i;
+ unsigned char id, rev, rev2, id2;
+
+ /* read ID and revision */
+ rev = (*ramdacPtr->ReadDAC)(pScrn, TIDAC_rev);
+ id = (*ramdacPtr->ReadDAC)(pScrn, TIDAC_id);
+
+ /* check if ID and revision are read only */
+ (*ramdacPtr->WriteDAC)(pScrn, ~rev, 0, TIDAC_rev);
+ (*ramdacPtr->WriteDAC)(pScrn, ~id, 0, TIDAC_id);
+ rev2 = (*ramdacPtr->ReadDAC)(pScrn, TIDAC_rev);
+ id2 = (*ramdacPtr->ReadDAC)(pScrn, TIDAC_id);
+
+ switch (id) {
+ case TIDAC_TVP_3030_ID:
+ if (id == id2 && rev == rev2) /* check for READ ONLY */
+ TIramdac_ID = TI3030_RAMDAC;
+ break;
+ case TIDAC_TVP_3026_ID:
+ if (id == id2 && rev == rev2) /* check for READ ONLY */
+ TIramdac_ID = TI3026_RAMDAC;
+ break;
+ }
+
+ (*ramdacPtr->WriteDAC)(pScrn, rev, 0, TIDAC_rev);
+ (*ramdacPtr->WriteDAC)(pScrn, id, 0, TIDAC_id);
+
+ if (TIramdac_ID == -1) {
+ xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
+ "Cannot determine TI RAMDAC type, aborting\n");
+ return NULL;
+ } else {
+ xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
+ "Attached RAMDAC is %s\n", TIramdacDeviceInfo[TIramdac_ID&0xFFFF].DeviceName);
+ }
+
+ for (i=0;ramdacs[i].token != -1;i++) {
+ if (ramdacs[i].token == TIramdac_ID)
+ RamDacIsSupported = TRUE;
+ }
+
+ if (!RamDacIsSupported) {
+ xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
+ "This TI RAMDAC is NOT supported by this driver, aborting\n");
+ return NULL;
+ }
+
+ ramdacHelperPtr = RamDacHelperCreateInfoRec();
+ switch (TIramdac_ID) {
+ case TI3030_RAMDAC:
+ ramdacHelperPtr->SetBpp = TIramdac3030SetBpp;
+ ramdacHelperPtr->HWCursorInit = TIramdacHWCursorInit;
+ break;
+ case TI3026_RAMDAC:
+ ramdacHelperPtr->SetBpp = TIramdac3026SetBpp;
+ ramdacHelperPtr->HWCursorInit = TIramdacHWCursorInit;
+ break;
+ }
+ ramdacPtr->RamDacType = TIramdac_ID;
+ ramdacHelperPtr->RamDacType = TIramdac_ID;
+ ramdacHelperPtr->Save = TIramdacSave;
+ ramdacHelperPtr->Restore = TIramdacRestore;
+
+ return ramdacHelperPtr;
+}
+
+void
+TIramdac3026SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr ramdacReg)
+{
+ switch (pScrn->bitsPerPixel) {
+ case 32:
+ /* order is important */
+ ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
+ ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x46;
+ ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x5c;
+ ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
+ ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
+ ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
+ ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x3C;
+ /* 0x2A & 0x2B are reserved */
+ ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
+ ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
+ ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
+ if (pScrn->overlayFlags & OVERLAY_8_32_PLANAR) {
+ ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x06;
+ ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x3C;
+ ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x01;
+ }
+ ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
+ break;
+ case 24:
+ /* order is important */
+ ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
+ ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x56;
+ ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x58;
+ ramdacReg->DacRegs[TIDAC_clock_select] = 0x25;
+ ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
+ ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x00;
+ ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C;
+ /* 0x2A & 0x2B are reserved */
+ ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
+ ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
+ ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
+ ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
+ break;
+ case 16:
+ /* order is important */
+#if 0
+ /* Matrox driver uses this */
+ ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x07;
+#else
+ ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
+#endif
+ if (pScrn->depth == 16) {
+ ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x45;
+ } else {
+ ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x44;
+ }
+#if 0
+ /* Matrox driver uses this */
+ ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x50;
+ ramdacReg->DacRegs[TIDAC_clock_select] = 0x15;
+ ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
+ ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x00;
+#else
+ ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x54;
+ ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
+ ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
+ ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
+#endif
+ ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C;
+ /* 0x2A & 0x2B are reserved */
+ ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
+ ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
+ ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
+ ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
+ break;
+ case 8:
+ /* order is important */
+ ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
+ ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x80;
+ ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x4c;
+ ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
+ ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
+ ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
+ ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x1C;
+ /* 0x2A & 0x2B are reserved */
+ ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_blue_low] = 0x00;
+ ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
+ ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x00;
+ ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
+ ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
+ break;
+ }
+}
+
+void
+TIramdac3030SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr ramdacReg)
+{
+ switch (pScrn->bitsPerPixel) {
+ case 32:
+ /* order is important */
+ ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
+ ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x46;
+ ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x5D;
+ ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
+ ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
+ ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
+ ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x3C;
+ /* 0x2A & 0x2B are reserved */
+ ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
+ ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
+ ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
+ if (pScrn->overlayFlags & OVERLAY_8_32_PLANAR) {
+ ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x06;
+ ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x3C;
+ ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x01;
+ }
+ ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
+ break;
+ case 24:
+ /* order is important */
+ ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
+ ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x56;
+ ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x58;
+ ramdacReg->DacRegs[TIDAC_clock_select] = 0x25;
+ ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
+ ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x00;
+ ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C;
+ /* 0x2A & 0x2B are reserved */
+ ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
+ ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
+ ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
+ ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
+ break;
+ case 16:
+ /* order is important */
+#if 0
+ /* Matrox driver uses this */
+ ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x07;
+#else
+ ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
+#endif
+ if (pScrn->depth == 16) {
+ ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x45;
+ } else {
+ ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x44;
+ }
+#if 0
+ /* Matrox driver uses this */
+ ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x50;
+ ramdacReg->DacRegs[TIDAC_clock_select] = 0x15;
+ ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
+ ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x00;
+#else
+ ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x55;
+ ramdacReg->DacRegs[TIDAC_clock_select] = 0x85;
+ ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
+ ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
+#endif
+ ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C;
+ /* 0x2A & 0x2B are reserved */
+ ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
+ ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
+ ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
+ ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
+ break;
+ case 8:
+ /* order is important */
+ ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
+ ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x80;
+ ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x4d;
+ ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
+ ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
+ ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
+ ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x1C;
+ /* 0x2A & 0x2B are reserved */
+ ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
+ ramdacReg->DacRegs[TIDAC_key_blue_low] = 0x00;
+ ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
+ ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x00;
+ ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
+ ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
+ break;
+ }
+}
+
+static void
+TIramdacShowCursor(ScrnInfoPtr pScrn)
+{
+ RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
+
+ /* Enable cursor - X11 mode */
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_ind_curs_ctrl, 0, 0x03);
+}
+
+static void
+TIramdacHideCursor(ScrnInfoPtr pScrn)
+{
+ RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
+
+ /* Disable cursor - X11 mode */
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_ind_curs_ctrl, 0, 0x00);
+}
+
+static void
+TIramdacSetCursorPosition(ScrnInfoPtr pScrn, int x, int y)
+{
+ RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
+
+ x += 64;
+ y += 64;
+
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_XLOW, 0, x & 0xff);
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_XHIGH, 0, (x >> 8) & 0x0f);
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_YLOW, 0, y & 0xff);
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_YHIGH, 0, (y >> 8) & 0x0f);
+}
+
+static void
+TIramdacSetCursorColors(ScrnInfoPtr pScrn, int bg, int fg)
+{
+ RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
+
+ /* Background color */
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_WRITE_ADDR, 0, 1);
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_COLOR, 0, ((bg&0x00ff0000) >> 16));
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_COLOR, 0, ((bg&0x0000ff00) >> 8));
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_COLOR, 0, (bg&0x000000ff) );
+
+ /* Foreground color */
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_WRITE_ADDR, 0, 2);
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_COLOR, 0, ((fg&0x00ff0000) >> 16));
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_COLOR, 0, ((fg&0x0000ff00) >> 8));
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_COLOR, 0, (fg&0x000000ff) );
+}
+
+static void
+TIramdacLoadCursorImage(ScrnInfoPtr pScrn, unsigned char *src)
+{
+ RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
+ int i = 1024;
+
+ /* reset A9,A8 */
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_ind_curs_ctrl, 0, 0x00);
+ /* reset cursor RAM load address A7..A0 */
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_INDEX, 0x00, 0x00);
+
+ while(i--) {
+ /* NOT_DONE: might need a delay here */
+ (*ramdacPtr->WriteDAC)(pScrn, TIDAC_CURS_RAM_DATA, 0, *(src++));
+ }
+}
+
+static Bool
+TIramdacUseHWCursor(ScreenPtr pScr, CursorPtr pCurs)
+{
+ return TRUE;
+}
+
+void
+TIramdacHWCursorInit(xf86CursorInfoPtr infoPtr)
+{
+ infoPtr->MaxWidth = 64;
+ infoPtr->MaxHeight = 64;
+ infoPtr->Flags = HARDWARE_CURSOR_BIT_ORDER_MSBFIRST |
+ HARDWARE_CURSOR_TRUECOLOR_AT_8BPP |
+ HARDWARE_CURSOR_SOURCE_MASK_NOT_INTERLEAVED;
+ infoPtr->SetCursorColors = TIramdacSetCursorColors;
+ infoPtr->SetCursorPosition = TIramdacSetCursorPosition;
+ infoPtr->LoadCursorImage = TIramdacLoadCursorImage;
+ infoPtr->HideCursor = TIramdacHideCursor;
+ infoPtr->ShowCursor = TIramdacShowCursor;
+ infoPtr->UseHWCursor = TIramdacUseHWCursor;
+}
+
+void TIramdacLoadPalette(
+ ScrnInfoPtr pScrn,
+ int numColors,
+ int *indices,
+ LOCO *colors,
+ VisualPtr pVisual
+){
+ RamDacRecPtr hwp = RAMDACSCRPTR(pScrn);
+ int i, index, shift;
+
+ if (pScrn->depth == 16) {
+ for(i = 0; i < numColors; i++) {
+ index = indices[i];
+ (*hwp->WriteAddress)(pScrn, index << 2);
+ (*hwp->WriteData)(pScrn, colors[index >> 1].red);
+ (*hwp->WriteData)(pScrn, colors[index].green);
+ (*hwp->WriteData)(pScrn, colors[index >> 1].blue);
+
+ if(index <= 31) {
+ (*hwp->WriteAddress)(pScrn, index << 3);
+ (*hwp->WriteData)(pScrn, colors[index].red);
+ (*hwp->WriteData)(pScrn, colors[(index << 1) + 1].green);
+ (*hwp->WriteData)(pScrn, colors[index].blue);
+ }
+ }
+} else {
+ shift = (pScrn->depth == 15) ? 3 : 0;
+
+ for(i = 0; i < numColors; i++) {
+ index = indices[i];
+ (*hwp->WriteAddress)(pScrn, index << shift);
+ (*hwp->WriteData)(pScrn, colors[index].red);
+ (*hwp->WriteData)(pScrn, colors[index].green);
+ (*hwp->WriteData)(pScrn, colors[index].blue);
+ }
+}
+}
+
+TIramdacLoadPaletteProc *TIramdacLoadPaletteWeak(void) {
+ return TIramdacLoadPalette;
+}
diff --git a/xorg-server/hw/xfree86/ramdac/xf86Cursor.c b/xorg-server/hw/xfree86/ramdac/xf86Cursor.c
index 91b5795c3..421e35b51 100644
--- a/xorg-server/hw/xfree86/ramdac/xf86Cursor.c
+++ b/xorg-server/hw/xfree86/ramdac/xf86Cursor.c
@@ -18,8 +18,7 @@
#include "inputstr.h"
extern InputInfo inputInfo;
-static int xf86CursorScreenKeyIndex;
-DevPrivateKey xf86CursorScreenKey = &xf86CursorScreenKeyIndex;
+DevPrivateKeyRec xf86CursorScreenKeyRec;
/* sprite functions */
@@ -65,6 +64,9 @@ xf86InitCursor(
if (!xf86InitHardwareCursor(pScreen, infoPtr))
return FALSE;
+ if (!dixRegisterPrivateKey(&xf86CursorScreenKeyRec, PRIVATE_SCREEN, 0))
+ return FALSE;
+
ScreenPriv = calloc(1, sizeof(xf86CursorScreenRec));
if (!ScreenPriv)
return FALSE;
diff --git a/xorg-server/hw/xfree86/ramdac/xf86CursorPriv.h b/xorg-server/hw/xfree86/ramdac/xf86CursorPriv.h
index 32be9c2f3..76e714b32 100644
--- a/xorg-server/hw/xfree86/ramdac/xf86CursorPriv.h
+++ b/xorg-server/hw/xfree86/ramdac/xf86CursorPriv.h
@@ -1,50 +1,51 @@
-
-#ifdef HAVE_XORG_CONFIG_H
-#include <xorg-config.h>
-#endif
-
-#ifndef _XF86CURSORPRIV_H
-#define _XF86CURSORPRIV_H
-
-#include "xf86Cursor.h"
-#include "mipointrst.h"
-
-typedef struct {
- Bool SWCursor;
- Bool isUp;
- Bool showTransparent;
- short HotX;
- short HotY;
- short x;
- short y;
- CursorPtr CurrentCursor, CursorToRestore;
- xf86CursorInfoPtr CursorInfoPtr;
- CloseScreenProcPtr CloseScreen;
- RecolorCursorProcPtr RecolorCursor;
- InstallColormapProcPtr InstallColormap;
- QueryBestSizeProcPtr QueryBestSize;
- miPointerSpriteFuncPtr spriteFuncs;
- Bool PalettedCursor;
- ColormapPtr pInstalledMap;
- Bool (*SwitchMode)(int, DisplayModePtr,int);
- xf86EnableDisableFBAccessProc *EnableDisableFBAccess;
- CursorPtr SavedCursor;
-
- /* Number of requests to force HW cursor */
- int ForceHWCursorCount;
- Bool HWCursorForced;
-
- pointer transparentData;
-} xf86CursorScreenRec, *xf86CursorScreenPtr;
-
-void xf86SetCursor(ScreenPtr pScreen, CursorPtr pCurs, int x, int y);
-void xf86SetTransparentCursor(ScreenPtr pScreen);
-void xf86MoveCursor(ScreenPtr pScreen, int x, int y);
-void xf86RecolorCursor(ScreenPtr pScreen, CursorPtr pCurs, Bool displayed);
-Bool xf86InitHardwareCursor(ScreenPtr pScreen, xf86CursorInfoPtr infoPtr);
-
-CARD32 xf86ReverseBitOrder(CARD32 data);
-
-extern _X_EXPORT DevPrivateKey xf86CursorScreenKey;
-
-#endif /* _XF86CURSORPRIV_H */
+
+#ifdef HAVE_XORG_CONFIG_H
+#include <xorg-config.h>
+#endif
+
+#ifndef _XF86CURSORPRIV_H
+#define _XF86CURSORPRIV_H
+
+#include "xf86Cursor.h"
+#include "mipointrst.h"
+
+typedef struct {
+ Bool SWCursor;
+ Bool isUp;
+ Bool showTransparent;
+ short HotX;
+ short HotY;
+ short x;
+ short y;
+ CursorPtr CurrentCursor, CursorToRestore;
+ xf86CursorInfoPtr CursorInfoPtr;
+ CloseScreenProcPtr CloseScreen;
+ RecolorCursorProcPtr RecolorCursor;
+ InstallColormapProcPtr InstallColormap;
+ QueryBestSizeProcPtr QueryBestSize;
+ miPointerSpriteFuncPtr spriteFuncs;
+ Bool PalettedCursor;
+ ColormapPtr pInstalledMap;
+ Bool (*SwitchMode)(int, DisplayModePtr,int);
+ xf86EnableDisableFBAccessProc *EnableDisableFBAccess;
+ CursorPtr SavedCursor;
+
+ /* Number of requests to force HW cursor */
+ int ForceHWCursorCount;
+ Bool HWCursorForced;
+
+ pointer transparentData;
+} xf86CursorScreenRec, *xf86CursorScreenPtr;
+
+void xf86SetCursor(ScreenPtr pScreen, CursorPtr pCurs, int x, int y);
+void xf86SetTransparentCursor(ScreenPtr pScreen);
+void xf86MoveCursor(ScreenPtr pScreen, int x, int y);
+void xf86RecolorCursor(ScreenPtr pScreen, CursorPtr pCurs, Bool displayed);
+Bool xf86InitHardwareCursor(ScreenPtr pScreen, xf86CursorInfoPtr infoPtr);
+
+CARD32 xf86ReverseBitOrder(CARD32 data);
+
+extern _X_EXPORT DevPrivateKeyRec xf86CursorScreenKeyRec;
+#define xf86CursorScreenKey (&xf86CursorScreenKeyRec)
+
+#endif /* _XF86CURSORPRIV_H */
diff --git a/xorg-server/hw/xfree86/ramdac/xf86RamDac.c b/xorg-server/hw/xfree86/ramdac/xf86RamDac.c
index 25d450c07..a170444a9 100644
--- a/xorg-server/hw/xfree86/ramdac/xf86RamDac.c
+++ b/xorg-server/hw/xfree86/ramdac/xf86RamDac.c
@@ -82,7 +82,7 @@ RamDacInit(ScrnInfoPtr pScrn, RamDacRecPtr ramdacPriv)
((RamDacScreenRecPtr) (pScrn)->privates[RamDacGetScreenIndex()].ptr);
ramdacScrPtr->RamDacRec = ramdacPriv;
- return(TRUE);
+ return TRUE;
}
void
@@ -132,12 +132,10 @@ RamDacFreeRec(ScrnInfoPtr pScrn)
ramdacScrPtr = ((RamDacScreenRecPtr)
(pScrn)->privates[RamDacGetScreenIndex()].ptr);
- if (ramdacHWPtr)
- free(ramdacHWPtr);
+ free(ramdacHWPtr);
ramdacHWPtr = NULL;
- if (ramdacScrPtr)
- free(ramdacScrPtr);
+ free(ramdacScrPtr);
ramdacScrPtr = NULL;
}