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-rw-r--r--mesalib/src/mesa/state_tracker/st_glsl_to_tgsi.cpp19
-rw-r--r--mesalib/src/mesa/state_tracker/st_mesa_to_tgsi.c19
2 files changed, 38 insertions, 0 deletions
diff --git a/mesalib/src/mesa/state_tracker/st_glsl_to_tgsi.cpp b/mesalib/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index b6abe84ac..1d91e3661 100644
--- a/mesalib/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/mesalib/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -4615,6 +4615,25 @@ st_translate_program(
if (sysInputs & (1 << i)) {
unsigned semName = mesa_sysval_to_semantic[i];
t->systemValues[i] = ureg_DECL_system_value(ureg, numSys, semName, 0);
+ if (semName == TGSI_SEMANTIC_INSTANCEID ||
+ semName == TGSI_SEMANTIC_VERTEXID) {
+ /* From Gallium perspective, these system values are always
+ * integer, and require native integer support. However, if
+ * native integer is supported on the vertex stage but not the
+ * pixel stage (e.g, i915g + draw), Mesa will generate IR that
+ * assumes these system values are floats. To resolve the
+ * inconsistency, we insert a U2F.
+ */
+ struct st_context *st = st_context(ctx);
+ struct pipe_screen *pscreen = st->pipe->screen;
+ assert(procType == TGSI_PROCESSOR_VERTEX);
+ assert(pscreen->get_shader_param(pscreen, PIPE_SHADER_VERTEX, PIPE_SHADER_CAP_INTEGERS));
+ if (!ctx->Const.NativeIntegers) {
+ struct ureg_dst temp = ureg_DECL_local_temporary(t->ureg);
+ ureg_U2F( t->ureg, ureg_writemask(temp, TGSI_WRITEMASK_X), t->systemValues[i]);
+ t->systemValues[i] = ureg_scalar(ureg_src(temp), 0);
+ }
+ }
numSys++;
sysInputs &= ~(1 << i);
}
diff --git a/mesalib/src/mesa/state_tracker/st_mesa_to_tgsi.c b/mesalib/src/mesa/state_tracker/st_mesa_to_tgsi.c
index e414ed88c..90af1b009 100644
--- a/mesalib/src/mesa/state_tracker/st_mesa_to_tgsi.c
+++ b/mesalib/src/mesa/state_tracker/st_mesa_to_tgsi.c
@@ -1159,6 +1159,25 @@ st_translate_mesa_program(
if (sysInputs & (1 << i)) {
unsigned semName = mesa_sysval_to_semantic[i];
t->systemValues[i] = ureg_DECL_system_value(ureg, numSys, semName, 0);
+ if (semName == TGSI_SEMANTIC_INSTANCEID ||
+ semName == TGSI_SEMANTIC_VERTEXID) {
+ /* From Gallium perspective, these system values are always
+ * integer, and require native integer support. However, if
+ * native integer is supported on the vertex stage but not the
+ * pixel stage (e.g, i915g + draw), Mesa will generate IR that
+ * assumes these system values are floats. To resolve the
+ * inconsistency, we insert a U2F.
+ */
+ struct st_context *st = st_context(ctx);
+ struct pipe_screen *pscreen = st->pipe->screen;
+ assert(procType == TGSI_PROCESSOR_VERTEX);
+ assert(pscreen->get_shader_param(pscreen, PIPE_SHADER_VERTEX, PIPE_SHADER_CAP_INTEGERS));
+ if (!ctx->Const.NativeIntegers) {
+ struct ureg_dst temp = ureg_DECL_local_temporary(t->ureg);
+ ureg_U2F( t->ureg, ureg_writemask(temp, TGSI_WRITEMASK_X), t->systemValues[i]);
+ t->systemValues[i] = ureg_scalar(ureg_src(temp), 0);
+ }
+ }
numSys++;
sysInputs &= ~(1 << i);
}