From f1c2db43dcf35d2cf4715390bd2391c28e42a8c2 Mon Sep 17 00:00:00 2001 From: marha Date: Sun, 22 Feb 2015 14:31:16 +0100 Subject: xwininfo fontconfig libX11 libXdmcp libfontenc libxcb libxcb/xcb-proto mesalib xserver xkeyboard-config mkfontscale git update 22 Feb 2015 xserver commit 3a06faf3fcdb7451125a46181f9152e8e59e9770 libxcb commit e3ec1f74637237ce500dfd0ca59f2e422da4e019 libxcb/xcb-proto commit 4c550465934164aab2449a125f75f4ca07816233 xkeyboard-config commit 26f344c93f8c6141e9233eb68088ba4fd56bc9ef libX11 commit c8e19b393defd53f046ddc2da3a16881221b3c34 libXdmcp commit 9f4cac7656b221ce2a8f97e7bd31e5e23126d001 libfontenc commit de1843aaf76015c9d99416f3122d169fe331b849 mkfontscale commit 87d628f8eec170ec13bb9feefb1ce05aed07d1d6 xwininfo commit 0c49f8f2bd56b1e77721e81030ea948386dcdf4e fontconfig commit d6d5adeb7940c0d0beb86489c2a1c2ce59e5c044 mesa commit 4359954d842caa2a9f8d4b50d70ecc789884b68b --- mesalib/src/glsl/nir/nir_intrinsics.h | 140 ++++++++++++++++++++++++++++++++++ 1 file changed, 140 insertions(+) create mode 100644 mesalib/src/glsl/nir/nir_intrinsics.h (limited to 'mesalib/src/glsl/nir/nir_intrinsics.h') diff --git a/mesalib/src/glsl/nir/nir_intrinsics.h b/mesalib/src/glsl/nir/nir_intrinsics.h new file mode 100644 index 000000000..d94866c85 --- /dev/null +++ b/mesalib/src/glsl/nir/nir_intrinsics.h @@ -0,0 +1,140 @@ +/* + * Copyright © 2014 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Connor Abbott (cwabbott0@gmail.com) + * + */ + +/** + * This header file defines all the available intrinsics in one place. It + * expands to a list of macros of the form: + * + * INTRINSIC(name, num_srcs, src_components, has_dest, dest_components, + * num_variables, num_indices, flags) + * + * Which should correspond one-to-one with the nir_intrinsic_info structure. It + * is included in both ir.h to create the nir_intrinsic enum (with members of + * the form nir_intrinsic_(name)) and and in opcodes.c to create + * nir_intrinsic_infos, which is a const array of nir_intrinsic_info structures + * for each intrinsic. + */ + +#define ARR(...) { __VA_ARGS__ } + + +INTRINSIC(load_var, 0, ARR(), true, 0, 1, 0, NIR_INTRINSIC_CAN_ELIMINATE) +INTRINSIC(store_var, 1, ARR(0), false, 0, 1, 0, 0) +INTRINSIC(copy_var, 0, ARR(), false, 0, 2, 0, 0) + +/* + * Interpolation of input. The interp_var_at* intrinsics are similar to the + * load_var intrinsic acting an a shader input except that they interpolate + * the input differently. The at_sample and at_offset intrinsics take an + * aditional source that is a integer sample id or a vec2 position offset + * respectively. + */ + +INTRINSIC(interp_var_at_centroid, 0, ARR(0), true, 0, 1, 0, + NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER) +INTRINSIC(interp_var_at_sample, 1, ARR(1), true, 0, 1, 0, + NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER) +INTRINSIC(interp_var_at_offset, 1, ARR(2), true, 0, 1, 0, + NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER) + +/* + * a barrier is an intrinsic with no inputs/outputs but which can't be moved + * around/optimized in general + */ +#define BARRIER(name) INTRINSIC(name, 0, ARR(), false, 0, 0, 0, 0) + +BARRIER(discard) + +INTRINSIC(emit_vertex, 0, ARR(), false, 0, 0, 1, 0) +INTRINSIC(end_primitive, 0, ARR(), false, 0, 0, 1, 0) + +/* + * Atomic counters + * + * The *_var variants take an atomic_uint nir_variable, while the other, + * lowered, variants take a constant buffer index and register offset. + */ + +#define ATOMIC(name, flags) \ + INTRINSIC(atomic_counter_##name##_var, 0, ARR(), true, 1, 1, 0, flags) \ + INTRINSIC(atomic_counter_##name, 1, ARR(1), true, 1, 0, 1, flags) + +ATOMIC(inc, 0) +ATOMIC(dec, 0) +ATOMIC(read, NIR_INTRINSIC_CAN_ELIMINATE) + +#define SYSTEM_VALUE(name, components) \ + INTRINSIC(load_##name, 0, ARR(), true, components, 0, 0, \ + NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER) + +SYSTEM_VALUE(front_face, 1) +SYSTEM_VALUE(vertex_id, 1) +SYSTEM_VALUE(instance_id, 1) +SYSTEM_VALUE(sample_id, 1) +SYSTEM_VALUE(sample_pos, 2) +SYSTEM_VALUE(sample_mask_in, 1) +SYSTEM_VALUE(invocation_id, 1) + +/* + * The first index is the address to load from, and the second index is the + * number of array elements to load. Indirect loads have an additional + * register input, which is added to the constant address to compute the + * final address to load from. For UBO's (and SSBO's), the first source is + * the (possibly constant) UBO buffer index and the indirect (if it exists) + * is the second source. + * + * For vector backends, the address is in terms of one vec4, and so each array + * element is +4 scalar components from the previous array element. For scalar + * backends, the address is in terms of a single 4-byte float/int and arrays + * elements begin immediately after the previous array element. + */ + +#define LOAD(name, extra_srcs, flags) \ + INTRINSIC(load_##name, extra_srcs, ARR(1), true, 0, 0, 2, flags) \ + INTRINSIC(load_##name##_indirect, extra_srcs + 1, ARR(1, 1), \ + true, 0, 0, 2, flags) + +LOAD(uniform, 0, NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER) +LOAD(ubo, 1, NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER) +LOAD(input, 0, NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER) +/* LOAD(ssbo, 1, 0) */ + +/* + * Stores work the same way as loads, except now the first register input is + * the value or array to store and the optional second input is the indirect + * offset. + */ + +#define STORE(name, num_indices, flags) \ + INTRINSIC(store_##name, 1, ARR(0), false, 0, 0, num_indices, flags) \ + INTRINSIC(store_##name##_indirect, 2, ARR(0, 1), false, 0, 0, \ + num_indices, flags) \ + +STORE(output, 2, 0) +/* STORE(ssbo, 3, 0) */ + +LAST_INTRINSIC(store_output_indirect) -- cgit v1.2.3