aboutsummaryrefslogtreecommitdiff
path: root/xorg-server/hw/xfree86/ramdac/TI.c
blob: 2492bb531c64e21342ad4d2c0cafb213561a73d8 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
/*
 * Copyright 1998 by Alan Hourihane, Wigan, England.
 *
 * Permission to use, copy, modify, distribute, and sell this software and its
 * documentation for any purpose is hereby granted without fee, provided that
 * the above copyright notice appear in all copies and that both that
 * copyright notice and this permission notice appear in supporting
 * documentation, and that the name of Alan Hourihane not be used in
 * advertising or publicity pertaining to distribution of the software without
 * specific, written prior permission.  Alan Hourihane makes no representations
 * about the suitability of this software for any purpose.  It is provided
 * "as is" without express or implied warranty.
 *
 * ALAN HOURIHANE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
 * EVENT SHALL ALAN HOURIHANE BE LIABLE FOR ANY SPECIAL, INDIRECT OR
 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
 * PERFORMANCE OF THIS SOFTWARE.
 *
 * Authors:  Alan Hourihane, <alanh@fairlite.demon.co.uk>
 *
 * Modified from IBM.c to support TI RAMDAC routines 
 *   by Jens Owen, <jens@tungstengraphics.com>.
 */

#ifdef HAVE_XORG_CONFIG_H
#include <xorg-config.h>
#endif

#include "xf86.h"
#include "xf86_OSproc.h"

#include "xf86Cursor.h"

#define INIT_TI_RAMDAC_INFO
#include "TIPriv.h"
#include "xf86RamDacPriv.h"

/* The following values are in kHz */
#define TI_MIN_VCO_FREQ  110000
#define TI_MAX_VCO_FREQ  220000

unsigned long
TIramdacCalculateMNPForClock(unsigned long RefClock,    /* In 100Hz units */
                             unsigned long ReqClock,    /* In 100Hz units */
                             char IsPixClock,   /* boolean, is this the pixel or the sys clock */
                             unsigned long MinClock,    /* Min VCO rating */
                             unsigned long MaxClock,    /* Max VCO rating */
                             unsigned long *rM, /* M Out */
                             unsigned long *rN, /* N Out */
                             unsigned long *rP  /* Min P In, P Out */
    )
{
    unsigned long n, p;
    unsigned long best_m = 0, best_n = 0;
    double VCO, IntRef = (double) RefClock;
    double m_err, inc_m, calc_m;
    unsigned long ActualClock;

    /* Make sure that MinClock <= ReqClock <= MaxClock */
    if (ReqClock < MinClock)
        ReqClock = MinClock;
    if (ReqClock > MaxClock)
        ReqClock = MaxClock;

    /*
     * ActualClock = VCO / 2 ^ p
     * Choose p so that TI_MIN_VCO_FREQ <= VCO <= TI_MAX_VCO_FREQ
     * Note that since TI_MAX_VCO_FREQ = 2 * TI_MIN_VCO_FREQ
     * we don't have to bother checking for this maximum limit.
     */
    VCO = (double) ReqClock;
    for (p = 0; p < 3 && VCO < TI_MIN_VCO_FREQ; (p)++)
        VCO *= 2.0;

    /*
     * We avoid doing multiplications by ( 65 - n ),
     * and add an increment instead - this keeps any error small.
     */
    inc_m = VCO / (IntRef * 8.0);

    /* Initial value of calc_m for the loop */
    calc_m = inc_m + inc_m + inc_m;

    /* Initial amount of error for an integer - impossibly large */
    m_err = 2.0;

    /* Search for the closest INTEGER value of ( 65 - m ) */
    for (n = 3; n <= 25; (n)++, calc_m += inc_m) {

        /* Ignore values of ( 65 - m ) which we can't use */
        if (calc_m < 3.0 || calc_m > 64.0)
            continue;

        /*
         * Pick the closest INTEGER (has smallest fractional part).
         * The optimizer should clean this up for us.
         */
        if ((calc_m - (int) calc_m) < m_err) {
            m_err = calc_m - (int) calc_m;
            best_m = (int) calc_m;
            best_n = n;
        }
    }

    /* 65 - ( 65 - x ) = x */
    *rM = 65 - best_m;
    *rN = 65 - best_n;
    *rP = p;

    /* Now all the calculations can be completed */
    VCO = 8.0 * IntRef * best_m / best_n;
    ActualClock = VCO / (1 << p);

    DebugF("f_out=%ld f_vco=%.1f n=%d m=%d p=%d\n",
           ActualClock, VCO, *rN, *rM, *rP);

    return ActualClock;
}

void
TIramdacRestore(ScrnInfoPtr pScrn, RamDacRecPtr ramdacPtr,
                RamDacRegRecPtr ramdacReg)
{
    int i;
    unsigned long status;

    /* Here we pass a short, so that we can evaluate a mask too
     * So that the mask is the high byte and the data the low byte
     * Order is important
     */
    TIRESTORE(TIDAC_latch_ctrl);
    TIRESTORE(TIDAC_true_color_ctrl);
    TIRESTORE(TIDAC_multiplex_ctrl);
    TIRESTORE(TIDAC_clock_select);
    TIRESTORE(TIDAC_palette_page);
    TIRESTORE(TIDAC_general_ctrl);
    TIRESTORE(TIDAC_misc_ctrl);
    /* 0x2A & 0x2B are reserved */
    TIRESTORE(TIDAC_key_over_low);
    TIRESTORE(TIDAC_key_over_high);
    TIRESTORE(TIDAC_key_red_low);
    TIRESTORE(TIDAC_key_red_high);
    TIRESTORE(TIDAC_key_green_low);
    TIRESTORE(TIDAC_key_green_high);
    TIRESTORE(TIDAC_key_blue_low);
    TIRESTORE(TIDAC_key_blue_high);
    TIRESTORE(TIDAC_key_ctrl);
    (*ramdacPtr->WriteDAC) (pScrn, TIDAC_clock_ctrl, 0, 0x30);
    (*ramdacPtr->WriteDAC) (pScrn, TIDAC_clock_ctrl, 0, 0x38);
    TIRESTORE(TIDAC_clock_ctrl);
    TIRESTORE(TIDAC_sense_test);
    TIRESTORE(TIDAC_ind_curs_ctrl);

    /* only restore clocks if they were valid to begin with */

    if (ramdacReg->DacRegs[TIDAC_PIXEL_VALID]) {
        /* Reset pixel clock */
        (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_addr, 0, 0x22);
        (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_pixel_data, 0, 0x3c);

        /* Restore N, M & P values for pixel clocks */
        (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_addr, 0, 0);
        (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_pixel_data, 0,
                                ramdacReg->DacRegs[TIDAC_PIXEL_N]);
        (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_pixel_data, 0,
                                ramdacReg->DacRegs[TIDAC_PIXEL_M]);
        (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_pixel_data, 0,
                                ramdacReg->DacRegs[TIDAC_PIXEL_P]);

        /* wait for pixel clock to lock */
        i = 1000000;
        do {
            status = (*ramdacPtr->ReadDAC) (pScrn, TIDAC_pll_pixel_data);
        } while ((!(status & 0x40)) && (--i));
        if (!(status & 0x40)) {
            xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
                       "Pixel clock setup timed out\n");
            return;
        }
    }

    if (ramdacReg->DacRegs[TIDAC_LOOP_VALID]) {
        /* Reset loop clock */
        (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_addr, 0, 0x22);
        (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_loop_data, 0, 0x70);

        /* Restore N, M & P values for pixel clocks */
        (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_addr, 0, 0);
        (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_loop_data, 0,
                                ramdacReg->DacRegs[TIDAC_LOOP_N]);
        (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_loop_data, 0,
                                ramdacReg->DacRegs[TIDAC_LOOP_M]);
        (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_loop_data, 0,
                                ramdacReg->DacRegs[TIDAC_LOOP_P]);

        /* wait for loop clock to lock */
        i = 1000000;
        do {
            status = (*ramdacPtr->ReadDAC) (pScrn, TIDAC_pll_loop_data);
        } while ((!(status & 0x40)) && (--i));
        if (!(status & 0x40)) {
            xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
                       "Loop clock setup timed out\n");
            return;
        }
    }

    /* restore palette */
    (*ramdacPtr->WriteAddress) (pScrn, 0);
#ifndef NOT_DONE
    for (i = 0; i < 768; i++)
        (*ramdacPtr->WriteData) (pScrn, ramdacReg->DAC[i]);
#else
    (*ramdacPtr->WriteData) (pScrn, 0);
    (*ramdacPtr->WriteData) (pScrn, 0);
    (*ramdacPtr->WriteData) (pScrn, 0);
    for (i = 0; i < 765; i++)
        (*ramdacPtr->WriteData) (pScrn, 0xff);
#endif
}

void
TIramdacSave(ScrnInfoPtr pScrn, RamDacRecPtr ramdacPtr,
             RamDacRegRecPtr ramdacReg)
{
    int i;

    (*ramdacPtr->ReadAddress) (pScrn, 0);
    for (i = 0; i < 768; i++)
        ramdacReg->DAC[i] = (*ramdacPtr->ReadData) (pScrn);

    /* Read back N,M and P values for pixel clock */
    (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_addr, 0, 0);
    ramdacReg->DacRegs[TIDAC_PIXEL_N] =
        (*ramdacPtr->ReadDAC) (pScrn, TIDAC_pll_pixel_data);
    (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_addr, 0, 0x11);
    ramdacReg->DacRegs[TIDAC_PIXEL_M] =
        (*ramdacPtr->ReadDAC) (pScrn, TIDAC_pll_pixel_data);
    (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_addr, 0, 0x22);
    ramdacReg->DacRegs[TIDAC_PIXEL_P] =
        (*ramdacPtr->ReadDAC) (pScrn, TIDAC_pll_pixel_data);

    /* Read back N,M and P values for loop clock */
    (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_addr, 0, 0);
    ramdacReg->DacRegs[TIDAC_LOOP_N] =
        (*ramdacPtr->ReadDAC) (pScrn, TIDAC_pll_loop_data);
    (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_addr, 0, 0x11);
    ramdacReg->DacRegs[TIDAC_LOOP_M] =
        (*ramdacPtr->ReadDAC) (pScrn, TIDAC_pll_loop_data);
    (*ramdacPtr->WriteDAC) (pScrn, TIDAC_pll_addr, 0, 0x22);
    ramdacReg->DacRegs[TIDAC_LOOP_P] =
        (*ramdacPtr->ReadDAC) (pScrn, TIDAC_pll_loop_data);

    /* Order is important */
    TISAVE(TIDAC_latch_ctrl);
    TISAVE(TIDAC_true_color_ctrl);
    TISAVE(TIDAC_multiplex_ctrl);
    TISAVE(TIDAC_clock_select);
    TISAVE(TIDAC_palette_page);
    TISAVE(TIDAC_general_ctrl);
    TISAVE(TIDAC_misc_ctrl);
    /* 0x2A & 0x2B are reserved */
    TISAVE(TIDAC_key_over_low);
    TISAVE(TIDAC_key_over_high);
    TISAVE(TIDAC_key_red_low);
    TISAVE(TIDAC_key_red_high);
    TISAVE(TIDAC_key_green_low);
    TISAVE(TIDAC_key_green_high);
    TISAVE(TIDAC_key_blue_low);
    TISAVE(TIDAC_key_blue_high);
    TISAVE(TIDAC_key_ctrl);
    TISAVE(TIDAC_clock_ctrl);
    TISAVE(TIDAC_sense_test);
    TISAVE(TIDAC_ind_curs_ctrl);
}

RamDacHelperRecPtr
TIramdacProbe(ScrnInfoPtr pScrn, RamDacSupportedInfoRecPtr ramdacs)
{
    RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
    RamDacHelperRecPtr ramdacHelperPtr = NULL;
    Bool RamDacIsSupported = FALSE;
    int TIramdac_ID = -1;
    int i;
    unsigned char id, rev, rev2, id2;

    /* read ID and revision */
    rev = (*ramdacPtr->ReadDAC) (pScrn, TIDAC_rev);
    id = (*ramdacPtr->ReadDAC) (pScrn, TIDAC_id);

    /* check if ID and revision are read only */
    (*ramdacPtr->WriteDAC) (pScrn, ~rev, 0, TIDAC_rev);
    (*ramdacPtr->WriteDAC) (pScrn, ~id, 0, TIDAC_id);
    rev2 = (*ramdacPtr->ReadDAC) (pScrn, TIDAC_rev);
    id2 = (*ramdacPtr->ReadDAC) (pScrn, TIDAC_id);

    switch (id) {
    case TIDAC_TVP_3030_ID:
        if (id == id2 && rev == rev2)   /* check for READ ONLY */
            TIramdac_ID = TI3030_RAMDAC;
        break;
    case TIDAC_TVP_3026_ID:
        if (id == id2 && rev == rev2)   /* check for READ ONLY */
            TIramdac_ID = TI3026_RAMDAC;
        break;
    }

    (*ramdacPtr->WriteDAC) (pScrn, rev, 0, TIDAC_rev);
    (*ramdacPtr->WriteDAC) (pScrn, id, 0, TIDAC_id);

    if (TIramdac_ID == -1) {
        xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
                   "Cannot determine TI RAMDAC type, aborting\n");
        return NULL;
    }
    else {
        xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
                   "Attached RAMDAC is %s\n",
                   TIramdacDeviceInfo[TIramdac_ID & 0xFFFF].DeviceName);
    }

    for (i = 0; ramdacs[i].token != -1; i++) {
        if (ramdacs[i].token == TIramdac_ID)
            RamDacIsSupported = TRUE;
    }

    if (!RamDacIsSupported) {
        xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
                   "This TI RAMDAC is NOT supported by this driver, aborting\n");
        return NULL;
    }

    ramdacHelperPtr = RamDacHelperCreateInfoRec();
    switch (TIramdac_ID) {
    case TI3030_RAMDAC:
        ramdacHelperPtr->SetBpp = TIramdac3030SetBpp;
        ramdacHelperPtr->HWCursorInit = TIramdacHWCursorInit;
        break;
    case TI3026_RAMDAC:
        ramdacHelperPtr->SetBpp = TIramdac3026SetBpp;
        ramdacHelperPtr->HWCursorInit = TIramdacHWCursorInit;
        break;
    }
    ramdacPtr->RamDacType = TIramdac_ID;
    ramdacHelperPtr->RamDacType = TIramdac_ID;
    ramdacHelperPtr->Save = TIramdacSave;
    ramdacHelperPtr->Restore = TIramdacRestore;

    return ramdacHelperPtr;
}

void
TIramdac3026SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr ramdacReg)
{
    switch (pScrn->bitsPerPixel) {
    case 32:
        /* order is important */
        ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
        ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x46;
        ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x5c;
        ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
        ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
        ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
        ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x3C;
        /* 0x2A & 0x2B are reserved */
        ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
        ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
        ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
        if (pScrn->overlayFlags & OVERLAY_8_32_PLANAR) {
            ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x06;
            ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x3C;
            ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x01;
        }
        ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
        break;
    case 24:
        /* order is important */
        ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
        ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x56;
        ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x58;
        ramdacReg->DacRegs[TIDAC_clock_select] = 0x25;
        ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
        ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x00;
        ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C;
        /* 0x2A & 0x2B are reserved */
        ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
        ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
        ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
        ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
        break;
    case 16:
        /* order is important */
#if 0
        /* Matrox driver uses this */
        ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x07;
#else
        ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
#endif
        if (pScrn->depth == 16) {
            ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x45;
        }
        else {
            ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x44;
        }
#if 0
        /* Matrox driver uses this */
        ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x50;
        ramdacReg->DacRegs[TIDAC_clock_select] = 0x15;
        ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
        ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x00;
#else
        ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x54;
        ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
        ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
        ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
#endif
        ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C;
        /* 0x2A & 0x2B are reserved */
        ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
        ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
        ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
        ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
        break;
    case 8:
        /* order is important */
        ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
        ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x80;
        ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x4c;
        ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
        ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
        ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
        ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x1C;
        /* 0x2A & 0x2B are reserved */
        ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_blue_low] = 0x00;
        ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
        ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x00;
        ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
        ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
        break;
    }
}

void
TIramdac3030SetBpp(ScrnInfoPtr pScrn, RamDacRegRecPtr ramdacReg)
{
    switch (pScrn->bitsPerPixel) {
    case 32:
        /* order is important */
        ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
        ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x46;
        ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x5D;
        ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
        ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
        ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
        ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x3C;
        /* 0x2A & 0x2B are reserved */
        ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
        ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
        ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
        if (pScrn->overlayFlags & OVERLAY_8_32_PLANAR) {
            ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x06;
            ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x3C;
            ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x01;
        }
        ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
        break;
    case 24:
        /* order is important */
        ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
        ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x56;
        ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x58;
        ramdacReg->DacRegs[TIDAC_clock_select] = 0x25;
        ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
        ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x00;
        ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C;
        /* 0x2A & 0x2B are reserved */
        ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
        ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
        ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
        ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
        break;
    case 16:
        /* order is important */
#if 0
        /* Matrox driver uses this */
        ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x07;
#else
        ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
#endif
        if (pScrn->depth == 16) {
            ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x45;
        }
        else {
            ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x44;
        }
#if 0
        /* Matrox driver uses this */
        ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x50;
        ramdacReg->DacRegs[TIDAC_clock_select] = 0x15;
        ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
        ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x00;
#else
        ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x55;
        ramdacReg->DacRegs[TIDAC_clock_select] = 0x85;
        ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
        ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
#endif
        ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x2C;
        /* 0x2A & 0x2B are reserved */
        ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_blue_low] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
        ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x10;
        ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
        ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
        break;
    case 8:
        /* order is important */
        ramdacReg->DacRegs[TIDAC_latch_ctrl] = 0x06;
        ramdacReg->DacRegs[TIDAC_true_color_ctrl] = 0x80;
        ramdacReg->DacRegs[TIDAC_multiplex_ctrl] = 0x4d;
        ramdacReg->DacRegs[TIDAC_clock_select] = 0x05;
        ramdacReg->DacRegs[TIDAC_palette_page] = 0x00;
        ramdacReg->DacRegs[TIDAC_general_ctrl] = 0x10;
        ramdacReg->DacRegs[TIDAC_misc_ctrl] = 0x1C;
        /* 0x2A & 0x2B are reserved */
        ramdacReg->DacRegs[TIDAC_key_over_low] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_over_high] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_red_low] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_red_high] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_green_low] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_green_high] = 0xFF;
        ramdacReg->DacRegs[TIDAC_key_blue_low] = 0x00;
        ramdacReg->DacRegs[TIDAC_key_blue_high] = 0x00;
        ramdacReg->DacRegs[TIDAC_key_ctrl] = 0x00;
        ramdacReg->DacRegs[TIDAC_sense_test] = 0x00;
        ramdacReg->DacRegs[TIDAC_ind_curs_ctrl] = 0x00;
        break;
    }
}

static void
TIramdacShowCursor(ScrnInfoPtr pScrn)
{
    RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);

    /* Enable cursor - X11 mode */
    (*ramdacPtr->WriteDAC) (pScrn, TIDAC_ind_curs_ctrl, 0, 0x03);
}

static void
TIramdacHideCursor(ScrnInfoPtr pScrn)
{
    RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);

    /* Disable cursor - X11 mode */
    (*ramdacPtr->WriteDAC) (pScrn, TIDAC_ind_curs_ctrl, 0, 0x00);
}

static void
TIramdacSetCursorPosition(ScrnInfoPtr pScrn, int x, int y)
{
    RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);

    x += 64;
    y += 64;

    (*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_XLOW, 0, x & 0xff);
    (*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_XHIGH, 0, (x >> 8) & 0x0f);
    (*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_YLOW, 0, y & 0xff);
    (*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_YHIGH, 0, (y >> 8) & 0x0f);
}

static void
TIramdacSetCursorColors(ScrnInfoPtr pScrn, int bg, int fg)
{
    RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);

    /* Background color */
    (*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_WRITE_ADDR, 0, 1);
    (*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_COLOR, 0,
                            ((bg & 0x00ff0000) >> 16));
    (*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_COLOR, 0,
                            ((bg & 0x0000ff00) >> 8));
    (*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_COLOR, 0, (bg & 0x000000ff));

    /* Foreground color */
    (*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_WRITE_ADDR, 0, 2);
    (*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_COLOR, 0,
                            ((fg & 0x00ff0000) >> 16));
    (*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_COLOR, 0,
                            ((fg & 0x0000ff00) >> 8));
    (*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_COLOR, 0, (fg & 0x000000ff));
}

static Bool
TIramdacLoadCursorImage(ScrnInfoPtr pScrn, unsigned char *src)
{
    RamDacRecPtr ramdacPtr = RAMDACSCRPTR(pScrn);
    int i = 1024;

    /* reset A9,A8 */
    (*ramdacPtr->WriteDAC) (pScrn, TIDAC_ind_curs_ctrl, 0, 0x00);
    /* reset cursor RAM load address A7..A0 */
    (*ramdacPtr->WriteDAC) (pScrn, TIDAC_INDEX, 0x00, 0x00);

    while (i--) {
        /* NOT_DONE: might need a delay here */
        (*ramdacPtr->WriteDAC) (pScrn, TIDAC_CURS_RAM_DATA, 0, *(src++));
    }
    return TRUE;
}

static Bool
TIramdacUseHWCursor(ScreenPtr pScr, CursorPtr pCurs)
{
    return TRUE;
}

void
TIramdacHWCursorInit(xf86CursorInfoPtr infoPtr)
{
    infoPtr->MaxWidth = 64;
    infoPtr->MaxHeight = 64;
    infoPtr->Flags = HARDWARE_CURSOR_BIT_ORDER_MSBFIRST |
        HARDWARE_CURSOR_TRUECOLOR_AT_8BPP |
        HARDWARE_CURSOR_SOURCE_MASK_NOT_INTERLEAVED;
    infoPtr->SetCursorColors = TIramdacSetCursorColors;
    infoPtr->SetCursorPosition = TIramdacSetCursorPosition;
    infoPtr->LoadCursorImageCheck = TIramdacLoadCursorImage;
    infoPtr->HideCursor = TIramdacHideCursor;
    infoPtr->ShowCursor = TIramdacShowCursor;
    infoPtr->UseHWCursor = TIramdacUseHWCursor;
}

void
TIramdacLoadPalette(ScrnInfoPtr pScrn,
                    int numColors,
                    int *indices, LOCO * colors, VisualPtr pVisual)
{
    RamDacRecPtr hwp = RAMDACSCRPTR(pScrn);
    int i, index, shift;

    if (pScrn->depth == 16) {
        for (i = 0; i < numColors; i++) {
            index = indices[i];
            (*hwp->WriteAddress) (pScrn, index << 2);
            (*hwp->WriteData) (pScrn, colors[index >> 1].red);
            (*hwp->WriteData) (pScrn, colors[index].green);
            (*hwp->WriteData) (pScrn, colors[index >> 1].blue);

            if (index <= 31) {
                (*hwp->WriteAddress) (pScrn, index << 3);
                (*hwp->WriteData) (pScrn, colors[index].red);
                (*hwp->WriteData) (pScrn, colors[(index << 1) + 1].green);
                (*hwp->WriteData) (pScrn, colors[index].blue);
            }
        }
    }
    else {
        shift = (pScrn->depth == 15) ? 3 : 0;

        for (i = 0; i < numColors; i++) {
            index = indices[i];
            (*hwp->WriteAddress) (pScrn, index << shift);
            (*hwp->WriteData) (pScrn, colors[index].red);
            (*hwp->WriteData) (pScrn, colors[index].green);
            (*hwp->WriteData) (pScrn, colors[index].blue);
        }
    }
}

TIramdacLoadPaletteProc *
TIramdacLoadPaletteWeak(void)
{
    return TIramdacLoadPalette;
}