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| author | marha <marha@users.sourceforge.net> | 2012-07-04 10:36:18 +0200 |
|---|---|---|
| committer | marha <marha@users.sourceforge.net> | 2012-07-04 10:36:18 +0200 |
| commit | fc8f37239f3af088819c18f5632b2608954af73a (patch) | |
| tree | 012ded3d00546b7f2fa807f466643eadf6f815ba /mesalib/src/glsl/lower_instructions.cpp | |
| parent | fdef5bff99e6079f64bc6b91c91b42195c85adeb (diff) | |
| download | vcxsrv-fc8f37239f3af088819c18f5632b2608954af73a.tar.gz vcxsrv-fc8f37239f3af088819c18f5632b2608954af73a.tar.bz2 vcxsrv-fc8f37239f3af088819c18f5632b2608954af73a.zip | |
mesa xserver git update 4 Jul 2012
Diffstat (limited to 'mesalib/src/glsl/lower_instructions.cpp')
| -rw-r--r-- | mesalib/src/glsl/lower_instructions.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/mesalib/src/glsl/lower_instructions.cpp b/mesalib/src/glsl/lower_instructions.cpp index d79eb0a7f..a8ef7654e 100644 --- a/mesalib/src/glsl/lower_instructions.cpp +++ b/mesalib/src/glsl/lower_instructions.cpp @@ -50,7 +50,7 @@ * * DIV_TO_MUL_RCP and INT_DIV_TO_MUL_RCP: * -------------------------------------- - * Breaks an ir_unop_div expression down to op0 * (rcp(op1)). + * Breaks an ir_binop_div expression down to op0 * (rcp(op1)). * * Many GPUs don't have a divide instruction (945 and 965 included), * but they do have an RCP instruction to compute an approximate @@ -74,7 +74,7 @@ * * MOD_TO_FRACT: * ------------- - * Breaks an ir_unop_mod expression down to (op1 * fract(op0 / op1)) + * Breaks an ir_binop_mod expression down to (op1 * fract(op0 / op1)) * * Many GPUs don't have a MOD instruction (945 and 965 included), and * if we have to break it down like this anyway, it gives an |