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-rw-r--r--mesalib/src/mesa/state_tracker/st_glsl_to_tgsi.cpp7
-rw-r--r--mesalib/src/mesa/state_tracker/st_mesa_to_tgsi.c11
2 files changed, 11 insertions, 7 deletions
diff --git a/mesalib/src/mesa/state_tracker/st_glsl_to_tgsi.cpp b/mesalib/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 64e0a8a46..69c1b412b 100644
--- a/mesalib/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/mesalib/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -2976,9 +2976,10 @@ glsl_to_tgsi_visitor::visit(ir_discard *ir)
if (ir->condition) {
ir->condition->accept(this);
this->result.negate = ~this->result.negate;
- emit(ir, TGSI_OPCODE_KIL, undef_dst, this->result);
+ emit(ir, TGSI_OPCODE_KILL_IF, undef_dst, this->result);
} else {
- emit(ir, TGSI_OPCODE_KILP);
+ /* unconditional kil */
+ emit(ir, TGSI_OPCODE_KILL);
}
}
@@ -4009,7 +4010,7 @@ get_bitmap_visitor(struct st_fragment_program *fp,
src0.negate = NEGATE_XYZW;
if (st->bitmap.tex_format == PIPE_FORMAT_L8_UNORM)
src0.swizzle = SWIZZLE_XXXX;
- inst = v->emit(NULL, TGSI_OPCODE_KIL, undef_dst, src0);
+ inst = v->emit(NULL, TGSI_OPCODE_KILL_IF, undef_dst, src0);
/* Now copy the instructions from the original glsl_to_tgsi_visitor into the
* new visitor. */
diff --git a/mesalib/src/mesa/state_tracker/st_mesa_to_tgsi.c b/mesalib/src/mesa/state_tracker/st_mesa_to_tgsi.c
index dd9f4fc53..67c6f53f6 100644
--- a/mesalib/src/mesa/state_tracker/st_mesa_to_tgsi.c
+++ b/mesalib/src/mesa/state_tracker/st_mesa_to_tgsi.c
@@ -585,9 +585,10 @@ translate_opcode( unsigned op )
case OPCODE_TRUNC:
return TGSI_OPCODE_TRUNC;
case OPCODE_KIL:
- return TGSI_OPCODE_KIL;
+ return TGSI_OPCODE_KILL_IF;
case OPCODE_KIL_NV:
- return TGSI_OPCODE_KILP;
+ /* XXX we don't support condition codes in TGSI */
+ return TGSI_OPCODE_KILL;
case OPCODE_LG2:
return TGSI_OPCODE_LG2;
case OPCODE_LOG:
@@ -614,8 +615,6 @@ translate_opcode( unsigned op )
return TGSI_OPCODE_RCP;
case OPCODE_RET:
return TGSI_OPCODE_RET;
- case OPCODE_RSQ:
- return TGSI_OPCODE_RSQ;
case OPCODE_SCS:
return TGSI_OPCODE_SCS;
case OPCODE_SEQ:
@@ -755,6 +754,10 @@ compile_instruction(
emit_ddy( t, dst[0], &inst->SrcReg[0] );
break;
+ case OPCODE_RSQ:
+ ureg_RSQ( ureg, dst[0], ureg_abs(src[0]) );
+ break;
+
default:
ureg_insn( ureg,
translate_opcode( inst->Opcode ),